2 include/comedi.h (installed as /usr/include/comedi.h)
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU Lesser General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 /* comedi's major device number */
32 #define COMEDI_MAJOR 98
35 maximum number of minor devices. This can be increased, although
36 kernel structures are currently statically allocated, thus you
37 don't want this to be much more than you actually use.
39 #define COMEDI_NDEVICES 16
41 /* number of config options in the config structure */
42 #define COMEDI_NDEVCONFOPTS 32
43 /*length of nth chunk of firmware data*/
44 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25
45 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26
46 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27
47 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28
48 #define COMEDI_DEVCONF_AUX_DATA_HI 29 /*most significant 32 bits of pointer address (if needed) */
49 #define COMEDI_DEVCONF_AUX_DATA_LO 30 /*least significant 32 bits of pointer address */
50 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */
52 /* max length of device and driver names */
53 #define COMEDI_NAMELEN 20
55 typedef unsigned int lsampl_t;
56 typedef unsigned short sampl_t;
58 /* packs and unpacks a channel/range number */
60 #define CR_PACK(chan,rng,aref) ( (((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan) )
61 #define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
63 #define CR_CHAN(a) ((a)&0xffff)
64 #define CR_RANGE(a) (((a)>>16)&0xff)
65 #define CR_AREF(a) (((a)>>24)&0x03)
67 #define CR_FLAGS_MASK 0xfc000000
68 #define CR_ALT_FILTER (1<<26)
69 #define CR_DITHER CR_ALT_FILTER
70 #define CR_DEGLITCH CR_ALT_FILTER
71 #define CR_ALT_SOURCE (1<<27)
72 #define CR_EDGE (1<<30)
73 #define CR_INVERT (1<<31)
75 #define AREF_GROUND 0x00 /* analog ref = analog ground */
76 #define AREF_COMMON 0x01 /* analog ref = analog common */
77 #define AREF_DIFF 0x02 /* analog ref = differential */
78 #define AREF_OTHER 0x03 /* analog ref = other (undefined) */
80 /* counters -- these are arbitrary values */
81 #define GPCT_RESET 0x0001
82 #define GPCT_SET_SOURCE 0x0002
83 #define GPCT_SET_GATE 0x0004
84 #define GPCT_SET_DIRECTION 0x0008
85 #define GPCT_SET_OPERATION 0x0010
86 #define GPCT_ARM 0x0020
87 #define GPCT_DISARM 0x0040
88 #define GPCT_GET_INT_CLK_FRQ 0x0080
90 #define GPCT_INT_CLOCK 0x0001
91 #define GPCT_EXT_PIN 0x0002
92 #define GPCT_NO_GATE 0x0004
93 #define GPCT_UP 0x0008
94 #define GPCT_DOWN 0x0010
95 #define GPCT_HWUD 0x0020
96 #define GPCT_SIMPLE_EVENT 0x0040
97 #define GPCT_SINGLE_PERIOD 0x0080
98 #define GPCT_SINGLE_PW 0x0100
99 #define GPCT_CONT_PULSE_OUT 0x0200
100 #define GPCT_SINGLE_PULSE_OUT 0x0400
104 #define INSN_MASK_WRITE 0x8000000
105 #define INSN_MASK_READ 0x4000000
106 #define INSN_MASK_SPECIAL 0x2000000
108 #define INSN_READ ( 0 | INSN_MASK_READ)
109 #define INSN_WRITE ( 1 | INSN_MASK_WRITE)
110 #define INSN_BITS ( 2 | INSN_MASK_READ|INSN_MASK_WRITE)
111 #define INSN_CONFIG ( 3 | INSN_MASK_READ|INSN_MASK_WRITE)
112 #define INSN_GTOD ( 4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
113 #define INSN_WAIT ( 5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
114 #define INSN_INTTRIG ( 6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
117 /* These flags are used in comedi_trig structures */
119 #define TRIG_BOGUS 0x0001 /* do the motions */
120 #define TRIG_DITHER 0x0002 /* enable dithering */
121 #define TRIG_DEGLITCH 0x0004 /* enable deglitching */
122 //#define TRIG_RT 0x0008 /* perform op in real time */
123 #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */
124 #define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */
125 //#define TRIG_WRITE 0x0040 /* write to bidirectional devices */
128 /* These flags are used in comedi_cmd structures */
130 #define CMDF_PRIORITY 0x00000008 /* try to use a real-time interrupt while performing command */
132 #define TRIG_RT CMDF_PRIORITY /* compatibility definition */
134 #define CMDF_WRITE 0x00000040
135 #define TRIG_WRITE CMDF_WRITE /* compatibility definition */
137 #define CMDF_RAWDATA 0x00000080
139 #define COMEDI_EV_START 0x00040000
140 #define COMEDI_EV_SCAN_BEGIN 0x00080000
141 #define COMEDI_EV_CONVERT 0x00100000
142 #define COMEDI_EV_SCAN_END 0x00200000
143 #define COMEDI_EV_STOP 0x00400000
145 #define TRIG_ROUND_MASK 0x00030000
146 #define TRIG_ROUND_NEAREST 0x00000000
147 #define TRIG_ROUND_DOWN 0x00010000
148 #define TRIG_ROUND_UP 0x00020000
149 #define TRIG_ROUND_UP_NEXT 0x00030000
151 /* trigger sources */
153 #define TRIG_ANY 0xffffffff
154 #define TRIG_INVALID 0x00000000
156 #define TRIG_NONE 0x00000001 /* never trigger */
157 #define TRIG_NOW 0x00000002 /* trigger now + N ns */
158 #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */
159 #define TRIG_TIME 0x00000008 /* trigger at time N ns */
160 #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */
161 #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */
162 #define TRIG_EXT 0x00000040 /* trigger on external signal N */
163 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
164 #define TRIG_OTHER 0x00000100 /* driver defined */
166 /* subdevice flags */
168 #define SDF_BUSY 0x0001 /* device is busy */
169 #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */
170 #define SDF_LOCKED 0x0004 /* subdevice is locked */
171 #define SDF_LOCK_OWNER 0x0008 /* you own lock */
172 #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */
173 #define SDF_FLAGS 0x0020 /* flags depend on channel */
174 #define SDF_RANGETYPE 0x0040 /* range type depends on channel */
175 #define SDF_MODE0 0x0080 /* can do mode 0 */
176 #define SDF_MODE1 0x0100 /* can do mode 1 */
177 #define SDF_MODE2 0x0200 /* can do mode 2 */
178 #define SDF_MODE3 0x0400 /* can do mode 3 */
179 #define SDF_MODE4 0x0800 /* can do mode 4 */
180 #define SDF_CMD 0x1000 /* can do commands (deprecated) */
181 #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */
182 #define SDF_CMD_WRITE 0x4000 /* can do output commands */
183 #define SDF_CMD_READ 0x8000 /* can do input commands */
185 #define SDF_READABLE 0x00010000 /* subdevice can be read (e.g. analog input) */
186 #define SDF_WRITABLE 0x00020000 /* subdevice can be written (e.g. analog output) */
187 #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */
188 #define SDF_INTERNAL 0x00040000 /* subdevice does not have externally visible lines */
189 #define SDF_RT 0x00080000 /* DEPRECATED: subdevice is RT capable */
190 #define SDF_GROUND 0x00100000 /* can do aref=ground */
191 #define SDF_COMMON 0x00200000 /* can do aref=common */
192 #define SDF_DIFF 0x00400000 /* can do aref=diff */
193 #define SDF_OTHER 0x00800000 /* can do aref=other */
194 #define SDF_DITHER 0x01000000 /* can do dithering */
195 #define SDF_DEGLITCH 0x02000000 /* can do deglitching */
196 #define SDF_MMAP 0x04000000 /* can do mmap() */
197 #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */
198 #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */
199 #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */
200 /* re recyle these flags for PWM */
201 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */
202 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */
206 /* subdevice types */
208 enum comedi_subdevice_type {
209 COMEDI_SUBD_UNUSED, /* unused by driver */
210 COMEDI_SUBD_AI, /* analog input */
211 COMEDI_SUBD_AO, /* analog output */
212 COMEDI_SUBD_DI, /* digital input */
213 COMEDI_SUBD_DO, /* digital output */
214 COMEDI_SUBD_DIO, /* digital input/output */
215 COMEDI_SUBD_COUNTER, /* counter */
216 COMEDI_SUBD_TIMER, /* timer */
217 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */
218 COMEDI_SUBD_CALIB, /* calibration DACs */
219 COMEDI_SUBD_PROC, /* processor, DSP */
220 COMEDI_SUBD_SERIAL, /* serial IO */
221 COMEDI_SUBD_PWM /* PWM */
224 /* configuration instructions */
226 enum configuration_ids {
227 INSN_CONFIG_DIO_INPUT = 0,
228 INSN_CONFIG_DIO_OUTPUT = 1,
229 INSN_CONFIG_DIO_OPENDRAIN = 2,
230 INSN_CONFIG_ANALOG_TRIG = 16,
231 // INSN_CONFIG_WAVEFORM = 17,
232 // INSN_CONFIG_TRIG = 18,
233 // INSN_CONFIG_COUNTER = 19,
234 INSN_CONFIG_ALT_SOURCE = 20,
235 INSN_CONFIG_DIGITAL_TRIG = 21,
236 INSN_CONFIG_BLOCK_SIZE = 22,
237 INSN_CONFIG_TIMER_1 = 23,
238 INSN_CONFIG_FILTER = 24,
239 INSN_CONFIG_CHANGE_NOTIFY = 25,
241 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
242 INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
243 INSN_CONFIG_DIO_QUERY = 28,
244 INSN_CONFIG_PWM_OUTPUT = 29,
245 INSN_CONFIG_GET_PWM_OUTPUT = 30,
246 INSN_CONFIG_ARM = 31,
247 INSN_CONFIG_DISARM = 32,
248 INSN_CONFIG_GET_COUNTER_STATUS = 33,
249 INSN_CONFIG_RESET = 34,
250 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, // Use CTR as single pulsegenerator
251 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, // Use CTR as pulsetraingenerator
252 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, // Use the counter as encoder
253 INSN_CONFIG_SET_GATE_SRC = 2001, // Set gate source
254 INSN_CONFIG_GET_GATE_SRC = 2002, // Get gate source
255 INSN_CONFIG_SET_CLOCK_SRC = 2003, // Set master clock source
256 INSN_CONFIG_GET_CLOCK_SRC = 2004, // Get master clock source
257 INSN_CONFIG_SET_OTHER_SRC = 2005, // Set other source
258 // INSN_CONFIG_GET_OTHER_SRC = 2006, // Get other source
259 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE, // Get size in bytes of subdevice's on-board fifos used during streaming input/output
260 INSN_CONFIG_SET_COUNTER_MODE = 4097,
261 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */
262 INSN_CONFIG_8254_READ_STATUS = 4098,
263 INSN_CONFIG_SET_ROUTING = 4099,
264 INSN_CONFIG_GET_ROUTING = 4109,
266 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
267 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
268 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
269 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay at the same time*/
270 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 /* gets H bridge data: duty cycle and the sign bit */
273 enum comedi_io_direction {
282 #define COMEDI_DEVCONFIG _IOW(CIO,0,comedi_devconfig)
283 #define COMEDI_DEVINFO _IOR(CIO,1,comedi_devinfo)
284 #define COMEDI_SUBDINFO _IOR(CIO,2,comedi_subdinfo)
285 #define COMEDI_CHANINFO _IOR(CIO,3,comedi_chaninfo)
286 #define COMEDI_TRIG _IOWR(CIO,4,comedi_trig)
287 #define COMEDI_LOCK _IO(CIO,5)
288 #define COMEDI_UNLOCK _IO(CIO,6)
289 #define COMEDI_CANCEL _IO(CIO,7)
290 #define COMEDI_RANGEINFO _IOR(CIO,8,comedi_rangeinfo)
291 #define COMEDI_CMD _IOR(CIO,9,comedi_cmd)
292 #define COMEDI_CMDTEST _IOR(CIO,10,comedi_cmd)
293 #define COMEDI_INSNLIST _IOR(CIO,11,comedi_insnlist)
294 #define COMEDI_INSN _IOR(CIO,12,comedi_insn)
295 #define COMEDI_BUFCONFIG _IOR(CIO,13,comedi_bufconfig)
296 #define COMEDI_BUFINFO _IOWR(CIO,14,comedi_bufinfo)
297 #define COMEDI_POLL _IO(CIO,15)
301 typedef struct comedi_trig_struct comedi_trig;
302 typedef struct comedi_cmd_struct comedi_cmd;
303 typedef struct comedi_insn_struct comedi_insn;
304 typedef struct comedi_insnlist_struct comedi_insnlist;
305 typedef struct comedi_chaninfo_struct comedi_chaninfo;
306 typedef struct comedi_subdinfo_struct comedi_subdinfo;
307 typedef struct comedi_devinfo_struct comedi_devinfo;
308 typedef struct comedi_devconfig_struct comedi_devconfig;
309 typedef struct comedi_rangeinfo_struct comedi_rangeinfo;
310 typedef struct comedi_krange_struct comedi_krange;
311 typedef struct comedi_bufconfig_struct comedi_bufconfig;
312 typedef struct comedi_bufinfo_struct comedi_bufinfo;
314 struct comedi_trig_struct {
315 unsigned int subdev; /* subdevice */
316 unsigned int mode; /* mode */
318 unsigned int n_chan; /* number of channels */
319 unsigned int *chanlist; /* channel/range list */
320 sampl_t *data; /* data list, size depends on subd flags */
321 unsigned int n; /* number of scans */
322 unsigned int trigsrc;
323 unsigned int trigvar;
324 unsigned int trigvar1;
325 unsigned int data_len;
326 unsigned int unused[3];
329 struct comedi_insn_struct {
334 unsigned int chanspec;
335 unsigned int unused[3];
338 struct comedi_insnlist_struct {
339 unsigned int n_insns;
343 struct comedi_cmd_struct {
347 unsigned int start_src;
348 unsigned int start_arg;
350 unsigned int scan_begin_src;
351 unsigned int scan_begin_arg;
353 unsigned int convert_src;
354 unsigned int convert_arg;
356 unsigned int scan_end_src;
357 unsigned int scan_end_arg;
359 unsigned int stop_src;
360 unsigned int stop_arg;
362 unsigned int *chanlist; /* channel/range list */
363 unsigned int chanlist_len;
365 sampl_t *data; /* data list, size depends on subd flags */
366 unsigned int data_len;
369 struct comedi_chaninfo_struct {
371 lsampl_t *maxdata_list;
372 unsigned int *flaglist;
373 unsigned int *rangelist;
374 unsigned int unused[4];
377 struct comedi_rangeinfo_struct {
378 unsigned int range_type;
382 struct comedi_krange_struct {
383 int min; /* fixed point, multiply by 1e-6 */
384 int max; /* fixed point, multiply by 1e-6 */
388 struct comedi_subdinfo_struct {
391 unsigned int subd_flags;
392 unsigned int timer_type;
393 unsigned int len_chanlist;
395 unsigned int flags; /* channel flags */
396 unsigned int range_type; /* lookup in kernel */
397 unsigned int settling_time_0;
398 unsigned int unused[9];
401 struct comedi_devinfo_struct {
402 unsigned int version_code;
403 unsigned int n_subdevs;
404 char driver_name[COMEDI_NAMELEN];
405 char board_name[COMEDI_NAMELEN];
411 struct comedi_devconfig_struct {
412 char board_name[COMEDI_NAMELEN];
413 int options[COMEDI_NDEVCONFOPTS];
416 struct comedi_bufconfig_struct {
417 unsigned int subdevice;
420 unsigned int maximum_size;
423 unsigned int unused[4];
426 struct comedi_bufinfo_struct {
427 unsigned int subdevice;
428 unsigned int bytes_read;
430 unsigned int buf_write_ptr;
431 unsigned int buf_read_ptr;
432 unsigned int buf_write_count;
433 unsigned int buf_read_count;
435 unsigned int bytes_written;
437 unsigned int unused[4];
442 #define __RANGE(a,b) ((((a)&0xffff)<<16)|((b)&0xffff))
444 #define RANGE_OFFSET(a) (((a)>>16)&0xffff)
445 #define RANGE_LENGTH(b) ((b)&0xffff)
447 #define RF_UNIT(flags) ((flags)&0xff)
448 #define RF_EXTERNAL (1<<8)
454 #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff)
457 /* only relevant to kernel modules. */
459 #define COMEDI_CB_EOS 1 /* end of scan */
460 #define COMEDI_CB_EOA 2 /* end of acquisition */
461 #define COMEDI_CB_BLOCK 4 /* DEPRECATED: convenient block size */
462 #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */
463 #define COMEDI_CB_ERROR 16 /* card error during acquisition */
464 #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */
466 /**********************************************************/
467 /* everything after this line is ALPHA */
468 /**********************************************************/
471 8254 specific configuration.
473 It supports two config commands:
475 0 ID: INSN_CONFIG_SET_COUNTER_MODE
477 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
479 I8254_BCD, I8254_BINARY
481 0 ID: INSN_CONFIG_8254_READ_STATUS
482 1 <-- Status byte returned here.
490 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
491 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
492 I8254_MODE2 = (2 << 1), /* Rate generator */
493 I8254_MODE3 = (3 << 1), /* Square wave mode */
494 I8254_MODE4 = (4 << 1), /* Software triggered strobe */
495 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
496 I8254_BCD = 1, /* use binary-coded decimal instead of binary (pretty useless) */
500 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) {
501 if (pfi_channel < 10)
502 return 0x1 + pfi_channel;
504 return 0xb + pfi_channel;
505 } static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) {
506 if (rtsi_channel < 7)
507 return 0xb + rtsi_channel;
511 /* mode bits for NI general-purpose counters, set with INSN_CONFIG_SET_COUNTER_MODE */
512 #define NI_GPCT_COUNTING_MODE_SHIFT 16
513 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
514 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
515 enum ni_gpct_mode_bits {
516 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
517 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
518 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
519 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
520 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
521 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
522 NI_GPCT_STOP_MODE_MASK = 0x60,
523 NI_GPCT_STOP_ON_GATE_BITS = 0x00,
524 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
525 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
526 NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
527 NI_GPCT_OUTPUT_MODE_MASK = 0x300,
528 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
529 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
530 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
531 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
532 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
533 NI_GPCT_DISARM_AT_TC_BITS = 0x400,
534 NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
535 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
536 NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
537 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
538 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
539 NI_GPCT_COUNTING_MODE_NORMAL_BITS =
540 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
541 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
542 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
543 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
544 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
545 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
546 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
547 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
548 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
549 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
550 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
551 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
552 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
553 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
554 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
555 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
556 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
557 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
558 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
559 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
560 NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
561 NI_GPCT_COUNTING_DIRECTION_MASK =
562 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
563 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
564 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
565 NI_GPCT_COUNTING_DIRECTION_UP_BITS =
566 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
567 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
568 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
569 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
570 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
571 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
572 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
573 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
574 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
575 NI_GPCT_OR_GATE_BIT = 0x10000000,
576 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
579 /* Bits for setting a clock source with
580 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
581 enum ni_gpct_clock_source_bits {
582 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
583 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
584 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
585 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
586 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
587 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
588 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
589 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, /* NI 660x-specific */
590 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
591 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
592 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
593 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
594 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
595 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */
596 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
597 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
599 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) { /* NI 660x-specific */
602 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) {
605 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) { /* no pfi on NI 660x */
609 /* Possibilities for setting a gate source with
610 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
611 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
612 enum ni_gpct_gate_select {
614 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
615 NI_GPCT_AI_START2_GATE_SELECT = 0x12,
616 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
617 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
618 NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
619 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
620 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
621 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
622 /* more gates for 660x */
623 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
624 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
625 /* more gates for 660x "second gate" */
626 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
627 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
628 /* m-series "second gate" sources are unknown,
629 we should add them here with an offset of 0x300 when known. */
630 NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
632 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) {
635 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) {
636 return NI_USUAL_RTSI_SELECT(n);
638 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) {
639 return NI_USUAL_PFI_SELECT(n);
641 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) {
645 /* Possibilities for setting a source with
646 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
647 enum ni_gpct_other_index {
648 NI_GPCT_SOURCE_ENCODER_A,
649 NI_GPCT_SOURCE_ENCODER_B,
650 NI_GPCT_SOURCE_ENCODER_Z
652 enum ni_gpct_other_select {
654 // Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT
655 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
657 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) {
658 return NI_USUAL_PFI_SELECT(n);
661 /* start sources for ni general-purpose counters for use with
663 enum ni_gpct_arm_source {
664 NI_GPCT_ARM_IMMEDIATE = 0x0,
665 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and the adjacent paired counter simultaneously */
666 /* NI doesn't document bits for selecting hardware arm triggers. If
667 the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least significant
668 bits (3 bits for 660x or 5 bits for m-series) through to the hardware.
669 This will at least allow someone to figure out what the bits do later. */
670 NI_GPCT_ARM_UNKNOWN = 0x1000,
673 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
674 enum ni_gpct_filter_select {
675 NI_GPCT_FILTER_OFF = 0x0,
676 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
677 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
678 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
679 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
680 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
681 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
684 /* PFI digital filtering options for ni m-series for use with INSN_CONFIG_FILTER. */
685 enum ni_pfi_filter_select {
686 NI_PFI_FILTER_OFF = 0x0,
687 NI_PFI_FILTER_125ns = 0x1,
688 NI_PFI_FILTER_6425ns = 0x2,
689 NI_PFI_FILTER_2550us = 0x3
692 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
693 enum ni_mio_clock_source {
694 NI_MIO_INTERNAL_CLOCK = 0,
695 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() */
696 /* the NI_MIO_PLL_* sources are m-series only */
697 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
698 NI_MIO_PLL_PXI10_CLOCK = 3,
699 NI_MIO_PLL_RTSI0_CLOCK = 4
701 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) {
702 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
705 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
706 The numbers assigned are not arbitrary, they correspond to the bits required
707 to program the board. */
708 enum ni_rtsi_routing {
709 NI_RTSI_OUTPUT_ADR_START1 = 0,
710 NI_RTSI_OUTPUT_ADR_START2 = 1,
711 NI_RTSI_OUTPUT_SCLKG = 2,
712 NI_RTSI_OUTPUT_DACUPDN = 3,
713 NI_RTSI_OUTPUT_DA_START1 = 4,
714 NI_RTSI_OUTPUT_G_SRC0 = 5,
715 NI_RTSI_OUTPUT_G_GATE0 = 6,
716 NI_RTSI_OUTPUT_RGOUT0 = 7,
717 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
718 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock on line 7 */
720 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) {
721 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
724 /* Signals which can be routed to an NI PFI pin on an m-series board
725 with INSN_CONFIG_SET_ROUTING. These numbers are also returned
726 by INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though
727 their routing cannot be changed. The numbers assigned are
728 not arbitrary, they correspond to the bits required
729 to program the board. */
730 enum ni_pfi_routing {
731 NI_PFI_OUTPUT_PFI_DEFAULT = 0,
732 NI_PFI_OUTPUT_AI_START1 = 1,
733 NI_PFI_OUTPUT_AI_START2 = 2,
734 NI_PFI_OUTPUT_AI_CONVERT = 3,
735 NI_PFI_OUTPUT_G_SRC1 = 4,
736 NI_PFI_OUTPUT_G_GATE1 = 5,
737 NI_PFI_OUTPUT_AO_UPDATE_N = 6,
738 NI_PFI_OUTPUT_AO_START1 = 7,
739 NI_PFI_OUTPUT_AI_START_PULSE = 8,
740 NI_PFI_OUTPUT_G_SRC0 = 9,
741 NI_PFI_OUTPUT_G_GATE0 = 10,
742 NI_PFI_OUTPUT_EXT_STROBE = 11,
743 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
744 NI_PFI_OUTPUT_GOUT0 = 13,
745 NI_PFI_OUTPUT_GOUT1 = 14,
746 NI_PFI_OUTPUT_FREQ_OUT = 15,
747 NI_PFI_OUTPUT_PFI_DO = 16,
748 NI_PFI_OUTPUT_I_ATRIG = 17,
749 NI_PFI_OUTPUT_RTSI0 = 18,
750 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
751 NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
752 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
753 NI_PFI_OUTPUT_CDI_SAMPLE = 29,
754 NI_PFI_OUTPUT_CDO_UPDATE = 30
756 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) {
757 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
760 /* Signals which can be routed to output on a NI PFI pin on a 660x board
761 with INSN_CONFIG_SET_ROUTING. The numbers assigned are
762 not arbitrary, they correspond to the bits required
763 to program the board. Lines 0 to 7 can only be set to
764 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
765 NI_660X_PFI_OUTPUT_COUNTER. */
766 enum ni_660x_pfi_routing {
767 NI_660X_PFI_OUTPUT_COUNTER = 1, // counter
768 NI_660X_PFI_OUTPUT_DIO = 2, // static digital output
771 /* NI External Trigger lines. These values are not arbitrary, but are related to
772 the bits required to program the board (offset by 1 for historical reasons). */
773 static inline unsigned NI_EXT_PFI(unsigned pfi_channel) {
774 return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
776 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) {
777 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
780 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
781 enum comedi_counter_status_flags {
782 COMEDI_COUNTER_ARMED = 0x1,
783 COMEDI_COUNTER_COUNTING = 0x2,
784 COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
787 /* Clock sources for CDIO subdevice on NI m-series boards.
788 Used as the scan_begin_arg for a comedi_command. These
789 sources may also be bitwise-or'd with CR_INVERT to change polarity. */
790 enum ni_m_series_cdio_scan_begin_src {
791 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
792 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
793 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
794 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
795 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
796 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
797 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
798 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
799 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
800 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
802 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
803 return NI_USUAL_PFI_SELECT(pfi_channel);
805 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned
807 return NI_USUAL_RTSI_SELECT(rtsi_channel);
810 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command
811 on NI boards. These scan begin sources can also be bitwise-or'd with
812 CR_INVERT to change polarity. */
813 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
814 return NI_USUAL_PFI_SELECT(pfi_channel);
816 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) {
817 return NI_USUAL_RTSI_SELECT(rtsi_channel);
820 /* Bits for setting a clock source with
821 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
822 enum ni_freq_out_clock_source_bits {
823 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, // 10 MHz
824 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC // 100 KHz
827 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
828 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
829 enum amplc_dio_clock_source {
830 AMPLC_DIO_CLK_CLKN, /* per channel external clock
831 input/output pin (pin is only an
832 input when clock source set to this
833 value, otherwise it is an output) */
834 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */
835 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */
836 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */
837 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */
838 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
839 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
840 (for channel 0, preceding counter
841 channel is channel 2 on preceding
842 counter subdevice, for first counter
843 subdevice, preceding counter
844 subdevice is the last counter
846 AMPLC_DIO_CLK_EXT /* per chip external input pin */
849 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
850 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
851 enum amplc_dio_gate_source {
852 AMPLC_DIO_GAT_VCC, /* internal high logic level */
853 AMPLC_DIO_GAT_GND, /* internal low logic level */
854 AMPLC_DIO_GAT_GATN, /* per channel external gate input */
855 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel
856 minus 2 (for channels 0 or 1,
857 channel minus 2 is channel 1 or 2 on
858 the preceding counter subdevice, for
859 the first counter subdevice the
860 preceding counter subdevice is the
861 last counter subdevice) */
862 AMPLC_DIO_GAT_RESERVED4,
863 AMPLC_DIO_GAT_RESERVED5,
864 AMPLC_DIO_GAT_RESERVED6,
865 AMPLC_DIO_GAT_RESERVED7
872 #endif /* _COMEDI_H */