comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 264         comedi_insn *insn,lsampl_t *data);
 265 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 266         comedi_insn *insn,lsampl_t *data);
 267 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 268         comedi_insn *insn,lsampl_t *data);
 269 static int ni_gpct_cmd(comedi_device *dev,comedi_subdevice *s);
 270 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 271 static int ni_gpct_cancel(comedi_device *dev,comedi_subdevice *s);
 272
 273 static int init_cs5529(comedi_device *dev);
 274 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 275 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 276 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 277 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 278
 279 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 280         comedi_insn *insn,lsampl_t *data);
 281 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 282         comedi_insn *insn, lsampl_t *data);
 283
 284 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 285
 286 enum aimodes
 287 {
 288         AIMODE_NONE = 0,
 289         AIMODE_HALF_FULL = 1,
 290         AIMODE_SCAN = 2,
 291         AIMODE_SAMPLE = 3,
 292 };
 293
 294 #define SERIAL_DISABLED         0
 295 #define SERIAL_600NS            600
 296 #define SERIAL_1_2US            1200
 297 #define SERIAL_10US                     10000
 298
 299 static const int num_adc_stages_611x = 3;
 300
 301 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 302         unsigned ai_mite_status, unsigned gpct0_mite_status);
 303 static void handle_b_interrupt(comedi_device *dev, unsigned short status,
 304         unsigned ao_mite_status, unsigned gpct1_mite_status);
 305 static void get_last_sample_611x( comedi_device *dev );
 306 static void get_last_sample_6143( comedi_device *dev );
 307 #ifdef PCIDMA
 308 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 309 static int ni_ai_drain_dma(comedi_device *dev );
 310
 311 /* DMA channel setup */
 312
 313 // negative channel means no channel
 314 static inline void ni_set_ai_dma_channel(comedi_device *dev, int channel)
 315 {
 316         unsigned long flags;
 317
 318         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 319         devpriv->ai_ao_select_reg &= ~AI_DMA_Select_Mask;
 320         if(channel >= 0)
 321         {
 322                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 323         }
 324         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 325         mmiowb();
 326         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 327 }
 328
 329 // negative channel means no channel
 330 static inline void ni_set_ao_dma_channel(comedi_device *dev, int channel)
 331 {
 332         unsigned long flags;
 333
 334         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 335         devpriv->ai_ao_select_reg &= ~AO_DMA_Select_Mask;
 336         if(channel >= 0)
 337         {
 338                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 339         }
 340         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 341         mmiowb();
 342         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 343 }
 344
 345 // negative mite_channel means no channel
 346 static inline void ni_set_gpct_dma_channel(comedi_device *dev, unsigned gpct_index, int mite_channel)
 347 {
 348         unsigned long flags;
 349
 350         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 351         devpriv->g0_g1_select_reg &= ~GPCT_DMA_Select_Mask(gpct_index);
 352         if(mite_channel >= 0)
 353         {
 354                 devpriv->g0_g1_select_reg |= GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 355         }
 356         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 357         mmiowb();
 358         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 359 }
 360
 361 static int ni_request_ai_mite_channel(comedi_device *dev)
 362 {
 363         unsigned long flags;
 364
 365         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 366         BUG_ON(devpriv->ai_mite_chan);
 367         devpriv->ai_mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 368         if(devpriv->ai_mite_chan == NULL)
 369         {
 370                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 371                 comedi_error(dev, "failed to reserve mite dma channel for analog input.");
 372                 return -EBUSY;
 373         }
 374         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 375         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 376         return 0;
 377 }
 378
 379 static int ni_request_ao_mite_channel(comedi_device *dev)
 380 {
 381         unsigned long flags;
 382
 383         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 384         BUG_ON(devpriv->ao_mite_chan);
 385         devpriv->ao_mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 386         if(devpriv->ao_mite_chan == NULL)
 387         {
 388                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 389                 comedi_error(dev, "failed to reserve mite dma channel for analog outut.");
 390                 return -EBUSY;
 391         }
 392         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 393         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 394         return 0;
 395 }
 396
 397 static int ni_request_gpct_mite_channel(comedi_device *dev, unsigned gpct_index)
 398 {
 399         unsigned long flags;
 400
 401         BUG_ON(gpct_index >= NUM_GPCT);
 402         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 403         BUG_ON(devpriv->gpct_mite_chan[gpct_index]);
 404         devpriv->gpct_mite_chan[gpct_index] = mite_request_channel(devpriv->mite, devpriv->gpct_mite_ring[gpct_index]);
 405         if(devpriv->gpct_mite_chan[gpct_index] == NULL)
 406         {
 407                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 408                 comedi_error(dev, "failed to reserve mite dma channel for counter.");
 409                 return -EBUSY;
 410         }
 411         ni_set_gpct_dma_channel(dev, gpct_index, devpriv->gpct_mite_chan[gpct_index]->channel);
 412         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 413         return 0;
 414 }
 415
 416 #endif  // PCIDMA
 417
 418 static void ni_release_ai_mite_channel(comedi_device *dev)
 419 {
 420 #ifdef PCIDMA
 421         unsigned long flags;
 422
 423         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 424         if(devpriv->ai_mite_chan)
 425         {
 426                 ni_set_ai_dma_channel(dev, -1);
 427                 mite_dma_disarm(devpriv->ai_mite_chan);
 428                 mite_dma_reset(devpriv->ai_mite_chan);
 429                 mite_release_channel(devpriv->ai_mite_chan);
 430                 devpriv->ai_mite_chan = NULL;
 431         }
 432         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 433 #endif  // PCIDMA
 434 }
 435
 436 static void ni_release_ao_mite_channel(comedi_device *dev)
 437 {
 438 #ifdef PCIDMA
 439         unsigned long flags;
 440
 441         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 442         if(devpriv->ao_mite_chan)
 443         {
 444                 ni_set_ao_dma_channel(dev, -1);
 445                 mite_dma_disarm(devpriv->ao_mite_chan);
 446                 mite_dma_reset(devpriv->ao_mite_chan);
 447                 mite_release_channel(devpriv->ao_mite_chan);
 448                 devpriv->ao_mite_chan = NULL;
 449         }
 450         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 451 #endif  // PCIDMA
 452 }
 453
 454 void ni_release_gpct_mite_channel(comedi_device *dev, unsigned gpct_index)
 455 {
 456 #ifdef PCIDMA
 457         unsigned long flags;
 458
 459         BUG_ON(gpct_index >= NUM_GPCT);
 460         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 461         if(devpriv->gpct_mite_chan[gpct_index])
 462         {
 463                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 464                 mite_dma_disarm(devpriv->gpct_mite_chan[gpct_index]);
 465                 mite_dma_reset(devpriv->gpct_mite_chan[gpct_index]);
 466                 mite_release_channel(devpriv->gpct_mite_chan[gpct_index]);
 467                 devpriv->gpct_mite_chan[gpct_index] = NULL;
 468         }
 469         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 470 #endif  // PCIDMA
 471 }
 472
 473 static void ni_clear_ai_fifo(comedi_device *dev){
 474         if(boardtype.reg_type == ni_reg_6143){
 475                 // Flush the 6143 data FIFO
 476                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 477                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 478                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 479         }else {
 480                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 481                 if(boardtype.reg_type == ni_reg_625x)
 482                 {
 483                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 484                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 485 #if 0
 486                 /* the NI example code does 3 convert pulses for 625x boards,
 487                 but that appears to be wrong in practice. */
 488                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 489                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 490                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 491 #endif
 492                 }
 493         }
 494 }
 495
 496 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 497 {
 498         devpriv->stc_writew(dev, data >> 16, reg);
 499         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 500 }
 501
 502 static uint32_t win_in2(comedi_device *dev, int reg)
 503 {
 504         uint32_t bits;
 505         bits = devpriv->stc_readw(dev, reg) << 16;
 506         bits |= devpriv->stc_readw(dev, reg + 1);
 507         return bits;
 508 }
 509
 510 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 511 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 512 {
 513         unsigned long flags;
 514
 515         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 516         ni_writew(addr,AO_Window_Address_611x);
 517         ni_writew(data,AO_Window_Data_611x);
 518         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 519 }
 520
 521 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 522 {
 523         unsigned long flags;
 524
 525         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 526         ni_writew(addr,AO_Window_Address_611x);
 527         ni_writel(data,AO_Window_Data_611x);
 528         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 529 }
 530
 531 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 532 {
 533         unsigned long flags;
 534         unsigned short data;
 535
 536         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 537         ni_writew(addr, AO_Window_Address_611x);
 538         data = ni_readw(AO_Window_Data_611x);
 539         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 540         return data;
 541 }
 542
 543 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 544 * share registers (such as Interrupt_A_Register) without interfering with
 545 * each other.
 546 *
 547 * NOTE: the switch/case statements are optimized out for a constant argument
 548 * so this is actually quite fast---  If you must wrap another function around this
 549 * make it inline to avoid a large speed penalty.
 550 *
 551 * value should only be 1 or 0.
 552 */
 553 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 554 {
 555         unsigned long flags;
 556
 557         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 558         switch (reg){
 559                 case Interrupt_A_Enable_Register:
 560                         if(value)
 561                                 devpriv->int_a_enable_reg |= bits;
 562                         else
 563                                 devpriv->int_a_enable_reg &= ~bits;
 564                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 565                         break;
 566                 case Interrupt_B_Enable_Register:
 567                         if(value)
 568                                 devpriv->int_b_enable_reg |= bits;
 569                         else
 570                                 devpriv->int_b_enable_reg &= ~bits;
 571                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 572                         break;
 573                 case IO_Bidirection_Pin_Register:
 574                         if(value)
 575                                 devpriv->io_bidirection_pin_reg |= bits;
 576                         else
 577                                 devpriv->io_bidirection_pin_reg &= ~bits;
 578                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 579                         break;
 580                 default:
 581                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 582                         rt_printk("reg is %d\n",reg);
 583                         break;
 584         }
 585         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags );
 586 }
 587
 588
 589 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 590 {
 591         comedi_device *dev=d;
 592         unsigned short a_status;
 593         unsigned short b_status;
 594         unsigned int ai_mite_status = 0;
 595         unsigned int ao_mite_status = 0;
 596         unsigned gpct0_mite_status = 0;
 597         unsigned gpct1_mite_status = 0;
 598         unsigned long flags;
 599         struct mite_struct *mite = devpriv->mite;
 600
 601         if(dev->attached == 0) return IRQ_NONE;
 602         smp_mb();       // make sure dev->attached is checked before handler does anything else.
 603
 604         // lock to avoid race with comedi_poll
 605         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 606         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 607         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 608         if(mite)
 609         {
 610                 unsigned long flags_too;
 611
 612                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 613                 if(devpriv->ai_mite_chan)
 614                         ai_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ai_mite_chan->channel));
 615                 if(devpriv->ao_mite_chan)
 616                         ao_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ao_mite_chan->channel));
 617                 if(devpriv->gpct_mite_chan[0])
 618                         gpct0_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->gpct_mite_chan[0]->channel));
 619                 if(devpriv->gpct_mite_chan[1])
 620                         gpct1_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->gpct_mite_chan[1]->channel));
 621                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 622         }
 623         if((a_status & Interrupt_A_St) || ((ai_mite_status | gpct0_mite_status) & CHSR_INT))
 624                 handle_a_interrupt(dev, a_status, ai_mite_status, gpct0_mite_status);
 625         if((b_status & Interrupt_B_St) || ((ao_mite_status | gpct1_mite_status) & CHSR_INT))
 626                 handle_b_interrupt(dev, b_status, ao_mite_status, gpct1_mite_status);
 627         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 628         return IRQ_HANDLED;
 629 }
 630
 631 #ifdef PCIDMA
 632 static void ni_sync_ai_dma(comedi_device *dev)
 633 {
 634         comedi_subdevice *s = dev->subdevices + 0;
 635         unsigned long flags;
 636
 637         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 638         if(devpriv->ai_mite_chan)
 639                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 640         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641 }
 642
 643 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 644 {
 645         comedi_subdevice *s = dev->subdevices + 1;
 646
 647         if(devpriv->ao_mite_chan == NULL) return;
 648         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 649
 650         if(mite_sync_output_dma(devpriv->ao_mite_chan, s->async) < 0)
 651         {
 652                 s->async->events |= COMEDI_CB_ERROR;
 653                 return;
 654         }
 655 }
 656
 657 // #define DEBUG_DMA_TIMING
 658 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 659 {
 660         static const int timeout = 10000;
 661         int i;
 662 #ifdef DEBUG_DMA_TIMING
 663         struct timeval start;
 664         do_gettimeofday(&start);
 665 #endif
 666         for(i = 0; i < timeout; i++)
 667         {
 668                 unsigned short b_status;
 669
 670                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 671                 if( b_status & AO_FIFO_Half_Full_St )
 672                         break;
 673                 /* if we poll too often, the pci bus activity seems
 674                  to slow the dma transfer down */
 675                 comedi_udelay(10);
 676         }
 677 #ifdef DEBUG_DMA_TIMING
 678         rt_printk("looped %i times waiting for ao fifo load.\n", i);
 679         struct timeval now;
 680         do_gettimeofday(&now);
 681         unsigned elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 682         rt_printk("total elapsed usec=%i\n", elapsed_usec);
 683         do_gettimeofday(&start);
 684         unsigned b_status;
 685         for(i = 0; i < 100; ++i)
 686         {
 687 //              devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
 688                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 689         }
 690         do_gettimeofday(&now);
 691         elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 692         rt_printk("usec to do 100 word xfers=%i\n", elapsed_usec);
 693 #endif
 694         if( i == timeout )
 695         {
 696                 comedi_error(dev, "timed out waiting for dma load");
 697                 return -EPIPE;
 698         }
 699         return 0;
 700 }
 701
 702 #endif //PCIDMA
 703 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 704 {
 705         if(devpriv->aimode == AIMODE_SCAN)
 706         {
 707 #ifdef PCIDMA
 708                 static const int timeout = 10;
 709                 int i;
 710
 711                 for(i = 0; i < timeout; i++)
 712                 {
 713                         ni_sync_ai_dma(dev);
 714                         if((s->async->events & COMEDI_CB_EOS)) break;
 715                         comedi_udelay(1);
 716                 }
 717 #else
 718                 ni_handle_fifo_dregs(dev);
 719                 s->async->events |= COMEDI_CB_EOS;
 720 #endif
 721         }
 722         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 723         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 724                 shutdown_ai_command( dev );
 725         }
 726 }
 727
 728 static void shutdown_ai_command( comedi_device *dev )
 729 {
 730         comedi_subdevice *s = dev->subdevices + 0;
 731
 732 #ifdef PCIDMA
 733         ni_ai_drain_dma( dev );
 734 #endif
 735         ni_handle_fifo_dregs(dev);
 736         get_last_sample_611x(dev);
 737         get_last_sample_6143(dev);
 738
 739         s->async->events |= COMEDI_CB_EOA;
 740 }
 741
 742 static void handle_gpct_interrupt(comedi_device *dev, struct mite_channel *mite_chan, unsigned short is_terminal_count)
 743 {
 744         unsigned gpct_mite_status;
 745
 746         gpct_mite_status = readl(mite_chan->mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 747         if(gpct_mite_status & CHSR_INT)
 748         {}
 749 }
 750
 751 static void ni_event(comedi_device *dev, comedi_subdevice *s, unsigned events)
 752 {
 753         if(events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
 754         {
 755                 switch(s->type)
 756                 {
 757                 case COMEDI_SUBD_AI:
 758                         ni_ai_reset(dev, s);
 759                         break;
 760                 case COMEDI_SUBD_AO:
 761                         ni_ao_reset(dev, s);
 762                         break;
 763                 default:
 764                         break;
 765                 }
 766         }
 767         comedi_event(dev, s, events);
 768 }
 769
 770 static void ack_a_interrupt(comedi_device *dev, unsigned short a_status)
 771 {
 772         unsigned short ack = 0;
 773
 774         /* test for all uncommon interrupt events at the same time */
 775         if(a_status & AI_SC_TC_St)
 776         {
 777                 ack |= AI_SC_TC_Interrupt_Ack;
 778         }
 779         if(a_status & AI_START1_St)
 780         {
 781                         ack |= AI_START1_Interrupt_Ack;
 782         }
 783         if(a_status & AI_START_St)
 784         {
 785                 ack |= AI_START_Interrupt_Ack;
 786         }
 787         if(a_status & AI_STOP_St)
 788         {
 789                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 790                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack*/;
 791         }
 792         if(a_status & G0_TC_St)
 793         {
 794                 ack |= G0_TC_Interrupt_Ack;
 795         }
 796         if(a_status & G0_Gate_Interrupt_St)
 797         {
 798                 ack |= G0_Gate_Interrupt_Ack;
 799         }
 800         if(ack) devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 801 }
 802
 803 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 804         unsigned ai_mite_status, unsigned gpct0_mite_status)
 805 {
 806         comedi_subdevice *s=dev->subdevices+0;
 807
 808         s->async->events = 0;
 809
 810 #ifdef DEBUG_INTERRUPT
 811         rt_printk("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
 812                 status, ai_mite_status);
 813         ni_mio_print_status_a(status);
 814 #endif
 815         ack_a_interrupt(dev, status);
 816 #ifdef PCIDMA
 817         /* Currently, mite.c requires us to handle LINKC and DONE */
 818         if(ai_mite_status & CHSR_LINKC){
 819                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 820                 ni_sync_ai_dma(dev);
 821         }
 822
 823         if(ai_mite_status & CHSR_DONE){
 824                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 825         }
 826
 827         if(ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 828                 rt_printk("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", ai_mite_status);
 829                 //mite_print_chsr(ai_mite_status);
 830                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 831                 //disable_irq(dev->irq);
 832         }
 833 #endif
 834
 835         /* test for all uncommon interrupt events at the same time */
 836         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 837                 if(status==0xffff){
 838                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 839                         /* we probably aren't even running a command now,
 840                          * so it's a good idea to be careful. */
 841                         if(s->subdev_flags&SDF_RUNNING){
 842                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 843                                 ni_event(dev, s, s->async->events);
 844                         }
 845                         return;
 846                 }
 847                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 848                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 849                                 status);
 850                         ni_mio_print_status_a(status);
 851
 852                         shutdown_ai_command( dev );
 853
 854                         s->async->events |= COMEDI_CB_ERROR;
 855                         if(status & (AI_Overrun_St | AI_Overflow_St))
 856                                 s->async->events |= COMEDI_CB_OVERFLOW;
 857
 858                         ni_event(dev, s, s->async->events);
 859
 860                         return;
 861                 }
 862                 if(status&AI_SC_TC_St){
 863 #ifdef DEBUG_INTERRUPT
 864                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 865 #endif
 866                         if(!devpriv->ai_continuous){
 867                                 shutdown_ai_command(dev);
 868                         }
 869                 }
 870         }
 871 #ifndef PCIDMA
 872         if(status&AI_FIFO_Half_Full_St){
 873                 int i;
 874                 static const int timeout = 10;
 875                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 876                  *fail to get the fifo less than half full, so loop to be sure.*/
 877                 for(i = 0; i < timeout; ++i)
 878                 {
 879                         ni_handle_fifo_half_full(dev);
 880                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 881                                 break;
 882                 }
 883         }
 884 #endif // !PCIDMA
 885
 886         if( (status & AI_STOP_St) ){
 887                 ni_handle_eos(dev, s);
 888         }
 889
 890         if(status & (G0_TC_St | G0_Gate_Interrupt_St))
 891         {
 892                 unsigned long flags;
 893
 894                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 895                 if(devpriv->gpct_mite_chan)
 896                         handle_gpct_interrupt(dev, devpriv->gpct_mite_chan[0], (status & G0_TC_St));
 897                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 898         }
 899
 900         ni_event(dev,s,s->async->events);
 901
 902 #ifdef DEBUG_INTERRUPT
 903         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 904         if(status&Interrupt_A_St){
 905                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 906         }
 907 #endif
 908 }
 909
 910 static void ack_b_interrupt(comedi_device *dev, unsigned short b_status)
 911 {
 912         unsigned short ack = 0;
 913         if(b_status & AO_BC_TC_St)
 914         {
 915                 ack |= AO_BC_TC_Interrupt_Ack;
 916         }
 917         if(b_status & AO_Overrun_St)
 918         {
 919                 ack |= AO_Error_Interrupt_Ack;
 920         }
 921         if(b_status & AO_START_St)
 922         {
 923                 ack |= AO_START_Interrupt_Ack;
 924         }
 925         if(b_status & AO_START1_St)
 926         {
 927                 ack |= AO_START1_Interrupt_Ack;
 928         }
 929         if(b_status & AO_UC_TC_St)
 930         {
 931                 ack |= AO_UC_TC_Interrupt_Ack;
 932         }
 933         if(b_status & AO_UI2_TC_St)
 934         {
 935                 ack |= AO_UI2_TC_Interrupt_Ack;
 936         }
 937         if(b_status & AO_UPDATE_St)
 938         {
 939                 ack |= AO_UPDATE_Interrupt_Ack;
 940         }
 941         if(b_status & G1_Gate_Interrupt_St)
 942         {
 943                 ack |= G1_Gate_Interrupt_Ack;
 944         }
 945         if(b_status & G1_TC_St)
 946         {
 947                 ack |= G1_TC_Interrupt_Ack;
 948         }
 949         if(ack) devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
 950 }
 951
 952 static void handle_b_interrupt(comedi_device *dev, unsigned short b_status,
 953         unsigned ao_mite_status, unsigned gpct1_mite_status)
 954 {
 955         comedi_subdevice *s=dev->subdevices+1;
 956         //unsigned short ack=0;
 957 #ifdef DEBUG_INTERRUPT
 958         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 959                 b_status,ao_mite_status);
 960         ni_mio_print_status_b(b_status);
 961 #endif
 962         ack_b_interrupt(dev, b_status);
 963
 964 #ifdef PCIDMA
 965         /* Currently, mite.c requires us to handle LINKC and DONE */
 966         if(ao_mite_status & CHSR_LINKC){
 967                 mite_handle_b_linkc(devpriv->mite, dev);
 968         }
 969
 970         if(ao_mite_status & CHSR_DONE){
 971                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 972         }
 973
 974         if(ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 975                 rt_printk("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", ao_mite_status);
 976                 //mite_print_chsr(ao_mite_status);
 977                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 978         }
 979 #endif
 980
 981         if(b_status==0xffff)return;
 982         if(b_status&AO_Overrun_St){
 983                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 984                 s->async->events |= COMEDI_CB_OVERFLOW;
 985         }
 986
 987         if(b_status&AO_BC_TC_St){
 988                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 989                 s->async->events |= COMEDI_CB_EOA;
 990         }
 991
 992 #ifndef PCIDMA
 993         if(b_status&AO_FIFO_Request_St){
 994                 int ret;
 995
 996                 ret = ni_ao_fifo_half_empty(dev,s);
 997                 if(!ret){
 998                         rt_printk("ni_mio_common: AO buffer underrun\n");
 999                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1000                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
1001                         s->async->events |= COMEDI_CB_OVERFLOW;
1002                 }
1003         }
1004 #endif
1005
1006         ni_event(dev,s,s->async->events);
1007 }
1008
1009 #ifdef DEBUG_STATUS_A
1010 static char *status_a_strings[]={
1011         "passthru0","fifo","G0_gate","G0_TC",
1012         "stop","start","sc_tc","start1",
1013         "start2","sc_tc_error","overflow","overrun",
1014         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
1015 };
1016
1017 static void ni_mio_print_status_a(int status)
1018 {
1019         int i;
1020
1021         rt_printk("A status:");
1022         for(i=15;i>=0;i--){
1023                 if(status&(1<<i)){
1024                         rt_printk(" %s",status_a_strings[i]);
1025                 }
1026         }
1027         rt_printk("\n");
1028 }
1029 #endif
1030
1031 #ifdef DEBUG_STATUS_B
1032 static char *status_b_strings[]={
1033         "passthru1","fifo","G1_gate","G1_TC",
1034         "UI2_TC","UPDATE","UC_TC","BC_TC",
1035         "start1","overrun","start","bc_tc_error",
1036         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
1037 };
1038
1039 static void ni_mio_print_status_b(int status)
1040 {
1041         int i;
1042
1043         rt_printk("B status:");
1044         for(i=15;i>=0;i--){
1045                 if(status&(1<<i)){
1046                         rt_printk(" %s",status_b_strings[i]);
1047                 }
1048         }
1049         rt_printk("\n");
1050 }
1051 #endif
1052
1053 #ifndef PCIDMA
1054
1055 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
1056 {
1057         comedi_async *async = s->async;
1058         comedi_cmd *cmd = &async->cmd;
1059         int chan;
1060         int i;
1061         sampl_t d;
1062         u32 packed_data;
1063         int range;
1064         int err = 1;
1065
1066         chan = async->cur_chan;
1067         for(i=0;i<n;i++){
1068                 err &= comedi_buf_get(async, &d);
1069                 if(err == 0) break;
1070
1071                 range = CR_RANGE(cmd->chanlist[chan]);
1072
1073                 if(boardtype.reg_type & ni_reg_6xxx_mask)
1074                 {
1075                         packed_data = d & 0xffff;
1076                         /* 6711 only has 16 bit wide ao fifo */
1077                         if(boardtype.reg_type != ni_reg_6711)
1078                         {
1079                                 err &= comedi_buf_get(async, &d);
1080                                 if(err == 0) break;
1081                                 chan++;
1082                                 i++;
1083                                 packed_data |= ( d << 16 ) & 0xffff0000;
1084                         }
1085                         ni_writel( packed_data, DAC_FIFO_Data_611x );
1086                 }else{
1087                         ni_writew(d, DAC_FIFO_Data);
1088                 }
1089                 chan++;
1090                 chan %= cmd->chanlist_len;
1091         }
1092         async->cur_chan = chan;
1093         if(err==0){
1094                 async->events |= COMEDI_CB_OVERFLOW;
1095         }
1096 }
1097
1098 /*
1099  *  There's a small problem if the FIFO gets really low and we
1100  *  don't have the data to fill it.  Basically, if after we fill
1101  *  the FIFO with all the data available, the FIFO is _still_
1102  *  less than half full, we never clear the interrupt.  If the
1103  *  IRQ is in edge mode, we never get another interrupt, because
1104  *  this one wasn't cleared.  If in level mode, we get flooded
1105  *  with interrupts that we can't fulfill, because nothing ever
1106  *  gets put into the buffer.
1107  *
1108  *  This kind of situation is recoverable, but it is easier to
1109  *  just pretend we had a FIFO underrun, since there is a good
1110  *  chance it will happen anyway.  This is _not_ the case for
1111  *  RT code, as RT code might purposely be running close to the
1112  *  metal.  Needs to be fixed eventually.
1113  */
1114 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
1115 {
1116         int n;
1117
1118         n = comedi_buf_read_n_available(s->async);
1119         if(n==0){
1120                 s->async->events |= COMEDI_CB_OVERFLOW;
1121                 return 0;
1122         }
1123
1124         n /= sizeof(sampl_t);
1125         if(n > boardtype.ao_fifo_depth / 2)
1126                 n = boardtype.ao_fifo_depth / 2;
1127
1128         ni_ao_fifo_load(dev,s,n);
1129
1130         s->async->events |= COMEDI_CB_BLOCK;
1131
1132         return 1;
1133 }
1134
1135 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
1136 {
1137         int n;
1138
1139         /* reset fifo */
1140         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
1141         if(boardtype.reg_type & ni_reg_6xxx_mask)
1142                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1143
1144         /* load some data */
1145         n = comedi_buf_read_n_available(s->async);
1146         if(n==0)return 0;
1147
1148         n /= sizeof(sampl_t);
1149         if(n > boardtype.ao_fifo_depth)
1150                 n = boardtype.ao_fifo_depth;
1151
1152         ni_ao_fifo_load(dev,s,n);
1153
1154         return n;
1155 }
1156
1157 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
1158         int n)
1159 {
1160         comedi_async *async = s->async;
1161         int i;
1162
1163         if(boardtype.reg_type == ni_reg_611x){
1164                 sampl_t data[2];
1165                 u32 dl;
1166
1167                 for( i = 0; i < n / 2; i++ ){
1168                         dl=ni_readl(ADC_FIFO_Data_611x);
1169                         /* This may get the hi/lo data in the wrong order */
1170                         data[0] = (dl>>16) & 0xffff;
1171                         data[1] = dl & 0xffff;
1172                         cfc_write_array_to_buffer(s, data, sizeof(data));
1173                 }
1174                 /* Check if there's a single sample stuck in the FIFO */
1175                 if( n % 2){
1176                         dl=ni_readl(ADC_FIFO_Data_611x);
1177                         data[0] = dl & 0xffff;
1178                         cfc_write_to_buffer(s, data[0]);
1179                 }
1180         } else if(boardtype.reg_type == ni_reg_6143){
1181                 sampl_t data[2];
1182                 u32     dl;
1183
1184                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1185                 for(i = 0; i < n / 2; i++){
1186                         dl = ni_readl(AIFIFO_Data_6143);
1187
1188                         data[0] = (dl >> 16) & 0xffff;
1189                         data[1] = dl & 0xffff;
1190                         cfc_write_array_to_buffer(s, data, sizeof(data));
1191                 }
1192                 if(n % 2){
1193                         /* Assume there is a single sample stuck in the FIFO */
1194                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1195                         dl = ni_readl(AIFIFO_Data_6143);
1196                         data[0] = (dl >> 16) & 0xffff;
1197                         cfc_write_to_buffer(s, data[0]);
1198                 }
1199         } else{
1200                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1201                 {
1202                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1203                         async->events |= COMEDI_CB_ERROR;
1204                         return;
1205                 }
1206                 for(i = 0; i < n; i++){
1207                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1208                 }
1209                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1210                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1211         }
1212 }
1213
1214 static void ni_handle_fifo_half_full(comedi_device *dev)
1215 {
1216         int n;
1217         comedi_subdevice *s=dev->subdevices+0;
1218
1219         n=boardtype.ai_fifo_depth/2;
1220
1221         ni_ai_fifo_read(dev,s,n);
1222 }
1223 #endif
1224
1225 #ifdef PCIDMA
1226 static int ni_ai_drain_dma(comedi_device *dev )
1227 {
1228         int i;
1229         static const int timeout = 10000;
1230
1231         if(devpriv->ai_mite_chan == NULL) return 0;
1232         for( i = 0; i < timeout; i++ )
1233         {
1234                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1235                         mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
1236                         break;
1237                 comedi_udelay(2);
1238         }
1239         if(i == timeout)
1240         {
1241                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1242                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1243                         mite_bytes_in_transit(devpriv->ai_mite_chan), devpriv->stc_readw(dev, AI_Status_1_Register));
1244                 return -1;
1245         }
1246
1247         ni_sync_ai_dma(dev);
1248
1249         return 0;
1250 }
1251 #endif
1252 /*
1253    Empties the AI fifo
1254 */
1255 static void ni_handle_fifo_dregs(comedi_device *dev)
1256 {
1257         comedi_subdevice *s=dev->subdevices+0;
1258         sampl_t data[2];
1259         u32 dl;
1260         short fifo_empty;
1261         int i;
1262
1263         if(boardtype.reg_type == ni_reg_611x){
1264                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1265                         dl=ni_readl(ADC_FIFO_Data_611x);
1266
1267                         /* This may get the hi/lo data in the wrong order */
1268                         data[0] = (dl>>16);
1269                         data[1] = (dl&0xffff);
1270                         cfc_write_array_to_buffer(s, data, sizeof(data));
1271                 }
1272         }else if(boardtype.reg_type == ni_reg_6143){
1273                 i = 0;
1274                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1275                         dl = ni_readl(AIFIFO_Data_6143);
1276
1277                         /* This may get the hi/lo data in the wrong order */
1278                         data[0] = (dl >> 16);
1279                         data[1] = (dl & 0xffff);
1280                         cfc_write_array_to_buffer(s, data, sizeof(data));
1281                         i += 2;
1282                 }
1283                 // Check if stranded sample is present
1284                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1285                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1286                         dl = ni_readl(AIFIFO_Data_6143);
1287                         data[0] = (dl >> 16) & 0xffff;
1288                         cfc_write_to_buffer(s, data[0]);
1289                 }
1290
1291         }else{
1292                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1293                 while(fifo_empty == 0)
1294                 {
1295                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1296                         {
1297                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1298                                 if(fifo_empty) break;
1299                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1300                         }
1301                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1302                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1303                 }
1304         }
1305 }
1306
1307 static void get_last_sample_611x( comedi_device *dev )
1308 {
1309         comedi_subdevice *s=dev->subdevices+0;
1310         sampl_t data;
1311         u32 dl;
1312
1313         if(boardtype.reg_type != ni_reg_611x) return;
1314
1315         /* Check if there's a single sample stuck in the FIFO */
1316         if(ni_readb(XXX_Status)&0x80){
1317                 dl=ni_readl(ADC_FIFO_Data_611x);
1318                 data = (dl&0xffff);
1319                 cfc_write_to_buffer(s, data);
1320         }
1321 }
1322
1323 static void get_last_sample_6143(comedi_device* dev)
1324 {
1325         comedi_subdevice*       s = dev->subdevices + 0;
1326         sampl_t                 data;
1327         u32                     dl;
1328
1329         if(boardtype.reg_type != ni_reg_6143) return;
1330
1331         /* Check if there's a single sample stuck in the FIFO */
1332         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1333                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1334                 dl = ni_readl(AIFIFO_Data_6143);
1335
1336                 /* This may get the hi/lo data in the wrong order */
1337                 data = (dl >> 16) & 0xffff;
1338                 cfc_write_to_buffer(s, data);
1339         }
1340 }
1341
1342 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1343         void *data, unsigned int num_bytes, unsigned int chan_index )
1344 {
1345         comedi_async *async = s->async;
1346         unsigned int i;
1347         unsigned int length = num_bytes / bytes_per_sample(s);
1348         sampl_t *array = data;
1349         lsampl_t *larray = data;
1350         for(i = 0; i < length; i++)
1351         {
1352 #ifdef PCIDMA
1353                 if(s->subdev_flags & SDF_LSAMPL)
1354                         larray[i] = le32_to_cpu(larray[i]);
1355                 else
1356                         array[i] = le16_to_cpu(array[i]);
1357 #endif
1358                 if(s->subdev_flags & SDF_LSAMPL)
1359                         larray[i] += devpriv->ai_offset[chan_index];
1360                 else
1361                         array[i] += devpriv->ai_offset[chan_index];
1362                 chan_index++;
1363                 chan_index %= async->cmd.chanlist_len;
1364         }
1365 }
1366
1367 #ifdef PCIDMA
1368
1369 static int ni_ai_setup_MITE_dma(comedi_device *dev)
1370 {
1371         comedi_subdevice *s = dev->subdevices + 0;
1372         int retval;
1373
1374         retval = ni_request_ai_mite_channel(dev);
1375         if(retval) return retval;
1376 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1377
1378         /* write alloc the entire buffer */
1379         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1380
1381         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
1382         switch(boardtype.reg_type)
1383         {
1384         case ni_reg_611x:
1385         case ni_reg_6143:
1386                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1387                 break;
1388         case ni_reg_628x:
1389                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1390                 break;
1391         default:
1392                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1393                 break;
1394         };
1395         /*start the MITE*/
1396         mite_dma_arm(devpriv->ai_mite_chan);
1397         return 0;
1398 }
1399
1400 static int ni_ao_setup_MITE_dma(comedi_device *dev)
1401 {
1402         comedi_subdevice *s = dev->subdevices + 1;
1403         int retval;
1404
1405         retval = ni_request_ao_mite_channel(dev);
1406         if(retval) return retval;
1407         //rt_printk("comedi_debug: using mite channel %i for ao.\n", devpriv->ao_mite_chan->channel);
1408
1409         /* read alloc the entire buffer */
1410         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1411
1412         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
1413         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1414         {
1415                 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1416         }else
1417         {
1418                 /* doing 32 instead of 16 bit wide transfers from memory
1419                  makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1420                 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1421         }
1422         /*start the MITE*/
1423         mite_dma_arm(devpriv->ao_mite_chan);
1424         return 0;
1425 }
1426
1427 #endif // PCIDMA
1428
1429 /*
1430    used for both cancel ioctl and board initialization
1431
1432    this is pretty harsh for a cancel, but it works...
1433  */
1434
1435 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1436 {
1437         ni_release_ai_mite_channel(dev);
1438         /* ai configuration */
1439         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1440
1441         ni_set_bits(dev, Interrupt_A_Enable_Register,
1442                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1443                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1444                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1445                 AI_FIFO_Interrupt_Enable,0);
1446
1447         ni_clear_ai_fifo(dev);
1448
1449         if(boardtype.reg_type != ni_reg_6143)
1450                 ni_writeb(0, Misc_Command);
1451
1452         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1453         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1454                 AI_Mode_1_Register);
1455         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1456         /* generate FIFO interrupts on non-empty */
1457         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1458         if(boardtype.reg_type == ni_reg_611x){
1459                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1460                         AI_SOC_Polarity |
1461                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1462                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1463                         AI_EXTMUX_CLK_Output_Select(0) |
1464                         AI_LOCALMUX_CLK_Output_Select(2) |
1465                         AI_SC_TC_Output_Select(3) |
1466                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High), AI_Output_Control_Register);
1467         }else if(boardtype.reg_type == ni_reg_6143){
1468                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1469                         AI_SOC_Polarity |
1470                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1471                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1472                         AI_EXTMUX_CLK_Output_Select(0) |
1473                         AI_LOCALMUX_CLK_Output_Select(2) |
1474                         AI_SC_TC_Output_Select(3) |
1475                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),AI_Output_Control_Register);
1476         }else{
1477                 unsigned ai_output_control_bits;
1478                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1479                         AI_SOC_Polarity |
1480                         AI_CONVERT_Pulse_Width |
1481                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1482                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1483                         AI_EXTMUX_CLK_Output_Select(0) |
1484                         AI_LOCALMUX_CLK_Output_Select(2) |
1485                         AI_SC_TC_Output_Select(3);
1486                 if(boardtype.reg_type == ni_reg_622x)
1487                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High);
1488                 else
1489                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low);
1490                 devpriv->stc_writew(dev, ai_output_control_bits, AI_Output_Control_Register);
1491         }
1492         /* the following registers should not be changed, because there
1493          * are no backup registers in devpriv.  If you want to change
1494          * any of these, add a backup register and other appropriate code:
1495          *      AI_Mode_1_Register
1496          *      AI_Mode_3_Register
1497          *      AI_Personal_Register
1498          *      AI_Output_Control_Register
1499         */
1500         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1501                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1502                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1503                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1504
1505         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1506
1507         return 0;
1508 }
1509
1510 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1511 {
1512         unsigned long flags = 0;
1513         int count;
1514
1515         // lock to avoid race with interrupt handler
1516         if(in_interrupt() == 0)
1517                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1518 #ifndef PCIDMA
1519         ni_handle_fifo_dregs(dev);
1520 #else
1521         ni_sync_ai_dma(dev);
1522 #endif
1523         count = s->async->buf_write_count - s->async->buf_read_count;
1524         if(in_interrupt() == 0)
1525                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1526
1527         return count;
1528 }
1529
1530
1531 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1532 {
1533         int i,n;
1534         const unsigned int mask = (1 << boardtype.adbits) - 1;
1535         unsigned signbits;
1536         unsigned short d;
1537         unsigned long dl;
1538
1539         ni_load_channelgain_list(dev,1,&insn->chanspec);
1540
1541         ni_clear_ai_fifo(dev);
1542
1543         signbits=devpriv->ai_offset[0];
1544         if(boardtype.reg_type == ni_reg_611x){
1545                 for(n=0; n < num_adc_stages_611x; n++){
1546                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1547                         comedi_udelay(1);
1548                 }
1549                 for(n=0; n<insn->n; n++){
1550                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1551                         /* The 611x has screwy 32-bit FIFOs. */
1552                         d = 0;
1553                         for(i=0; i<NI_TIMEOUT; i++){
1554                                 if(ni_readb(XXX_Status)&0x80)
1555                                 {
1556                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1557                                         break;
1558                                 }
1559                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1560                                 {
1561                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1562                                         break;
1563                                 }
1564                         }
1565                         if(i==NI_TIMEOUT){
1566                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1567                                 return -ETIME;
1568                         }
1569                         d += signbits;
1570                         data[ n ] = d;
1571                 }
1572         }else if(boardtype.reg_type == ni_reg_6143){
1573                 for(n = 0; n < insn->n; n++){
1574                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1575
1576                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1577                         dl = 0;
1578                         for(i = 0; i < NI_TIMEOUT; i++){
1579                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1580                                 {
1581                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1582                                         dl = ni_readl(AIFIFO_Data_6143);
1583                                         break;
1584                                 }
1585                         }
1586                         if(i == NI_TIMEOUT){
1587                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1588                                 return -ETIME;
1589                         }
1590                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1591                 }
1592         }else{
1593                 for(n = 0; n < insn->n; n++){
1594                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1595                         for(i = 0; i < NI_TIMEOUT; i++){
1596                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1597                                         break;
1598                         }
1599                         if(i == NI_TIMEOUT){
1600                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1601                                 return -ETIME;
1602                         }
1603                         if(boardtype.reg_type & ni_reg_m_series_mask)
1604                         {
1605                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1606                         }else
1607                         {
1608                                 d = ni_readw(ADC_FIFO_Data_Register);
1609                                 d += signbits; /* subtle: needs to be short addition */
1610                                 data[n] = d;
1611                         }
1612                 }
1613         }
1614         return insn->n;
1615 }
1616
1617 void ni_prime_channelgain_list(comedi_device *dev)
1618 {
1619         int i;
1620         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1621         for(i = 0; i < NI_TIMEOUT; ++i)
1622         {
1623                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1624                 {
1625                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1626                         return;
1627                 }
1628                 comedi_udelay(1);
1629         }
1630         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1631 }
1632
1633 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1634         unsigned int *list)
1635 {
1636         unsigned int chan, range, aref;
1637         unsigned int i;
1638         unsigned offset;
1639         unsigned int dither;
1640         unsigned range_code;
1641
1642         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1643
1644 //      offset = 1 << (boardtype.adbits - 1);
1645         if((list[0] & CR_ALT_SOURCE))
1646         {
1647                 unsigned bypass_bits;
1648                 chan = CR_CHAN(list[0]);
1649                 range = CR_RANGE(list[0]);
1650                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1651                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1652                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1653                 bypass_bits |= chan;
1654                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1655                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1656                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1657                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1658                 if(dither)
1659                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1660                 // don't use 2's complement encoding
1661                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1662                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1663         }else
1664         {
1665                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1666         }
1667         offset = 0;
1668         for(i = 0; i < n_chan; i++)
1669         {
1670                 unsigned config_bits = 0;
1671                 chan = CR_CHAN(list[i]);
1672                 aref = CR_AREF(list[i]);
1673                 range = CR_RANGE(list[i]);
1674                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1675
1676                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1677                 devpriv->ai_offset[i] = offset;
1678                 switch( aref )
1679                 {
1680                         case AREF_DIFF:
1681                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1682                                 break;
1683                         case AREF_COMMON:
1684                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1685                                 break;
1686                         case AREF_GROUND:
1687                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1688                                 break;
1689                         case AREF_OTHER:
1690                                 break;
1691                 }
1692                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1693                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1694                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1695                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1696                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1697                 // don't use 2's complement encoding
1698                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1699                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1700         }
1701         ni_prime_channelgain_list(dev);
1702 }
1703
1704 /*
1705  * Notes on the 6110 and 6111:
1706  * These boards a slightly different than the rest of the series, since
1707  * they have multiple A/D converters.
1708  * From the driver side, the configuration memory is a
1709  * little different.
1710  * Configuration Memory Low:
1711  *   bits 15-9: same
1712  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1713  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1714  *       1001 gain=0.1 (+/- 50)
1715  *       1010 0.2
1716  *       1011 0.1
1717  *       0001 1
1718  *       0010 2
1719  *       0011 5
1720  *       0100 10
1721  *       0101 20
1722  *       0110 50
1723  * Configuration Memory High:
1724  *   bits 12-14: Channel Type
1725  *       001 for differential
1726  *       000 for calibration
1727  *   bit 11: coupling  (this is not currently handled)
1728  *       1 AC coupling
1729  *       0 DC coupling
1730  *   bits 0-2: channel
1731  *       valid channels are 0-3
1732  */
1733 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1734         unsigned int *list)
1735 {
1736         unsigned int chan,range,aref;
1737         unsigned int i;
1738         unsigned int hi,lo;
1739         unsigned offset;
1740         unsigned int dither;
1741
1742         if(boardtype.reg_type & ni_reg_m_series_mask)
1743         {
1744                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1745                 return;
1746         }
1747         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1748                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1749                         // ready to go.
1750                         return;
1751                 }
1752                 devpriv->changain_state=1;
1753                 devpriv->changain_spec=list[0];
1754         }else{
1755                 devpriv->changain_state=0;
1756         }
1757
1758         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1759
1760         // Set up Calibration mode if required
1761         if(boardtype.reg_type == ni_reg_6143){
1762                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1763                         // Strobe Relay enable bit
1764                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1765                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1766                         devpriv->ai_calib_source_enabled = 1;
1767                         msleep_interruptible(100);      // Allow relays to change
1768                 }
1769                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1770                         // Strobe Relay disable bit
1771                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1772                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1773                         devpriv->ai_calib_source_enabled = 0;
1774                         msleep_interruptible(100);      // Allow relays to change
1775                 }
1776         }
1777
1778         offset=1<<(boardtype.adbits-1);
1779         for(i=0;i<n_chan;i++){
1780                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1781                         chan=devpriv->ai_calib_source;
1782                 }else{
1783                         chan=CR_CHAN(list[i]);
1784                 }
1785                 aref=CR_AREF(list[i]);
1786                 range=CR_RANGE(list[i]);
1787                 dither=((list[i]&CR_ALT_FILTER)!=0);
1788
1789                 /* fix the external/internal range differences */
1790                 range = ni_gainlkup[boardtype.gainlkup][range];
1791                 if(boardtype.reg_type == ni_reg_611x)
1792                         devpriv->ai_offset[i] = offset;
1793                 else
1794                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1795
1796                 hi = 0;
1797                 if( ( list[i] & CR_ALT_SOURCE ) )
1798                 {
1799                         if(boardtype.reg_type == ni_reg_611x)
1800                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1801                 }else
1802                 {
1803                         if(boardtype.reg_type == ni_reg_611x)
1804                                 aref = AREF_DIFF;
1805                         else if(boardtype.reg_type == ni_reg_6143)
1806                                 aref = AREF_OTHER;
1807                         switch( aref )
1808                         {
1809                                 case AREF_DIFF:
1810                                         hi |= AI_DIFFERENTIAL;
1811                                         break;
1812                                 case AREF_COMMON:
1813                                         hi |= AI_COMMON;
1814                                         break;
1815                                 case AREF_GROUND:
1816                                         hi |= AI_GROUND;
1817                                         break;
1818                                 case AREF_OTHER:
1819                                         break;
1820                         }
1821                 }
1822                 hi |= AI_CONFIG_CHANNEL( chan );
1823
1824                 ni_writew(hi,Configuration_Memory_High);
1825
1826                 if(boardtype.reg_type != ni_reg_6143){
1827                         lo = range;
1828                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1829                         if( dither ) lo |= AI_DITHER;
1830
1831                         ni_writew(lo,Configuration_Memory_Low);
1832                 }
1833         }
1834
1835         /* prime the channel/gain list */
1836         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1837                 ni_prime_channelgain_list(dev);
1838         }
1839 }
1840
1841 static int ni_ns_to_timer(const comedi_device *dev, unsigned nanosec, int round_mode)
1842 {
1843         int divider;
1844         switch(round_mode)
1845         {
1846         case TRIG_ROUND_NEAREST:
1847         default:
1848                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1849                 break;
1850         case TRIG_ROUND_DOWN:
1851                 divider = (nanosec) / devpriv->clock_ns;
1852                 break;
1853         case TRIG_ROUND_UP:
1854                 divider=(nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1855                 break;
1856         }
1857         return divider - 1;
1858 }
1859
1860 static unsigned ni_timer_to_ns(const comedi_device *dev, int timer)
1861 {
1862         return devpriv->clock_ns * (timer + 1);
1863 }
1864
1865 static unsigned ni_min_ai_scan_period_ns(comedi_device *dev, unsigned num_channels)
1866 {
1867         switch(boardtype.reg_type)
1868         {
1869         case ni_reg_611x:
1870         case ni_reg_6143:
1871         // simultaneously-sampled inputs
1872                 return boardtype.ai_speed;
1873                 break;
1874         default:
1875         // multiplexed inputs
1876                 break;
1877         };
1878         return boardtype.ai_speed * num_channels;
1879 }
1880
1881 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1882 {
1883         int err=0;
1884         int tmp;
1885         int sources;
1886
1887         /* step 1: make sure trigger sources are trivially valid */
1888
1889         tmp=cmd->start_src;
1890         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1891         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1892
1893         tmp=cmd->scan_begin_src;
1894         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1895         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1896
1897         tmp=cmd->convert_src;
1898         sources = TRIG_TIMER | TRIG_EXT;
1899         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1900         cmd->convert_src &= sources;
1901         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1902
1903         tmp=cmd->scan_end_src;
1904         cmd->scan_end_src &= TRIG_COUNT;
1905         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1906
1907         tmp=cmd->stop_src;
1908         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1909         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1910
1911         if(err)return 1;
1912
1913         /* step 2: make sure trigger sources are unique and mutually compatible */
1914
1915         /* note that mutual compatiblity is not an issue here */
1916         if(cmd->start_src!=TRIG_NOW &&
1917            cmd->start_src!=TRIG_INT &&
1918            cmd->start_src!=TRIG_EXT)err++;
1919         if(cmd->scan_begin_src!=TRIG_TIMER &&
1920            cmd->scan_begin_src!=TRIG_EXT &&
1921            cmd->scan_begin_src!=TRIG_OTHER)err++;
1922         if(cmd->convert_src!=TRIG_TIMER &&
1923            cmd->convert_src!=TRIG_EXT &&
1924            cmd->convert_src!=TRIG_NOW)err++;
1925         if(cmd->stop_src!=TRIG_COUNT &&
1926            cmd->stop_src!=TRIG_NONE)err++;
1927
1928         if(err)return 2;
1929
1930         /* step 3: make sure arguments are trivially compatible */
1931
1932         if(cmd->start_src==TRIG_EXT){
1933                 /* external trigger */
1934                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1935
1936                 if(tmp > 16) tmp = 16;
1937                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1938                 if(cmd->start_arg != tmp){
1939                         cmd->start_arg = tmp;
1940                         err++;
1941                 }
1942         }else{
1943                 if(cmd->start_arg!=0){
1944                         /* true for both TRIG_NOW and TRIG_INT */
1945                         cmd->start_arg=0;
1946                         err++;
1947                 }
1948         }
1949         if(cmd->scan_begin_src==TRIG_TIMER){
1950                 if(cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, cmd->chanlist_len))
1951                 {
1952                         cmd->scan_begin_arg = ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
1953                         err++;
1954                 }
1955                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1956                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1957                         err++;
1958                 }
1959         }else if(cmd->scan_begin_src==TRIG_EXT){
1960                 /* external trigger */
1961                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1962
1963                 if(tmp>16)tmp=16;
1964                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1965                 if(cmd->scan_begin_arg!=tmp){
1966                         cmd->scan_begin_arg = tmp;
1967                         err++;
1968                 }
1969         }else{ /* TRIG_OTHER */
1970                 if(cmd->scan_begin_arg){
1971                         cmd->scan_begin_arg=0;
1972                         err++;
1973                 }
1974         }
1975         if(cmd->convert_src==TRIG_TIMER){
1976                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1977                         if(cmd->convert_arg != 0){
1978                                 cmd->convert_arg = 0;
1979                                 err++;
1980                         }
1981                 }else{
1982                         if(cmd->convert_arg<boardtype.ai_speed){
1983                                 cmd->convert_arg=boardtype.ai_speed;
1984                                 err++;
1985                         }
1986                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1987                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1988                                 err++;
1989                         }
1990                 }
1991         }else if(cmd->convert_src == TRIG_EXT){
1992                 /* external trigger */
1993                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1994
1995                 if(tmp>16)tmp=16;
1996                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1997                 if(cmd->convert_arg!=tmp){
1998                         cmd->convert_arg = tmp;
1999                         err++;
2000                 }
2001         }else if(cmd->convert_src == TRIG_NOW){
2002                 if(cmd->convert_arg != 0){
2003                         cmd->convert_arg = 0;
2004                         err++;
2005                 }
2006         }
2007
2008         if(cmd->scan_end_arg!=cmd->chanlist_len){
2009                 cmd->scan_end_arg=cmd->chanlist_len;
2010                 err++;
2011         }
2012         if(cmd->stop_src==TRIG_COUNT){
2013                 unsigned int max_count = 0x01000000;
2014
2015                 if(boardtype.reg_type == ni_reg_611x )
2016                         max_count -= num_adc_stages_611x;
2017                 if(cmd->stop_arg > max_count){
2018                         cmd->stop_arg = max_count;
2019                         err++;
2020                 }
2021                 if(cmd->stop_arg < 1){
2022                         cmd->stop_arg = 1;
2023                         err++;
2024                 }
2025         }else{
2026                 /* TRIG_NONE */
2027                 if(cmd->stop_arg!=0){
2028                         cmd->stop_arg=0;
2029                         err++;
2030                 }
2031         }
2032
2033         if(err)return 3;
2034
2035         /* step 4: fix up any arguments */
2036
2037         if(cmd->scan_begin_src==TRIG_TIMER){
2038                 tmp=cmd->scan_begin_arg;
2039                 cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags & TRIG_ROUND_MASK));
2040                 if(tmp!=cmd->scan_begin_arg)err++;
2041         }
2042         if(cmd->convert_src==TRIG_TIMER){
2043                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
2044                         tmp=cmd->convert_arg;
2045                         cmd->convert_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->convert_arg, cmd->flags & TRIG_ROUND_MASK));
2046                         if(tmp!=cmd->convert_arg)err++;
2047                         if(cmd->scan_begin_src==TRIG_TIMER &&
2048                                 cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg)
2049                         {
2050                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
2051                                 err++;
2052                         }
2053                 }
2054         }
2055
2056         if(err)return 4;
2057
2058         return 0;
2059 }
2060
2061 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
2062 {
2063         const comedi_cmd *cmd=&s->async->cmd;
2064         int timer;
2065         int mode1=0; /* mode1 is needed for both stop and convert */
2066         int mode2=0;
2067         int start_stop_select=0;
2068         unsigned int stop_count;
2069         int interrupt_a_enable=0;
2070
2071         MDPRINTK("ni_ai_cmd\n");
2072         if(dev->irq == 0)
2073         {
2074                 comedi_error(dev, "cannot run command without an irq");
2075                 return -EIO;
2076         }
2077         ni_clear_ai_fifo(dev);
2078
2079         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
2080
2081         /* start configuration */
2082         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
2083
2084         /* disable analog triggering for now, since it
2085          * interferes with the use of pfi0 */
2086         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2087         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
2088
2089         switch(cmd->start_src){
2090                 case TRIG_INT:
2091                 case TRIG_NOW:
2092                         devpriv->stc_writew(dev, AI_START2_Select(0)|
2093                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
2094                                 AI_Trigger_Select_Register);
2095                         break;
2096                 case TRIG_EXT:
2097                 {
2098                         int chan = CR_CHAN(cmd->start_arg);
2099                         unsigned int bits = AI_START2_Select(0)|
2100                                 AI_START1_Sync |
2101                                 AI_START1_Select(chan + 1);
2102
2103                         if(cmd->start_arg & CR_INVERT)
2104                                 bits |= AI_START1_Polarity;
2105                         if(cmd->start_arg & CR_EDGE)
2106                                 bits |= AI_START1_Edge;
2107                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
2108                         break;
2109                 }
2110         }
2111
2112         mode2 &= ~AI_Pre_Trigger;
2113         mode2 &= ~AI_SC_Initial_Load_Source;
2114         mode2 &= ~AI_SC_Reload_Mode;
2115         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2116
2117         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
2118                 start_stop_select |= AI_STOP_Polarity;
2119                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
2120                 start_stop_select |= AI_STOP_Sync;
2121         }else
2122         {
2123                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
2124         }
2125         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2126
2127         devpriv->ai_cmd2 = 0;
2128         switch(cmd->stop_src){
2129         case TRIG_COUNT:
2130                 stop_count = cmd->stop_arg - 1;
2131
2132                 if(boardtype.reg_type == ni_reg_611x){
2133                         // have to take 3 stage adc pipeline into account
2134                         stop_count += num_adc_stages_611x;
2135                 }
2136                 /* stage number of scans */
2137                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
2138
2139                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2140                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2141                 /* load SC (Scan Count) */
2142                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2143
2144                 devpriv->ai_continuous = 0;
2145                 if( stop_count == 0 ){
2146                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2147                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2148                         // this is required to get the last sample for chanlist_len > 1, not sure why
2149                         if(cmd->chanlist_len > 1)
2150                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
2151                 }
2152                 break;
2153         case TRIG_NONE:
2154                 /* stage number of scans */
2155                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
2156
2157                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2158                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2159
2160                 /* load SC (Scan Count) */
2161                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2162
2163                 devpriv->ai_continuous = 1;
2164
2165                 break;
2166         }
2167
2168         switch(cmd->scan_begin_src){
2169         case TRIG_TIMER:
2170                 /*
2171                         stop bits for non 611x boards
2172                         AI_SI_Special_Trigger_Delay=0
2173                         AI_Pre_Trigger=0
2174                         AI_START_STOP_Select_Register:
2175                         AI_START_Polarity=0 (?) rising edge
2176                         AI_START_Edge=1         edge triggered
2177                         AI_START_Sync=1 (?)
2178                         AI_START_Select=0               SI_TC
2179                         AI_STOP_Polarity=0              rising edge
2180                         AI_STOP_Edge=0          level
2181                         AI_STOP_Sync=1
2182                         AI_STOP_Select=19               external pin (configuration mem)
2183                  */
2184                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2185                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2186
2187                 mode2 |= AI_SI_Reload_Mode(0);
2188                 /* AI_SI_Initial_Load_Source=A */
2189                 mode2 &= ~AI_SI_Initial_Load_Source;
2190                 //mode2 |= AI_SC_Reload_Mode;
2191                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2192
2193                 /* load SI */
2194                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2195                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
2196                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
2197                 break;
2198         case TRIG_EXT:
2199                 if( cmd->scan_begin_arg & CR_EDGE )
2200                         start_stop_select |= AI_START_Edge;
2201                 /* AI_START_Polarity==1 is falling edge */
2202                 if( cmd->scan_begin_arg & CR_INVERT )
2203                         start_stop_select |= AI_START_Polarity;
2204                 if( cmd->scan_begin_src != cmd->convert_src ||
2205                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
2206                         start_stop_select |= AI_START_Sync;
2207                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2208                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2209                 break;
2210         }
2211
2212         switch(cmd->convert_src){
2213         case TRIG_TIMER:
2214         case TRIG_NOW:
2215                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
2216                         timer = 1;
2217                 else
2218                         timer = ni_ns_to_timer(dev, cmd->convert_arg, TRIG_ROUND_NEAREST);
2219                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
2220                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
2221
2222                 /* AI_SI2_Reload_Mode = alternate */
2223                 /* AI_SI2_Initial_Load_Source = A */
2224                 mode2 &= ~AI_SI2_Initial_Load_Source;
2225                 mode2 |= AI_SI2_Reload_Mode;
2226                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2227
2228                 /* AI_SI2_Load */
2229                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2230
2231                 mode2 |= AI_SI2_Reload_Mode; // alternate
2232                 mode2 |= AI_SI2_Initial_Load_Source; // B
2233
2234                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2235                 break;
2236         case TRIG_EXT:
2237                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2238                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2239                         mode1 |= AI_CONVERT_Source_Polarity;
2240                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2241
2242                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2243                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2244
2245                 break;
2246         }
2247
2248         if(dev->irq){
2249
2250                 /* interrupt on FIFO, errors, SC_TC */
2251                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2252                         AI_SC_TC_Interrupt_Enable;
2253
2254 #ifndef PCIDMA
2255                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2256 #endif
2257
2258                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2259                         /* wake on end-of-scan */
2260                         devpriv->aimode=AIMODE_SCAN;
2261                 }else{
2262                         devpriv->aimode=AIMODE_HALF_FULL;
2263                 }
2264
2265                 switch(devpriv->aimode){
2266                 case AIMODE_HALF_FULL:
2267                         /*generate FIFO interrupts and DMA requests on half-full */
2268 #ifdef PCIDMA
2269                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2270 #else
2271                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2272 #endif
2273                         break;
2274                 case AIMODE_SAMPLE:
2275                         /*generate FIFO interrupts on non-empty */
2276                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2277                         break;
2278                 case AIMODE_SCAN:
2279 #ifdef PCIDMA
2280                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2281 #else
2282                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2283 #endif
2284                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2285                         break;
2286                 default:
2287                         break;
2288                 }
2289
2290                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2291
2292                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2293
2294                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2295         }else{
2296                 /* interrupt on nothing */
2297                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2298
2299                 /* XXX start polling if necessary */
2300                 MDPRINTK("interrupting on nothing\n");
2301         }
2302
2303         /* end configuration */
2304         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2305
2306         switch(cmd->scan_begin_src){
2307         case TRIG_TIMER:
2308                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2309                         AI_Command_1_Register);
2310                 break;
2311         case TRIG_EXT:
2312                 /* XXX AI_SI_Arm? */
2313                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2314                         AI_Command_1_Register);
2315                 break;
2316         }
2317
2318 #ifdef PCIDMA
2319         {
2320                 int retval = ni_ai_setup_MITE_dma(dev);
2321                 if(retval) return retval;
2322         }
2323         //mite_dump_regs(devpriv->mite);
2324 #endif
2325
2326         switch(cmd->start_src){
2327         case TRIG_NOW:
2328                 /* AI_START1_Pulse */
2329                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2330                 s->async->inttrig=NULL;
2331                 break;
2332         case TRIG_EXT:
2333                 s->async->inttrig=NULL;
2334                 break;
2335         case TRIG_INT:
2336                 s->async->inttrig=ni_ai_inttrig;
2337                 break;
2338         }
2339
2340         MDPRINTK("exit ni_ai_cmd\n");
2341
2342         return 0;
2343 }
2344
2345 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2346         unsigned int trignum)
2347 {
2348         if(trignum!=0)return -EINVAL;
2349
2350         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2351         s->async->inttrig=NULL;
2352
2353         return 1;
2354 }
2355
2356 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2357         comedi_insn *insn, lsampl_t *data);
2358
2359 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2360         comedi_insn *insn, lsampl_t *data)
2361 {
2362         if(insn->n<1)return -EINVAL;
2363
2364         switch(data[0]){
2365         case INSN_CONFIG_ANALOG_TRIG:
2366                 return ni_ai_config_analog_trig(dev,s,insn,data);
2367         case INSN_CONFIG_ALT_SOURCE:
2368                 if(boardtype.reg_type & ni_reg_m_series_mask)
2369                 {
2370                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2371                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2372                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2373                         {
2374                                 return -EINVAL;
2375                         }
2376                         devpriv->ai_calib_source = data[1];
2377                 } else if(boardtype.reg_type == ni_reg_6143)
2378                 {
2379                         unsigned int calib_source;
2380
2381                         calib_source = data[1] & 0xf;
2382
2383
2384                         if(calib_source > 0xF)
2385                                 return -EINVAL;
2386
2387                         devpriv->ai_calib_source = calib_source;
2388                         ni_writew(calib_source, Calibration_Channel_6143);
2389                 }else
2390                 {
2391                         unsigned int calib_source;
2392                         unsigned int calib_source_adjust;
2393
2394                         calib_source = data[1] & 0xf;
2395                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2396
2397                         if(calib_source >= 8)
2398                                 return -EINVAL;
2399                         devpriv->ai_calib_source = calib_source;
2400                         if(boardtype.reg_type == ni_reg_611x){
2401                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2402                         }
2403                 }
2404                 return 2;
2405         default:
2406                 break;
2407         }
2408
2409         return -EINVAL;
2410 }
2411
2412 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2413         comedi_insn *insn, lsampl_t *data)
2414 {
2415         unsigned int a,b,modebits;
2416         int err=0;
2417
2418         /* data[1] is flags
2419          * data[2] is analog line
2420          * data[3] is set level
2421          * data[4] is reset level */
2422         if(!boardtype.has_analog_trig)return -EINVAL;
2423         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2424                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2425                 err++;
2426         }
2427         if(data[2]>=boardtype.n_adchan){
2428                 data[2]=boardtype.n_adchan-1;
2429                 err++;
2430         }
2431         if(data[3]>255){ /* a */
2432                 data[3]=255;
2433                 err++;
2434         }
2435         if(data[4]>255){ /* b */
2436                 data[4]=255;
2437                 err++;
2438         }
2439         /*
2440          * 00 ignore
2441          * 01 set
2442          * 10 reset
2443          *
2444          * modes:
2445          *   1 level:                    +b-   +a-
2446          *     high mode                00 00 01 10
2447          *     low mode                 00 00 10 01
2448          *   2 level: (a<b)
2449          *     hysteresis low mode      10 00 00 01
2450          *     hysteresis high mode     01 00 00 10
2451          *     middle mode              10 01 01 10
2452          */
2453
2454         a=data[3];
2455         b=data[4];
2456         modebits=data[1]&0xff;
2457         if(modebits&0xf0){
2458                 /* two level mode */
2459                 if(b<a){
2460                         /* swap order */
2461                         a=data[4];
2462                         b=data[3];
2463                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2464                 }
2465                 devpriv->atrig_low = a;
2466                 devpriv->atrig_high = b;
2467                 switch(modebits){
2468                 case 0x81:      /* low hysteresis mode */
2469                         devpriv->atrig_mode = 6;
2470                         break;
2471                 case 0x42:      /* high hysteresis mode */
2472                         devpriv->atrig_mode = 3;
2473                         break;
2474                 case 0x96:      /* middle window mode */
2475                         devpriv->atrig_mode = 2;
2476                         break;
2477                 default:
2478                         data[1]&=~0xff;
2479                         err++;
2480                 }
2481         }else{
2482                 /* one level mode */
2483                 if(b!=0){
2484                         data[4]=0;
2485                         err++;
2486                 }
2487                 switch(modebits){
2488                 case 0x06:      /* high window mode */
2489                         devpriv->atrig_high = a;
2490                         devpriv->atrig_mode = 0;
2491                         break;
2492                 case 0x09:      /* low window mode */
2493                         devpriv->atrig_low = a;
2494                         devpriv->atrig_mode = 1;
2495                         break;
2496                 default:
2497                         data[1]&=~0xff;
2498                         err++;
2499                 }
2500         }
2501         if(err)return -EAGAIN;
2502         return 5;
2503 }
2504
2505 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2506 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2507         void *data, unsigned int num_bytes, unsigned int chan_index )
2508 {
2509         comedi_async *async = s->async;
2510         unsigned int range;
2511         unsigned int i;
2512         unsigned int offset;
2513         unsigned int length = num_bytes / sizeof( sampl_t );
2514         sampl_t *array = data;
2515
2516         offset = 1 << (boardtype.aobits - 1);
2517         for(i = 0; i < length; i++)
2518         {
2519                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2520                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2521                         array[i] -= offset;
2522 #ifdef PCIDMA
2523                 array[i] = cpu_to_le16( array[i] );
2524 #endif
2525                 chan_index++;
2526                 chan_index %= async->cmd.chanlist_len;
2527         }
2528 }
2529
2530 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2531         unsigned int chanspec[], unsigned int n_chans, int timed)
2532 {
2533         unsigned int range;
2534         unsigned int chan;
2535         unsigned int conf;
2536         int i;
2537         int invert = 0;
2538
2539         for(i = 0; i < boardtype.n_aochan; ++i)
2540         {
2541                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2542         }
2543         for(i=0;i<n_chans;i++)
2544         {
2545                 comedi_krange *krange;
2546                 chan = CR_CHAN(chanspec[i]);
2547                 range = CR_RANGE(chanspec[i]);
2548                 krange = s->range_table->range + range;
2549                 invert = 0;
2550                 conf = 0;
2551                 switch(krange->max - krange->min)
2552                 {
2553                 case 20000000:
2554                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2555                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2556                         break;
2557                 case 10000000:
2558                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2559                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2560                         break;
2561                 case 4000000:
2562                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2563                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2564                         break;
2565                 case 2000000:
2566                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2567                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2568                         break;
2569                 default:
2570                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2571                         break;
2572                 }
2573                 switch(krange->max + krange->min)
2574                 {
2575                 case 0:
2576                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2577                         break;
2578                 case 10000000:
2579                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2580                         break;
2581                 default:
2582                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2583                         break;
2584                 }
2585                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2586                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2587                 devpriv->ao_conf[chan] = conf;
2588                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2589         }
2590         return invert;
2591 }
2592
2593 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2594         unsigned int chanspec[], unsigned int n_chans)
2595 {
2596         unsigned int range;
2597         unsigned int chan;
2598         unsigned int conf;
2599         int i;
2600         int invert = 0;
2601
2602         for(i=0;i<n_chans;i++)
2603         {
2604                 chan = CR_CHAN(chanspec[i]);
2605                 range = CR_RANGE(chanspec[i]);
2606                 conf = AO_Channel(chan);
2607
2608                 if(boardtype.ao_unipolar){
2609                         if((range&1) == 0){
2610                                 conf |= AO_Bipolar;
2611                                 invert = (1<<(boardtype.aobits-1));
2612                         }else{
2613                                 invert = 0;
2614                         }
2615                         if(range&2)
2616                                 conf |= AO_Ext_Ref;
2617                 }else{
2618                         conf |= AO_Bipolar;
2619                         invert = (1<<(boardtype.aobits-1));
2620                 }
2621
2622                 /* not all boards can deglitch, but this shouldn't hurt */
2623                 if(chanspec[i] & CR_DEGLITCH)
2624                         conf |= AO_Deglitch;
2625
2626                 /* analog reference */
2627                 /* AREF_OTHER connects AO ground to AI ground, i think */
2628                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2629
2630                 ni_writew(conf,AO_Configuration);
2631                 devpriv->ao_conf[chan] = conf;
2632         }
2633         return invert;
2634 }
2635
2636 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2637         unsigned int chanspec[], unsigned int n_chans, int timed)
2638 {
2639         if(boardtype.reg_type & ni_reg_m_series_mask)
2640                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2641         else
2642                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2643 }
2644 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2645         comedi_insn *insn,lsampl_t *data)
2646 {
2647         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2648
2649         return 1;
2650 }
2651
2652 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2653         comedi_insn *insn,lsampl_t *data)
2654 {
2655         unsigned int chan = CR_CHAN(insn->chanspec);
2656         unsigned int invert;
2657
2658         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2659
2660         devpriv->ao[chan] = data[0];
2661
2662         if(boardtype.reg_type & ni_reg_m_series_mask)
2663         {
2664                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2665         }
2666         else
2667                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2668
2669         return 1;
2670 }
2671
2672 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2673         comedi_insn *insn,lsampl_t *data)
2674 {
2675         unsigned int chan = CR_CHAN(insn->chanspec);
2676         unsigned int invert;
2677
2678         ao_win_out(1 << chan, AO_Immediate_671x);
2679         invert = 1 << (boardtype.aobits - 1);
2680
2681         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2682
2683         devpriv->ao[chan] = data[0];
2684         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2685
2686         return 1;
2687 }
2688
2689 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2690         unsigned int trignum)
2691 {
2692         int ret;
2693         int interrupt_b_bits;
2694         int i;
2695         static const int timeout = 1000;
2696
2697         if(trignum!=0) return -EINVAL;
2698
2699         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2700         interrupt_b_bits = AO_Error_Interrupt_Enable;
2701 #ifdef PCIDMA
2702         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2703         if(boardtype.reg_type & ni_reg_6xxx_mask)
2704                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2705         ret = ni_ao_setup_MITE_dma(dev);
2706         if(ret) return ret;
2707         ret = ni_ao_wait_for_dma_load(dev);
2708         if(ret < 0) return ret;
2709
2710 #else
2711         ret = ni_ao_prep_fifo(dev,s);
2712         if(ret==0)return -EPIPE;
2713
2714         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2715 #endif
2716
2717         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2718         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2719         /* wait for DACs to be loaded */
2720         for(i = 0; i < timeout; i++)
2721         {
2722                 comedi_udelay(1);
2723                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2724                         break;
2725         }
2726         if(i == timeout)
2727         {
2728                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2729                 return -EIO;
2730         }
2731         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2732         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2733
2734         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2735
2736         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2737                 AO_Command_1_Register);
2738
2739         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2740
2741         s->async->inttrig=NULL;
2742
2743         return 0;
2744 }
2745
2746 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2747 {
2748         const comedi_cmd *cmd = &s->async->cmd;
2749         int trigvar;
2750         int bits;
2751         int i;
2752
2753         if(dev->irq == 0)
2754         {
2755                 comedi_error(dev, "cannot run command without an irq");
2756                 return -EIO;
2757         }
2758         trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2759
2760         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2761
2762         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2763
2764         if(boardtype.reg_type & ni_reg_6xxx_mask)
2765         {
2766                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2767
2768                 bits = 0;
2769                 for(i = 0; i < cmd->chanlist_len; i++)
2770                 {
2771                         int chan;
2772
2773                         chan = CR_CHAN(cmd->chanlist[i]);
2774                         bits |= 1 << chan;
2775                         ao_win_out(chan, AO_Waveform_Generation_611x);
2776                 }
2777                 ao_win_out(bits, AO_Timed_611x);
2778         }
2779
2780         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2781
2782         if(cmd->stop_src==TRIG_NONE){
2783                 devpriv->ao_mode1|=AO_Continuous;
2784                 devpriv->ao_mode1&=~AO_Trigger_Once;
2785         }else{
2786                 devpriv->ao_mode1&=~AO_Continuous;
2787                 devpriv->ao_mode1|=AO_Trigger_Once;
2788         }
2789         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2790         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2791         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2792         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2793         devpriv->ao_mode3&=~AO_Trigger_Length;
2794         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2795
2796         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2797         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2798         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2799         if(cmd->stop_src==TRIG_NONE){
2800                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2801         }else{
2802                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2803         }
2804         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2805         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2806         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2807         switch(cmd->stop_src){
2808         case TRIG_COUNT:
2809                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2810                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2811                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2812                 break;
2813         case TRIG_NONE:
2814                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2815                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2816                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2817                 break;
2818         default:
2819                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2820                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2821                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2822         }
2823
2824         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2825         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2826         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2827         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2828         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2829         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2830         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2831         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2832         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2833
2834         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2835                 if(cmd->scan_end_arg>1){
2836                         devpriv->ao_mode1|=AO_Multiple_Channels;
2837                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2838                                 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
2839                                 AO_Output_Control_Register);
2840                 }else{
2841                         unsigned bits;
2842                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2843                         bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
2844                         if(boardtype.reg_type & ni_reg_m_series_mask)
2845                         {
2846                                 bits |= AO_Number_Of_Channels(0);
2847                         }else
2848                         {
2849                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2850                         }
2851                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2852                 }
2853                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2854         }
2855
2856         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2857
2858         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2859         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2860
2861         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
2862 #ifdef PCIDMA
2863         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2864 #else
2865         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2866 #endif
2867         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2868         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2869
2870         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2871                 AO_TMRDACWR_Pulse_Width;
2872         if( boardtype.ao_fifo_depth )
2873                 bits |= AO_FIFO_Enable;
2874         else
2875                 bits |= AO_DMA_PIO_Control;
2876 #if 0
2877         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
2878         verified with bus analyzer. */
2879         if(boardtype.reg_type & ni_reg_m_series_mask)
2880                 bits |= AO_Number_Of_DAC_Packages;
2881 #endif
2882         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2883         // enable sending of ao dma requests
2884         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2885
2886         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2887
2888         if(cmd->stop_src==TRIG_COUNT) {
2889                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2890                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2891                         AO_BC_TC_Interrupt_Enable, 1);
2892         }
2893
2894         s->async->inttrig=ni_ao_inttrig;
2895
2896         return 0;
2897 }
2898
2899 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2900 {
2901         int err=0;
2902         int tmp;
2903
2904         /* step 1: make sure trigger sources are trivially valid */
2905
2906         tmp=cmd->start_src;
2907         cmd->start_src &= TRIG_INT;
2908         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2909
2910         tmp=cmd->scan_begin_src;
2911         cmd->scan_begin_src &= TRIG_TIMER;
2912         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2913
2914         tmp=cmd->convert_src;
2915         cmd->convert_src &= TRIG_NOW;
2916         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2917
2918         tmp=cmd->scan_end_src;
2919         cmd->scan_end_src &= TRIG_COUNT;
2920         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2921
2922         tmp=cmd->stop_src;
2923         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2924         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2925
2926         if(err)return 1;
2927
2928         /* step 2: make sure trigger sources are unique and mutually compatible */
2929
2930         if(cmd->stop_src!=TRIG_COUNT &&
2931            cmd->stop_src!=TRIG_NONE)err++;
2932
2933         if(err)return 2;
2934
2935         /* step 3: make sure arguments are trivially compatible */
2936
2937         if(cmd->start_arg!=0){
2938                 cmd->start_arg=0;
2939                 err++;
2940         }
2941         if(cmd->scan_begin_arg < boardtype.ao_speed){
2942                 cmd->scan_begin_arg = boardtype.ao_speed;
2943                 err++;
2944         }
2945         if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){ /* XXX check */
2946                 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2947                 err++;
2948         }
2949         if(cmd->convert_arg!=0){
2950                 cmd->convert_arg=0;
2951                 err++;
2952         }
2953         if(cmd->scan_end_arg!=cmd->chanlist_len){
2954                 cmd->scan_end_arg=cmd->chanlist_len;
2955                 err++;
2956         }
2957         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2958                 if(cmd->stop_arg>0x00ffffff){
2959                         cmd->stop_arg=0x00ffffff;
2960                         err++;
2961                 }
2962         }else{
2963                 /* TRIG_NONE */
2964                 if(cmd->stop_arg!=0){
2965                         cmd->stop_arg=0;
2966                         err++;
2967                 }
2968         }
2969
2970         if(err)return 3;
2971
2972         /* step 4: fix up any arguments */
2973
2974         tmp = cmd->scan_begin_arg;
2975         cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK));
2976         if(tmp!=cmd->scan_begin_arg)err++;
2977
2978         if(err)return 4;
2979
2980         /* step 5: fix up chanlist */
2981
2982         if(err)return 5;
2983
2984         return 0;
2985 }
2986
2987
2988 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2989 {
2990         //devpriv->ao0p=0x0000;
2991         //ni_writew(devpriv->ao0p,AO_Configuration);
2992
2993         //devpriv->ao1p=AO_Channel(1);
2994         //ni_writew(devpriv->ao1p,AO_Configuration);
2995
2996         ni_release_ao_mite_channel(dev);
2997
2998         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2999         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
3000         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
3001         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3002         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
3003         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3004                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3005         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
3006         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
3007         devpriv->ao_cmd1=0;
3008         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
3009         devpriv->ao_cmd2=0;
3010         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3011         devpriv->ao_mode1=0;
3012         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3013         devpriv->ao_mode2=0;
3014         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3015         if(boardtype.reg_type & ni_reg_m_series_mask)
3016                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3017         else
3018                 devpriv->ao_mode3 = 0;
3019         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3020         devpriv->ao_trigger_select = 0;
3021         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
3022         if(boardtype.reg_type & ni_reg_6xxx_mask){
3023                 ao_win_out(0x3, AO_Immediate_671x);
3024                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3025         }
3026         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3027
3028         return 0;
3029 }
3030
3031 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
3032         comedi_insn *insn,lsampl_t *data)
3033 {
3034 #ifdef DEBUG_DIO
3035         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
3036                 CR_CHAN(insn->chanspec),data[0]);
3037 #endif
3038         switch(data[0]){
3039         case INSN_CONFIG_DIO_OUTPUT:
3040                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
3041                 break;
3042         case INSN_CONFIG_DIO_INPUT:
3043                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
3044                 break;
3045         case INSN_CONFIG_DIO_QUERY:
3046                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
3047                 return insn->n;
3048                 break;
3049         default:
3050                 return -EINVAL;
3051         }
3052
3053         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3054         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3055         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3056
3057         return 1;
3058 }
3059
3060 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3061         comedi_insn *insn,lsampl_t *data)
3062 {
3063 #ifdef DEBUG_DIO
3064         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3065 #endif
3066         if(insn->n!=2)return -EINVAL;
3067         if(data[0]){
3068                 /* Perform check to make sure we're not using the
3069                    serial part of the dio */
3070                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3071                         return -EBUSY;
3072
3073                 s->state &= ~data[0];
3074                 s->state |= (data[0]&data[1]);
3075                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3076                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3077                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3078         }
3079         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3080
3081         return 2;
3082 }
3083
3084 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
3085         comedi_insn *insn, lsampl_t *data)
3086 {
3087 #ifdef DEBUG_DIO
3088         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3089                 CR_CHAN(insn->chanspec), data[0]);
3090 #endif
3091         switch(data[0])
3092         {
3093         case INSN_CONFIG_DIO_OUTPUT:
3094                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3095                 break;
3096         case INSN_CONFIG_DIO_INPUT:
3097                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3098                 break;
3099         case INSN_CONFIG_DIO_QUERY:
3100                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
3101                 return insn->n;
3102                 break;
3103         default:
3104                 return -EINVAL;
3105         }
3106
3107         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3108
3109         return 1;
3110 }
3111
3112 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3113         comedi_insn *insn, lsampl_t *data)
3114 {
3115 #ifdef DEBUG_DIO
3116         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3117 #endif
3118         if(insn->n!=2)return -EINVAL;
3119         if(data[0]){
3120                 s->state &= ~data[0];
3121                 s->state |= (data[0] & data[1]);
3122                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3123         }
3124         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3125
3126         return 2;
3127 }
3128
3129 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
3130                                  comedi_insn *insn,lsampl_t *data)
3131 {
3132         int err = insn->n;
3133         unsigned char byte_out, byte_in;
3134
3135         if(insn->n!=2)return -EINVAL;
3136
3137         switch(data[0]) {
3138         case INSN_CONFIG_SERIAL_CLOCK:
3139
3140 #ifdef DEBUG_DIO
3141                 rt_printk("SPI serial clock Config cd\n", data[1]);
3142 #endif
3143                 devpriv->serial_hw_mode = 1;
3144                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3145
3146                 if(data[1] == SERIAL_DISABLED) {
3147                         devpriv->serial_hw_mode = 0;
3148                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3149                                                   DIO_Software_Serial_Control);
3150                         data[1] = SERIAL_DISABLED;
3151                         devpriv->serial_interval_ns = data[1];
3152                 }
3153                 else if(data[1] <= SERIAL_600NS) {
3154                         /* Warning: this clock speed is too fast to reliably
3155                         control SCXI. */
3156                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3157                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3158                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3159                         data[1] = SERIAL_600NS;
3160                         devpriv->serial_interval_ns = data[1];
3161                 }
3162                 else if(data[1] <= SERIAL_1_2US) {
3163                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3164                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3165                                 DIO_Serial_Out_Divide_By_2;
3166                         data[1] = SERIAL_1_2US;
3167                         devpriv->serial_interval_ns = data[1];
3168                 }
3169                 else if(data[1] <= SERIAL_10US) {
3170                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3171                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3172                                 DIO_Serial_Out_Divide_By_2;
3173                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3174                         600ns/1.2us. If you turn divide_by_2 off with the
3175                         slow clock, you will still get 10us, except then
3176                         all your delays are wrong. */
3177                         data[1] = SERIAL_10US;
3178                         devpriv->serial_interval_ns = data[1];
3179                 }
3180                 else {
3181                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3182                                                   DIO_Software_Serial_Control);
3183                         devpriv->serial_hw_mode = 0;
3184                         data[1] = (data[1] / 1000) * 1000;
3185                         devpriv->serial_interval_ns = data[1];
3186                 }
3187
3188                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3189                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
3190                 return 1;
3191
3192         break;
3193
3194         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3195
3196                 if(devpriv->serial_interval_ns == 0) {
3197                         return -EINVAL;
3198                 }
3199
3200                 byte_out = data[1] & 0xFF;
3201
3202                 if(devpriv->serial_hw_mode) {
3203                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
3204                 } else if(devpriv->serial_interval_ns > 0) {
3205                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
3206                 } else {
3207                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3208                         return -EINVAL;
3209                 }
3210                 if(err < 0) return err;
3211                 data[1] = byte_in & 0xFF;
3212                 return insn->n;
3213
3214         break;
3215         default:
3216                 return -EINVAL;
3217         }
3218
3219 }
3220
3221 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3222                                    unsigned char data_out,
3223                                    unsigned char *data_in)
3224 {
3225         unsigned int status1;
3226         int err = 0, count = 20;
3227
3228 #ifdef DEBUG_DIO
3229         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3230 #endif
3231
3232         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3233         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3234         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3235
3236         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3237         if(status1 & DIO_Serial_IO_In_Progress_St) {
3238                 err = -EBUSY;
3239                 goto Error;
3240         }
3241
3242         devpriv->dio_control |= DIO_HW_Serial_Start;
3243         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3244         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3245
3246         /* Wait until STC says we're done, but don't loop infinitely. */
3247         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3248                 /* Delay one bit per loop */
3249                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3250                 if(--count < 0) {
3251                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3252                         err = -ETIME;
3253                         goto Error;
3254                 }
3255         }
3256
3257         /* Delay for last bit. This delay is absolutely necessary, because
3258            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3259         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3260
3261         if(data_in != NULL) {
3262                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3263 #ifdef DEBUG_DIO
3264                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3265 #endif
3266         }
3267
3268  Error:
3269         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3270
3271         return err;
3272 }
3273
3274 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3275                                    unsigned char data_out,
3276                                    unsigned char *data_in)
3277 {
3278         unsigned char mask, input = 0;
3279
3280 #ifdef DEBUG_DIO
3281         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3282 #endif
3283
3284         /* Wait for one bit before transfer */
3285         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3286
3287         for(mask = 0x80; mask; mask >>= 1) {
3288                 /* Output current bit; note that we cannot touch s->state
3289            because it is a per-subdevice field, and serial is
3290                    a separate subdevice from DIO. */
3291                 devpriv->dio_output &= ~DIO_SDOUT;
3292                 if(data_out & mask) {
3293                         devpriv->dio_output |= DIO_SDOUT;
3294                 }
3295                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3296
3297                 /* Assert SDCLK (active low, inverted), wait for half of
3298                    the delay, deassert SDCLK, and wait for the other half. */
3299                 devpriv->dio_control |= DIO_Software_Serial_Control;
3300                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3301
3302                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3303
3304                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3305                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3306
3307                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3308
3309                 /* Input current bit */
3310                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3311 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3312                         input |= mask;
3313                 }
3314         }
3315 #ifdef DEBUG_DIO
3316         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3317 #endif
3318         if(data_in) *data_in = input;
3319
3320         return 0;
3321 }
3322
3323 static void mio_common_detach(comedi_device *dev)
3324 {
3325         if(dev->subdevices && boardtype.has_8255)
3326                 subdev_8255_cleanup(dev,dev->subdevices+3);
3327 }
3328
3329 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3330 {
3331         int i;
3332
3333         for(i = 0; i < s->n_chan; i++)
3334                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3335 }
3336
3337 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3338 {
3339         unsigned stc_register;
3340         switch(reg)
3341         {
3342         case NITIO_G0_Autoincrement_Reg:
3343                 stc_register = G_Autoincrement_Register(0);
3344                 break;
3345         case NITIO_G1_Autoincrement_Reg:
3346                 stc_register = G_Autoincrement_Register(1);
3347                 break;
3348         case NITIO_G0_Command_Reg:
3349                 stc_register = G_Command_Register(0);
3350                 break;
3351         case NITIO_G1_Command_Reg:
3352                 stc_register = G_Command_Register(1);
3353                 break;
3354         case NITIO_G0_HW_Save_Reg:
3355                 stc_register = G_HW_Save_Register(0);
3356                 break;
3357         case NITIO_G1_HW_Save_Reg:
3358                 stc_register = G_HW_Save_Register(1);
3359                 break;
3360         case NITIO_G0_SW_Save_Reg:
3361                 stc_register = G_Save_Register(0);
3362                 break;
3363         case NITIO_G1_SW_Save_Reg:
3364                 stc_register = G_Save_Register(1);
3365                 break;
3366         case NITIO_G0_Mode_Reg:
3367                 stc_register = G_Mode_Register(0);
3368                 break;
3369         case NITIO_G1_Mode_Reg:
3370                 stc_register = G_Mode_Register(1);
3371                 break;
3372         case NITIO_G0_LoadA_Reg:
3373                 stc_register = G_Load_A_Register(0);
3374                 break;
3375         case NITIO_G1_LoadA_Reg:
3376                 stc_register = G_Load_A_Register(1);
3377                 break;
3378         case NITIO_G0_LoadB_Reg:
3379                 stc_register = G_Load_B_Register(0);
3380                 break;
3381         case NITIO_G1_LoadB_Reg:
3382                 stc_register = G_Load_B_Register(1);
3383                 break;
3384         case NITIO_G0_Input_Select_Reg:
3385                 stc_register = G_Input_Select_Register(0);
3386                 break;
3387         case NITIO_G1_Input_Select_Reg:
3388                 stc_register = G_Input_Select_Register(1);
3389                 break;
3390         case NITIO_G01_Status_Reg:
3391                 stc_register = G_Status_Register;
3392                 break;
3393         case NITIO_G01_Joint_Reset_Reg:
3394                 stc_register = Joint_Reset_Register;
3395                 break;
3396         case NITIO_G01_Joint_Status1_Reg:
3397                 stc_register = Joint_Status_1_Register;
3398                 break;
3399         case NITIO_G01_Joint_Status2_Reg:
3400                 stc_register = Joint_Status_2_Register;
3401                 break;
3402         default:
3403                 rt_printk("%s: unhandled register 0x%x in switch.\n", __FUNCTION__, reg);
3404                 BUG();
3405                 return 0;
3406                 break;
3407         }
3408         return stc_register;
3409 }
3410
3411 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg)
3412 {
3413         comedi_device *dev = counter->dev;
3414         unsigned stc_register;
3415         /* bits in the join reset register which are relevant to counters */
3416         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3417         switch(reg)
3418         {
3419         /* m-series-only registers */
3420         case NITIO_G0_Counting_Mode_Reg:
3421                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3422                 break;
3423         case NITIO_G1_Counting_Mode_Reg:
3424                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3425                 break;
3426         case NITIO_G0_Second_Gate_Reg:
3427                 ni_writew(bits, M_Offset_G0_Second_Gate);
3428                 break;
3429         case NITIO_G1_Second_Gate_Reg:
3430                 ni_writew(bits, M_Offset_G1_Second_Gate);
3431                 break;
3432         case NITIO_G0_ABZ_Reg:
3433                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
3434                 break;
3435         case NITIO_G1_ABZ_Reg:
3436                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
3437                 break;
3438
3439         /* 32 bit registers */
3440         case NITIO_G0_LoadA_Reg:
3441         case NITIO_G1_LoadA_Reg:
3442         case NITIO_G0_LoadB_Reg:
3443         case NITIO_G1_LoadB_Reg:
3444                 stc_register = ni_gpct_to_stc_register(reg);
3445                 devpriv->stc_writel(dev, bits, stc_register);
3446                 break;
3447         /* 16 bit registers */
3448         case NITIO_G01_Joint_Reset_Reg:
3449                 BUG_ON(bits & ~gpct_joint_reset_mask);
3450                 /* fall-through */
3451         default:
3452                 stc_register = ni_gpct_to_stc_register(reg);
3453                 devpriv->stc_writew(dev, bits, stc_register);
3454         }
3455 }
3456
3457 static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg)
3458 {
3459         comedi_device *dev = counter->dev;
3460         unsigned stc_register;
3461         switch(reg)
3462         {
3463         /* 32 bit registers */
3464         case NITIO_G0_HW_Save_Reg:
3465         case NITIO_G1_HW_Save_Reg:
3466         case NITIO_G0_SW_Save_Reg:
3467         case NITIO_G1_SW_Save_Reg:
3468                 stc_register = ni_gpct_to_stc_register(reg);
3469                 return devpriv->stc_readl(dev, stc_register);
3470                 break;
3471         /* 16 bit registers */
3472         default:
3473                 stc_register = ni_gpct_to_stc_register(reg);
3474                 return devpriv->stc_readw(dev, stc_register);
3475                 break;
3476         }
3477         return 0;
3478 }
3479
3480 static int ni_alloc_private(comedi_device *dev)
3481 {
3482         int ret;
3483
3484         ret = alloc_private(dev, sizeof(ni_private));
3485         if(ret < 0) return ret;
3486
3487         spin_lock_init(&devpriv->window_lock);
3488         spin_lock_init(&devpriv->soft_reg_copy_lock);
3489         spin_lock_init(&devpriv->mite_channel_lock);
3490
3491         return 0;
3492 };
3493
3494 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3495 {
3496         comedi_subdevice *s;
3497         unsigned j;
3498
3499         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3500         {
3501                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3502                 return -EINVAL;
3503         }
3504
3505         if(alloc_subdevices(dev, 11 + NUM_GPCT) < 0)
3506                 return -ENOMEM;
3507
3508         /* analog input subdevice */
3509
3510         s=dev->subdevices+0;
3511         dev->read_subdev=s;
3512         if(boardtype.n_adchan){
3513                 s->type=COMEDI_SUBD_AI;
3514                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
3515                 if(boardtype.reg_type != ni_reg_611x)
3516                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3517                 if(boardtype.adbits > 16)
3518                         s->subdev_flags |= SDF_LSAMPL;
3519                 if(boardtype.reg_type & ni_reg_m_series_mask)
3520                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3521                 s->n_chan=boardtype.n_adchan;
3522                 s->len_chanlist=512;
3523                 s->maxdata=(1<<boardtype.adbits)-1;
3524                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3525                 s->insn_read = &ni_ai_insn_read;
3526                 s->insn_config = &ni_ai_insn_config;
3527                 s->do_cmdtest = &ni_ai_cmdtest;
3528                 s->do_cmd = &ni_ai_cmd;
3529                 s->cancel = &ni_ai_reset;
3530                 s->poll = &ni_ai_poll;
3531                 s->munge = &ni_ai_munge;
3532 #ifdef PCIDMA
3533                 s->async_dma_dir = DMA_FROM_DEVICE;
3534 #endif
3535         }else{
3536                 s->type=COMEDI_SUBD_UNUSED;
3537         }
3538
3539         /* analog output subdevice */
3540
3541         s = dev->subdevices + 1;
3542         if(boardtype.n_aochan){
3543                 s->type = COMEDI_SUBD_AO;
3544                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
3545                 if(boardtype.reg_type & ni_reg_m_series_mask)
3546                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3547                 s->n_chan = boardtype.n_aochan;
3548                 s->maxdata = (1 << boardtype.aobits) - 1;
3549                 s->range_table = boardtype.ao_range_table;
3550                 s->insn_read = &ni_ao_insn_read;
3551                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3552                         s->insn_write = &ni_ao_insn_write_671x;
3553                 }else{
3554                         s->insn_write = &ni_ao_insn_write;
3555                 }
3556 #ifdef PCIDMA
3557                 if(boardtype.n_aochan){
3558                         s->async_dma_dir = DMA_TO_DEVICE;
3559 #else
3560                 if(boardtype.ao_fifo_depth){
3561 #endif
3562                         dev->write_subdev=s;
3563                         s->subdev_flags |= SDF_CMD_WRITE;
3564                         s->do_cmd = &ni_ao_cmd;
3565                         s->do_cmdtest = &ni_ao_cmdtest;
3566                         s->len_chanlist = boardtype.n_aochan;
3567                         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
3568                                 s->munge=ni_ao_munge;
3569                 }
3570                 s->cancel = &ni_ao_reset;
3571         }else{
3572                 s->type = COMEDI_SUBD_UNUSED;
3573         }
3574         if((boardtype.reg_type & ni_reg_67xx_mask))
3575                 init_ao_67xx(dev, s);
3576
3577         /* digital i/o subdevice */
3578
3579         s=dev->subdevices+2;
3580         s->type=COMEDI_SUBD_DIO;
3581         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3582         s->maxdata=1;
3583         s->io_bits=0;           /* all bits input */
3584         s->range_table=&range_digital;
3585         s->n_chan = boardtype.num_p0_dio_channels;
3586         if(boardtype.reg_type & ni_reg_m_series_mask)
3587         {
3588                 s->insn_bits = ni_m_series_dio_insn_bits;
3589                 s->insn_config=ni_m_series_dio_insn_config;
3590                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3591         }else
3592         {
3593                 s->insn_bits=ni_dio_insn_bits;
3594                 s->insn_config=ni_dio_insn_config;
3595                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3596                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3597         }
3598
3599         /* 8255 device */
3600         s=dev->subdevices+3;
3601         if(boardtype.has_8255){
3602                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3603         }else{
3604                 s->type=COMEDI_SUBD_UNUSED;
3605         }
3606
3607         /* formerly general purpose counter/timer device, but no longer used */
3608         s=dev->subdevices+4;
3609         s->type = COMEDI_SUBD_UNUSED;
3610
3611         /* calibration subdevice -- ai and ao */
3612         s=dev->subdevices+5;
3613         s->type=COMEDI_SUBD_CALIB;
3614         if(boardtype.reg_type & ni_reg_m_series_mask)
3615         {
3616                 // internal PWM analog output used for AI nonlinearity calibration
3617                 s->subdev_flags = SDF_INTERNAL;
3618                 s->insn_config = &ni_m_series_pwm_config;
3619                 s->n_chan = 1;
3620                 s->maxdata = 0;
3621                 ni_writel(0x0, M_Offset_Cal_PWM);
3622         } else if(boardtype.reg_type == ni_reg_6143)
3623         {
3624                 // internal PWM analog output used for AI nonlinearity calibration
3625                 s->subdev_flags = SDF_INTERNAL;
3626                 s->insn_config = &ni_6143_pwm_config;
3627                 s->n_chan = 1;
3628                 s->maxdata = 0;
3629         }else
3630         {
3631                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3632                 s->insn_read = &ni_calib_insn_read;
3633                 s->insn_write = &ni_calib_insn_write;
3634                 caldac_setup(dev, s);
3635         }
3636
3637         /* EEPROM */
3638         s=dev->subdevices+6;
3639         s->type=COMEDI_SUBD_MEMORY;
3640         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3641         s->maxdata=0xff;
3642         if(boardtype.reg_type & ni_reg_m_series_mask)
3643         {
3644                 s->n_chan = M_SERIES_EEPROM_SIZE;
3645                 s->insn_read = &ni_m_series_eeprom_insn_read;
3646         }else
3647         {
3648                 s->n_chan = 512;
3649                 s->insn_read = &ni_eeprom_insn_read;
3650         }
3651         /* PFI */
3652         s=dev->subdevices + 7;
3653         s->type = COMEDI_SUBD_DIO;
3654         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3655         if(boardtype.reg_type & ni_reg_m_series_mask)
3656         {
3657                 unsigned i;
3658                 s->n_chan = 16;
3659                 ni_writew(s->state, M_Offset_PFI_DO);
3660                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3661                 {
3662                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3663                 }
3664         }else
3665         {
3666                 s->n_chan = 10;
3667         }
3668         s->maxdata = 1;
3669         s->insn_bits = ni_pfi_insn_bits;
3670         s->insn_config = ni_pfi_insn_config;
3671         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3672
3673         /* cs5529 calibration adc */
3674         s = dev->subdevices + 8;
3675         if(boardtype.reg_type & ni_reg_67xx_mask)
3676         {
3677                 s->type = COMEDI_SUBD_AI;
3678                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3679                 // one channel for each analog output channel
3680                 s->n_chan = boardtype.n_aochan;
3681                 s->maxdata = (1 << 16) - 1;
3682                 s->range_table = &range_unknown; /* XXX */
3683                 s->insn_read=cs5529_ai_insn_read;
3684                 s->insn_config=NULL;
3685                 init_cs5529(dev);
3686         }else
3687         {
3688                 s->type=COMEDI_SUBD_UNUSED;
3689         }
3690
3691         /* Serial */
3692         s=dev->subdevices+9;
3693         s->type=COMEDI_SUBD_SERIAL;
3694         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3695         s->n_chan=1;
3696         s->maxdata=0xff;
3697         s->insn_config = ni_serial_insn_config;
3698         devpriv->serial_interval_ns = 0;
3699         devpriv->serial_hw_mode = 0;
3700
3701         /* RTSI */
3702         s=dev->subdevices + 10;
3703         s->type = COMEDI_SUBD_DIO;
3704         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3705         s->n_chan = 8;
3706         s->maxdata = 1;
3707         s->insn_bits = ni_rtsi_insn_bits;
3708         s->insn_config = ni_rtsi_insn_config;
3709         ni_rtsi_init(dev);
3710
3711         /* General purpose counters */
3712         for(j = 0; j < NUM_GPCT; ++j)
3713         {
3714                 s = dev->subdevices + 11 + j;
3715                 s->type = COMEDI_SUBD_COUNTER;
3716                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
3717                 s->n_chan = 3;
3718                 if(boardtype.reg_type & ni_reg_m_series_mask)
3719                         s->maxdata = 0xffffffff;
3720                 else
3721                         s->maxdata = 0xffffff;
3722                 s->insn_read = ni_gpct_insn_read;
3723                 s->insn_write = ni_gpct_insn_write;
3724                 s->insn_config = ni_gpct_insn_config;
3725                 s->do_cmd = ni_gpct_cmd;
3726                 s->do_cmdtest = ni_gpct_cmdtest;
3727                 s->cancel = ni_gpct_cancel;
3728                 s->async_dma_dir = DMA_BIDIRECTIONAL;
3729                 s->private = &devpriv->counters[j];
3730
3731                 devpriv->counters[j].dev = dev;
3732                 devpriv->counters[j].chip_index = 0;
3733                 devpriv->counters[j].counter_index = j;
3734                 devpriv->counters[j].write_register = ni_gpct_write_register;
3735                 devpriv->counters[j].read_register = ni_gpct_read_register;
3736                 if(boardtype.reg_type & ni_reg_m_series_mask)
3737                 {
3738                         devpriv->counters[j].variant = ni_gpct_variant_m_series;
3739                 }else
3740                 {
3741                         devpriv->counters[j].variant = ni_gpct_variant_e_series;
3742                 }
3743                 devpriv->counters[j].clock_period_ps = 0;
3744                 devpriv->counters[j].mite_chan = NULL;
3745                 ni_tio_init_counter(&devpriv->counters[j]);
3746         }
3747
3748         /* ai configuration */
3749         ni_ai_reset(dev,dev->subdevices+0);
3750         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3751                 // BEAM is this needed for PCI-6143 ??
3752                 devpriv->clock_and_fout =
3753                         Slow_Internal_Time_Divide_By_2 |
3754                         Slow_Internal_Timebase |
3755                         Clock_To_Board_Divide_By_2 |
3756                         Clock_To_Board |
3757                         AI_Output_Divide_By_2 |
3758                         AO_Output_Divide_By_2;
3759         }else{
3760                 devpriv->clock_and_fout =
3761                         Slow_Internal_Time_Divide_By_2 |
3762                         Slow_Internal_Timebase |
3763                         Clock_To_Board_Divide_By_2 |
3764                         Clock_To_Board;
3765         }
3766         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3767
3768         /* analog output configuration */
3769         ni_ao_reset(dev,dev->subdevices + 1);
3770
3771         if(dev->irq){
3772                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3773                         (Interrupt_Output_On_3_Pins&0) |
3774                         Interrupt_A_Enable |
3775                         Interrupt_B_Enable |
3776                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3777                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3778                         Interrupt_Control_Register
3779                 );
3780         }
3781
3782         /* DMA setup */
3783         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
3784         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
3785
3786         if(boardtype.reg_type & ni_reg_6xxx_mask)
3787         {
3788                 ni_writeb( 0, Magic_611x );
3789         }else if(boardtype.reg_type & ni_reg_m_series_mask)
3790         {
3791                 int channel;
3792                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3793                 {
3794                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3795                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3796                 }
3797                 ni_writeb(0x0, M_Offset_AO_Calibration);
3798         }
3799
3800         printk("\n");
3801         return 0;
3802 }
3803
3804
3805
3806 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3807 {
3808         comedi_device *dev=(comedi_device *)arg;
3809
3810         if(dir){
3811                 ni_writeb(data,Port_A+2*port);
3812                 return 0;
3813         }else{
3814                 return ni_readb(Port_A+2*port);
3815         }
3816 }
3817
3818 /*
3819         presents the EEPROM as a subdevice
3820 */
3821
3822 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3823         comedi_insn *insn,lsampl_t *data)
3824 {
3825         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3826
3827         return 1;
3828 }
3829
3830 /*
3831         reads bytes out of eeprom
3832 */
3833
3834 static int ni_read_eeprom(comedi_device *dev,int addr)
3835 {
3836         int bit;
3837         int bitstring;
3838
3839         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3840         ni_writeb(0x04,Serial_Command);
3841         for(bit=0x8000;bit;bit>>=1){
3842                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3843                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3844         }
3845         bitstring=0;
3846         for(bit=0x80;bit;bit>>=1){
3847                 ni_writeb(0x04,Serial_Command);
3848                 ni_writeb(0x05,Serial_Command);
3849                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3850         }
3851         ni_writeb(0x00,Serial_Command);
3852
3853         return bitstring;
3854 }
3855
3856 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3857         comedi_insn *insn,lsampl_t *data)
3858 {
3859         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3860
3861         return 1;
3862 }
3863
3864 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3865 {
3866         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3867         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3868         return 3;
3869 }
3870
3871 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3872         comedi_insn *insn, lsampl_t *data)
3873 {
3874         unsigned up_count, down_count;
3875         switch(data[0])
3876         {
3877         case INSN_CONFIG_PWM_OUTPUT:
3878                 switch(data[1])
3879                 {
3880                 case TRIG_ROUND_NEAREST:
3881                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3882                         break;
3883                 case TRIG_ROUND_DOWN:
3884                         up_count = data[2] / devpriv->clock_ns;
3885                         break;
3886                 case TRIG_ROUND_UP:
3887                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3888                         break;
3889                 default:
3890                         return -EINVAL;
3891                         break;
3892                 }
3893                 switch(data[3])
3894                 {
3895                 case TRIG_ROUND_NEAREST:
3896                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3897                         break;
3898                 case TRIG_ROUND_DOWN:
3899                         down_count = data[4] / devpriv->clock_ns;
3900                         break;
3901                 case TRIG_ROUND_UP:
3902                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3903                         break;
3904                 default:
3905                         return -EINVAL;
3906                         break;
3907                 }
3908                 if(up_count * devpriv->clock_ns != data[2] ||
3909                         down_count * devpriv->clock_ns != data[4])
3910                 {
3911                         data[2] = up_count * devpriv->clock_ns;
3912                         data[4] = down_count * devpriv->clock_ns;
3913                         return -EAGAIN;
3914                 }
3915                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3916                 devpriv->pwm_up_count = up_count;
3917                 devpriv->pwm_down_count = down_count;
3918                 return 5;
3919                 break;
3920         case INSN_CONFIG_GET_PWM_OUTPUT:
3921                 return ni_get_pwm_config(dev, data);
3922                 break;
3923         default:
3924                 return -EINVAL;
3925                 break;
3926         }
3927         return 0;
3928 }
3929
3930 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3931         comedi_insn *insn, lsampl_t *data)
3932 {
3933         unsigned up_count, down_count;
3934         switch(data[0])
3935         {
3936         case INSN_CONFIG_PWM_OUTPUT:
3937                 switch(data[1])
3938                 {
3939                 case TRIG_ROUND_NEAREST:
3940                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3941                         break;
3942                 case TRIG_ROUND_DOWN:
3943                         up_count = data[2] / devpriv->clock_ns;
3944                         break;
3945                 case TRIG_ROUND_UP:
3946                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3947                         break;
3948                 default:
3949                         return -EINVAL;
3950                         break;
3951                 }
3952                 switch(data[3])
3953                 {
3954                 case TRIG_ROUND_NEAREST:
3955                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3956                         break;
3957                 case TRIG_ROUND_DOWN:
3958                         down_count = data[4] / devpriv->clock_ns;
3959                         break;
3960                 case TRIG_ROUND_UP:
3961                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3962                         break;
3963                 default:
3964                         return -EINVAL;
3965                         break;
3966                 }
3967                 if(up_count * devpriv->clock_ns != data[2] ||
3968                         down_count * devpriv->clock_ns != data[4])
3969                 {
3970                         data[2] = up_count * devpriv->clock_ns;
3971                         data[4] = down_count * devpriv->clock_ns;
3972                         return -EAGAIN;
3973                 }
3974                 ni_writel(up_count, Calibration_HighTime_6143);
3975                 devpriv->pwm_up_count = up_count;
3976                 ni_writel(down_count, Calibration_LowTime_6143);
3977                 devpriv->pwm_down_count = down_count;
3978                 return 5;
3979                 break;
3980         case INSN_CONFIG_GET_PWM_OUTPUT:
3981                 return ni_get_pwm_config(dev, data);
3982         default:
3983                 return -EINVAL;
3984                 break;
3985         }
3986         return 0;
3987 }
3988
3989 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3990 /*
3991         calibration subdevice
3992 */
3993 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3994         comedi_insn *insn,lsampl_t *data)
3995 {
3996         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3997
3998         return 1;
3999 }
4000
4001 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
4002         comedi_insn *insn,lsampl_t *data)
4003 {
4004         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4005
4006         return 1;
4007 }
4008
4009 static int pack_mb88341(int addr,int val,int *bitstring);
4010 static int pack_dac8800(int addr,int val,int *bitstring);
4011 static int pack_dac8043(int addr,int val,int *bitstring);
4012 static int pack_ad8522(int addr,int val,int *bitstring);
4013 static int pack_ad8804(int addr,int val,int *bitstring);
4014 static int pack_ad8842(int addr,int val,int *bitstring);
4015
4016 struct caldac_struct{
4017         int n_chans;
4018         int n_bits;
4019         int (*packbits)(int,int,int *);
4020 };
4021
4022 static struct caldac_struct caldacs[] = {
4023         [mb88341] = { 12, 8, pack_mb88341 },
4024         [dac8800] = { 8, 8, pack_dac8800 },
4025         [dac8043] = { 1, 12, pack_dac8043 },
4026         [ad8522]  = { 2, 12, pack_ad8522 },
4027         [ad8804] = { 12, 8, pack_ad8804 },
4028         [ad8842] = { 8, 8, pack_ad8842 },
4029         [ad8804_debug] = { 16, 8, pack_ad8804 },
4030 };
4031
4032 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
4033 {
4034         int i,j;
4035         int n_dacs;
4036         int n_chans=0;
4037         int n_bits;
4038         int diffbits=0;
4039         int type;
4040         int chan;
4041
4042         type = boardtype.caldac[0];
4043         if(type==caldac_none)return;
4044         n_bits=caldacs[type].n_bits;
4045         for(i=0;i<3;i++){
4046                 type = boardtype.caldac[i];
4047                 if(type==caldac_none)break;
4048                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
4049                 n_chans+=caldacs[type].n_chans;
4050         }
4051         n_dacs=i;
4052         s->n_chan=n_chans;
4053
4054         if(diffbits){
4055
4056                 if(n_chans>MAX_N_CALDACS){
4057                         printk("BUG! MAX_N_CALDACS too small\n");
4058                 }
4059                 s->maxdata_list=devpriv->caldac_maxdata_list;
4060                 chan=0;
4061                 for(i=0;i<n_dacs;i++){
4062                         type = boardtype.caldac[i];
4063                         for(j=0;j<caldacs[type].n_chans;j++){
4064                                 s->maxdata_list[chan]=
4065                                         (1<<caldacs[type].n_bits)-1;
4066                                 chan++;
4067                         }
4068                 }
4069
4070                 for( chan = 0; chan < s->n_chan; chan++ )
4071                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
4072         }else{
4073                 type = boardtype.caldac[0];
4074                 s->maxdata=(1<<caldacs[type].n_bits)-1;
4075
4076                 for( chan = 0; chan < s->n_chan; chan++ )
4077                         ni_write_caldac( dev, i, s->maxdata / 2 );
4078         }
4079 }
4080
4081 static void ni_write_caldac(comedi_device *dev,int addr,int val)
4082 {
4083         unsigned int loadbit=0,bits=0,bit,bitstring=0;
4084         int i;
4085         int type;
4086
4087         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4088         if( devpriv->caldacs[ addr ] == val ) return;
4089         devpriv->caldacs[ addr ] = val;
4090
4091         for(i=0;i<3;i++){
4092                 type = boardtype.caldac[i];
4093                 if(type==caldac_none)break;
4094                 if(addr<caldacs[type].n_chans){
4095                         bits=caldacs[type].packbits(addr,val,&bitstring);
4096                         loadbit=SerDacLd(i);
4097                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4098                         break;
4099                 }
4100                 addr-=caldacs[type].n_chans;
4101         }
4102
4103         for(bit=1<<(bits-1);bit;bit>>=1){
4104                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
4105                 comedi_udelay(1);
4106                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
4107                 comedi_udelay(1);
4108         }
4109         ni_writeb(loadbit,Serial_Command);
4110         comedi_udelay(1);
4111         ni_writeb(0,Serial_Command);
4112 }
4113
4114
4115
4116 static int pack_mb88341(int addr,int val,int *bitstring)
4117 {
4118         /*
4119            Fujitsu MB 88341
4120            Note that address bits are reversed.  Thanks to
4121            Ingo Keen for noticing this.
4122
4123            Note also that the 88341 expects address values from
4124            1-12, whereas we use channel numbers 0-11.  The NI
4125            docs use 1-12, also, so be careful here.
4126         */
4127         addr++;
4128         *bitstring=((addr&0x1)<<11) |
4129                   ((addr&0x2)<<9)  |
4130                   ((addr&0x4)<<7)  |
4131                   ((addr&0x8)<<5)  |
4132                   (val&0xff);
4133         return 12;
4134 }
4135
4136 static int pack_dac8800(int addr,int val,int *bitstring)
4137 {
4138         *bitstring=((addr&0x7)<<8)|(val&0xff);
4139         return 11;
4140 }
4141
4142 static int pack_dac8043(int addr,int val,int *bitstring)
4143 {
4144         *bitstring=val&0xfff;
4145         return 12;
4146 }
4147
4148 static int pack_ad8522(int addr,int val,int *bitstring)
4149 {
4150         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
4151         return 16;
4152 }
4153
4154 static int pack_ad8804(int addr,int val,int *bitstring)
4155 {
4156         *bitstring=((addr&0xf)<<8) | (val&0xff);
4157         return 12;
4158 }
4159
4160 static int pack_ad8842(int addr,int val,int *bitstring)
4161 {
4162         *bitstring=((addr+1)<<8) | (val&0xff);
4163         return 12;
4164 }
4165
4166
4167 #if 0
4168 /*
4169  *      Read the GPCTs current value.
4170  */
4171 static int GPCT_G_Watch(comedi_device *dev, int chan)
4172 {
4173         unsigned int hi1,hi2,lo;
4174
4175         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4176         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4177
4178         devpriv->gpct_command[chan] |= G_Save_Trace;
4179         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
4180
4181         /* This procedure is used because the two registers cannot
4182          * be read atomically. */
4183         do{
4184                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4185                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4186                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4187         }while(hi1!=hi2);
4188
4189         return (hi1<<16)|lo;
4190 }
4191
4192 static void GPCT_Reset(comedi_device *dev, int chan)
4193 {
4194         int temp_ack_reg=0;
4195
4196         //printk("GPCT_Reset...");
4197         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4198
4199         switch (chan) {
4200                 case 0:
4201                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4202                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4203                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4204                         temp_ack_reg |= G0_Gate_Error_Confirm;
4205                         temp_ack_reg |= G0_TC_Error_Confirm;
4206                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4207                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4208                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4209
4210                         //problem...this interferes with the other ctr...
4211                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4212                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4213                         break;
4214                 case 1:
4215                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4216                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4217                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4218                         temp_ack_reg |= G1_Gate_Error_Confirm;
4219                         temp_ack_reg |= G1_TC_Error_Confirm;
4220                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4221                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4222                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4223
4224                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4225                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4226                         break;
4227         };
4228
4229         devpriv->gpct_mode[chan] = 0;
4230         devpriv->gpct_input_select[chan] = 0;
4231         devpriv->gpct_command[chan] = 0;
4232
4233         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4234
4235         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4236         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4237         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4238
4239         //printk("exit GPCT_Reset\n");
4240 }
4241
4242 #endif
4243
4244 static int ni_gpct_insn_config(comedi_device *dev, comedi_subdevice *s,
4245         comedi_insn *insn, lsampl_t *data)
4246 {
4247         struct ni_gpct *counter = s->private;
4248         return ni_tio_insn_config(counter, insn, data);
4249 }
4250
4251 static int ni_gpct_insn_read(comedi_device *dev, comedi_subdevice *s,
4252         comedi_insn *insn,lsampl_t *data)
4253 {
4254         struct ni_gpct *counter = s->private;
4255         return ni_tio_rinsn(counter, insn, data);
4256 }
4257
4258 static int ni_gpct_insn_write(comedi_device *dev, comedi_subdevice *s,
4259         comedi_insn *insn, lsampl_t *data)
4260 {
4261         struct ni_gpct *counter = s->private;
4262         return ni_tio_winsn(counter, insn, data);
4263 }
4264
4265 static int ni_gpct_cmd(comedi_device *dev, comedi_subdevice *s)
4266 {
4267 // XXX set M_Offset_GX_DMA_Config for m-series
4268 #ifdef PCIDMA
4269         struct ni_gpct *counter = s->private;
4270         const comedi_cmd *cmd = &s->async->cmd;
4271         int retval = ni_request_gpct_mite_channel(dev, counter->counter_index);
4272         if(retval)
4273         {
4274                 comedi_error(dev, "no dma channel available for use by counter");
4275                 return retval;
4276         }
4277         return ni_tio_cmd(counter, s->async);
4278 #else
4279         return -ENOTSUPP;
4280 #endif
4281 }
4282
4283 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
4284 {
4285         struct ni_gpct *counter = s->private;
4286         //XXX check chanlist_len == 1
4287         return ni_tio_cmdtest(counter);
4288 }
4289
4290 static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s)
4291 {
4292         struct ni_gpct *counter = s->private;
4293         int retval = ni_tio_cancel(counter);
4294         ni_release_gpct_mite_channel(dev, counter->counter_index);
4295         return retval;
4296 }
4297
4298 /*
4299  *
4300  *  Programmable Function Inputs
4301  *
4302  */
4303
4304 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4305 {
4306         unsigned pfi_reg_index;
4307         unsigned array_offset;
4308         if((source & 0x1f) != source) return -EINVAL;
4309         pfi_reg_index = 1 + chan / 3;
4310         array_offset = pfi_reg_index - 1;
4311         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4312         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4313         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4314         return 2;
4315 }
4316
4317 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4318 {
4319         // pre-m-series boards have fixed signals on pfi pins
4320         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4321         return 2;
4322 }
4323
4324 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4325 {
4326         if(boardtype.reg_type & ni_reg_m_series_mask)
4327                 return ni_m_series_set_pfi_routing(dev, chan, source);
4328         else
4329                 return ni_old_set_pfi_routing(dev, chan, source);
4330 }
4331
4332 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4333 {
4334         const unsigned array_offset = chan / 3;
4335         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4336 }
4337
4338 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4339 {
4340         // pre-m-series boards have fixed signals on pfi pins
4341         switch(chan)
4342         {
4343         case 0:
4344                 return NI_PFI_OUTPUT_AI_START1;
4345                 break;
4346         case 1:
4347                 return NI_PFI_OUTPUT_AI_START2;
4348                 break;
4349         case 2:
4350                 return NI_PFI_OUTPUT_AI_CONVERT;
4351                 break;
4352         case 3:
4353                 return NI_PFI_OUTPUT_G_SRC1;
4354                 break;
4355         case 4:
4356                 return NI_PFI_OUTPUT_G_GATE1;
4357                 break;
4358         case 5:
4359                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4360                 break;
4361         case 6:
4362                 return NI_PFI_OUTPUT_AO_START1;
4363                 break;
4364         case 7:
4365                 return NI_PFI_OUTPUT_AI_START_PULSE;
4366                 break;
4367         case 8:
4368                 return NI_PFI_OUTPUT_G_SRC0;
4369                 break;
4370         case 9:
4371                 return NI_PFI_OUTPUT_G_GATE0;
4372                 break;
4373         default:
4374                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4375                 break;
4376         }
4377         return 0;
4378 }
4379
4380 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4381 {
4382         if(boardtype.reg_type & ni_reg_m_series_mask)
4383                 return ni_m_series_get_pfi_routing(dev, chan);
4384         else
4385                 return ni_old_get_pfi_routing(dev, chan);
4386 }
4387
4388 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4389         comedi_insn *insn,lsampl_t *data)
4390 {
4391         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4392         {
4393                 data[1] = 0;
4394                 return 2;
4395         }
4396         if(data[0])
4397         {
4398                 s->state &= ~data[0];
4399                 s->state |= (data[0] & data[1]);
4400                 ni_writew(s->state, M_Offset_PFI_DO);
4401         }
4402         data[1] = ni_readw(M_Offset_PFI_DI);
4403         return 2;
4404 }
4405
4406 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4407         comedi_insn *insn,lsampl_t *data)
4408 {
4409         unsigned int chan;
4410
4411         if(insn->n < 1)return -EINVAL;
4412
4413         chan = CR_CHAN(insn->chanspec);
4414
4415         switch(data[0]){
4416         case COMEDI_OUTPUT:
4417                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4418                 break;
4419         case COMEDI_INPUT:
4420                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4421                 break;
4422         case INSN_CONFIG_DIO_QUERY:
4423                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4424                 return insn->n;
4425                 break;
4426         case INSN_CONFIG_SET_ROUTING:
4427                 return ni_set_pfi_routing(dev, chan, data[1]);
4428                 break;
4429         case INSN_CONFIG_GET_ROUTING:
4430                 data[1] = ni_get_pfi_routing(dev, chan);
4431                 return 2;
4432                 break;
4433         default:
4434                 return -EINVAL;
4435         }
4436
4437         return 1;
4438 }
4439
4440 /*
4441  *
4442  *  NI RTSI Bus Functions
4443  *
4444  */
4445 static void ni_rtsi_init(comedi_device *dev)
4446 {
4447         // Initialises the RTSI bus signal switch to a default state
4448
4449         // Set clock mode to internal
4450         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4451         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4452         {
4453                 rt_printk("ni_set_master_clock failed, bug?");
4454         }
4455         // default internal lines routing to RTSI bus lines
4456         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4457                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4458                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4459                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4460         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4461                 RTSI_Trig_A_Output_Register);
4462         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4463                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4464                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4465         if(boardtype.reg_type & ni_reg_m_series_mask)
4466                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4467         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4468                 RTSI_Trig_B_Output_Register);
4469
4470         // Sets the source and direction of the 4 on board lines
4471 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4472 }
4473
4474 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4475         comedi_insn *insn,lsampl_t *data)
4476 {
4477         if(insn->n != 2) return -EINVAL;
4478
4479         data[1] = 0;
4480
4481         return 2;
4482 }
4483
4484 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4485  * given an arbitrary frequency input clock */
4486 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4487         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4488 {
4489         unsigned div;
4490         unsigned best_div = 1;
4491         static const unsigned max_div = 0x10;
4492         unsigned mult;
4493         unsigned best_mult = 1;
4494         static const unsigned max_mult = 0x100;
4495         static const unsigned pico_per_nano = 1000;
4496
4497         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4498         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4499          * 20 MHz for most timing clocks */
4500         static const unsigned target_picosec = 12500;
4501         static const unsigned fudge_factor_80_to_20Mhz = 4;
4502         int best_period_picosec = 0;
4503         for(div = 1; div <= max_div; ++div)
4504         {
4505                 for(mult = 1; mult <= max_mult; ++mult)
4506                 {
4507                         unsigned new_period_ps = (reference_picosec * div) / mult;
4508                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4509                         {
4510                                 best_period_picosec = new_period_ps;
4511                                 best_div = div;
4512                                 best_mult = mult;
4513                         }
4514                 }
4515         }
4516         if(best_period_picosec == 0)
4517         {
4518                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4519                 return -EIO;
4520         }
4521         *freq_divider = best_div;
4522         *freq_multiplier = best_mult;
4523         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4524         return 0;
4525 }
4526
4527 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4528 {
4529         if(boardtype.reg_type & ni_reg_m_series_mask) return 8;
4530         else return 7;
4531 }
4532
4533 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4534 {
4535         static const unsigned min_period_ns = 50;
4536         static const unsigned max_period_ns = 1000;
4537         static const unsigned timeout = 1000;
4538         unsigned pll_control_bits;
4539         unsigned freq_divider;
4540         unsigned freq_multiplier;
4541         unsigned i;
4542         int retval;
4543         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4544         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4545         if(period_ns < min_period_ns || period_ns > max_period_ns)
4546         {
4547                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4548                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4549                 return -EINVAL;
4550         }
4551         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4552         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4553         pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4554         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4555         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4556         switch(source)
4557         {
4558         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4559                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4560                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4561                         &freq_multiplier, &devpriv->clock_ns);
4562                 if(retval < 0) return retval;
4563                 break;
4564         case NI_MIO_PLL_PXI10_CLOCK:
4565                 /* pxi clock is 10MHz */
4566                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4567                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4568                         &freq_multiplier, &devpriv->clock_ns);
4569                 if(retval < 0) return retval;
4570                 break;
4571         default:
4572                 {
4573                         unsigned rtsi_channel;
4574                         static const unsigned max_rtsi_channel = 7;
4575                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4576                         {
4577                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4578                                 {
4579                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4580                                         break;
4581                                 }
4582                         }
4583                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4584                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4585                                 &freq_multiplier, &devpriv->clock_ns);
4586                         if(retval < 0) return retval;
4587                 }
4588                 break;
4589         }
4590         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4591         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4592 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4593 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4594         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4595         devpriv->clock_source = source;
4596         /* it seems to typically take a few hundred microseconds for PLL to lock */
4597         for(i = 0; i < timeout; ++i)
4598         {
4599                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4600                 {
4601                         break;
4602                 }
4603                 udelay(1);
4604         }
4605         if(i == timeout)
4606         {
4607                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4608                         __FUNCTION__, source, period_ns);
4609                 return -ETIMEDOUT;
4610         }
4611         return 3;
4612 }
4613
4614 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4615 {
4616         if(source == NI_MIO_INTERNAL_CLOCK)
4617         {
4618                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4619                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4620                 devpriv->clock_ns = 50;
4621                 if(boardtype.reg_type & ni_reg_m_series_mask)
4622                 {
4623                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4624                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4625                         ni_writew(0, M_Offset_PLL_Control);
4626                 }
4627                 devpriv->clock_source = source;
4628         }else
4629         {
4630                 if(boardtype.reg_type & ni_reg_m_series_mask)
4631                 {
4632                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4633                 }else
4634                 {
4635                         if(source == NI_MIO_RTSI_CLOCK)
4636                         {
4637                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4638                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4639                                 if(devpriv->clock_ns == 0)
4640                                 {
4641                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4642                                                 __FUNCTION__);
4643                                         return -EINVAL;
4644                                 }else
4645                                 {
4646                                         devpriv->clock_ns = period_ns;
4647                                 }
4648                                 devpriv->clock_source = source;
4649                         }else
4650                                 return -EINVAL;
4651                 }
4652         }
4653         return 3;
4654 }
4655
4656 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4657 {
4658         if(chan >= num_configurable_rtsi_channels(dev))
4659         {
4660                 if(chan == old_RTSI_clock_channel)
4661                 {
4662                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4663                         else
4664                         {
4665                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4666                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4667                                 return 0;
4668                         }
4669                 }
4670                 return 0;
4671         }
4672         switch(source)
4673         {
4674         case NI_RTSI_OUTPUT_ADR_START1:
4675         case NI_RTSI_OUTPUT_ADR_START2:
4676         case NI_RTSI_OUTPUT_SCLKG:
4677         case NI_RTSI_OUTPUT_DACUPDN:
4678         case NI_RTSI_OUTPUT_DA_START1:
4679         case NI_RTSI_OUTPUT_G_SRC0:
4680         case NI_RTSI_OUTPUT_G_GATE0:
4681         case NI_RTSI_OUTPUT_RGOUT0:
4682         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4683                 return 1;
4684                 break;
4685         case NI_RTSI_OUTPUT_RTSI_OSC:
4686                 if(boardtype.reg_type & ni_reg_m_series_mask)
4687                         return 1;
4688                 else return 0;
4689                 break;
4690         default:
4691                 return 0;
4692                 break;
4693         }
4694 }
4695
4696 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4697 {
4698         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4699         if(chan < 4)
4700         {
4701                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4702                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4703                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4704                         RTSI_Trig_A_Output_Register);
4705         }else if(chan < 8)
4706         {
4707                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4708                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4709                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4710                         RTSI_Trig_B_Output_Register);
4711         }
4712         return 2;
4713 }
4714
4715 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4716 {
4717         if(chan < 4)
4718         {
4719                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4720         }else if(chan < num_configurable_rtsi_channels(dev))
4721         {
4722                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4723         }else
4724         {
4725                 if(chan == old_RTSI_clock_channel)
4726                         return NI_RTSI_OUTPUT_RTSI_OSC;
4727                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4728                 return 0;
4729         }
4730 }
4731
4732 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4733         comedi_insn *insn,lsampl_t *data)
4734 {
4735         unsigned int chan = CR_CHAN(insn->chanspec);
4736         switch(data[0]){
4737         case INSN_CONFIG_DIO_OUTPUT:
4738                 if(chan < num_configurable_rtsi_channels(dev))
4739                 {
4740                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4741                 }else if(chan == old_RTSI_clock_channel)
4742                 {
4743                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4744                 }
4745                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4746                 break;
4747         case INSN_CONFIG_DIO_INPUT:
4748                 if(chan < num_configurable_rtsi_channels(dev))
4749                 {
4750                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4751                 }else if(chan == old_RTSI_clock_channel)
4752                 {
4753                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4754                 }
4755                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4756                 break;
4757         case INSN_CONFIG_DIO_QUERY:
4758                 if(chan < num_configurable_rtsi_channels(dev))
4759                 {
4760                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0)) ?
4761                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4762                 }else if(chan == old_RTSI_clock_channel)
4763                 {
4764                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4765                 }
4766                 return 2;
4767                 break;
4768         case INSN_CONFIG_SET_CLOCK_SRC:
4769                 return ni_set_master_clock(dev, data[1], data[2]);
4770                 break;
4771         case INSN_CONFIG_GET_CLOCK_SRC:
4772                 data[1] = devpriv->clock_source;
4773                 data[2] = devpriv->clock_ns;
4774                 return 3;
4775                 break;
4776         case INSN_CONFIG_SET_ROUTING:
4777                 return ni_set_rtsi_routing(dev, chan, data[1]);
4778                 break;
4779         case INSN_CONFIG_GET_ROUTING:
4780                 data[1] = ni_get_rtsi_routing(dev, chan);
4781                 return 2;
4782                 break;
4783         default:
4784                 return -EINVAL;
4785                 break;
4786         }
4787         return 1;
4788 }
4789
4790 static int cs5529_wait_for_idle(comedi_device *dev)
4791 {
4792         unsigned short status;
4793         const int timeout = HZ;
4794         int i;
4795
4796         for(i = 0; i < timeout; i++)
4797         {
4798                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4799                 if((status & CSS_ADC_BUSY) == 0)
4800                 {
4801                         break;
4802                 }
4803                 set_current_state(TASK_INTERRUPTIBLE);
4804                 if(schedule_timeout(1))
4805                 {
4806                         return -EIO;
4807                 }
4808         }
4809 //printk("looped %i times waiting for idle\n", i);
4810         if(i == timeout)
4811         {
4812                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4813                 return -ETIME;
4814         }
4815         return 0;
4816 }
4817
4818 static void cs5529_command(comedi_device *dev, unsigned short value)
4819 {
4820         static const int timeout = 100;
4821         int i;
4822
4823         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4824         /* give time for command to start being serially clocked into cs5529.
4825          * this insures that the CSS_ADC_BUSY bit will get properly
4826          * set before we exit this function.
4827         */
4828         for(i = 0; i < timeout; i++)
4829         {
4830                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4831                         break;
4832                 comedi_udelay(1);
4833         }
4834 //printk("looped %i times writing command to cs5529\n", i);
4835         if(i == timeout)
4836         {
4837                 comedi_error(dev, "possible problem - never saw adc go busy?");
4838         }
4839 }
4840
4841 /* write to cs5529 register */
4842 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4843 {
4844         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4845         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4846         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4847         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4848         if(cs5529_wait_for_idle(dev))
4849                 comedi_error(dev, "time or signal in cs5529_config_write()");
4850 }
4851
4852 /* read from cs5529 register */
4853 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4854 {
4855         unsigned int value;
4856
4857         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4858         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4859         if(cs5529_wait_for_idle(dev))
4860                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4861         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4862         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4863         return value;
4864 }
4865
4866 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4867 {
4868         int retval;
4869         unsigned short status;
4870
4871         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4872         retval = cs5529_wait_for_idle(dev);
4873         if(retval)
4874         {
4875                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4876                 return -ETIME;
4877         }
4878         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4879         if(status & CSS_OSC_DETECT)
4880         {
4881                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4882                 return -EIO;
4883         }
4884         if(status & CSS_OVERRANGE)
4885         {
4886                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4887         }
4888         if(data)
4889         {
4890                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4891                 /* cs5529 returns 16 bit signed data in bipolar mode */
4892                 *data ^= (1 << 15);
4893         }
4894         return 0;
4895 }
4896
4897 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4898 {
4899         int n, retval;
4900         unsigned short sample;
4901         unsigned int channel_select;
4902         const unsigned int INTERNAL_REF = 0x1000;
4903
4904         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4905          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4906          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4907         if(insn->chanspec & CR_ALT_SOURCE)
4908                 channel_select = INTERNAL_REF;
4909         else
4910                 channel_select = CR_CHAN(insn->chanspec);
4911         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4912
4913         for(n = 0; n < insn->n; n++)
4914         {
4915                 retval = cs5529_do_conversion(dev, &sample);
4916                 if(retval < 0) return retval;
4917                 data[n] = sample;
4918         }
4919         return insn->n;
4920 }
4921
4922 static int init_cs5529(comedi_device *dev)
4923 {
4924         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4925
4926 #if 1
4927         /* do self-calibration */
4928         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4929         /* need to force a conversion for calibration to run */
4930         cs5529_do_conversion(dev, NULL);
4931 #else
4932         /* force gain calibration to 1 */
4933         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4934         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4935         if(cs5529_wait_for_idle(dev))
4936                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4937 #endif
4938         if(0)
4939         {
4940                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4941                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4942                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4943         }
4944         return 0;
4945 }
4946
4947