comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222
 223 static void ni_rtsi_init(comedi_device *dev);
 224 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 225         comedi_insn *insn,lsampl_t *data);
 226 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 227         comedi_insn *insn,lsampl_t *data);
 228
 229 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 230 static int ni_read_eeprom(comedi_device *dev,int addr);
 231
 232 #ifdef DEBUG_STATUS_A
 233 static void ni_mio_print_status_a(int status);
 234 #else
 235 #define ni_mio_print_status_a(a)
 236 #endif
 237 #ifdef DEBUG_STATUS_B
 238 static void ni_mio_print_status_b(int status);
 239 #else
 240 #define ni_mio_print_status_b(a)
 241 #endif
 242
 243 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 244 #ifndef PCIDMA
 245 static void ni_handle_fifo_half_full(comedi_device *dev);
 246 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 247 #endif
 248 static void ni_handle_fifo_dregs(comedi_device *dev);
 249 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 250         unsigned int trignum);
 251 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 252         unsigned int *list);
 253 static void shutdown_ai_command( comedi_device *dev );
 254
 255 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 256         unsigned int trignum);
 257
 258 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 259
 260 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 261
 262 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode);
 263
 264
 265 /*GPCT function def's*/
 266 static int GPCT_G_Watch(comedi_device *dev, int chan);
 267
 268 static void GPCT_Reset(comedi_device *dev, int chan);
 269 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 270 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 271 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 272 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 273 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 274 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 275 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 276 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 277
 278 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 279         comedi_insn *insn,lsampl_t *data);
 280 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 281         comedi_insn *insn,lsampl_t *data);
 282 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 283         comedi_insn *insn,lsampl_t *data);
 284
 285 static int init_cs5529(comedi_device *dev);
 286 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 287 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 288 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 289 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 290
 291 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 292         comedi_insn *insn,lsampl_t *data);
 293 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 294         comedi_insn *insn, lsampl_t *data);
 295
 296 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 297
 298 enum aimodes
 299 {
 300         AIMODE_NONE = 0,
 301         AIMODE_HALF_FULL = 1,
 302         AIMODE_SCAN = 2,
 303         AIMODE_SAMPLE = 3,
 304 };
 305
 306 #define SERIAL_DISABLED         0
 307 #define SERIAL_600NS            600
 308 #define SERIAL_1_2US            1200
 309 #define SERIAL_10US                     10000
 310
 311 static const int num_adc_stages_611x = 3;
 312
 313 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 314         unsigned int m_status);
 315 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 316         unsigned int m_status);
 317 static void get_last_sample_611x( comedi_device *dev );
 318 static void get_last_sample_6143( comedi_device *dev );
 319 #ifdef PCIDMA
 320 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 321 static int ni_ai_drain_dma(comedi_device *dev );
 322 #endif
 323
 324 static void ni_flush_ai_fifo(comedi_device *dev){
 325         if(boardtype.reg_type == ni_reg_6143){
 326                 // Flush the 6143 data FIFO
 327                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 328                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 329                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 330         }
 331         else {
 332                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 333         }
 334 }
 335
 336 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 337 {
 338         devpriv->stc_writew(dev, data >> 16, reg);
 339         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 340 }
 341
 342 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 343 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 344 {
 345         unsigned long flags;
 346
 347         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 348         ni_writew(addr,AO_Window_Address_611x);
 349         ni_writew(data,AO_Window_Data_611x);
 350         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 351 }
 352
 353 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 354 {
 355         unsigned long flags;
 356
 357         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 358         ni_writew(addr,AO_Window_Address_611x);
 359         ni_writel(data,AO_Window_Data_611x);
 360         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 361 }
 362
 363 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 364 {
 365         unsigned long flags;
 366         unsigned short data;
 367
 368         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 369         ni_writew(addr, AO_Window_Address_611x);
 370         data = ni_readw(AO_Window_Data_611x);
 371         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 372         return data;
 373 }
 374
 375 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 376 * share registers (such as Interrupt_A_Register) without interfering with
 377 * each other.
 378 *
 379 * NOTE: the switch/case statements are optimized out for a constant argument
 380 * so this is actually quite fast---  If you must wrap another function around this
 381 * make it inline to avoid a large speed penalty.
 382 *
 383 * value should only be 1 or 0.
 384 */
 385 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 386 {
 387         unsigned long flags;
 388
 389         comedi_spin_lock_irqsave( &devpriv->window_lock, flags );
 390         switch (reg){
 391                 case Interrupt_A_Enable_Register:
 392                         if(value)
 393                                 devpriv->int_a_enable_reg |= bits;
 394                         else
 395                                 devpriv->int_a_enable_reg &= ~bits;
 396                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 397                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 398                         break;
 399                 case Interrupt_B_Enable_Register:
 400                         if(value)
 401                                 devpriv->int_b_enable_reg |= bits;
 402                         else
 403                                 devpriv->int_b_enable_reg &= ~bits;
 404                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 405                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 406                         break;
 407                 case IO_Bidirection_Pin_Register:
 408                         if(value)
 409                                 devpriv->io_bidirection_pin_reg |= bits;
 410                         else
 411                                 devpriv->io_bidirection_pin_reg &= ~bits;
 412                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 413                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 414                         break;
 415                 default:
 416                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 417                         rt_printk("reg is %d\n",reg);
 418                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 419                         break;
 420         }
 421 }
 422
 423
 424 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 425 {
 426         comedi_device *dev=d;
 427         unsigned short a_status;
 428         unsigned short b_status;
 429         unsigned int m0_status;
 430         unsigned int m1_status;
 431         unsigned long flags;
 432 #ifdef PCIDMA
 433         struct mite_struct *mite = devpriv->mite;
 434 #endif
 435
 436         if(dev->attached == 0) return IRQ_NONE;
 437         // lock to avoid race with comedi_poll
 438         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 439         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 440         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 441 #ifdef PCIDMA
 442         m0_status=readl(mite->mite_io_addr + MITE_CHSR(AI_DMA_CHAN));
 443         m1_status=readl(mite->mite_io_addr + MITE_CHSR(AO_DMA_CHAN));
 444 #else
 445         m0_status = 0;
 446         m1_status = 0;
 447 #endif
 448
 449         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 450                 handle_a_interrupt(dev, a_status, m0_status);
 451         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 452                 handle_b_interrupt(dev, b_status, m1_status);
 453         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 454         return IRQ_HANDLED;
 455 }
 456
 457 #ifdef PCIDMA
 458 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 459 {
 460         int count;
 461         comedi_subdevice *s = dev->subdevices + 0;
 462         comedi_async *async = s->async;
 463         unsigned int nbytes, old_alloc_count;
 464         unsigned int bytes_per_scan = bytes_per_sample(s) * async->cmd.chanlist_len;
 465
 466         old_alloc_count = async->buf_write_alloc_count;
 467         // write alloc as much as we can
 468         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 469
 470         nbytes = mite_bytes_written_to_memory_lb(mite, AI_DMA_CHAN);
 471         rmb();
 472         if( (int)(mite_bytes_written_to_memory_ub(mite, AI_DMA_CHAN) - old_alloc_count) > 0 ){
 473                 rt_printk("ni_mio_common: DMA overwrite of free area\n");
 474                 ni_ai_reset(dev,s);
 475                 async->events |= COMEDI_CB_OVERFLOW;
 476                 return;
 477         }
 478
 479         count = nbytes - async->buf_write_count;
 480         if( count <= 0 ){
 481                 /* it's possible count will be negative due to
 482                  * conservative value returned by mite_bytes_transferred */
 483                 return;
 484         }
 485         comedi_buf_write_free(async, count);
 486
 487         async->scan_progress += count;
 488         if( async->scan_progress >= bytes_per_scan )
 489         {
 490                 async->scan_progress %= bytes_per_scan;
 491                 async->events |= COMEDI_CB_EOS;
 492         }
 493         async->events |= COMEDI_CB_BLOCK;
 494 }
 495
 496 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 497 {
 498         int count;
 499         comedi_subdevice *s = dev->subdevices + 1;
 500         comedi_async *async = s->async;
 501         u32 nbytes_ub, nbytes_lb;
 502         unsigned int new_write_count;
 503         u32 stop_count = async->cmd.stop_arg * sizeof(sampl_t);
 504
 505         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 506
 507         new_write_count = async->buf_write_count;
 508         mb();
 509         nbytes_lb = mite_bytes_read_from_memory_lb(mite, AO_DMA_CHAN);
 510         if(async->cmd.stop_src == TRIG_COUNT &&
 511                 (int) (nbytes_lb - stop_count) > 0)
 512                 nbytes_lb = stop_count;
 513         mb();
 514         nbytes_ub = mite_bytes_read_from_memory_ub(mite, AO_DMA_CHAN);
 515         if(async->cmd.stop_src == TRIG_COUNT &&
 516                 (int) (nbytes_ub - stop_count) > 0)
 517                 nbytes_ub = stop_count;
 518         if((int)(nbytes_ub - devpriv->last_buf_write_count) > 0){
 519                 rt_printk("ni_mio_common: DMA underrun\n");
 520                 ni_ao_reset(dev,s);
 521                 async->events |= COMEDI_CB_OVERFLOW;
 522                 return;
 523         }
 524         mb();
 525         devpriv->last_buf_write_count = new_write_count;
 526
 527         count = nbytes_lb - async->buf_read_count;
 528         if(count < 0){
 529                 return;
 530         }
 531         comedi_buf_read_free(async, count);
 532
 533         async->events |= COMEDI_CB_BLOCK;
 534 }
 535
 536 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 537 {
 538         static const int timeout = 10000;
 539         int i;
 540
 541         for(i = 0; i < timeout; i++)
 542         {
 543                 unsigned short b_status;
 544
 545                 b_status = devpriv->stc_readw(dev,  AO_Status_1_Register );
 546                 if( b_status & AO_FIFO_Half_Full_St )
 547                         break;
 548                 /* if we poll too often, the pci bus activity seems
 549                  to slow the dma transfer down */
 550                 comedi_udelay(10);
 551         }
 552         if( i == timeout )
 553         {
 554                 comedi_error(dev, "timed out waiting for dma load");
 555                 return -EPIPE;
 556         }
 557         return 0;
 558 }
 559
 560 #endif //PCIDMA
 561 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 562 {
 563         if(devpriv->aimode == AIMODE_SCAN)
 564         {
 565 #ifdef PCIDMA
 566                 static const int timeout = 10;
 567                 int i;
 568
 569                 for(i = 0; i < timeout; i++)
 570                 {
 571                         ni_sync_ai_dma(devpriv->mite, dev);
 572                         if((s->async->events & COMEDI_CB_EOS)) break;
 573                         comedi_udelay(1);
 574                 }
 575 #else
 576                 ni_handle_fifo_dregs(dev);
 577                 s->async->events |= COMEDI_CB_EOS;
 578 #endif
 579         }
 580         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 581         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 582                 shutdown_ai_command( dev );
 583                 ni_ai_reset(dev, s);
 584         }
 585 }
 586
 587 static void shutdown_ai_command( comedi_device *dev )
 588 {
 589         comedi_subdevice *s = dev->subdevices + 0;
 590
 591 #ifdef PCIDMA
 592         ni_ai_drain_dma( dev );
 593         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 594 #endif
 595         ni_handle_fifo_dregs(dev);
 596         get_last_sample_611x(dev);
 597         get_last_sample_6143(dev);
 598
 599         ni_set_bits(dev, Interrupt_A_Enable_Register,
 600                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 601                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 602                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 603                 AI_FIFO_Interrupt_Enable,0);
 604
 605         s->async->events |= COMEDI_CB_EOA;
 606 }
 607
 608 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 609         unsigned int m_status)
 610 {
 611         comedi_subdevice *s=dev->subdevices+0;
 612         unsigned short ack=0;
 613
 614         s->async->events = 0;
 615
 616 #ifdef DEBUG_INTERRUPT
 617         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 618                 status, m_status);
 619         ni_mio_print_status_a(status);
 620 #endif
 621
 622
 623 #ifdef PCIDMA
 624         /* Currently, mite.c requires us to handle LINKC and DONE */
 625         if(m_status & CHSR_LINKC){
 626                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 627                 ni_sync_ai_dma(devpriv->mite, dev);
 628         }
 629
 630         if(m_status & CHSR_DONE){
 631                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 632         }
 633
 634         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 635                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 636                 //mite_print_chsr(m_status);
 637                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 638                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 639                 //disable_irq(dev->irq);
 640         }
 641 #endif
 642
 643         /* test for all uncommon interrupt events at the same time */
 644         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 645                 if(status==0xffff){
 646                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 647                         /* we probably aren't even running a command now,
 648                          * so it's a good idea to be careful. */
 649                         if(s->subdev_flags&SDF_RUNNING){
 650                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 651                                 //comedi_event(dev,s,s->async->events);
 652                         }
 653                         return;
 654                 }
 655                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 656                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 657                                 status);
 658                         ni_mio_print_status_a(status);
 659
 660                         ni_ai_reset(dev,dev->subdevices);
 661
 662
 663                         shutdown_ai_command( dev );
 664
 665                         s->async->events |= COMEDI_CB_ERROR;
 666                         if(status & (AI_Overrun_St | AI_Overflow_St))
 667                                 s->async->events |= COMEDI_CB_OVERFLOW;
 668
 669                         comedi_event(dev,s,s->async->events);
 670
 671                         return;
 672                 }
 673                 if(status&AI_SC_TC_St){
 674 #ifdef DEBUG_INTERRUPT
 675                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 676 #endif
 677                         if(!devpriv->ai_continuous){
 678                                 shutdown_ai_command( dev );
 679                         }
 680                         ack|=AI_SC_TC_Interrupt_Ack;
 681                 }
 682                 if(status&AI_START1_St){
 683                         ack|=AI_START1_Interrupt_Ack;
 684                 }
 685         }
 686 #ifndef PCIDMA
 687         if(status&AI_FIFO_Half_Full_St){
 688                 int i;
 689                 static const int timeout = 10;
 690                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 691                  *fail to get the fifo less than half full, so loop to be sure.*/
 692                 for(i = 0; i < timeout; ++i)
 693                 {
 694                         ni_handle_fifo_half_full(dev);
 695                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 696                                 break;
 697                 }
 698         }
 699 #endif // !PCIDMA
 700
 701         if( (status & AI_STOP_St) ){
 702                 ni_handle_eos(dev, s);
 703                 /* we need to ack the START, also */
 704                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 705         }
 706 #if 0
 707         if(devpriv->aimode==AIMODE_SAMPLE){
 708                 ni_handle_fifo_dregs(dev);
 709
 710                 //s->async->events |= COMEDI_CB_SAMPLE;
 711         }
 712 #endif
 713         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 714
 715         comedi_event(dev,s,s->async->events);
 716
 717 #ifdef DEBUG_INTERRUPT
 718         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 719         if(status&Interrupt_A_St){
 720                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 721         }
 722 #endif
 723 }
 724
 725 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 726 {
 727         comedi_subdevice *s=dev->subdevices+1;
 728         //unsigned short ack=0;
 729 #ifdef DEBUG_INTERRUPT
 730         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 731                 b_status,m_status);
 732         ni_mio_print_status_b(b_status);
 733 #endif
 734
 735
 736 #ifdef PCIDMA
 737         /* Currently, mite.c requires us to handle LINKC and DONE */
 738         if(m_status & CHSR_LINKC){
 739                 mite_handle_b_linkc(devpriv->mite, dev);
 740         }
 741
 742         if(m_status & CHSR_DONE){
 743                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 744         }
 745
 746         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 747                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 748                 //mite_print_chsr(m_status);
 749                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 750                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 751        }
 752 #endif
 753
 754         if(b_status==0xffff)return;
 755         if(b_status&AO_Overrun_St){
 756                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 757                 ni_ao_reset(dev,s);
 758                 s->async->events |= COMEDI_CB_OVERFLOW;
 759         }
 760
 761         if(b_status&AO_BC_TC_St){
 762                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 763                 ni_ao_reset(dev,s);
 764                 s->async->events |= COMEDI_CB_EOA;
 765         }
 766
 767 #ifndef PCIDMA
 768         if(b_status&AO_FIFO_Request_St){
 769                 int ret;
 770
 771                 ret = ni_ao_fifo_half_empty(dev,s);
 772                 if(!ret){
 773                         rt_printk("ni_mio_common: AO buffer underrun\n");
 774                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 775                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 776                         s->async->events |= COMEDI_CB_OVERFLOW;
 777                 }
 778         }
 779 #endif
 780
 781         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 782         if(b_status&Interrupt_B_St){
 783                 if(b_status&AO_FIFO_Request_St){
 784                         rt_printk("ni_mio_common: AO buffer underrun\n");
 785                 }
 786                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 787                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 788                 ni_ao_reset(dev,s);
 789                 s->async->events |= COMEDI_CB_OVERFLOW;
 790         }
 791
 792         comedi_event(dev,s,s->async->events);
 793 }
 794
 795 #ifdef DEBUG_STATUS_A
 796 static char *status_a_strings[]={
 797         "passthru0","fifo","G0_gate","G0_TC",
 798         "stop","start","sc_tc","start1",
 799         "start2","sc_tc_error","overflow","overrun",
 800         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 801 };
 802
 803 static void ni_mio_print_status_a(int status)
 804 {
 805         int i;
 806
 807         rt_printk("A status:");
 808         for(i=15;i>=0;i--){
 809                 if(status&(1<<i)){
 810                         rt_printk(" %s",status_a_strings[i]);
 811                 }
 812         }
 813         rt_printk("\n");
 814 }
 815 #endif
 816
 817 #ifdef DEBUG_STATUS_B
 818 static char *status_b_strings[]={
 819         "passthru1","fifo","G1_gate","G1_TC",
 820         "UI2_TC","UPDATE","UC_TC","BC_TC",
 821         "start1","overrun","start","bc_tc_error",
 822         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 823 };
 824
 825 static void ni_mio_print_status_b(int status)
 826 {
 827         int i;
 828
 829         rt_printk("B status:");
 830         for(i=15;i>=0;i--){
 831                 if(status&(1<<i)){
 832                         rt_printk(" %s",status_b_strings[i]);
 833                 }
 834         }
 835         rt_printk("\n");
 836 }
 837 #endif
 838
 839 #ifndef PCIDMA
 840
 841 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 842 {
 843         comedi_async *async = s->async;
 844         comedi_cmd *cmd = &async->cmd;
 845         int chan;
 846         int i;
 847         sampl_t d;
 848         u32 packed_data;
 849         int range;
 850         int err = 1;
 851
 852         chan = async->cur_chan;
 853         for(i=0;i<n;i++){
 854                 err &= comedi_buf_get(async, &d);
 855                 if(err == 0) break;
 856
 857                 range = CR_RANGE(cmd->chanlist[chan]);
 858
 859                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 860                 {
 861                         packed_data = d & 0xffff;
 862                         /* 6711 only has 16 bit wide ao fifo */
 863                         if(boardtype.reg_type != ni_reg_6711)
 864                         {
 865                                 err &= comedi_buf_get(async, &d);
 866                                 if(err == 0) break;
 867                                 chan++;
 868                                 i++;
 869                                 packed_data |= ( d << 16 ) & 0xffff0000;
 870                         }
 871                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 872                 }else{
 873                         ni_writew(d, DAC_FIFO_Data);
 874                 }
 875                 chan++;
 876                 chan %= cmd->chanlist_len;
 877         }
 878         async->cur_chan = chan;
 879         if(err==0){
 880                 async->events |= COMEDI_CB_OVERFLOW;
 881         }
 882 }
 883
 884 /*
 885  *  There's a small problem if the FIFO gets really low and we
 886  *  don't have the data to fill it.  Basically, if after we fill
 887  *  the FIFO with all the data available, the FIFO is _still_
 888  *  less than half full, we never clear the interrupt.  If the
 889  *  IRQ is in edge mode, we never get another interrupt, because
 890  *  this one wasn't cleared.  If in level mode, we get flooded
 891  *  with interrupts that we can't fulfill, because nothing ever
 892  *  gets put into the buffer.
 893  *
 894  *  This kind of situation is recoverable, but it is easier to
 895  *  just pretend we had a FIFO underrun, since there is a good
 896  *  chance it will happen anyway.  This is _not_ the case for
 897  *  RT code, as RT code might purposely be running close to the
 898  *  metal.  Needs to be fixed eventually.
 899  */
 900 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 901 {
 902         int n;
 903
 904         n = comedi_buf_read_n_available(s);
 905         if(n==0){
 906                 s->async->events |= COMEDI_CB_OVERFLOW;
 907                 return 0;
 908         }
 909
 910         n /= sizeof(sampl_t);
 911         if(n > boardtype.ao_fifo_depth / 2)
 912                 n = boardtype.ao_fifo_depth / 2;
 913
 914         ni_ao_fifo_load(dev,s,n);
 915
 916         s->async->events |= COMEDI_CB_BLOCK;
 917
 918         return 1;
 919 }
 920
 921 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 922 {
 923         int n;
 924
 925         /* reset fifo */
 926         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
 927         if(boardtype.reg_type & ni_reg_6xxx_mask)
 928                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 929
 930         /* load some data */
 931         n = comedi_buf_read_n_available(s);
 932         if(n==0)return 0;
 933
 934         n /= sizeof(sampl_t);
 935         if(n > boardtype.ao_fifo_depth)
 936                 n = boardtype.ao_fifo_depth;
 937
 938         ni_ao_fifo_load(dev,s,n);
 939
 940         return n;
 941 }
 942
 943 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 944         int n)
 945 {
 946         comedi_async *async = s->async;
 947         int i;
 948
 949         if(boardtype.reg_type == ni_reg_611x){
 950                 sampl_t data[2];
 951                 u32 dl;
 952
 953                 for( i = 0; i < n / 2; i++ ){
 954                         dl=ni_readl(ADC_FIFO_Data_611x);
 955                         /* This may get the hi/lo data in the wrong order */
 956                         data[0] = (dl>>16) & 0xffff;
 957                         data[1] = dl & 0xffff;
 958                         cfc_write_array_to_buffer(s, data, sizeof(data));
 959                 }
 960                 /* Check if there's a single sample stuck in the FIFO */
 961                 if( n % 2){
 962                         dl=ni_readl(ADC_FIFO_Data_611x);
 963                         data[0] = dl & 0xffff;
 964                         cfc_write_to_buffer(s, data[0]);
 965                 }
 966         } else if(boardtype.reg_type == ni_reg_6143){
 967                 sampl_t data[2];
 968                 u32     dl;
 969
 970                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
 971                 for(i = 0; i < n / 2; i++){
 972                         dl = ni_readl(AIFIFO_Data_6143);
 973
 974                         data[0] = (dl >> 16) & 0xffff;
 975                         data[1] = dl & 0xffff;
 976                         cfc_write_array_to_buffer(s, data, sizeof(data));
 977                 }
 978                 if(n % 2){
 979                         /* Assume there is a single sample stuck in the FIFO */
 980                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
 981                         dl = ni_readl(AIFIFO_Data_6143);
 982                         data[0] = (dl >> 16) & 0xffff;
 983                         cfc_write_to_buffer(s, data[0]);
 984                 }
 985         } else{
 986                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
 987                 {
 988                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
 989                         async->events |= COMEDI_CB_ERROR;
 990                         return;
 991                 }
 992                 for(i = 0; i < n; i++){
 993                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
 994                 }
 995                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
 996                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
 997         }
 998 }
 999
1000 static void ni_handle_fifo_half_full(comedi_device *dev)
1001 {
1002         int n;
1003         comedi_subdevice *s=dev->subdevices+0;
1004
1005         n=boardtype.ai_fifo_depth/2;
1006
1007         ni_ai_fifo_read(dev,s,n);
1008 }
1009 #endif
1010
1011 #ifdef PCIDMA
1012 static int ni_ai_drain_dma(comedi_device *dev )
1013 {
1014         struct mite_struct *mite = devpriv->mite;
1015         int i;
1016         static const int timeout = 10000;
1017
1018         for( i = 0; i < timeout; i++ )
1019         {
1020                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1021                         mite_bytes_in_transit(mite, AI_DMA_CHAN) == 0)
1022                         break;
1023                 comedi_udelay(2);
1024         }
1025         if(i == timeout)
1026         {
1027                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1028                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1029                         mite_bytes_in_transit(mite, AI_DMA_CHAN), devpriv->stc_readw(dev, AI_Status_1_Register));
1030                 return -1;
1031         }
1032
1033         ni_sync_ai_dma( mite, dev );
1034
1035         return 0;
1036 }
1037 #endif
1038 /*
1039    Empties the AI fifo
1040 */
1041 static void ni_handle_fifo_dregs(comedi_device *dev)
1042 {
1043         comedi_subdevice *s=dev->subdevices+0;
1044         sampl_t data[2];
1045         u32 dl;
1046         short fifo_empty;
1047         int i;
1048
1049         if(boardtype.reg_type == ni_reg_611x){
1050                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1051                         dl=ni_readl(ADC_FIFO_Data_611x);
1052
1053                         /* This may get the hi/lo data in the wrong order */
1054                         data[0] = (dl>>16);
1055                         data[1] = (dl&0xffff);
1056                         cfc_write_array_to_buffer(s, data, sizeof(data));
1057                 }
1058         }else if(boardtype.reg_type == ni_reg_6143){
1059                 i = 0;
1060                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1061                         dl = ni_readl(AIFIFO_Data_6143);
1062
1063                         /* This may get the hi/lo data in the wrong order */
1064                         data[0] = (dl >> 16);
1065                         data[1] = (dl & 0xffff);
1066                         cfc_write_array_to_buffer(s, data, sizeof(data));
1067                         i += 2;
1068                 }
1069                 // Check if stranded sample is present
1070                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1071                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1072                         dl = ni_readl(AIFIFO_Data_6143);
1073                         data[0] = (dl >> 16) & 0xffff;
1074                         cfc_write_to_buffer(s, data[0]);
1075                 }
1076
1077         }else{
1078                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1079                 while(fifo_empty == 0)
1080                 {
1081                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1082                         {
1083                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1084                                 if(fifo_empty) break;
1085                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1086                         }
1087                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1088                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1089                 }
1090         }
1091 }
1092
1093 static void get_last_sample_611x( comedi_device *dev )
1094 {
1095         comedi_subdevice *s=dev->subdevices+0;
1096         sampl_t data;
1097         u32 dl;
1098
1099         if(boardtype.reg_type != ni_reg_611x) return;
1100
1101         /* Check if there's a single sample stuck in the FIFO */
1102         if(ni_readb(XXX_Status)&0x80){
1103                 dl=ni_readl(ADC_FIFO_Data_611x);
1104                 data = (dl&0xffff);
1105                 cfc_write_to_buffer(s, data);
1106         }
1107 }
1108
1109 static void get_last_sample_6143(comedi_device* dev)
1110 {
1111         comedi_subdevice*       s = dev->subdevices + 0;
1112         sampl_t                 data;
1113         u32                     dl;
1114
1115         if(boardtype.reg_type != ni_reg_6143) return;
1116
1117         /* Check if there's a single sample stuck in the FIFO */
1118         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1119                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1120                 dl = ni_readl(AIFIFO_Data_6143);
1121
1122                 /* This may get the hi/lo data in the wrong order */
1123                 data = (dl >> 16) & 0xffff;
1124                 cfc_write_to_buffer(s, data);
1125         }
1126 }
1127
1128 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1129         void *data, unsigned int num_bytes, unsigned int chan_index )
1130 {
1131         comedi_async *async = s->async;
1132         unsigned int i;
1133         unsigned int length = num_bytes / bytes_per_sample(s);
1134         sampl_t *array = data;
1135         lsampl_t *larray = data;
1136         for(i = 0; i < length; i++)
1137         {
1138 #ifdef PCIDMA
1139                 if(s->subdev_flags & SDF_LSAMPL)
1140                         larray[i] = le32_to_cpu(larray[i]);
1141                 else
1142                         array[i] = le16_to_cpu(array[i]);
1143 #endif
1144                 if(s->subdev_flags & SDF_LSAMPL)
1145                         larray[i] += devpriv->ai_offset[chan_index];
1146                 else
1147                         array[i] += devpriv->ai_offset[chan_index];
1148                 chan_index++;
1149                 chan_index %= async->cmd.chanlist_len;
1150         }
1151 }
1152
1153 #ifdef PCIDMA
1154
1155 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1156 {
1157         struct mite_struct *mite = devpriv->mite;
1158         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1159         comedi_subdevice *s = dev->subdevices + 0;
1160
1161         /* write alloc the entire buffer */
1162         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1163
1164         mite_chan->current_link = 0;
1165         mite_chan->dir = COMEDI_INPUT;
1166         switch(boardtype.reg_type)
1167         {
1168         case ni_reg_611x:
1169         case ni_reg_6143:
1170                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1171                 break;
1172         case ni_reg_m_series:
1173                 if(boardtype.adbits > 16)
1174                         mite_prep_dma(mite, AI_DMA_CHAN, 32, 32);
1175                 else
1176                         mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);       //guess
1177                 break;
1178         default:
1179                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1180                 break;
1181         };
1182         /*start the MITE*/
1183         mite_dma_arm(mite, AI_DMA_CHAN);
1184 }
1185
1186 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1187 {
1188         struct mite_struct *mite = devpriv->mite;
1189         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1190         comedi_subdevice *s = dev->subdevices + 1;
1191
1192         devpriv->last_buf_write_count = s->async->buf_write_count;
1193
1194         mite_chan->current_link = 0;
1195         mite_chan->dir = COMEDI_OUTPUT;
1196         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1197                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1198         else
1199                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1200
1201         /*start the MITE*/
1202         mite_dma_arm(mite, AO_DMA_CHAN);
1203 }
1204
1205 #endif // PCIDMA
1206
1207 /*
1208    used for both cancel ioctl and board initialization
1209
1210    this is pretty harsh for a cancel, but it works...
1211  */
1212
1213 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1214 {
1215 #ifdef PCIDMA
1216         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1217 #endif
1218         /* ai configuration */
1219         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1220
1221         ni_set_bits(dev, Interrupt_A_Enable_Register,
1222                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1223                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1224                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1225                 AI_FIFO_Interrupt_Enable,0);
1226
1227         ni_flush_ai_fifo(dev);
1228
1229         if(boardtype.reg_type != ni_reg_6143)
1230                 ni_writeb(0, Misc_Command);
1231
1232         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1233         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1234                 AI_Mode_1_Register);
1235         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1236         /* generate FIFO interrupts on non-empty */
1237         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1238         if(boardtype.reg_type == ni_reg_611x){
1239                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1240                         AI_SOC_Polarity |
1241                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1242                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1243                         AI_EXTMUX_CLK_Output_Select(0) |
1244                         AI_LOCALMUX_CLK_Output_Select(2) |
1245                         AI_SC_TC_Output_Select(3) |
1246                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1247         }else if(boardtype.reg_type == ni_reg_6143){
1248                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1249                         AI_SOC_Polarity |
1250                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1251                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1252                         AI_EXTMUX_CLK_Output_Select(0) |
1253                         AI_LOCALMUX_CLK_Output_Select(2) |
1254                         AI_SC_TC_Output_Select(3) |
1255                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1256         }else{
1257                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1258                         AI_SOC_Polarity |
1259                         AI_CONVERT_Pulse_Width |
1260                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1261                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1262                         AI_EXTMUX_CLK_Output_Select(0) |
1263                         AI_LOCALMUX_CLK_Output_Select(2) |
1264                         AI_SC_TC_Output_Select(3) |
1265                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1266         }
1267         /* the following registers should not be changed, because there
1268          * are no backup registers in devpriv.  If you want to change
1269          * any of these, add a backup register and other appropriate code:
1270          *      AI_Mode_1_Register
1271          *      AI_Mode_3_Register
1272          *      AI_Personal_Register
1273          *      AI_Output_Control_Register
1274         */
1275         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1276                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1277                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1278                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1279
1280         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1281
1282         return 0;
1283 }
1284
1285 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1286 {
1287         unsigned long flags = 0;
1288         int count;
1289
1290         // lock to avoid race with interrupt handler
1291         if(in_interrupt() == 0)
1292                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1293 #ifndef PCIDMA
1294         ni_handle_fifo_dregs(dev);
1295 #else
1296         ni_sync_ai_dma(devpriv->mite, dev);
1297 #endif
1298         count = s->async->buf_write_count - s->async->buf_read_count;
1299         if(in_interrupt() == 0)
1300                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1301
1302         return count;
1303 }
1304
1305
1306 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1307 {
1308         int i,n;
1309         const unsigned int mask = (1 << boardtype.adbits) - 1;
1310         unsigned signbits;
1311         unsigned short d;
1312         unsigned long dl;
1313
1314         ni_load_channelgain_list(dev,1,&insn->chanspec);
1315
1316         ni_flush_ai_fifo(dev);
1317
1318         signbits=devpriv->ai_offset[0];
1319         if(boardtype.reg_type == ni_reg_611x){
1320                 for(n=0; n < num_adc_stages_611x; n++){
1321                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1322                         comedi_udelay(1);
1323                 }
1324                 for(n=0; n<insn->n; n++){
1325                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1326                         /* The 611x has screwy 32-bit FIFOs. */
1327                         d = 0;
1328                         for(i=0; i<NI_TIMEOUT; i++){
1329                                 if(ni_readb(XXX_Status)&0x80)
1330                                 {
1331                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1332                                         break;
1333                                 }
1334                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1335                                 {
1336                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1337                                         break;
1338                                 }
1339                         }
1340                         if(i==NI_TIMEOUT){
1341                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1342                                 return -ETIME;
1343                         }
1344                         d += signbits;
1345                         data[ n ] = d;
1346                 }
1347         }else if(boardtype.reg_type == ni_reg_6143){
1348                 for(n = 0; n < insn->n; n++){
1349                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1350
1351                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1352                         dl = 0;
1353                         for(i = 0; i < NI_TIMEOUT; i++){
1354                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1355                                 {
1356                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1357                                         dl = ni_readl(AIFIFO_Data_6143);
1358                                         break;
1359                                 }
1360                         }
1361                         if(i == NI_TIMEOUT){
1362                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1363                                 return -ETIME;
1364                         }
1365                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1366                 }
1367         }else{
1368                 for(n=0;n<insn->n;n++){
1369                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1370                         for(i=0;i<NI_TIMEOUT;i++){
1371                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1372                                         break;
1373                         }
1374                         if(i==NI_TIMEOUT){
1375                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1376                                 return -ETIME;
1377                         }
1378                         if(boardtype.reg_type == ni_reg_m_series)
1379                         {
1380                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1381                         }else
1382                         {
1383                                 d = ni_readw(ADC_FIFO_Data_Register);
1384                                 d += signbits; /* subtle: needs to be short addition */
1385                                 data[n] = d;
1386                         }
1387                 }
1388         }
1389         return insn->n;
1390 }
1391
1392 void ni_prime_channelgain_list(comedi_device *dev)
1393 {
1394         int i;
1395         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1396         for(i = 0; i < NI_TIMEOUT; ++i)
1397         {
1398                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1399                 {
1400                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1401                         return;
1402                 }
1403                 comedi_udelay(1);
1404         }
1405         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1406 }
1407
1408 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1409         unsigned int *list)
1410 {
1411         unsigned int chan, range, aref;
1412         unsigned int i;
1413         unsigned config_bits = 0;
1414         unsigned offset;
1415         unsigned int dither;
1416         unsigned range_code;
1417
1418         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1419
1420 //      offset = 1 << (boardtype.adbits - 1);
1421         if((list[0] & CR_ALT_SOURCE))
1422         {
1423                 chan = CR_CHAN(list[0]);
1424                 range = CR_RANGE(list[0]);
1425                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1426                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1427                 unsigned bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1428                 bypass_bits |= chan;
1429                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1430                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1431                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1432                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1433                 if(dither)
1434                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1435                 // don't use 2's complement encoding
1436                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1437                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1438         }else
1439         {
1440                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1441         }
1442         offset = 0;
1443         for(i = 0; i < n_chan; i++)
1444         {
1445                 chan = CR_CHAN(list[i]);
1446                 aref = CR_AREF(list[i]);
1447                 range = CR_RANGE(list[i]);
1448                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1449
1450                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1451                 devpriv->ai_offset[i] = offset;
1452
1453                 switch( aref )
1454                 {
1455                         case AREF_DIFF:
1456                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1457                                 break;
1458                         case AREF_COMMON:
1459                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1460                                 break;
1461                         case AREF_GROUND:
1462                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1463                                 break;
1464                         case AREF_OTHER:
1465                                 break;
1466                 }
1467                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1468                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1469                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1470                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1471                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1472                 // don't use 2's complement encoding
1473                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1474                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1475         }
1476         ni_prime_channelgain_list(dev);
1477 }
1478
1479 /*
1480  * Notes on the 6110 and 6111:
1481  * These boards a slightly different than the rest of the series, since
1482  * they have multiple A/D converters.
1483  * From the driver side, the configuration memory is a
1484  * little different.
1485  * Configuration Memory Low:
1486  *   bits 15-9: same
1487  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1488  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1489  *       1001 gain=0.1 (+/- 50)
1490  *       1010 0.2
1491  *       1011 0.1
1492  *       0001 1
1493  *       0010 2
1494  *       0011 5
1495  *       0100 10
1496  *       0101 20
1497  *       0110 50
1498  * Configuration Memory High:
1499  *   bits 12-14: Channel Type
1500  *       001 for differential
1501  *       000 for calibration
1502  *   bit 11: coupling  (this is not currently handled)
1503  *       1 AC coupling
1504  *       0 DC coupling
1505  *   bits 0-2: channel
1506  *       valid channels are 0-3
1507  */
1508 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1509         unsigned int *list)
1510 {
1511         unsigned int chan,range,aref;
1512         unsigned int i;
1513         unsigned int hi,lo;
1514         unsigned offset;
1515         unsigned int dither;
1516
1517         if(boardtype.reg_type == ni_reg_m_series)
1518         {
1519                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1520                 return;
1521         }
1522         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1523                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1524                         // ready to go.
1525                         return;
1526                 }
1527                 devpriv->changain_state=1;
1528                 devpriv->changain_spec=list[0];
1529         }else{
1530                 devpriv->changain_state=0;
1531         }
1532
1533         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1534
1535         // Set up Calibration mode if required
1536         if(boardtype.reg_type == ni_reg_6143){
1537                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1538                         // Strobe Relay enable bit
1539                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1540                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1541                         devpriv->ai_calib_source_enabled = 1;
1542                         msleep_interruptible(100);      // Allow relays to change
1543                 }
1544                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1545                         // Strobe Relay disable bit
1546                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1547                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1548                         devpriv->ai_calib_source_enabled = 0;
1549                         msleep_interruptible(100);      // Allow relays to change
1550                 }
1551         }
1552
1553         offset=1<<(boardtype.adbits-1);
1554         for(i=0;i<n_chan;i++){
1555                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1556                         chan=devpriv->ai_calib_source;
1557                 }else{
1558                         chan=CR_CHAN(list[i]);
1559                 }
1560                 aref=CR_AREF(list[i]);
1561                 range=CR_RANGE(list[i]);
1562                 dither=((list[i]&CR_ALT_FILTER)!=0);
1563
1564                 /* fix the external/internal range differences */
1565                 range = ni_gainlkup[boardtype.gainlkup][range];
1566                 if(boardtype.reg_type == ni_reg_611x)
1567                         devpriv->ai_offset[i] = offset;
1568                 else
1569                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1570
1571                 hi = 0;
1572                 if( ( list[i] & CR_ALT_SOURCE ) )
1573                 {
1574                         if(boardtype.reg_type == ni_reg_611x)
1575                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1576                 }else
1577                 {
1578                         if(boardtype.reg_type == ni_reg_611x)
1579                                 aref = AREF_DIFF;
1580                         else if(boardtype.reg_type == ni_reg_6143)
1581                                 aref = AREF_OTHER;
1582                         switch( aref )
1583                         {
1584                                 case AREF_DIFF:
1585                                         hi |= AI_DIFFERENTIAL;
1586                                         break;
1587                                 case AREF_COMMON:
1588                                         hi |= AI_COMMON;
1589                                         break;
1590                                 case AREF_GROUND:
1591                                         hi |= AI_GROUND;
1592                                         break;
1593                                 case AREF_OTHER:
1594                                         break;
1595                         }
1596                 }
1597                 hi |= AI_CONFIG_CHANNEL( chan );
1598
1599                 ni_writew(hi,Configuration_Memory_High);
1600
1601                 if(boardtype.reg_type != ni_reg_6143){
1602                         lo = range;
1603                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1604                         if( dither ) lo |= AI_DITHER;
1605
1606                         ni_writew(lo,Configuration_Memory_Low);
1607                 }
1608         }
1609
1610         /* prime the channel/gain list */
1611         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1612                 ni_prime_channelgain_list(dev);
1613         }
1614 }
1615
1616 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode)
1617 {
1618         int divider;
1619         switch(round_mode)
1620         {
1621         case TRIG_ROUND_NEAREST:
1622         default:
1623                 divider = (*nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1624                 break;
1625         case TRIG_ROUND_DOWN:
1626                 divider = (*nanosec) / devpriv->clock_ns;
1627                 break;
1628         case TRIG_ROUND_UP:
1629                 divider=(*nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1630                 break;
1631         }
1632
1633         *nanosec = devpriv->clock_ns * divider;
1634         return divider - 1;
1635 }
1636
1637 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1638 {
1639         int err=0;
1640         int tmp;
1641         int sources;
1642
1643         /* step 1: make sure trigger sources are trivially valid */
1644
1645         tmp=cmd->start_src;
1646         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1647         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1648
1649         tmp=cmd->scan_begin_src;
1650         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1651         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1652
1653         tmp=cmd->convert_src;
1654         sources = TRIG_TIMER | TRIG_EXT;
1655         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1656         cmd->convert_src &= sources;
1657         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1658
1659         tmp=cmd->scan_end_src;
1660         cmd->scan_end_src &= TRIG_COUNT;
1661         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1662
1663         tmp=cmd->stop_src;
1664         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1665         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1666
1667         if(err)return 1;
1668
1669         /* step 2: make sure trigger sources are unique and mutually compatible */
1670
1671         /* note that mutual compatiblity is not an issue here */
1672         if(cmd->start_src!=TRIG_NOW &&
1673            cmd->start_src!=TRIG_INT &&
1674            cmd->start_src!=TRIG_EXT)err++;
1675         if(cmd->scan_begin_src!=TRIG_TIMER &&
1676            cmd->scan_begin_src!=TRIG_EXT &&
1677            cmd->scan_begin_src!=TRIG_OTHER)err++;
1678         if(cmd->convert_src!=TRIG_TIMER &&
1679            cmd->convert_src!=TRIG_EXT &&
1680            cmd->convert_src!=TRIG_NOW)err++;
1681         if(cmd->stop_src!=TRIG_COUNT &&
1682            cmd->stop_src!=TRIG_NONE)err++;
1683
1684         if(err)return 2;
1685
1686         /* step 3: make sure arguments are trivially compatible */
1687
1688         if(cmd->start_src==TRIG_EXT){
1689                 /* external trigger */
1690                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1691
1692                 if(tmp > 16) tmp = 16;
1693                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1694                 if(cmd->start_arg != tmp){
1695                         cmd->start_arg = tmp;
1696                         err++;
1697                 }
1698         }else{
1699                 if(cmd->start_arg!=0){
1700                         /* true for both TRIG_NOW and TRIG_INT */
1701                         cmd->start_arg=0;
1702                         err++;
1703                 }
1704         }
1705         if(cmd->scan_begin_src==TRIG_TIMER){
1706                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1707                         cmd->scan_begin_arg=boardtype.ai_speed;
1708                         err++;
1709                 }
1710                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1711                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1712                         err++;
1713                 }
1714         }else if(cmd->scan_begin_src==TRIG_EXT){
1715                 /* external trigger */
1716                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1717
1718                 if(tmp>16)tmp=16;
1719                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1720                 if(cmd->scan_begin_arg!=tmp){
1721                         cmd->scan_begin_arg = tmp;
1722                         err++;
1723                 }
1724         }else{ /* TRIG_OTHER */
1725                 if(cmd->scan_begin_arg){
1726                         cmd->scan_begin_arg=0;
1727                         err++;
1728                 }
1729         }
1730         if(cmd->convert_src==TRIG_TIMER){
1731                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1732                         if(cmd->convert_arg != 0){
1733                                 cmd->convert_arg = 0;
1734                                 err++;
1735                         }
1736                 }else{
1737                         if(cmd->convert_arg<boardtype.ai_speed){
1738                                 cmd->convert_arg=boardtype.ai_speed;
1739                                 err++;
1740                         }
1741                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1742                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1743                                 err++;
1744                         }
1745                 }
1746         }else if(cmd->convert_src == TRIG_EXT){
1747                 /* external trigger */
1748                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1749
1750                 if(tmp>16)tmp=16;
1751                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1752                 if(cmd->convert_arg!=tmp){
1753                         cmd->convert_arg = tmp;
1754                         err++;
1755                 }
1756         }else if(cmd->convert_src == TRIG_NOW){
1757                 if(cmd->convert_arg != 0){
1758                         cmd->convert_arg = 0;
1759                         err++;
1760                 }
1761         }
1762
1763         if(cmd->scan_end_arg!=cmd->chanlist_len){
1764                 cmd->scan_end_arg=cmd->chanlist_len;
1765                 err++;
1766         }
1767         if(cmd->stop_src==TRIG_COUNT){
1768                 unsigned int max_count = 0x01000000;
1769
1770                 if(boardtype.reg_type == ni_reg_611x )
1771                         max_count -= num_adc_stages_611x;
1772                 if(cmd->stop_arg > max_count){
1773                         cmd->stop_arg = max_count;
1774                         err++;
1775                 }
1776                 if(cmd->stop_arg < 1){
1777                         cmd->stop_arg = 1;
1778                         err++;
1779                 }
1780         }else{
1781                 /* TRIG_NONE */
1782                 if(cmd->stop_arg!=0){
1783                         cmd->stop_arg=0;
1784                         err++;
1785                 }
1786         }
1787
1788         if(err)return 3;
1789
1790         /* step 4: fix up any arguments */
1791
1792         if(cmd->scan_begin_src==TRIG_TIMER){
1793                 tmp=cmd->scan_begin_arg;
1794                 ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
1795                 if(tmp!=cmd->scan_begin_arg)err++;
1796         }
1797         if(cmd->convert_src==TRIG_TIMER){
1798                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1799                         tmp=cmd->convert_arg;
1800                         ni_ns_to_timer(dev, &cmd->convert_arg, cmd->flags&TRIG_ROUND_MASK);
1801                         if(tmp!=cmd->convert_arg)err++;
1802                         if(cmd->scan_begin_src==TRIG_TIMER &&
1803                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1804                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1805                                 err++;
1806                         }
1807                 }
1808         }
1809
1810         if(err)return 4;
1811
1812         return 0;
1813 }
1814
1815 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1816 {
1817         comedi_cmd *cmd=&s->async->cmd;
1818         int timer;
1819         int mode1=0; /* mode1 is needed for both stop and convert */
1820         int mode2=0;
1821         int start_stop_select=0;
1822         unsigned int stop_count;
1823         int interrupt_a_enable=0;
1824
1825         MDPRINTK("ni_ai_cmd\n");
1826         if(dev->irq == 0)
1827         {
1828                 comedi_error(dev, "cannot run command without an irq");
1829                 return -EIO;
1830         }
1831         ni_flush_ai_fifo(dev);
1832
1833         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1834
1835         /* start configuration */
1836         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1837
1838         /* disable analog triggering for now, since it
1839          * interferes with the use of pfi0 */
1840         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1841         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1842
1843         switch(cmd->start_src){
1844                 case TRIG_INT:
1845                 case TRIG_NOW:
1846                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1847                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1848                                 AI_Trigger_Select_Register);
1849                         break;
1850                 case TRIG_EXT:
1851                 {
1852                         int chan = CR_CHAN(cmd->start_arg);
1853                         unsigned int bits = AI_START2_Select(0)|
1854                                 AI_START1_Sync |
1855                                 AI_START1_Select(chan + 1);
1856
1857                         if(cmd->start_arg & CR_INVERT)
1858                                 bits |= AI_START1_Polarity;
1859                         if(cmd->start_arg & CR_EDGE)
1860                                 bits |= AI_START1_Edge;
1861                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1862                         break;
1863                 }
1864         }
1865
1866         mode2 &= ~AI_Pre_Trigger;
1867         mode2 &= ~AI_SC_Initial_Load_Source;
1868         mode2 &= ~AI_SC_Reload_Mode;
1869         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1870
1871         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1872                 start_stop_select |= AI_STOP_Polarity;
1873                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1874                 start_stop_select |= AI_STOP_Sync;
1875         }else
1876         {
1877                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
1878         }
1879         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1880
1881         devpriv->ai_cmd2 = 0;
1882         switch(cmd->stop_src){
1883         case TRIG_COUNT:
1884                 stop_count = cmd->stop_arg - 1;
1885
1886                 if(boardtype.reg_type == ni_reg_611x){
1887                         // have to take 3 stage adc pipeline into account
1888                         stop_count += num_adc_stages_611x;
1889                 }
1890                 /* stage number of scans */
1891                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
1892
1893                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1894                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1895                 /* load SC (Scan Count) */
1896                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1897
1898                 devpriv->ai_continuous = 0;
1899                 if( stop_count == 0 ){
1900                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1901                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1902                         // this is required to get the last sample for chanlist_len > 1, not sure why
1903                         if(cmd->chanlist_len > 1)
1904                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
1905                 }
1906                 break;
1907         case TRIG_NONE:
1908                 /* stage number of scans */
1909                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
1910
1911                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1912                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1913
1914                 /* load SC (Scan Count) */
1915                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1916
1917                 devpriv->ai_continuous = 1;
1918
1919                 break;
1920         }
1921
1922         switch(cmd->scan_begin_src){
1923         case TRIG_TIMER:
1924                 /*
1925                         stop bits for non 611x boards
1926                         AI_SI_Special_Trigger_Delay=0
1927                         AI_Pre_Trigger=0
1928                         AI_START_STOP_Select_Register:
1929                         AI_START_Polarity=0 (?) rising edge
1930                         AI_START_Edge=1         edge triggered
1931                         AI_START_Sync=1 (?)
1932                         AI_START_Select=0               SI_TC
1933                         AI_STOP_Polarity=0              rising edge
1934                         AI_STOP_Edge=0          level
1935                         AI_STOP_Sync=1
1936                         AI_STOP_Select=19               external pin (configuration mem)
1937                  */
1938                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1939                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1940
1941                 mode2 |= AI_SI_Reload_Mode(0);
1942                 /* AI_SI_Initial_Load_Source=A */
1943                 mode2 &= ~AI_SI_Initial_Load_Source;
1944                 //mode2 |= AI_SC_Reload_Mode;
1945                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1946
1947                 /* load SI */
1948                 timer = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
1949                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
1950                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
1951                 break;
1952         case TRIG_EXT:
1953                 if( cmd->scan_begin_arg & CR_EDGE )
1954                         start_stop_select |= AI_START_Edge;
1955                 /* AI_START_Polarity==1 is falling edge */
1956                 if( cmd->scan_begin_arg & CR_INVERT )
1957                         start_stop_select |= AI_START_Polarity;
1958                 if( cmd->scan_begin_src != cmd->convert_src ||
1959                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1960                         start_stop_select |= AI_START_Sync;
1961                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
1962                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1963                 break;
1964         }
1965
1966         switch(cmd->convert_src){
1967         case TRIG_TIMER:
1968         case TRIG_NOW:
1969                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
1970                         timer = 1;
1971                 else
1972                         timer = ni_ns_to_timer(dev, &cmd->convert_arg, TRIG_ROUND_NEAREST);
1973                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
1974                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
1975
1976                 /* AI_SI2_Reload_Mode = alternate */
1977                 /* AI_SI2_Initial_Load_Source = A */
1978                 mode2 &= ~AI_SI2_Initial_Load_Source;
1979                 mode2 |= AI_SI2_Reload_Mode;
1980                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
1981
1982                 /* AI_SI2_Load */
1983                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
1984
1985                 mode2 |= AI_SI2_Reload_Mode; // alternate
1986                 mode2 |= AI_SI2_Initial_Load_Source; // B
1987
1988                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
1989                 break;
1990         case TRIG_EXT:
1991                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
1992                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
1993                         mode1 |= AI_CONVERT_Source_Polarity;
1994                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1995
1996                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
1997                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1998
1999                 break;
2000         }
2001
2002         if(dev->irq){
2003
2004                 /* interrupt on FIFO, errors, SC_TC */
2005                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2006                         AI_SC_TC_Interrupt_Enable;
2007
2008 #ifndef PCIDMA
2009                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2010 #endif
2011
2012                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2013                         /* wake on end-of-scan */
2014                         devpriv->aimode=AIMODE_SCAN;
2015                 }else{
2016                         devpriv->aimode=AIMODE_HALF_FULL;
2017                 }
2018
2019                 switch(devpriv->aimode){
2020                 case AIMODE_HALF_FULL:
2021                         /*generate FIFO interrupts and DMA requests on half-full */
2022 #ifdef PCIDMA
2023                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2024 #else
2025                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2026 #endif
2027                         break;
2028                 case AIMODE_SAMPLE:
2029                         /*generate FIFO interrupts on non-empty */
2030                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2031                         break;
2032                 case AIMODE_SCAN:
2033 #ifdef PCIDMA
2034                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2035 #else
2036                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2037 #endif
2038                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2039                         break;
2040                 default:
2041                         break;
2042                 }
2043
2044                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2045
2046                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2047
2048                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2049         }else{
2050                 /* interrupt on nothing */
2051                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2052
2053                 /* XXX start polling if necessary */
2054                 MDPRINTK("interrupting on nothing\n");
2055         }
2056
2057         /* end configuration */
2058         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2059
2060         switch(cmd->scan_begin_src){
2061         case TRIG_TIMER:
2062                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2063                         AI_Command_1_Register);
2064                 break;
2065         case TRIG_EXT:
2066                 /* XXX AI_SI_Arm? */
2067                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2068                         AI_Command_1_Register);
2069                 break;
2070         }
2071
2072 #ifdef PCIDMA
2073         ni_ai_setup_MITE_dma(dev,cmd);
2074         //mite_dump_regs(devpriv->mite);
2075 #endif
2076
2077         switch(cmd->start_src){
2078         case TRIG_NOW:
2079                 /* AI_START1_Pulse */
2080                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2081                 s->async->inttrig=NULL;
2082                 break;
2083         case TRIG_EXT:
2084                 s->async->inttrig=NULL;
2085                 break;
2086         case TRIG_INT:
2087                 s->async->inttrig=ni_ai_inttrig;
2088                 break;
2089         }
2090
2091         MDPRINTK("exit ni_ai_cmd\n");
2092
2093         return 0;
2094 }
2095
2096 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2097         unsigned int trignum)
2098 {
2099         if(trignum!=0)return -EINVAL;
2100
2101         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2102         s->async->inttrig=NULL;
2103
2104         return 1;
2105 }
2106
2107 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2108         comedi_insn *insn, lsampl_t *data);
2109
2110 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2111         comedi_insn *insn, lsampl_t *data)
2112 {
2113         if(insn->n<1)return -EINVAL;
2114
2115         switch(data[0]){
2116         case INSN_CONFIG_ANALOG_TRIG:
2117                 return ni_ai_config_analog_trig(dev,s,insn,data);
2118         case INSN_CONFIG_ALT_SOURCE:
2119                 if(boardtype.reg_type == ni_reg_m_series)
2120                 {
2121                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2122                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2123                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2124                         {
2125                                 return -EINVAL;
2126                         }
2127                         devpriv->ai_calib_source = data[1];
2128                 } else if(boardtype.reg_type == ni_reg_6143)
2129                 {
2130                         unsigned int calib_source;
2131
2132                         calib_source = data[1] & 0xf;
2133
2134
2135                         if(calib_source > 0xF)
2136                                 return -EINVAL;
2137
2138                         devpriv->ai_calib_source = calib_source;
2139                         ni_writew(calib_source, Calibration_Channel_6143);
2140                 }else
2141                 {
2142                         unsigned int calib_source;
2143                         unsigned int calib_source_adjust;
2144
2145                         calib_source = data[1] & 0xf;
2146                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2147
2148                         if(calib_source >= 8)
2149                                 return -EINVAL;
2150                         devpriv->ai_calib_source = calib_source;
2151                         if(boardtype.reg_type == ni_reg_611x){
2152                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2153                         }
2154                 }
2155                 return 2;
2156         default:
2157                 break;
2158         }
2159
2160         return -EINVAL;
2161 }
2162
2163 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2164         comedi_insn *insn, lsampl_t *data)
2165 {
2166         unsigned int a,b,modebits;
2167         int err=0;
2168
2169         /* data[1] is flags
2170          * data[2] is analog line
2171          * data[3] is set level
2172          * data[4] is reset level */
2173         if(!boardtype.has_analog_trig)return -EINVAL;
2174         if(insn->n!=5)return -EINVAL;
2175         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2176                 data[1]&=~(COMEDI_EV_SCAN_BEGIN&0xffff);
2177                 err++;
2178         }
2179         if(data[2]>=boardtype.n_adchan){
2180                 data[2]=boardtype.n_adchan-1;
2181                 err++;
2182         }
2183         if(data[3]>255){ /* a */
2184                 data[3]=255;
2185                 err++;
2186         }
2187         if(data[4]>255){ /* b */
2188                 data[4]=255;
2189                 err++;
2190         }
2191         /*
2192          * 00 ignore
2193          * 01 set
2194          * 10 reset
2195          *
2196          * modes:
2197          *   1 level:                    +b-   +a-
2198          *     high mode                00 00 01 10
2199          *     low mode                 00 00 10 01
2200          *   2 level: (a<b)
2201          *     hysteresis low mode      10 00 00 01
2202          *     hysteresis high mode     01 00 00 10
2203          *     middle mode              10 01 01 10
2204          */
2205
2206         a=data[3];
2207         b=data[4];
2208         modebits=data[1]&0xff;
2209         if(modebits&0xf0){
2210                 /* two level mode */
2211                 if(b<a){
2212                         /* swap order */
2213                         a=data[4];
2214                         b=data[3];
2215                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2216                 }
2217                 devpriv->atrig_low = a;
2218                 devpriv->atrig_high = b;
2219                 switch(modebits){
2220                 case 0x81:      /* low hysteresis mode */
2221                         devpriv->atrig_mode = 6;
2222                         break;
2223                 case 0x42:      /* high hysteresis mode */
2224                         devpriv->atrig_mode = 3;
2225                         break;
2226                 case 0x96:      /* middle window mode */
2227                         devpriv->atrig_mode = 2;
2228                         break;
2229                 default:
2230                         data[1]&=~0xff;
2231                         err++;
2232                 }
2233         }else{
2234                 /* one level mode */
2235                 if(b!=0){
2236                         data[4]=0;
2237                         err++;
2238                 }
2239                 switch(modebits){
2240                 case 0x06:      /* high window mode */
2241                         devpriv->atrig_high = a;
2242                         devpriv->atrig_mode = 0;
2243                         break;
2244                 case 0x09:      /* low window mode */
2245                         devpriv->atrig_low = a;
2246                         devpriv->atrig_mode = 1;
2247                         break;
2248                 default:
2249                         data[1]&=~0xff;
2250                         err++;
2251                 }
2252         }
2253         if(err)return -EAGAIN;
2254         return 5;
2255 }
2256
2257 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2258 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2259         void *data, unsigned int num_bytes, unsigned int chan_index )
2260 {
2261         comedi_async *async = s->async;
2262         unsigned int range;
2263         unsigned int i;
2264         unsigned int offset;
2265         unsigned int length = num_bytes / sizeof( sampl_t );
2266         sampl_t *array = data;
2267
2268         offset = 1 << (boardtype.aobits - 1);
2269         for(i = 0; i < length; i++)
2270         {
2271                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2272                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2273                         array[i] -= offset;
2274 #ifdef PCIDMA
2275                 array[i] = cpu_to_le16( array[i] );
2276 #endif
2277                 chan_index++;
2278                 chan_index %= async->cmd.chanlist_len;
2279         }
2280 }
2281
2282 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2283         unsigned int chanspec[], unsigned int n_chans)
2284 {
2285         unsigned int range;
2286         unsigned int chan;
2287         unsigned int conf;
2288         int i;
2289         int invert = 0;
2290
2291         for(i=0;i<n_chans;i++){
2292                 chan = CR_CHAN(chanspec[i]);
2293                 range = CR_RANGE(chanspec[i]);
2294                 if(boardtype.reg_type == ni_reg_m_series)
2295                 {
2296                         comedi_krange *krange = s->range_table->range + range;
2297                         invert = 0;
2298                         conf = 0;
2299                         switch(krange->max - krange->min)
2300                         {
2301                         case 20000000:
2302                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2303                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2304                                 break;
2305                         case 10000000:
2306                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2307                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2308                                 break;
2309                         case 4000000:
2310                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2311                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2312                                 break;
2313                         case 2000000:
2314                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2315                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2316                                 break;
2317                         default:
2318                                 rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2319                                 break;
2320                         }
2321                         switch(krange->max + krange->min)
2322                         {
2323                         case 0:
2324                                 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2325                                 break;
2326                         case 10000000:
2327                                 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2328                                 break;
2329                         default:
2330                                 rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2331                                 break;
2332                         }
2333                         ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2334                 }else
2335                 {
2336                         conf = AO_Channel(chan);
2337
2338                         if(boardtype.ao_unipolar){
2339                                 if((range&1) == 0){
2340                                         conf |= AO_Bipolar;
2341                                         invert = (1<<(boardtype.aobits-1));
2342                                 }else{
2343                                         invert = 0;
2344                                 }
2345                                 if(range&2)
2346                                         conf |= AO_Ext_Ref;
2347                         }else{
2348                                 conf |= AO_Bipolar;
2349                                 invert = (1<<(boardtype.aobits-1));
2350                         }
2351
2352                         /* not all boards can deglitch, but this shouldn't hurt */
2353                         if(chanspec[i] & CR_DEGLITCH)
2354                                 conf |= AO_Deglitch;
2355
2356                         /* analog reference */
2357                         /* AREF_OTHER connects AO ground to AI ground, i think */
2358                         conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2359
2360                         ni_writew(conf,AO_Configuration);
2361                 }
2362                 devpriv->ao_conf[chan] = conf;
2363         }
2364         return invert;
2365 }
2366
2367 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2368         comedi_insn *insn,lsampl_t *data)
2369 {
2370         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2371
2372         return 1;
2373 }
2374
2375 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2376         comedi_insn *insn,lsampl_t *data)
2377 {
2378         unsigned int chan = CR_CHAN(insn->chanspec);
2379         unsigned int invert;
2380
2381         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2382
2383         devpriv->ao[chan] = data[0];
2384
2385         if(boardtype.reg_type == ni_reg_m_series)
2386         {
2387                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2388         }
2389         else
2390                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2391
2392         return 1;
2393 }
2394
2395 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2396         comedi_insn *insn,lsampl_t *data)
2397 {
2398         unsigned int chan = CR_CHAN(insn->chanspec);
2399         unsigned int invert;
2400
2401         ao_win_out(1 << chan, AO_Immediate_671x);
2402         invert = 1 << (boardtype.aobits - 1);
2403
2404         ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2405
2406         devpriv->ao[chan] = data[0];
2407         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2408
2409         return 1;
2410 }
2411
2412 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2413         unsigned int trignum)
2414 {
2415         int ret;
2416         int interrupt_b_bits;
2417         int i;
2418         static const int timeout = 1000;
2419
2420         if(trignum!=0)return -EINVAL;
2421
2422         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2423         interrupt_b_bits = AO_Error_Interrupt_Enable;
2424 #ifdef PCIDMA
2425         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2426         if(boardtype.reg_type & ni_reg_6xxx_mask)
2427                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2428         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2429         ret = ni_ao_wait_for_dma_load(dev);
2430         if(ret < 0) return ret;
2431
2432 #else
2433         ret = ni_ao_prep_fifo(dev,s);
2434         if(ret==0)return -EPIPE;
2435
2436         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2437 #endif
2438
2439         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2440         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2441         /* wait for DACs to be loaded */
2442         for(i = 0; i < timeout; i++)
2443         {
2444                 comedi_udelay(10);
2445                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2446                         break;
2447         }
2448         if(i == timeout)
2449         {
2450                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2451                 return -EIO;
2452         }
2453         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2454         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2455
2456         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2457
2458         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2459                 AO_Command_1_Register);
2460
2461         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2462
2463         s->async->inttrig=NULL;
2464
2465         return 0;
2466 }
2467
2468 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2469 {
2470         comedi_cmd *cmd = &s->async->cmd;
2471         int trigvar;
2472         int bits;
2473         int i;
2474
2475         if(dev->irq == 0)
2476         {
2477                 comedi_error(dev, "cannot run command without an irq");
2478                 return -EIO;
2479         }
2480         trigvar = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2481
2482         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2483
2484         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2485
2486         if(boardtype.reg_type & ni_reg_6xxx_mask)
2487         {
2488                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2489
2490                 bits = 0;
2491                 for(i = 0; i < cmd->chanlist_len; i++)
2492                 {
2493                         int chan;
2494
2495                         chan = CR_CHAN(cmd->chanlist[i]);
2496                         bits |= 1 << chan;
2497                         ao_win_out(chan, AO_Waveform_Generation_611x);
2498                 }
2499                 ao_win_out(bits, AO_Timed_611x);
2500         }
2501
2502         ni_ao_config_chanlist(dev,s,cmd->chanlist,cmd->chanlist_len);
2503
2504         if(cmd->stop_src==TRIG_NONE){
2505                 devpriv->ao_mode1|=AO_Continuous;
2506                 devpriv->ao_mode1&=~AO_Trigger_Once;
2507         }else{
2508                 devpriv->ao_mode1&=~AO_Continuous;
2509                 devpriv->ao_mode1|=AO_Trigger_Once;
2510         }
2511         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2512         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2513         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2514         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2515         devpriv->ao_mode3&=~AO_Trigger_Length;
2516         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2517
2518         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2519         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2520         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2521         if(cmd->stop_src==TRIG_NONE){
2522                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2523         }else{
2524                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2525         }
2526         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2527         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2528         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2529         switch(cmd->stop_src){
2530         case TRIG_COUNT:
2531                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2532                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2533                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2534                 break;
2535         case TRIG_NONE:
2536                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2537                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2538                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2539                 break;
2540         default:
2541                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2542                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2543                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2544         }
2545
2546         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2547         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2548         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2549         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2550         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2551         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2552         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2553         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2554         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2555
2556         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2557                 if(cmd->scan_end_arg>1){
2558                         devpriv->ao_mode1|=AO_Multiple_Channels;
2559                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2560                                 AO_UPDATE_Output_Select(1),
2561                                 AO_Output_Control_Register);
2562                 }else{
2563                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2564                         devpriv->stc_writew(dev, AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]))|
2565                                 AO_UPDATE_Output_Select(1),
2566                                 AO_Output_Control_Register);
2567                 }
2568                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2569         }
2570
2571         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2572
2573         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2574         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2575
2576         devpriv->ao_mode2 &= AO_FIFO_Mode_Mask;
2577 #ifdef PCIDMA
2578         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2579 #else
2580         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2581 #endif
2582         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2583         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2584
2585         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2586                 AO_TMRDACWR_Pulse_Width;
2587         if( boardtype.ao_fifo_depth )
2588                 bits |= AO_FIFO_Enable;
2589         else
2590                 bits |= AO_DMA_PIO_Control;
2591         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2592         // enable sending of ao dma requests
2593         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2594
2595         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2596
2597         if(cmd->stop_src==TRIG_COUNT) {
2598                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2599                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2600                         AO_BC_TC_Interrupt_Enable, 1);
2601         }
2602
2603         s->async->inttrig=ni_ao_inttrig;
2604
2605         return 0;
2606 }
2607
2608 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2609 {
2610         int err=0;
2611         int tmp;
2612
2613         /* step 1: make sure trigger sources are trivially valid */
2614
2615         tmp=cmd->start_src;
2616         cmd->start_src &= TRIG_INT;
2617         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2618
2619         tmp=cmd->scan_begin_src;
2620         cmd->scan_begin_src &= TRIG_TIMER;
2621         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2622
2623         tmp=cmd->convert_src;
2624         cmd->convert_src &= TRIG_NOW;
2625         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2626
2627         tmp=cmd->scan_end_src;
2628         cmd->scan_end_src &= TRIG_COUNT;
2629         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2630
2631         tmp=cmd->stop_src;
2632         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2633         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2634
2635         if(err)return 1;
2636
2637         /* step 2: make sure trigger sources are unique and mutually compatible */
2638
2639         if(cmd->stop_src!=TRIG_COUNT &&
2640            cmd->stop_src!=TRIG_NONE)err++;
2641
2642         if(err)return 2;
2643
2644         /* step 3: make sure arguments are trivially compatible */
2645
2646         if(cmd->start_arg!=0){
2647                 cmd->start_arg=0;
2648                 err++;
2649         }
2650 #if 0
2651         /* XXX need ao_speed */
2652         if(cmd->scan_begin_arg<boardtype.ao_speed){
2653                 cmd->scan_begin_arg=boardtype.ao_speed;
2654                 err++;
2655         }
2656 #endif
2657         if(cmd->scan_begin_arg>devpriv->clock_ns*0xffffff){ /* XXX check */
2658                 cmd->scan_begin_arg=devpriv->clock_ns*0xffffff;
2659                 err++;
2660         }
2661         if(cmd->convert_arg!=0){
2662                 cmd->convert_arg=0;
2663                 err++;
2664         }
2665         if(cmd->scan_end_arg!=cmd->chanlist_len){
2666                 cmd->scan_end_arg=cmd->chanlist_len;
2667                 err++;
2668         }
2669         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2670                 if(cmd->stop_arg>0x00ffffff){
2671                         cmd->stop_arg=0x00ffffff;
2672                         err++;
2673                 }
2674         }else{
2675                 /* TRIG_NONE */
2676                 if(cmd->stop_arg!=0){
2677                         cmd->stop_arg=0;
2678                         err++;
2679                 }
2680         }
2681
2682         if(err)return 3;
2683
2684         /* step 4: fix up any arguments */
2685
2686         tmp = cmd->scan_begin_arg;
2687         ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
2688         if(tmp!=cmd->scan_begin_arg)err++;
2689
2690         if(err)return 4;
2691
2692         /* step 5: fix up chanlist */
2693
2694         if(err)return 5;
2695
2696         return 0;
2697 }
2698
2699
2700 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2701 {
2702         //devpriv->ao0p=0x0000;
2703         //ni_writew(devpriv->ao0p,AO_Configuration);
2704
2705         //devpriv->ao1p=AO_Channel(1);
2706         //ni_writew(devpriv->ao1p,AO_Configuration);
2707
2708 #ifdef PCIDMA
2709         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2710         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
2711 #endif
2712
2713         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2714         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2715         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2716         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2717         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2718         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2719                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2720         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2721         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2722         devpriv->ao_cmd1=0;
2723         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2724         devpriv->ao_cmd2=0;
2725         devpriv->ao_mode1=0;
2726         devpriv->ao_mode2=0;
2727         if(boardtype.reg_type == ni_reg_m_series)
2728                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2729         else
2730                 devpriv->ao_mode3 = 0;
2731         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2732         devpriv->ao_trigger_select=0;
2733         if(boardtype.reg_type & ni_reg_6xxx_mask){
2734                 ao_win_out(0x3, AO_Immediate_671x);
2735                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2736         }
2737         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2738
2739         return 0;
2740 }
2741
2742 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2743         comedi_insn *insn,lsampl_t *data)
2744 {
2745 #ifdef DEBUG_DIO
2746         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2747                 CR_CHAN(insn->chanspec),data[0]);
2748 #endif
2749         switch(data[0]){
2750         case INSN_CONFIG_DIO_OUTPUT:
2751                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2752                 break;
2753         case INSN_CONFIG_DIO_INPUT:
2754                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2755                 break;
2756         case INSN_CONFIG_DIO_QUERY:
2757                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2758                 return insn->n;
2759                 break;
2760         default:
2761                 return -EINVAL;
2762         }
2763
2764         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2765         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2766         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2767
2768         return 1;
2769 }
2770
2771 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2772         comedi_insn *insn,lsampl_t *data)
2773 {
2774 #ifdef DEBUG_DIO
2775         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2776 #endif
2777         if(insn->n!=2)return -EINVAL;
2778         if(data[0]){
2779                 /* Perform check to make sure we're not using the
2780                    serial part of the dio */
2781                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2782                         return -EBUSY;
2783
2784                 s->state &= ~data[0];
2785                 s->state |= (data[0]&data[1]);
2786                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2787                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2788                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2789         }
2790         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2791
2792         return 2;
2793 }
2794
2795 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2796         comedi_insn *insn, lsampl_t *data)
2797 {
2798 #ifdef DEBUG_DIO
2799         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
2800                 CR_CHAN(insn->chanspec), data[0]);
2801 #endif
2802         switch(data[0])
2803         {
2804         case INSN_CONFIG_DIO_OUTPUT:
2805                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2806                 break;
2807         case INSN_CONFIG_DIO_INPUT:
2808                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2809                 break;
2810         case INSN_CONFIG_DIO_QUERY:
2811                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2812                 return insn->n;
2813                 break;
2814         default:
2815                 return -EINVAL;
2816         }
2817
2818         ni_writel(s->io_bits, M_Offset_DIO_Direction);
2819
2820         return 1;
2821 }
2822
2823 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2824         comedi_insn *insn, lsampl_t *data)
2825 {
2826 #ifdef DEBUG_DIO
2827         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2828 #endif
2829         if(insn->n!=2)return -EINVAL;
2830         if(data[0]){
2831                 s->state &= ~data[0];
2832                 s->state |= (data[0] & data[1]);
2833                 ni_writel(s->state, M_Offset_Static_Digital_Output);
2834         }
2835         data[1] = ni_readl(M_Offset_Static_Digital_Input);
2836
2837         return 2;
2838 }
2839
2840 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2841                                  comedi_insn *insn,lsampl_t *data)
2842 {
2843         int err = insn->n;
2844         unsigned char byte_out, byte_in;
2845
2846         if(insn->n!=2)return -EINVAL;
2847
2848         switch(data[0]) {
2849         case INSN_CONFIG_SERIAL_CLOCK:
2850
2851 #ifdef DEBUG_DIO
2852                 rt_printk("SPI serial clock Config cd\n", data[1]);
2853 #endif
2854                 devpriv->serial_hw_mode = 1;
2855                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2856
2857                 if(data[1] == SERIAL_DISABLED) {
2858                         devpriv->serial_hw_mode = 0;
2859                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2860                                                   DIO_Software_Serial_Control);
2861                         data[1] = SERIAL_DISABLED;
2862                         devpriv->serial_interval_ns = data[1];
2863                 }
2864                 else if(data[1] <= SERIAL_600NS) {
2865                         /* Warning: this clock speed is too fast to reliably
2866                         control SCXI. */
2867                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2868                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2869                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2870                         data[1] = SERIAL_600NS;
2871                         devpriv->serial_interval_ns = data[1];
2872                 }
2873                 else if(data[1] <= SERIAL_1_2US) {
2874                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2875                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2876                                 DIO_Serial_Out_Divide_By_2;
2877                         data[1] = SERIAL_1_2US;
2878                         devpriv->serial_interval_ns = data[1];
2879                 }
2880                 else if(data[1] <= SERIAL_10US) {
2881                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2882                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2883                                 DIO_Serial_Out_Divide_By_2;
2884                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2885                         600ns/1.2us. If you turn divide_by_2 off with the
2886                         slow clock, you will still get 10us, except then
2887                         all your delays are wrong. */
2888                         data[1] = SERIAL_10US;
2889                         devpriv->serial_interval_ns = data[1];
2890                 }
2891                 else {
2892                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2893                                                   DIO_Software_Serial_Control);
2894                         devpriv->serial_hw_mode = 0;
2895                         data[1] = (data[1] / 1000) * 1000;
2896                         devpriv->serial_interval_ns = data[1];
2897                 }
2898
2899                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2900                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
2901                 return 1;
2902
2903         break;
2904
2905         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2906
2907                 if(devpriv->serial_interval_ns == 0) {
2908                         return -EINVAL;
2909                 }
2910
2911                 byte_out = data[1] & 0xFF;
2912
2913                 if(devpriv->serial_hw_mode) {
2914                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2915                 } else if(devpriv->serial_interval_ns > 0) {
2916                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2917                 } else {
2918                         rt_printk("ni_serial_insn_config: serial disabled!\n");
2919                         return -EINVAL;
2920                 }
2921                 if(err < 0) return err;
2922                 data[1] = byte_in & 0xFF;
2923                 return insn->n;
2924
2925         break;
2926         default:
2927                 return -EINVAL;
2928         }
2929
2930 }
2931
2932 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2933                                    unsigned char data_out,
2934                                    unsigned char *data_in)
2935 {
2936         unsigned int status1;
2937         int err = 0, count = 20;
2938
2939 #ifdef DEBUG_DIO
2940         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
2941 #endif
2942
2943         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
2944         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
2945         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2946
2947         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
2948         if(status1 & DIO_Serial_IO_In_Progress_St) {
2949                 err = -EBUSY;
2950                 goto Error;
2951         }
2952
2953         devpriv->dio_control |= DIO_HW_Serial_Start;
2954         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2955         devpriv->dio_control &= ~DIO_HW_Serial_Start;
2956
2957         /* Wait until STC says we're done, but don't loop infinitely. */
2958         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
2959                 /* Delay one bit per loop */
2960                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2961                 if(--count < 0) {
2962                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
2963                         err = -ETIME;
2964                         goto Error;
2965                 }
2966         }
2967
2968         /* Delay for last bit. This delay is absolutely necessary, because
2969            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
2970         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2971
2972         if(data_in != NULL) {
2973                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
2974 #ifdef DEBUG_DIO
2975                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
2976 #endif
2977         }
2978
2979  Error:
2980         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2981
2982         return err;
2983 }
2984
2985 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2986                                    unsigned char data_out,
2987                                    unsigned char *data_in)
2988 {
2989         unsigned char mask, input = 0;
2990
2991 #ifdef DEBUG_DIO
2992         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
2993 #endif
2994
2995         /* Wait for one bit before transfer */
2996         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2997
2998         for(mask = 0x80; mask; mask >>= 1) {
2999                 /* Output current bit; note that we cannot touch s->state
3000            because it is a per-subdevice field, and serial is
3001                    a separate subdevice from DIO. */
3002                 devpriv->dio_output &= ~DIO_SDOUT;
3003                 if(data_out & mask) {
3004                         devpriv->dio_output |= DIO_SDOUT;
3005                 }
3006                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3007
3008                 /* Assert SDCLK (active low, inverted), wait for half of
3009                    the delay, deassert SDCLK, and wait for the other half. */
3010                 devpriv->dio_control |= DIO_Software_Serial_Control;
3011                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3012
3013                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3014
3015                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3016                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3017
3018                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3019
3020                 /* Input current bit */
3021                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3022 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3023                         input |= mask;
3024                 }
3025         }
3026 #ifdef DEBUG_DIO
3027         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3028 #endif
3029         if(data_in) *data_in = input;
3030
3031         return 0;
3032 }
3033
3034 static void mio_common_detach(comedi_device *dev)
3035 {
3036         if(dev->subdevices && boardtype.has_8255)
3037                 subdev_8255_cleanup(dev,dev->subdevices+3);
3038 }
3039
3040 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3041 {
3042         int i;
3043
3044         for(i = 0; i < s->n_chan; i++)
3045                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3046 }
3047
3048 static int ni_alloc_private(comedi_device *dev)
3049 {
3050         int ret;
3051
3052         ret = alloc_private(dev, sizeof(ni_private));
3053         if(ret < 0) return ret;
3054
3055         spin_lock_init(&devpriv->window_lock);
3056
3057         return 0;
3058 };
3059
3060 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3061 {
3062         comedi_subdevice *s;
3063         int bits;
3064
3065         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3066         {
3067                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3068                 return -EINVAL;
3069         }
3070
3071         if(alloc_subdevices(dev, 11) < 0)
3072                 return -ENOMEM;
3073
3074         /* analog input subdevice */
3075
3076         s=dev->subdevices+0;
3077         dev->read_subdev=s;
3078         if(boardtype.n_adchan){
3079                 s->type=COMEDI_SUBD_AI;
3080                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER;
3081                 if(boardtype.reg_type != ni_reg_611x)
3082                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3083                 if(boardtype.adbits > 16)
3084                         s->subdev_flags |= SDF_LSAMPL;
3085                 if(boardtype.reg_type == ni_reg_m_series)
3086                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3087                 s->n_chan=boardtype.n_adchan;
3088                 s->len_chanlist=512;
3089                 s->maxdata=(1<<boardtype.adbits)-1;
3090                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3091                 s->insn_read=ni_ai_insn_read;
3092                 s->insn_config=ni_ai_insn_config;
3093                 s->do_cmdtest=ni_ai_cmdtest;
3094                 s->do_cmd=ni_ai_cmd;
3095                 s->cancel=ni_ai_reset;
3096                 s->poll=ni_ai_poll;
3097                 s->munge=ni_ai_munge;
3098         }else{
3099                 s->type=COMEDI_SUBD_UNUSED;
3100         }
3101
3102         /* analog output subdevice */
3103
3104         s=dev->subdevices+1;
3105         if(boardtype.n_aochan){
3106                 dev->write_subdev=s;
3107                 s->type=COMEDI_SUBD_AO;
3108                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
3109                 if(boardtype.reg_type == ni_reg_m_series)
3110                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3111                 s->n_chan=boardtype.n_aochan;
3112                 s->maxdata=(1<<boardtype.aobits)-1;
3113                 s->range_table = boardtype.ao_range_table;
3114                 s->insn_read=ni_ao_insn_read;
3115                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3116                         s->insn_write=ni_ao_insn_write_671x;
3117                 }else{
3118                         s->insn_write=ni_ao_insn_write;
3119                 }
3120 #ifdef PCIDMA
3121                 if(boardtype.n_aochan){
3122 #else
3123                 if(boardtype.ao_fifo_depth){
3124 #endif
3125                         s->do_cmd=ni_ao_cmd;
3126                         s->do_cmdtest=ni_ao_cmdtest;
3127                         s->len_chanlist = boardtype.n_aochan;
3128                         if(boardtype.reg_type != ni_reg_m_series)
3129                                 s->munge=ni_ao_munge;
3130                 }
3131                 s->cancel=ni_ao_reset;
3132         }else{
3133                 s->type=COMEDI_SUBD_UNUSED;
3134         }
3135         if((boardtype.reg_type & ni_reg_67xx_mask))
3136                 init_ao_67xx(dev, s);
3137
3138         /* digital i/o subdevice */
3139
3140         s=dev->subdevices+2;
3141         s->type=COMEDI_SUBD_DIO;
3142         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3143         s->maxdata=1;
3144         s->io_bits=0;           /* all bits input */
3145         s->range_table=&range_digital;
3146         if(boardtype.reg_type == ni_reg_m_series)
3147         {
3148                 s->n_chan = 32;
3149                 s->insn_bits = ni_m_series_dio_insn_bits;
3150                 s->insn_config=ni_m_series_dio_insn_config;
3151                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3152         }else
3153         {
3154                 s->n_chan=8;
3155                 s->insn_bits=ni_dio_insn_bits;
3156                 s->insn_config=ni_dio_insn_config;
3157                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3158                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3159         }
3160
3161         /* 8255 device */
3162         s=dev->subdevices+3;
3163         if(boardtype.has_8255){
3164                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3165         }else{
3166                 s->type=COMEDI_SUBD_UNUSED;
3167         }
3168
3169         /* general purpose counter/timer device */
3170         s=dev->subdevices+4;
3171         s->type=COMEDI_SUBD_COUNTER;
3172         s->subdev_flags=SDF_READABLE|SDF_WRITABLE;
3173         s->insn_read=  ni_gpct_insn_read;
3174         s->insn_write= ni_gpct_insn_write;
3175         s->insn_config=ni_gpct_insn_config;
3176         s->n_chan=2;
3177         s->maxdata=1;
3178         devpriv->an_trig_etc_reg = 0;
3179         GPCT_Reset(dev,0);
3180         GPCT_Reset(dev,1);
3181
3182         /* calibration subdevice -- ai and ao */
3183         s=dev->subdevices+5;
3184         s->type=COMEDI_SUBD_CALIB;
3185         if(boardtype.reg_type == ni_reg_m_series)
3186         {
3187                 // internal PWM analog output used for AI nonlinearity calibration
3188                 s->subdev_flags = SDF_INTERNAL;
3189                 s->insn_config = &ni_m_series_pwm_config;
3190                 s->n_chan = 1;
3191                 s->maxdata = 0;
3192                 ni_writel(0x0, M_Offset_Cal_PWM);
3193         } else if(boardtype.reg_type == ni_reg_6143)
3194         {
3195                 // internal PWM analog output used for AI nonlinearity calibration
3196                 s->subdev_flags = SDF_INTERNAL;
3197                 s->insn_config = &ni_6143_pwm_config;
3198                 s->n_chan = 1;
3199                 s->maxdata = 0;
3200         }else
3201         {
3202                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3203                 s->insn_read = &ni_calib_insn_read;
3204                 s->insn_write = &ni_calib_insn_write;
3205                 caldac_setup(dev, s);
3206         }
3207
3208         /* EEPROM */
3209         s=dev->subdevices+6;
3210         s->type=COMEDI_SUBD_MEMORY;
3211         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3212         s->maxdata=0xff;
3213         if(boardtype.reg_type == ni_reg_m_series)
3214         {
3215                 s->n_chan = M_SERIES_EEPROM_SIZE;
3216                 s->insn_read = &ni_m_series_eeprom_insn_read;
3217         }else
3218         {
3219                 s->n_chan = 512;
3220                 s->insn_read = &ni_eeprom_insn_read;
3221         }
3222         /* PFI */
3223         s=dev->subdevices + 7;
3224         s->type = COMEDI_SUBD_DIO;
3225         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3226         if(boardtype.reg_type == ni_reg_m_series)
3227         {
3228                 s->n_chan = 16;
3229         }else
3230         {
3231                 s->n_chan = 10;
3232         }
3233         s->maxdata = 1;
3234         s->insn_bits = ni_pfi_insn_bits;
3235         s->insn_config = ni_pfi_insn_config;
3236         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3237
3238         /* cs5529 calibration adc */
3239         s = dev->subdevices + 8;
3240         if(boardtype.reg_type & ni_reg_67xx_mask)
3241         {
3242                 s->type = COMEDI_SUBD_AI;
3243                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3244                 // one channel for each analog output channel
3245                 s->n_chan = boardtype.n_aochan;
3246                 s->maxdata = (1 << 16) - 1;
3247                 s->range_table = &range_unknown; /* XXX */
3248                 s->insn_read=cs5529_ai_insn_read;
3249                 s->insn_config=NULL;
3250                 init_cs5529(dev);
3251         }else
3252         {
3253                 s->type=COMEDI_SUBD_UNUSED;
3254         }
3255
3256         /* Serial */
3257         s=dev->subdevices+9;
3258         s->type=COMEDI_SUBD_SERIAL;
3259         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3260         s->n_chan=1;
3261         s->maxdata=0xff;
3262         s->insn_config = ni_serial_insn_config;
3263         devpriv->serial_interval_ns = 0;
3264         devpriv->serial_hw_mode = 0;
3265
3266         /* RTSI */
3267         s=dev->subdevices + 10;
3268         s->type = COMEDI_SUBD_DIO;
3269         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3270         s->n_chan = 8;
3271         s->maxdata = 1;
3272         s->insn_bits = ni_rtsi_insn_bits;
3273         s->insn_config = ni_rtsi_insn_config;
3274         ni_rtsi_init(dev);
3275
3276         /* ai configuration */
3277         ni_ai_reset(dev,dev->subdevices+0);
3278         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3279                 // BEAM is this needed for PCI-6143 ??
3280                 devpriv->clock_and_fout =
3281                         Slow_Internal_Time_Divide_By_2 |
3282                         Slow_Internal_Timebase |
3283                         Clock_To_Board_Divide_By_2 |
3284                         Clock_To_Board |
3285                         AI_Output_Divide_By_2 |
3286                         AO_Output_Divide_By_2;
3287         }else{
3288                 devpriv->clock_and_fout =
3289                         Slow_Internal_Time_Divide_By_2 |
3290                         Slow_Internal_Timebase |
3291                         Clock_To_Board_Divide_By_2 |
3292                         Clock_To_Board;
3293         }
3294         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3295
3296         /* analog output configuration */
3297         ni_ao_reset(dev,dev->subdevices + 1);
3298
3299         if(dev->irq){
3300                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3301                         (Interrupt_Output_On_3_Pins&0) |
3302                         Interrupt_A_Enable |
3303                         Interrupt_B_Enable |
3304                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3305                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3306                         Interrupt_Control_Register
3307                 );
3308         }
3309
3310         /* DMA setup */
3311         /* tell the STC which dma channels to use for AI and AO */
3312         bits = 1 << ( AI_DMA_CHAN );
3313         bits |= 1 << ( AO_DMA_CHAN + 4 );
3314         ni_writeb( bits, AI_AO_Select);
3315         /* tell the STC which dma channels to use for
3316          * General purpose counters 0 and 1 */
3317         bits = 1 << ( GPC0_DMA_CHAN );
3318         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
3319         ni_writeb( bits, G0_G1_Select);
3320
3321         if(boardtype.reg_type & ni_reg_6xxx_mask)
3322         {
3323                 ni_writeb( 0, Magic_611x );
3324         }else if(boardtype.reg_type == ni_reg_m_series)
3325         {
3326                 int channel;
3327                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3328                 {
3329                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3330                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3331                 }
3332                 ni_writeb(0x0, M_Offset_AO_Calibration);
3333         }
3334
3335         printk("\n");
3336         return 0;
3337 }
3338
3339
3340
3341 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3342 {
3343         comedi_device *dev=(comedi_device *)arg;
3344
3345         if(dir){
3346                 ni_writeb(data,Port_A+2*port);
3347                 return 0;
3348         }else{
3349                 return ni_readb(Port_A+2*port);
3350         }
3351 }
3352
3353 /*
3354         presents the EEPROM as a subdevice
3355 */
3356
3357 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3358         comedi_insn *insn,lsampl_t *data)
3359 {
3360         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3361
3362         return 1;
3363 }
3364
3365 /*
3366         reads bytes out of eeprom
3367 */
3368
3369 static int ni_read_eeprom(comedi_device *dev,int addr)
3370 {
3371         int bit;
3372         int bitstring;
3373
3374         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3375         ni_writeb(0x04,Serial_Command);
3376         for(bit=0x8000;bit;bit>>=1){
3377                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3378                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3379         }
3380         bitstring=0;
3381         for(bit=0x80;bit;bit>>=1){
3382                 ni_writeb(0x04,Serial_Command);
3383                 ni_writeb(0x05,Serial_Command);
3384                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3385         }
3386         ni_writeb(0x00,Serial_Command);
3387
3388         return bitstring;
3389 }
3390
3391 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3392         comedi_insn *insn,lsampl_t *data)
3393 {
3394         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3395
3396         return 1;
3397 }
3398
3399 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3400 {
3401         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3402         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3403         return 3;
3404 }
3405
3406 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3407         comedi_insn *insn, lsampl_t *data)
3408 {
3409         unsigned up_count, down_count;
3410         switch(data[0])
3411         {
3412         case INSN_CONFIG_PWM_OUTPUT:
3413                 switch(data[1])
3414                 {
3415                 case TRIG_ROUND_NEAREST:
3416                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3417                         break;
3418                 case TRIG_ROUND_DOWN:
3419                         up_count = data[2] / devpriv->clock_ns;
3420                         break;
3421                 case TRIG_ROUND_UP:
3422                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3423                         break;
3424                 default:
3425                         return -EINVAL;
3426                         break;
3427                 }
3428                 switch(data[3])
3429                 {
3430                 case TRIG_ROUND_NEAREST:
3431                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3432                         break;
3433                 case TRIG_ROUND_DOWN:
3434                         down_count = data[4] / devpriv->clock_ns;
3435                         break;
3436                 case TRIG_ROUND_UP:
3437                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3438                         break;
3439                 default:
3440                         return -EINVAL;
3441                         break;
3442                 }
3443                 if(up_count * devpriv->clock_ns != data[2] ||
3444                         down_count * devpriv->clock_ns != data[4])
3445                 {
3446                         data[2] = up_count * devpriv->clock_ns;
3447                         data[4] = down_count * devpriv->clock_ns;
3448                         return -EAGAIN;
3449                 }
3450                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3451                 devpriv->pwm_up_count = up_count;
3452                 devpriv->pwm_down_count = down_count;
3453                 return 5;
3454                 break;
3455         case INSN_CONFIG_GET_PWM_OUTPUT:
3456                 return ni_get_pwm_config(dev, data);
3457                 break;
3458         default:
3459                 return -EINVAL;
3460                 break;
3461         }
3462         return 0;
3463 }
3464
3465 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3466         comedi_insn *insn, lsampl_t *data)
3467 {
3468         unsigned up_count, down_count;
3469         switch(data[0])
3470         {
3471         case INSN_CONFIG_PWM_OUTPUT:
3472                 switch(data[1])
3473                 {
3474                 case TRIG_ROUND_NEAREST:
3475                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3476                         break;
3477                 case TRIG_ROUND_DOWN:
3478                         up_count = data[2] / devpriv->clock_ns;
3479                         break;
3480                 case TRIG_ROUND_UP:
3481                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3482                         break;
3483                 default:
3484                         return -EINVAL;
3485                         break;
3486                 }
3487                 switch(data[3])
3488                 {
3489                 case TRIG_ROUND_NEAREST:
3490                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3491                         break;
3492                 case TRIG_ROUND_DOWN:
3493                         down_count = data[4] / devpriv->clock_ns;
3494                         break;
3495                 case TRIG_ROUND_UP:
3496                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3497                         break;
3498                 default:
3499                         return -EINVAL;
3500                         break;
3501                 }
3502                 if(up_count * devpriv->clock_ns != data[2] ||
3503                         down_count * devpriv->clock_ns != data[4])
3504                 {
3505                         data[2] = up_count * devpriv->clock_ns;
3506                         data[4] = down_count * devpriv->clock_ns;
3507                         return -EAGAIN;
3508                 }
3509                 ni_writel(up_count, Calibration_HighTime_6143);
3510                 devpriv->pwm_up_count = up_count;
3511                 ni_writel(down_count, Calibration_LowTime_6143);
3512                 devpriv->pwm_down_count = down_count;
3513                 return 5;
3514                 break;
3515         case INSN_CONFIG_GET_PWM_OUTPUT:
3516                 return ni_get_pwm_config(dev, data);
3517         default:
3518                 return -EINVAL;
3519                 break;
3520         }
3521         return 0;
3522 }
3523
3524 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3525 /*
3526         calibration subdevice
3527 */
3528 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3529         comedi_insn *insn,lsampl_t *data)
3530 {
3531         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3532
3533         return 1;
3534 }
3535
3536 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3537         comedi_insn *insn,lsampl_t *data)
3538 {
3539         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3540
3541         return 1;
3542 }
3543
3544 static int pack_mb88341(int addr,int val,int *bitstring);
3545 static int pack_dac8800(int addr,int val,int *bitstring);
3546 static int pack_dac8043(int addr,int val,int *bitstring);
3547 static int pack_ad8522(int addr,int val,int *bitstring);
3548 static int pack_ad8804(int addr,int val,int *bitstring);
3549 static int pack_ad8842(int addr,int val,int *bitstring);
3550
3551 struct caldac_struct{
3552         int n_chans;
3553         int n_bits;
3554         int (*packbits)(int,int,int *);
3555 };
3556
3557 static struct caldac_struct caldacs[] = {
3558         [mb88341] = { 12, 8, pack_mb88341 },
3559         [dac8800] = { 8, 8, pack_dac8800 },
3560         [dac8043] = { 1, 12, pack_dac8043 },
3561         [ad8522]  = { 2, 12, pack_ad8522 },
3562         [ad8804] = { 12, 8, pack_ad8804 },
3563         [ad8842] = { 8, 8, pack_ad8842 },
3564         [ad8804_debug] = { 16, 8, pack_ad8804 },
3565 };
3566
3567 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3568 {
3569         int i,j;
3570         int n_dacs;
3571         int n_chans=0;
3572         int n_bits;
3573         int diffbits=0;
3574         int type;
3575         int chan;
3576
3577         type = boardtype.caldac[0];
3578         if(type==caldac_none)return;
3579         n_bits=caldacs[type].n_bits;
3580         for(i=0;i<3;i++){
3581                 type = boardtype.caldac[i];
3582                 if(type==caldac_none)break;
3583                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3584                 n_chans+=caldacs[type].n_chans;
3585         }
3586         n_dacs=i;
3587         s->n_chan=n_chans;
3588
3589         if(diffbits){
3590
3591                 if(n_chans>MAX_N_CALDACS){
3592                         printk("BUG! MAX_N_CALDACS too small\n");
3593                 }
3594                 s->maxdata_list=devpriv->caldac_maxdata_list;
3595                 chan=0;
3596                 for(i=0;i<n_dacs;i++){
3597                         type = boardtype.caldac[i];
3598                         for(j=0;j<caldacs[type].n_chans;j++){
3599                                 s->maxdata_list[chan]=
3600                                         (1<<caldacs[type].n_bits)-1;
3601                                 chan++;
3602                         }
3603                 }
3604
3605                 for( chan = 0; chan < s->n_chan; chan++ )
3606                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3607         }else{
3608                 type = boardtype.caldac[0];
3609                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3610
3611                 for( chan = 0; chan < s->n_chan; chan++ )
3612                         ni_write_caldac( dev, i, s->maxdata / 2 );
3613         }
3614 }
3615
3616 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3617 {
3618         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3619         int i;
3620         int type;
3621
3622         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3623         if( devpriv->caldacs[ addr ] == val ) return;
3624         devpriv->caldacs[ addr ] = val;
3625
3626         for(i=0;i<3;i++){
3627                 type = boardtype.caldac[i];
3628                 if(type==caldac_none)break;
3629                 if(addr<caldacs[type].n_chans){
3630                         bits=caldacs[type].packbits(addr,val,&bitstring);
3631                         loadbit=SerDacLd(i);
3632                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3633                         break;
3634                 }
3635                 addr-=caldacs[type].n_chans;
3636         }
3637
3638         for(bit=1<<(bits-1);bit;bit>>=1){
3639                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3640                 comedi_udelay(1);
3641                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3642                 comedi_udelay(1);
3643         }
3644         ni_writeb(loadbit,Serial_Command);
3645         comedi_udelay(1);
3646         ni_writeb(0,Serial_Command);
3647 }
3648
3649
3650
3651 static int pack_mb88341(int addr,int val,int *bitstring)
3652 {
3653         /*
3654            Fujitsu MB 88341
3655            Note that address bits are reversed.  Thanks to
3656            Ingo Keen for noticing this.
3657
3658            Note also that the 88341 expects address values from
3659            1-12, whereas we use channel numbers 0-11.  The NI
3660            docs use 1-12, also, so be careful here.
3661         */
3662         addr++;
3663         *bitstring=((addr&0x1)<<11) |
3664                   ((addr&0x2)<<9)  |
3665                   ((addr&0x4)<<7)  |
3666                   ((addr&0x8)<<5)  |
3667                   (val&0xff);
3668         return 12;
3669 }
3670
3671 static int pack_dac8800(int addr,int val,int *bitstring)
3672 {
3673         *bitstring=((addr&0x7)<<8)|(val&0xff);
3674         return 11;
3675 }
3676
3677 static int pack_dac8043(int addr,int val,int *bitstring)
3678 {
3679         *bitstring=val&0xfff;
3680         return 12;
3681 }
3682
3683 static int pack_ad8522(int addr,int val,int *bitstring)
3684 {
3685         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3686         return 16;
3687 }
3688
3689 static int pack_ad8804(int addr,int val,int *bitstring)
3690 {
3691         *bitstring=((addr&0xf)<<8) | (val&0xff);
3692         return 12;
3693 }
3694
3695 static int pack_ad8842(int addr,int val,int *bitstring)
3696 {
3697         *bitstring=((addr+1)<<8) | (val&0xff);
3698         return 12;
3699 }
3700
3701
3702
3703
3704
3705 /*
3706  *
3707  *  General Purpose Counter/Timer section
3708  *
3709  */
3710
3711 /*
3712  * Low level stuff...Each STC counter has two 24 bit load registers
3713  * (A&B).  Just make it easier to access them.
3714  *
3715  * These are inlined _only_ because they are used once in subsequent
3716  * code.  Otherwise they should not be inlined.
3717  */
3718 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3719 {
3720         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_A_Register(chan));
3721 }
3722
3723 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3724 {
3725         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_B_Register(chan));
3726 }
3727
3728 /*  Load a value into the counter, using register A as the intermediate step.
3729 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3730 *  reset its value.
3731 */
3732 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3733 {
3734         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3735         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3736         GPCT_Load_A(dev,chan,value);
3737         devpriv->stc_writew(dev,  devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3738 }
3739
3740 /*
3741  *      Read the GPCTs current value.
3742  */
3743 static int GPCT_G_Watch(comedi_device *dev, int chan)
3744 {
3745         unsigned int hi1,hi2,lo;
3746
3747         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3748         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3749
3750         devpriv->gpct_command[chan] |= G_Save_Trace;
3751         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
3752
3753         /* This procedure is used because the two registers cannot
3754          * be read atomically. */
3755         do{
3756                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3757                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
3758                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3759         }while(hi1!=hi2);
3760
3761         return (hi1<<16)|lo;
3762 }
3763
3764
3765 static int GPCT_Disarm(comedi_device *dev, int chan)
3766 {
3767         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3768         return 0;
3769 }
3770
3771
3772 static int GPCT_Arm(comedi_device *dev, int chan)
3773 {
3774         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3775         /* If the counter is doing pulse width measurement, then make
3776          sure that the counter did not start counting right away.  This would
3777          indicate that we started acquiring the pulse after it had already
3778          started and our measurement would be inaccurate */
3779         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3780                 int g_status;
3781
3782                 g_status=devpriv->stc_readw(dev, G_Status_Register);
3783
3784                 if(chan == 0){
3785                         //TIM 5/2/01 possible error with very short pulses
3786                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3787                                 //error: we missed the beginning of the pulse
3788                                 return -EINVAL; //there is probably a more accurate error code...
3789                         }
3790                 }else{
3791                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3792                                 //error: we missed the beginning of the pulse
3793                                 return -EINVAL;
3794                         }
3795                 }
3796         }
3797         return 0;
3798 }
3799
3800 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3801 {
3802         //printk("GPCT_Set_Source...");
3803         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3804         switch(source) {
3805                 case GPCT_INT_CLOCK:
3806                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3807                 break;
3808         case GPCT_EXT_PIN:
3809                 if(chan==0)
3810                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3811                 else
3812                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3813                 break;
3814         default:
3815                 return -EINVAL;
3816         }
3817         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3818         //printk("exit GPCT_Set_Source\n");
3819         return 0;
3820 }
3821
3822 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3823 {
3824         //printk("GPCT_Set_Gate...");
3825         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3826         switch(gate) {
3827         case GPCT_NO_GATE:
3828                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3829                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3830                 break;
3831         case GPCT_EXT_PIN:
3832                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3833                 if(chan==0){
3834                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3835                 }else{
3836                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3837                 }
3838                 break;
3839         default:
3840                 return -EINVAL;
3841         }
3842         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3843         devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3844         //printk("exit GPCT_Set_Gate\n");
3845         return 0;
3846 }
3847
3848 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3849 {
3850         //printk("GPCT_Set_Direction...");
3851
3852         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3853         switch (direction) {
3854                 case GPCT_UP:
3855                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3856                         break;
3857                 case GPCT_DOWN:
3858                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3859                         break;
3860                 case GPCT_HWUD:
3861                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3862                         break;
3863                 default:
3864                         rt_printk("Error direction=0x%08x..",direction);
3865                         return -EINVAL;
3866         }
3867         devpriv->stc_writew(dev, devpriv->gpct_command[chan], G_Command_Register(chan));
3868         //TIM 4/23/01 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3869         //printk("exit GPCT_Set_Direction\n");
3870         return 0;
3871 }
3872
3873 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3874 {
3875
3876         //NOTE: possible residual bits from multibit masks can corrupt
3877         //If you config for several measurements between Resets, watch out!
3878
3879         //printk("GPCT_Event_Counting...");
3880
3881         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3882
3883         // Gating_Mode = 1
3884         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3885         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3886
3887         // Trigger_Mode_For_Edge_Gate = 1
3888         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3889         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3890
3891         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3892         //printk("exit GPCT_Event_Counting\n");
3893 }
3894
3895 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3896 {
3897         //printk("GPCT_Period_Meas...");
3898
3899         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3900
3901
3902         //NOTE: possible residual bits from multibit masks can corrupt
3903         //If you config for several measurements between Resets, watch out!
3904         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3905         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3906
3907         // Output_Mode = 3
3908         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3909         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3910
3911
3912         //Gating Mode=2
3913         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3914         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
3915
3916         // Trigger_Mode_For_Edge_Gate=0
3917         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3918         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
3919
3920         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3921         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3922         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3923         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3924
3925         // Stop_Mode = 2
3926         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3927         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3928
3929         // Counting_Once = 2
3930         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3931         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3932
3933         // Up_Down = 1
3934         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3935         devpriv->gpct_command[chan] |= G_Up_Down(1);
3936
3937         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3938         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3939         //printk("exit GPCT_Period_Meas\n");
3940 }
3941
3942 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
3943 {
3944         //printk("GPCT_Pulse_Width_Meas...");
3945
3946         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
3947
3948         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3949         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3950
3951         // Output_Mode = 3
3952         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3953         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3954
3955         //Gating Mode=1
3956         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3957         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
3958
3959         // Trigger_Mode_For_Edge_Gate=2
3960         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3961         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
3962
3963
3964         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
3965         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
3966
3967         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3968         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3969
3970         // Stop_Mode = 0
3971         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3972         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3973
3974         // Counting_Once = 2
3975         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3976         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3977
3978         // Up_Down = 1
3979         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3980         devpriv->gpct_command[chan] |= G_Up_Down(1);
3981
3982         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3983         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3984
3985         //printk("exit GPCT_Pulse_Width_Meas\n");
3986 }
3987
3988 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
3989 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
3990 be modified to send a pulse in response to a trigger event at its gate.*/
3991 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
3992 {
3993         //printk("GPCT_Gen_Cont...");
3994
3995         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
3996
3997         // Set length of the pulse
3998         GPCT_Load_B(dev,chan, length-1);
3999
4000         //Load next time using B, This is reset by GPCT_Load_Using_A()
4001         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4002
4003         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4004         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4005
4006         // Output_Mode = 3
4007         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4008         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4009
4010         //Gating Mode=0 for untriggered single pulse
4011         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4012         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
4013
4014         // Trigger_Mode_For_Edge_Gate=0
4015         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4016         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4017
4018
4019         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4020         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4021         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
4022         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4023
4024         // Stop_Mode = 2
4025         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4026         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
4027
4028         // Counting_Once = 2
4029         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4030         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
4031
4032         // Up_Down = 1
4033         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4034         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
4035
4036         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4037         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4038
4039         //printk("exit GPCT_Gen_Cont\n");
4040 }
4041
4042 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
4043 {
4044         //printk("GPCT_Gen_Cont...");
4045
4046         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
4047
4048         // Set length of the pulse
4049         GPCT_Load_B(dev,chan, length-1);
4050
4051         //Load next time using B, This is reset by GPCT_Load_Using_A()
4052         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4053
4054         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4055         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4056
4057         // Output_Mode = 3
4058         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4059         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4060
4061         //Gating Mode=0 for untriggered single pulse
4062         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4063         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
4064
4065         // Trigger_Mode_For_Edge_Gate=0
4066         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4067         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4068
4069
4070         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4071         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4072         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
4073         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4074
4075         // Stop_Mode = 2
4076         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4077         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
4078
4079         // Counting_Once = 2
4080         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4081         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
4082
4083         // Up_Down = 1
4084         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4085         devpriv->gpct_command[chan] |= G_Up_Down(0);
4086
4087         //TIM 4/26/01
4088         //This seems pretty unsafe since I don't think it is cleared anywhere.
4089         //I don't think this is working
4090         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
4091         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
4092
4093
4094         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4095         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4096
4097         //printk("exit GPCT_Gen_Cont\n");
4098 }
4099
4100 static void GPCT_Reset(comedi_device *dev, int chan)
4101 {
4102         int temp_ack_reg=0;
4103
4104         //printk("GPCT_Reset...");
4105         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4106
4107         switch (chan) {
4108                 case 0:
4109                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4110                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4111                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4112                         temp_ack_reg |= G0_Gate_Error_Confirm;
4113                         temp_ack_reg |= G0_TC_Error_Confirm;
4114                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4115                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4116                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4117
4118                         //problem...this interferes with the other ctr...
4119                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4120                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4121                         break;
4122                 case 1:
4123                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4124                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4125                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4126                         temp_ack_reg |= G1_Gate_Error_Confirm;
4127                         temp_ack_reg |= G1_TC_Error_Confirm;
4128                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4129                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4130                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4131
4132                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4133                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4134                         break;
4135         };
4136
4137         devpriv->gpct_mode[chan] = 0;
4138         devpriv->gpct_input_select[chan] = 0;
4139         devpriv->gpct_command[chan] = 0;
4140
4141         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4142
4143         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4144         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4145         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4146
4147         //printk("exit GPCT_Reset\n");
4148 }
4149
4150 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
4151         comedi_insn *insn,lsampl_t *data)
4152 {
4153         int retval=0;
4154         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4155         switch(data[0]){
4156         case GPCT_RESET:
4157                 if(insn->n!=1)return -EINVAL;
4158                 GPCT_Reset(dev,insn->chanspec);
4159                 break;
4160         case GPCT_SET_SOURCE:
4161                 if(insn->n!=2)return -EINVAL;
4162                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
4163                 break;
4164         case GPCT_SET_GATE:
4165                 if(insn->n!=2)return -EINVAL;
4166                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
4167                 break;
4168         case GPCT_SET_DIRECTION:
4169                 if(insn->n!=2) return -EINVAL;
4170                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
4171                 break;
4172         case GPCT_GET_INT_CLK_FRQ:
4173                 if(insn->n!=2) return -EINVAL;
4174                 //There are actually 2 internal clocks on the STC, we always
4175                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
4176                 //NOTE: This is not the final interface, ideally the user
4177                 //will never need to know the int. clk. freq.
4178                 data[1]=50;//50ns = 20MHz = internal timebase of STC
4179                 break;
4180         case GPCT_SET_OPERATION:
4181                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
4182                 switch(data[1]){
4183                         case GPCT_SIMPLE_EVENT:
4184                                 GPCT_Event_Counting(dev,insn->chanspec);
4185                                 break;
4186                         case GPCT_SINGLE_PERIOD:
4187                                 GPCT_Period_Meas(dev,insn->chanspec);
4188                                 break;
4189                         case GPCT_SINGLE_PW:
4190                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
4191                                 break;
4192                         case GPCT_SINGLE_PULSE_OUT:
4193                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
4194                                 break;
4195                         case GPCT_CONT_PULSE_OUT:
4196                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
4197                                 break;
4198                         default:
4199                                 rt_printk("unsupported GPCT operation!\n");
4200                                 return -EINVAL;
4201                 }
4202                 break;
4203         case GPCT_ARM:
4204                 if(insn->n!=1)return -EINVAL;
4205                 retval=GPCT_Arm(dev,insn->chanspec);
4206                 break;
4207         case GPCT_DISARM:
4208                 if(insn->n!=1)return -EINVAL;
4209                 retval=GPCT_Disarm(dev,insn->chanspec);
4210                 break;
4211         default:
4212                 return -EINVAL;
4213         }
4214
4215         //catch any errors from return values
4216         if(retval==0){
4217                 return insn->n;
4218         }else{
4219                 if(data[0]!=GPCT_ARM){
4220                         rt_printk("error: retval was %d\n",retval);
4221                         rt_printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4222                 }
4223
4224                 return retval;
4225         }
4226 }
4227
4228 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
4229         comedi_insn *insn,lsampl_t *data) {
4230
4231         int chan=insn->chanspec;
4232         int cur_op = devpriv->gpct_cur_operation[chan];
4233
4234         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
4235         if(insn->n!=1)return -EINVAL;
4236
4237         data[0] = GPCT_G_Watch(dev,insn->chanspec);
4238
4239         /* for certain modes (period and pulse width measurment), the value
4240         in the counter is not valid until the counter stops.  If the value is
4241         invalid, return a 0 */
4242         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
4243                 /* is the counter still running? */
4244                 if(devpriv->stc_readw(dev, G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
4245                         data[0]=0;
4246         }
4247         return 1;
4248 }
4249
4250 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
4251         comedi_insn *insn,lsampl_t *data) {
4252
4253         //printk("in ni_gpct_insn_write");
4254         if(insn->n!=1)return -EINVAL;
4255         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
4256         return 1;
4257 }
4258
4259
4260 /*
4261  *
4262  *  Programmable Function Inputs
4263  *
4264  */
4265
4266 int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4267 {
4268         if((source & 0x1f) != source) return -EINVAL;
4269         const unsigned pfi_reg_index = 1 + chan / 3;
4270         const unsigned array_offset = pfi_reg_index - 1;
4271         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4272         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4273         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4274         return 2;
4275 }
4276
4277 int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4278 {
4279         // pre-m-series boards have fixed signals on pfi pins
4280         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4281         return 2;
4282 }
4283
4284 int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4285 {
4286         if(boardtype.reg_type == ni_reg_m_series)
4287                 return ni_m_series_set_pfi_routing(dev, chan, source);
4288         else
4289                 return ni_old_set_pfi_routing(dev, chan, source);
4290 }
4291
4292 unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4293 {
4294         const unsigned array_offset = chan / 3;
4295         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4296 }
4297
4298 unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4299 {
4300         // pre-m-series boards have fixed signals on pfi pins
4301         switch(chan)
4302         {
4303         case 0:
4304                 return NI_PFI_OUTPUT_AI_START1;
4305                 break;
4306         case 1:
4307                 return NI_PFI_OUTPUT_AI_START2;
4308                 break;
4309         case 2:
4310                 return NI_PFI_OUTPUT_AI_CONVERT;
4311                 break;
4312         case 3:
4313                 return NI_PFI_OUTPUT_G_SRC1;
4314                 break;
4315         case 4:
4316                 return NI_PFI_OUTPUT_G_GATE1;
4317                 break;
4318         case 5:
4319                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4320                 break;
4321         case 6:
4322                 return NI_PFI_OUTPUT_AO_START1;
4323                 break;
4324         case 7:
4325                 return NI_PFI_OUTPUT_AI_START_PULSE;
4326                 break;
4327         case 8:
4328                 return NI_PFI_OUTPUT_G_SRC0;
4329                 break;
4330         case 9:
4331                 return NI_PFI_OUTPUT_G_GATE0;
4332                 break;
4333         default:
4334                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4335                 break;
4336         }
4337         return 0;
4338 }
4339
4340 unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4341 {
4342         if(boardtype.reg_type == ni_reg_m_series)
4343                 return ni_m_series_get_pfi_routing(dev, chan);
4344         else
4345                 return ni_old_get_pfi_routing(dev, chan);
4346 }
4347
4348 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4349         comedi_insn *insn,lsampl_t *data)
4350 {
4351         if(insn->n!=2)return -EINVAL;
4352
4353         data[1] = 0;
4354
4355         return 2;
4356 }
4357
4358 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4359         comedi_insn *insn,lsampl_t *data)
4360 {
4361         unsigned int chan;
4362
4363         if(insn->n < 1)return -EINVAL;
4364
4365         chan = CR_CHAN(insn->chanspec);
4366
4367         switch(data[0]){
4368         case COMEDI_OUTPUT:
4369                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4370                 break;
4371         case COMEDI_INPUT:
4372                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4373                 break;
4374         case INSN_CONFIG_DIO_QUERY:
4375                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4376                 return insn->n;
4377                 break;
4378         case INSN_CONFIG_SET_ROUTING:
4379                 return ni_set_pfi_routing(dev, chan, data[1]);
4380                 break;
4381         case INSN_CONFIG_GET_ROUTING:
4382                 data[1] = ni_get_pfi_routing(dev, chan);
4383                 return 2;
4384                 break;
4385         default:
4386                 return -EINVAL;
4387         }
4388
4389         return 1;
4390 }
4391
4392 /*
4393  *
4394  *  NI RTSI Bus Functions
4395  *
4396  */
4397 static void ni_rtsi_init(comedi_device *dev)
4398 {
4399         // Initialises the RTSI bus signal switch to a default state
4400
4401         // Set clock mode to internal
4402         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4403         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4404         {
4405                 rt_printk("ni_set_master_clock failed, bug?");
4406         }
4407         // default internal lines routing to RTSI bus lines
4408         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4409                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4410                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4411                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4412         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4413                 RTSI_Trig_A_Output_Register);
4414         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4415                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4416                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4417         if(boardtype.reg_type == ni_reg_m_series)
4418                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4419         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4420                 RTSI_Trig_B_Output_Register);
4421
4422         // Sets the source and direction of the 4 on board lines
4423 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4424 }
4425
4426 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4427         comedi_insn *insn,lsampl_t *data)
4428 {
4429         if(insn->n != 2) return -EINVAL;
4430
4431         data[1] = 0;
4432
4433         return 2;
4434 }
4435
4436 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4437  * given an arbitrary frequency input clock */
4438 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4439         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4440 {
4441         unsigned div;
4442         unsigned best_div = 1;
4443         static const unsigned max_div = 0x10;
4444         unsigned mult;
4445         unsigned best_mult = 1;
4446         static const unsigned max_mult = 0x100;
4447         static const unsigned pico_per_nano = 1000;
4448
4449         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4450         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4451          * 20 MHz for most timing clocks */
4452         static const unsigned target_picosec = 12500;
4453         int best_period_picosec = 0;
4454         for(div = 1; div <= max_div; ++div)
4455         {
4456                 for(mult = 1; mult <= max_mult; ++mult)
4457                 {
4458                         unsigned new_period_ps = (reference_picosec * div) / mult;
4459                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4460                         {
4461                                 best_period_picosec = new_period_ps;
4462                                 best_div = div;
4463                                 best_mult = mult;
4464                         }
4465                 }
4466         }
4467         if(best_period_picosec == 0)
4468         {
4469                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4470                 return -EIO;
4471         }
4472         *freq_divider = best_div;
4473         *freq_multiplier = best_mult;
4474         static const unsigned fudge_factor_80_to_20Mhz = 4;
4475         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4476         return 0;
4477 }
4478
4479 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4480 {
4481         if(boardtype.reg_type == ni_reg_m_series) return 8;
4482         else return 7;
4483 }
4484
4485 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4486 {
4487         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4488         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4489         static const unsigned min_period_ns = 50;
4490         static const unsigned max_period_ns = 1000;
4491         if(period_ns < min_period_ns || period_ns > max_period_ns)
4492         {
4493                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4494                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4495                 return -EINVAL;
4496         }
4497         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4498         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4499         unsigned pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4500         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit;
4501         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4502         int retval;
4503         unsigned freq_divider;
4504         unsigned freq_multiplier;
4505         switch(source)
4506         {
4507         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4508                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4509                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4510                         &freq_multiplier, &devpriv->clock_ns);
4511                 if(retval < 0) return retval;
4512                 break;
4513         case NI_MIO_PLL_PXI10_CLOCK:
4514                 /* pxi clock is 10MHz */
4515                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4516                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4517                         &freq_multiplier, &devpriv->clock_ns);
4518                 if(retval < 0) return retval;
4519                 break;
4520         default:
4521                 {
4522                         unsigned rtsi_channel;
4523                         static const unsigned max_rtsi_channel = 7;
4524                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4525                         {
4526                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4527                                 {
4528                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4529                                         break;
4530                                 }
4531                         }
4532                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4533                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4534                                 &freq_multiplier, &devpriv->clock_ns);
4535                         if(retval < 0) return retval;
4536                 }
4537                 break;
4538         }
4539         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4540         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4541 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4542 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4543         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4544         devpriv->clock_source = source;
4545         unsigned i;
4546         static const unsigned timeout = 1000;
4547         /* it seems to typically take a few hundred microseconds for PLL to lock */
4548         for(i = 0; i < timeout; ++i)
4549         {
4550                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4551                 {
4552                         break;
4553                 }
4554                 udelay(1);
4555         }
4556         if(i == timeout)
4557         {
4558                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4559                         __FUNCTION__, source, period_ns);
4560                 return -ETIMEDOUT;
4561         }
4562         return 3;
4563 }
4564
4565 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4566 {
4567         if(source == NI_MIO_INTERNAL_CLOCK)
4568         {
4569                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4570                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4571                 devpriv->clock_ns = 50;
4572                 if(boardtype.reg_type == ni_reg_m_series)
4573                 {
4574                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4575                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4576                         ni_writew(0, M_Offset_PLL_Control);
4577                 }
4578                 devpriv->clock_source = source;
4579         }else
4580         {
4581                 if(boardtype.reg_type == ni_reg_m_series)
4582                 {
4583                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4584                 }else
4585                 {
4586                         if(source == NI_MIO_RTSI_CLOCK)
4587                         {
4588                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4589                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4590                                 if(devpriv->clock_ns == 0)
4591                                 {
4592                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4593                                                 __FUNCTION__);
4594                                         return -EINVAL;
4595                                 }else
4596                                 {
4597                                         devpriv->clock_ns = period_ns;
4598                                 }
4599                                 devpriv->clock_source = source;
4600                         }else
4601                                 return -EINVAL;
4602                 }
4603         }
4604         return 3;
4605 }
4606
4607 int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4608 {
4609         if(chan >= num_configurable_rtsi_channels(dev))
4610         {
4611                 if(chan == old_RTSI_clock_channel)
4612                 {
4613                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4614                         else
4615                         {
4616                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4617                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4618                                 return 0;
4619                         }
4620                 }
4621                 return 0;
4622         }
4623         switch(source)
4624         {
4625         case NI_RTSI_OUTPUT_ADR_START1:
4626         case NI_RTSI_OUTPUT_ADR_START2:
4627         case NI_RTSI_OUTPUT_SCLKG:
4628         case NI_RTSI_OUTPUT_DACUPDN:
4629         case NI_RTSI_OUTPUT_DA_START1:
4630         case NI_RTSI_OUTPUT_G_SRC0:
4631         case NI_RTSI_OUTPUT_G_GATE0:
4632         case NI_RTSI_OUTPUT_RGOUT0:
4633         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4634                 return 1;
4635                 break;
4636         case NI_RTSI_OUTPUT_RTSI_OSC:
4637                 if(boardtype.reg_type == ni_reg_m_series)
4638                         return 1;
4639                 else return 0;
4640                 break;
4641         default:
4642                 return 0;
4643                 break;
4644         }
4645 }
4646
4647 int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4648 {
4649         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4650         if(chan < 4)
4651         {
4652                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4653                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4654                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4655                         RTSI_Trig_A_Output_Register);
4656         }else if(chan < 8)
4657         {
4658                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4659                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4660                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4661                         RTSI_Trig_B_Output_Register);
4662         }
4663         return 2;
4664 }
4665
4666 unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4667 {
4668         if(chan < 4)
4669         {
4670                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4671         }else if(chan < num_configurable_rtsi_channels(dev))
4672         {
4673                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4674         }else
4675         {
4676                 if(chan == old_RTSI_clock_channel)
4677                         return NI_RTSI_OUTPUT_RTSI_OSC;
4678                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4679                 return 0;
4680         }
4681 }
4682
4683 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4684         comedi_insn *insn,lsampl_t *data)
4685 {
4686         unsigned int chan = CR_CHAN(insn->chanspec);
4687         switch(data[0]){
4688         case INSN_CONFIG_DIO_OUTPUT:
4689                 if(chan < num_configurable_rtsi_channels(dev))
4690                 {
4691                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4692                 }else if(chan == old_RTSI_clock_channel)
4693                 {
4694                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4695                 }
4696                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4697                 break;
4698         case INSN_CONFIG_DIO_INPUT:
4699                 if(chan < num_configurable_rtsi_channels(dev))
4700                 {
4701                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4702                 }else if(chan == old_RTSI_clock_channel)
4703                 {
4704                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4705                 }
4706                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4707                 break;
4708         case INSN_CONFIG_DIO_QUERY:
4709                 if(chan < num_configurable_rtsi_channels(dev))
4710                 {
4711                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series)) ?
4712                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4713                 }else if(chan == old_RTSI_clock_channel)
4714                 {
4715                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4716                 }
4717                 return 2;
4718                 break;
4719         case INSN_CONFIG_SET_CLOCK_SRC:
4720                 return ni_set_master_clock(dev, data[1], data[2]);
4721                 break;
4722         case INSN_CONFIG_GET_CLOCK_SRC:
4723                 data[1] = devpriv->clock_source;
4724                 data[2] = devpriv->clock_ns;
4725                 return 3;
4726                 break;
4727         case INSN_CONFIG_SET_ROUTING:
4728                 return ni_set_rtsi_routing(dev, chan, data[1]);
4729                 break;
4730         case INSN_CONFIG_GET_ROUTING:
4731                 data[1] = ni_get_rtsi_routing(dev, chan);
4732                 return 2;
4733                 break;
4734         default:
4735                 return -EINVAL;
4736                 break;
4737         }
4738         return 1;
4739 }
4740
4741 static int cs5529_wait_for_idle(comedi_device *dev)
4742 {
4743         unsigned short status;
4744         const int timeout = HZ;
4745         int i;
4746
4747         for(i = 0; i < timeout; i++)
4748         {
4749                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4750                 if((status & CSS_ADC_BUSY) == 0)
4751                 {
4752                         break;
4753                 }
4754                 set_current_state(TASK_INTERRUPTIBLE);
4755                 if(schedule_timeout(1))
4756                 {
4757                         return -EIO;
4758                 }
4759         }
4760 //printk("looped %i times waiting for idle\n", i);
4761         if(i == timeout)
4762         {
4763                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4764                 return -ETIME;
4765         }
4766         return 0;
4767 }
4768
4769 static void cs5529_command(comedi_device *dev, unsigned short value)
4770 {
4771         static const int timeout = 100;
4772         int i;
4773
4774         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4775         /* give time for command to start being serially clocked into cs5529.
4776          * this insures that the CSS_ADC_BUSY bit will get properly
4777          * set before we exit this function.
4778         */
4779         for(i = 0; i < timeout; i++)
4780         {
4781                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4782                         break;
4783                 comedi_udelay(1);
4784         }
4785 //printk("looped %i times writing command to cs5529\n", i);
4786         if(i == timeout)
4787         {
4788                 comedi_error(dev, "possible problem - never saw adc go busy?");
4789         }
4790 }
4791
4792 /* write to cs5529 register */
4793 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4794 {
4795         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4796         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4797         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4798         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4799         if(cs5529_wait_for_idle(dev))
4800                 comedi_error(dev, "time or signal in cs5529_config_write()");
4801 }
4802
4803 /* read from cs5529 register */
4804 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4805 {
4806         unsigned int value;
4807
4808         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4809         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4810         if(cs5529_wait_for_idle(dev))
4811                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4812         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4813         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4814         return value;
4815 }
4816
4817 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4818 {
4819         int retval;
4820         unsigned short status;
4821
4822         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4823         retval = cs5529_wait_for_idle(dev);
4824         if(retval)
4825         {
4826                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4827                 return -ETIME;
4828         }
4829         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4830         if(status & CSS_OSC_DETECT)
4831         {
4832                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4833                 return -EIO;
4834         }
4835         if(status & CSS_OVERRANGE)
4836         {
4837                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4838         }
4839         if(data)
4840         {
4841                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4842                 /* cs5529 returns 16 bit signed data in bipolar mode */
4843                 *data ^= (1 << 15);
4844         }
4845         return 0;
4846 }
4847
4848 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4849 {
4850         int n, retval;
4851         unsigned short sample;
4852         unsigned int channel_select;
4853         const unsigned int INTERNAL_REF = 0x1000;
4854
4855         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4856          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4857          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4858         if(insn->chanspec & CR_ALT_SOURCE)
4859                 channel_select = INTERNAL_REF;
4860         else
4861                 channel_select = CR_CHAN(insn->chanspec);
4862         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4863
4864         for(n = 0; n < insn->n; n++)
4865         {
4866                 retval = cs5529_do_conversion(dev, &sample);
4867                 if(retval < 0) return retval;
4868                 data[n] = sample;
4869         }
4870         return insn->n;
4871 }
4872
4873 static int init_cs5529(comedi_device *dev)
4874 {
4875         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4876
4877 #if 1
4878         /* do self-calibration */
4879         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4880         /* need to force a conversion for calibration to run */
4881         cs5529_do_conversion(dev, NULL);
4882 #else
4883         /* force gain calibration to 1 */
4884         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4885         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4886         if(cs5529_wait_for_idle(dev))
4887                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4888 #endif
4889         if(0)
4890         {
4891                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4892                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4893                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4894         }
4895         return 0;
4896 }
4897
4898