comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static const short ni_gainlkup[][16] = {
  78         /* ai_gain_16 */
  79         {0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107},
  81         /* ai_gain_8 */
  82         {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  83         /* ai_gain_14 */
  84         {1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107},
  86         /* ai_gain_4 */
  87         {0, 1, 4, 7},
  88         /* ai_gain_611x */
  89         {0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006},
  90         /* ai_gain_622x */
  91         {0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         {1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  96 };
  97
  98 static const comedi_lrange range_ni_E_ai = { 16, {
  99                         RANGE(-10, 10),
 100                         RANGE(-5, 5),
 101                         RANGE(-2.5, 2.5),
 102                         RANGE(-1, 1),
 103                         RANGE(-0.5, 0.5),
 104                         RANGE(-0.25, 0.25),
 105                         RANGE(-0.1, 0.1),
 106                         RANGE(-0.05, 0.05),
 107                         RANGE(0, 20),
 108                         RANGE(0, 10),
 109                         RANGE(0, 5),
 110                         RANGE(0, 2),
 111                         RANGE(0, 1),
 112                         RANGE(0, 0.5),
 113                         RANGE(0, 0.2),
 114                         RANGE(0, 0.1),
 115         }
 116 };
 117 static const comedi_lrange range_ni_E_ai_limited = { 8, {
 118                         RANGE(-10, 10),
 119                         RANGE(-5, 5),
 120                         RANGE(-1, 1),
 121                         RANGE(-0.1, 0.1),
 122                         RANGE(0, 10),
 123                         RANGE(0, 5),
 124                         RANGE(0, 1),
 125                         RANGE(0, 0.1),
 126         }
 127 };
 128 static const comedi_lrange range_ni_E_ai_limited14 = { 14, {
 129                         RANGE(-10, 10),
 130                         RANGE(-5, 5),
 131                         RANGE(-2, 2),
 132                         RANGE(-1, 1),
 133                         RANGE(-0.5, 0.5),
 134                         RANGE(-0.2, 0.2),
 135                         RANGE(-0.1, 0.1),
 136                         RANGE(0, 10),
 137                         RANGE(0, 5),
 138                         RANGE(0, 2),
 139                         RANGE(0, 1),
 140                         RANGE(0, 0.5),
 141                         RANGE(0, 0.2),
 142                         RANGE(0, 0.1),
 143         }
 144 };
 145 static const comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 146                         RANGE(-10, 10),
 147                         RANGE(-5, 5),
 148                         RANGE(-0.5, 0.5),
 149                         RANGE(-0.05, 0.05),
 150         }
 151 };
 152 static const comedi_lrange range_ni_E_ai_611x = { 8, {
 153                         RANGE(-50, 50),
 154                         RANGE(-20, 20),
 155                         RANGE(-10, 10),
 156                         RANGE(-5, 5),
 157                         RANGE(-2, 2),
 158                         RANGE(-1, 1),
 159                         RANGE(-0.5, 0.5),
 160                         RANGE(-0.2, 0.2),
 161         }
 162 };
 163 static const comedi_lrange range_ni_M_ai_622x = { 4, {
 164                         RANGE(-10, 10),
 165                         RANGE(-5, 5),
 166                         RANGE(-1, 1),
 167                         RANGE(-0.2, 0.2),
 168         }
 169 };
 170 static const comedi_lrange range_ni_M_ai_628x = { 7, {
 171                         RANGE(-10, 10),
 172                         RANGE(-5, 5),
 173                         RANGE(-2, 2),
 174                         RANGE(-1, 1),
 175                         RANGE(-0.5, 0.5),
 176                         RANGE(-0.2, 0.2),
 177                         RANGE(-0.1, 0.1),
 178         }
 179 };
 180 static const comedi_lrange range_ni_S_ai_6143 = { 1, {
 181                         RANGE(-5, +5),
 182         }
 183 };
 184 static const comedi_lrange range_ni_E_ao_ext = { 4, {
 185                         RANGE(-10, 10),
 186                         RANGE(0, 10),
 187                         RANGE_ext(-1, 1),
 188                         RANGE_ext(0, 1),
 189         }
 190 };
 191
 192 static const comedi_lrange *const ni_range_lkup[] = {
 193         &range_ni_E_ai,
 194         &range_ni_E_ai_limited,
 195         &range_ni_E_ai_limited14,
 196         &range_ni_E_ai_bipolar4,
 197         &range_ni_E_ai_611x,
 198         &range_ni_M_ai_622x,
 199         &range_ni_M_ai_628x,
 200         &range_ni_S_ai_6143
 201 };
 202
 203 static int ni_dio_insn_config(comedi_device * dev, comedi_subdevice * s,
 204         comedi_insn * insn, lsampl_t * data);
 205 static int ni_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
 206         comedi_insn * insn, lsampl_t * data);
 207 static int ni_cdio_cmdtest(comedi_device * dev, comedi_subdevice * s,
 208         comedi_cmd * cmd);
 209 static int ni_cdio_cmd(comedi_device * dev, comedi_subdevice * s);
 210 static int ni_cdio_cancel(comedi_device * dev, comedi_subdevice * s);
 211 static void handle_cdio_interrupt(comedi_device * dev);
 212 static int ni_cdo_inttrig(comedi_device * dev, comedi_subdevice * s,
 213         unsigned int trignum);
 214
 215 static int ni_serial_insn_config(comedi_device * dev, comedi_subdevice * s,
 216         comedi_insn * insn, lsampl_t * data);
 217 static int ni_serial_hw_readwrite8(comedi_device * dev, comedi_subdevice * s,
 218         unsigned char data_out, unsigned char *data_in);
 219 static int ni_serial_sw_readwrite8(comedi_device * dev, comedi_subdevice * s,
 220         unsigned char data_out, unsigned char *data_in);
 221
 222 static int ni_calib_insn_read(comedi_device * dev, comedi_subdevice * s,
 223         comedi_insn * insn, lsampl_t * data);
 224 static int ni_calib_insn_write(comedi_device * dev, comedi_subdevice * s,
 225         comedi_insn * insn, lsampl_t * data);
 226
 227 static int ni_eeprom_insn_read(comedi_device * dev, comedi_subdevice * s,
 228         comedi_insn * insn, lsampl_t * data);
 229 static int ni_m_series_eeprom_insn_read(comedi_device * dev,
 230         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data);
 231
 232 static int ni_pfi_insn_bits(comedi_device * dev, comedi_subdevice * s,
 233         comedi_insn * insn, lsampl_t * data);
 234 static int ni_pfi_insn_config(comedi_device * dev, comedi_subdevice * s,
 235         comedi_insn * insn, lsampl_t * data);
 236 static unsigned ni_old_get_pfi_routing(comedi_device * dev, unsigned chan);
 237
 238 static void ni_rtsi_init(comedi_device * dev);
 239 static int ni_rtsi_insn_bits(comedi_device * dev, comedi_subdevice * s,
 240         comedi_insn * insn, lsampl_t * data);
 241 static int ni_rtsi_insn_config(comedi_device * dev, comedi_subdevice * s,
 242         comedi_insn * insn, lsampl_t * data);
 243
 244 static void caldac_setup(comedi_device * dev, comedi_subdevice * s);
 245 static int ni_read_eeprom(comedi_device * dev, int addr);
 246
 247 #ifdef DEBUG_STATUS_A
 248 static void ni_mio_print_status_a(int status);
 249 #else
 250 #define ni_mio_print_status_a(a)
 251 #endif
 252 #ifdef DEBUG_STATUS_B
 253 static void ni_mio_print_status_b(int status);
 254 #else
 255 #define ni_mio_print_status_b(a)
 256 #endif
 257
 258 static int ni_ai_reset(comedi_device * dev, comedi_subdevice * s);
 259 #ifndef PCIDMA
 260 static void ni_handle_fifo_half_full(comedi_device * dev);
 261 static int ni_ao_fifo_half_empty(comedi_device * dev, comedi_subdevice * s);
 262 #endif
 263 static void ni_handle_fifo_dregs(comedi_device * dev);
 264 static int ni_ai_inttrig(comedi_device * dev, comedi_subdevice * s,
 265         unsigned int trignum);
 266 static void ni_load_channelgain_list(comedi_device * dev, unsigned int n_chan,
 267         unsigned int *list);
 268 static void shutdown_ai_command(comedi_device * dev);
 269
 270 static int ni_ao_inttrig(comedi_device * dev, comedi_subdevice * s,
 271         unsigned int trignum);
 272
 273 static int ni_ao_reset(comedi_device * dev, comedi_subdevice * s);
 274
 275 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 276
 277 static int ni_gpct_insn_write(comedi_device * dev, comedi_subdevice * s,
 278         comedi_insn * insn, lsampl_t * data);
 279 static int ni_gpct_insn_read(comedi_device * dev, comedi_subdevice * s,
 280         comedi_insn * insn, lsampl_t * data);
 281 static int ni_gpct_insn_config(comedi_device * dev, comedi_subdevice * s,
 282         comedi_insn * insn, lsampl_t * data);
 283 static int ni_gpct_cmd(comedi_device * dev, comedi_subdevice * s);
 284 static int ni_gpct_cmdtest(comedi_device * dev, comedi_subdevice * s,
 285         comedi_cmd * cmd);
 286 static int ni_gpct_cancel(comedi_device * dev, comedi_subdevice * s);
 287 static void handle_gpct_interrupt(comedi_device * dev,
 288         unsigned short counter_index);
 289
 290 static int init_cs5529(comedi_device * dev);
 291 static int cs5529_do_conversion(comedi_device * dev, unsigned short *data);
 292 static int cs5529_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
 293         comedi_insn * insn, lsampl_t * data);
 294 static unsigned int cs5529_config_read(comedi_device * dev,
 295         unsigned int reg_select_bits);
 296 static void cs5529_config_write(comedi_device * dev, unsigned int value,
 297         unsigned int reg_select_bits);
 298
 299 static int ni_m_series_pwm_config(comedi_device * dev, comedi_subdevice * s,
 300         comedi_insn * insn, lsampl_t * data);
 301 static int ni_6143_pwm_config(comedi_device * dev, comedi_subdevice * s,
 302         comedi_insn * insn, lsampl_t * data);
 303
 304 static int ni_set_master_clock(comedi_device * dev, unsigned source,
 305         unsigned period_ns);
 306 static void ack_a_interrupt(comedi_device * dev, unsigned short a_status);
 307 static void ack_b_interrupt(comedi_device * dev, unsigned short b_status);
 308
 309 enum aimodes {
 310         AIMODE_NONE = 0,
 311         AIMODE_HALF_FULL = 1,
 312         AIMODE_SCAN = 2,
 313         AIMODE_SAMPLE = 3,
 314 };
 315
 316 enum ni_common_subdevices {
 317         NI_AI_SUBDEV,
 318         NI_AO_SUBDEV,
 319         NI_DIO_SUBDEV,
 320         NI_8255_DIO_SUBDEV,
 321         NI_UNUSED_SUBDEV,
 322         NI_CALIBRATION_SUBDEV,
 323         NI_EEPROM_SUBDEV,
 324         NI_PFI_DIO_SUBDEV,
 325         NI_CS5529_CALIBRATION_SUBDEV,
 326         NI_SERIAL_SUBDEV,
 327         NI_RTSI_SUBDEV,
 328         NI_GPCT0_SUBDEV,
 329         NI_GPCT1_SUBDEV,
 330         NI_FREQ_OUT_SUBDEV,
 331         NI_NUM_SUBDEVICES
 332 };
 333 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 334 {
 335         switch (counter_index) {
 336         case 0:
 337                 return NI_GPCT0_SUBDEV;
 338                 break;
 339         case 1:
 340                 return NI_GPCT1_SUBDEV;
 341                 break;
 342         default:
 343                 break;
 344         }
 345         BUG();
 346         return NI_GPCT0_SUBDEV;
 347 }
 348
 349 enum timebase_nanoseconds {
 350         TIMEBASE_1_NS = 50,
 351         TIMEBASE_2_NS = 10000
 352 };
 353
 354 #define SERIAL_DISABLED         0
 355 #define SERIAL_600NS            600
 356 #define SERIAL_1_2US            1200
 357 #define SERIAL_10US                     10000
 358
 359 static const int num_adc_stages_611x = 3;
 360
 361 static void handle_a_interrupt(comedi_device * dev, unsigned short status,
 362         unsigned ai_mite_status);
 363 static void handle_b_interrupt(comedi_device * dev, unsigned short status,
 364         unsigned ao_mite_status);
 365 static void get_last_sample_611x(comedi_device * dev);
 366 static void get_last_sample_6143(comedi_device * dev);
 367
 368 static inline void ni_set_bitfield(comedi_device * dev, int reg,
 369         unsigned bit_mask, unsigned bit_values)
 370 {
 371         unsigned long flags;
 372
 373         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 374         switch (reg) {
 375         case Interrupt_A_Enable_Register:
 376                 devpriv->int_a_enable_reg &= ~bit_mask;
 377                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 378                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 379                         Interrupt_A_Enable_Register);
 380                 break;
 381         case Interrupt_B_Enable_Register:
 382                 devpriv->int_b_enable_reg &= ~bit_mask;
 383                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 384                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 385                         Interrupt_B_Enable_Register);
 386                 break;
 387         case IO_Bidirection_Pin_Register:
 388                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 389                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 390                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 391                         IO_Bidirection_Pin_Register);
 392                 break;
 393         case AI_AO_Select:
 394                 devpriv->ai_ao_select_reg &= ~bit_mask;
 395                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 396                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 397                 break;
 398         case G0_G1_Select:
 399                 devpriv->g0_g1_select_reg &= ~bit_mask;
 400                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 401                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 402                 break;
 403         default:
 404                 rt_printk("Warning %s() called with invalid register\n",
 405                         __FUNCTION__);
 406                 rt_printk("reg is %d\n", reg);
 407                 break;
 408         }
 409         mmiowb();
 410         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 411 }
 412
 413 #ifdef PCIDMA
 414 static int ni_ai_drain_dma(comedi_device * dev);
 415
 416 /* DMA channel setup */
 417
 418 // negative channel means no channel
 419 static inline void ni_set_ai_dma_channel(comedi_device * dev, int channel)
 420 {
 421         unsigned bitfield;
 422
 423         if (channel >= 0) {
 424                 bitfield =
 425                         (ni_stc_dma_channel_select_bitfield(channel) <<
 426                         AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 427         } else {
 428                 bitfield = 0;
 429         }
 430         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 431 }
 432
 433 // negative channel means no channel
 434 static inline void ni_set_ao_dma_channel(comedi_device * dev, int channel)
 435 {
 436         unsigned bitfield;
 437
 438         if (channel >= 0) {
 439                 bitfield =
 440                         (ni_stc_dma_channel_select_bitfield(channel) <<
 441                         AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 442         } else {
 443                 bitfield = 0;
 444         }
 445         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 446 }
 447
 448 // negative mite_channel means no channel
 449 static inline void ni_set_gpct_dma_channel(comedi_device * dev,
 450         unsigned gpct_index, int mite_channel)
 451 {
 452         unsigned bitfield;
 453
 454         if (mite_channel >= 0) {
 455                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 456         } else {
 457                 bitfield = 0;
 458         }
 459         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 460                 bitfield);
 461 }
 462
 463 // negative mite_channel means no channel
 464 static inline void ni_set_cdo_dma_channel(comedi_device * dev, int mite_channel)
 465 {
 466         unsigned long flags;
 467
 468         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 469         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 470         if (mite_channel >= 0) {
 471                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 472                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 473                    Definitely works for dma channels 0 and 1. */
 474                 devpriv->cdio_dma_select_reg |=
 475                         (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 476                         CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 477         }
 478         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 479         mmiowb();
 480         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 481 }
 482
 483 static int ni_request_ai_mite_channel(comedi_device * dev)
 484 {
 485         unsigned long flags;
 486
 487         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 488         BUG_ON(devpriv->ai_mite_chan);
 489         devpriv->ai_mite_chan =
 490                 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 491         if (devpriv->ai_mite_chan == NULL) {
 492                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 493                         flags);
 494                 comedi_error(dev,
 495                         "failed to reserve mite dma channel for analog input.");
 496                 return -EBUSY;
 497         }
 498         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 499         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 500         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 501         return 0;
 502 }
 503
 504 static int ni_request_ao_mite_channel(comedi_device * dev)
 505 {
 506         unsigned long flags;
 507
 508         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 509         BUG_ON(devpriv->ao_mite_chan);
 510         devpriv->ao_mite_chan =
 511                 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 512         if (devpriv->ao_mite_chan == NULL) {
 513                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 514                         flags);
 515                 comedi_error(dev,
 516                         "failed to reserve mite dma channel for analog outut.");
 517                 return -EBUSY;
 518         }
 519         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 520         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 521         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 522         return 0;
 523 }
 524
 525 static int ni_request_gpct_mite_channel(comedi_device * dev,
 526         unsigned gpct_index, enum comedi_io_direction direction)
 527 {
 528         unsigned long flags;
 529         struct mite_channel *mite_chan;
 530
 531         BUG_ON(gpct_index >= NUM_GPCT);
 532         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 533         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 534         mite_chan =
 535                 mite_request_channel(devpriv->mite,
 536                 devpriv->gpct_mite_ring[gpct_index]);
 537         if (mite_chan == NULL) {
 538                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 539                         flags);
 540                 comedi_error(dev,
 541                         "failed to reserve mite dma channel for counter.");
 542                 return -EBUSY;
 543         }
 544         mite_chan->dir = direction;
 545         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 546                 mite_chan);
 547         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 548         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 549         return 0;
 550 }
 551
 552 #endif // PCIDMA
 553
 554 static int ni_request_cdo_mite_channel(comedi_device * dev)
 555 {
 556 #ifdef PCIDMA
 557         unsigned long flags;
 558
 559         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 560         BUG_ON(devpriv->cdo_mite_chan);
 561         devpriv->cdo_mite_chan =
 562                 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 563         if (devpriv->cdo_mite_chan == NULL) {
 564                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 565                         flags);
 566                 comedi_error(dev,
 567                         "failed to reserve mite dma channel for correlated digital outut.");
 568                 return -EBUSY;
 569         }
 570         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 571         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 572         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 573 #endif // PCIDMA
 574         return 0;
 575 }
 576
 577 static void ni_release_ai_mite_channel(comedi_device * dev)
 578 {
 579 #ifdef PCIDMA
 580         unsigned long flags;
 581
 582         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 583         if (devpriv->ai_mite_chan) {
 584                 ni_set_ai_dma_channel(dev, -1);
 585                 mite_release_channel(devpriv->ai_mite_chan);
 586                 devpriv->ai_mite_chan = NULL;
 587         }
 588         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 589 #endif // PCIDMA
 590 }
 591
 592 static void ni_release_ao_mite_channel(comedi_device * dev)
 593 {
 594 #ifdef PCIDMA
 595         unsigned long flags;
 596
 597         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 598         if (devpriv->ao_mite_chan) {
 599                 ni_set_ao_dma_channel(dev, -1);
 600                 mite_release_channel(devpriv->ao_mite_chan);
 601                 devpriv->ao_mite_chan = NULL;
 602         }
 603         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 604 #endif // PCIDMA
 605 }
 606
 607 void ni_release_gpct_mite_channel(comedi_device * dev, unsigned gpct_index)
 608 {
 609 #ifdef PCIDMA
 610         unsigned long flags;
 611
 612         BUG_ON(gpct_index >= NUM_GPCT);
 613         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 614         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 615                 struct mite_channel *mite_chan =
 616                         devpriv->counter_dev->counters[gpct_index].mite_chan;
 617
 618                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 619                 ni_tio_set_mite_channel(&devpriv->counter_dev->
 620                         counters[gpct_index], NULL);
 621                 mite_release_channel(mite_chan);
 622         }
 623         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 624 #endif // PCIDMA
 625 }
 626
 627 static void ni_release_cdo_mite_channel(comedi_device * dev)
 628 {
 629 #ifdef PCIDMA
 630         unsigned long flags;
 631
 632         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 633         if (devpriv->cdo_mite_chan) {
 634                 ni_set_cdo_dma_channel(dev, -1);
 635                 mite_release_channel(devpriv->cdo_mite_chan);
 636                 devpriv->cdo_mite_chan = NULL;
 637         }
 638         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 639 #endif // PCIDMA
 640 }
 641
 642 // e-series boards use the second irq signals to generate dma requests for their counters
 643 static void ni_e_series_enable_second_irq(comedi_device * dev,
 644         unsigned gpct_index, short enable)
 645 {
 646         if (boardtype.reg_type & ni_reg_m_series_mask)
 647                 return;
 648         switch (gpct_index) {
 649         case 0:
 650                 if (enable) {
 651                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 652                                 Second_IRQ_A_Enable_Register);
 653                 } else {
 654                         devpriv->stc_writew(dev, 0,
 655                                 Second_IRQ_A_Enable_Register);
 656                 }
 657                 break;
 658         case 1:
 659                 if (enable) {
 660                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 661                                 Second_IRQ_B_Enable_Register);
 662                 } else {
 663                         devpriv->stc_writew(dev, 0,
 664                                 Second_IRQ_B_Enable_Register);
 665                 }
 666                 break;
 667         default:
 668                 BUG();
 669                 break;
 670         }
 671 }
 672
 673 static void ni_clear_ai_fifo(comedi_device * dev)
 674 {
 675         if (boardtype.reg_type == ni_reg_6143) {
 676                 // Flush the 6143 data FIFO
 677                 ni_writel(0x10, AIFIFO_Control_6143);   // Flush fifo
 678                 ni_writel(0x00, AIFIFO_Control_6143);   // Flush fifo
 679                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   // Wait for complete
 680         } else {
 681                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 682                 if (boardtype.reg_type == ni_reg_625x) {
 683                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 684                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 685 #if 0
 686                         /* the NI example code does 3 convert pulses for 625x boards,
 687                            but that appears to be wrong in practice. */
 688                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 689                                 AI_Command_1_Register);
 690                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 691                                 AI_Command_1_Register);
 692                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 693                                 AI_Command_1_Register);
 694 #endif
 695                 }
 696         }
 697 }
 698
 699 static void win_out2(comedi_device * dev, uint32_t data, int reg)
 700 {
 701         devpriv->stc_writew(dev, data >> 16, reg);
 702         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 703 }
 704
 705 static uint32_t win_in2(comedi_device * dev, int reg)
 706 {
 707         uint32_t bits;
 708         bits = devpriv->stc_readw(dev, reg) << 16;
 709         bits |= devpriv->stc_readw(dev, reg + 1);
 710         return bits;
 711 }
 712
 713 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 714 static inline void ni_ao_win_outw(comedi_device * dev, uint16_t data, int addr)
 715 {
 716         unsigned long flags;
 717
 718         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 719         ni_writew(addr, AO_Window_Address_611x);
 720         ni_writew(data, AO_Window_Data_611x);
 721         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 722 }
 723
 724 static inline void ni_ao_win_outl(comedi_device * dev, uint32_t data, int addr)
 725 {
 726         unsigned long flags;
 727
 728         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 729         ni_writew(addr, AO_Window_Address_611x);
 730         ni_writel(data, AO_Window_Data_611x);
 731         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 732 }
 733
 734 static inline unsigned short ni_ao_win_inw(comedi_device * dev, int addr)
 735 {
 736         unsigned long flags;
 737         unsigned short data;
 738
 739         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 740         ni_writew(addr, AO_Window_Address_611x);
 741         data = ni_readw(AO_Window_Data_611x);
 742         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 743         return data;
 744 }
 745
 746 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 747 * share registers (such as Interrupt_A_Register) without interfering with
 748 * each other.
 749 *
 750 * NOTE: the switch/case statements are optimized out for a constant argument
 751 * so this is actually quite fast---  If you must wrap another function around this
 752 * make it inline to avoid a large speed penalty.
 753 *
 754 * value should only be 1 or 0.
 755 */
 756 static inline void ni_set_bits(comedi_device * dev, int reg, unsigned bits,
 757         unsigned value)
 758 {
 759         unsigned bit_values;
 760
 761         if (value)
 762                 bit_values = bits;
 763         else
 764                 bit_values = 0;
 765         ni_set_bitfield(dev, reg, bits, bit_values);
 766 }
 767
 768 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 769 {
 770         comedi_device *dev = d;
 771         unsigned short a_status;
 772         unsigned short b_status;
 773         unsigned int ai_mite_status = 0;
 774         unsigned int ao_mite_status = 0;
 775         unsigned long flags;
 776         struct mite_struct *mite = devpriv->mite;
 777
 778         if (dev->attached == 0)
 779                 return IRQ_NONE;
 780         smp_mb();               // make sure dev->attached is checked before handler does anything else.
 781
 782         // lock to avoid race with comedi_poll
 783         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 784         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 785         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 786         if (mite) {
 787                 unsigned long flags_too;
 788
 789                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock,
 790                         flags_too);
 791                 if (devpriv->ai_mite_chan) {
 792                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 793                         if (ai_mite_status & CHSR_LINKC)
 794                                 writel(CHOR_CLRLC,
 795                                         devpriv->mite->mite_io_addr +
 796                                         MITE_CHOR(devpriv->ai_mite_chan->
 797                                                 channel));
 798                 }
 799                 if (devpriv->ao_mite_chan) {
 800                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 801                         if (ao_mite_status & CHSR_LINKC)
 802                                 writel(CHOR_CLRLC,
 803                                         mite->mite_io_addr +
 804                                         MITE_CHOR(devpriv->ao_mite_chan->
 805                                                 channel));
 806                 }
 807                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 808                         flags_too);
 809         }
 810         ack_a_interrupt(dev, a_status);
 811         ack_b_interrupt(dev, b_status);
 812         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 813                 handle_a_interrupt(dev, a_status, ai_mite_status);
 814         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 815                 handle_b_interrupt(dev, b_status, ao_mite_status);
 816         handle_gpct_interrupt(dev, 0);
 817         handle_gpct_interrupt(dev, 1);
 818         handle_cdio_interrupt(dev);
 819
 820         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 821         return IRQ_HANDLED;
 822 }
 823
 824 #ifdef PCIDMA
 825 static void ni_sync_ai_dma(comedi_device * dev)
 826 {
 827         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 828         unsigned long flags;
 829
 830         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 831         if (devpriv->ai_mite_chan)
 832                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 833         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 834 }
 835
 836 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device * dev)
 837 {
 838         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
 839         unsigned long flags;
 840
 841         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 842         if (devpriv->ao_mite_chan) {
 843                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 844         }
 845         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 846 }
 847
 848 static int ni_ao_wait_for_dma_load(comedi_device * dev)
 849 {
 850         static const int timeout = 10000;
 851         int i;
 852         for (i = 0; i < timeout; i++) {
 853                 unsigned short b_status;
 854
 855                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 856                 if (b_status & AO_FIFO_Half_Full_St)
 857                         break;
 858                 /* if we poll too often, the pci bus activity seems
 859                    to slow the dma transfer down */
 860                 comedi_udelay(10);
 861         }
 862         if (i == timeout) {
 863                 comedi_error(dev, "timed out waiting for dma load");
 864                 return -EPIPE;
 865         }
 866         return 0;
 867 }
 868
 869 #endif //PCIDMA
 870 static void ni_handle_eos(comedi_device * dev, comedi_subdevice * s)
 871 {
 872         if (devpriv->aimode == AIMODE_SCAN) {
 873 #ifdef PCIDMA
 874                 static const int timeout = 10;
 875                 int i;
 876
 877                 for (i = 0; i < timeout; i++) {
 878                         ni_sync_ai_dma(dev);
 879                         if ((s->async->events & COMEDI_CB_EOS))
 880                                 break;
 881                         comedi_udelay(1);
 882                 }
 883 #else
 884                 ni_handle_fifo_dregs(dev);
 885                 s->async->events |= COMEDI_CB_EOS;
 886 #endif
 887         }
 888         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 889         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 890                 shutdown_ai_command(dev);
 891         }
 892 }
 893
 894 static void shutdown_ai_command(comedi_device * dev)
 895 {
 896         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 897
 898 #ifdef PCIDMA
 899         ni_ai_drain_dma(dev);
 900 #endif
 901         ni_handle_fifo_dregs(dev);
 902         get_last_sample_611x(dev);
 903         get_last_sample_6143(dev);
 904
 905         s->async->events |= COMEDI_CB_EOA;
 906 }
 907
 908 static void ni_event(comedi_device * dev, comedi_subdevice * s)
 909 {
 910         if (s->async->
 911                 events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
 912         {
 913                 switch (s - dev->subdevices) {
 914                 case NI_AI_SUBDEV:
 915                         ni_ai_reset(dev, s);
 916                         break;
 917                 case NI_AO_SUBDEV:
 918                         ni_ao_reset(dev, s);
 919                         break;
 920                 case NI_GPCT0_SUBDEV:
 921                 case NI_GPCT1_SUBDEV:
 922                         ni_gpct_cancel(dev, s);
 923                         break;
 924                 case NI_DIO_SUBDEV:
 925                         ni_cdio_cancel(dev, s);
 926                         break;
 927                 default:
 928                         break;
 929                 }
 930         }
 931         comedi_event(dev, s);
 932 }
 933
 934 static void handle_gpct_interrupt(comedi_device * dev,
 935         unsigned short counter_index)
 936 {
 937         comedi_subdevice *s = dev->subdevices + NI_GPCT_SUBDEV(counter_index);
 938
 939         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 940                 s);
 941         if (s->async->events)
 942                 ni_event(dev, s);
 943 }
 944
 945 static void ack_a_interrupt(comedi_device * dev, unsigned short a_status)
 946 {
 947         unsigned short ack = 0;
 948
 949         if (a_status & AI_SC_TC_St) {
 950                 ack |= AI_SC_TC_Interrupt_Ack;
 951         }
 952         if (a_status & AI_START1_St) {
 953                 ack |= AI_START1_Interrupt_Ack;
 954         }
 955         if (a_status & AI_START_St) {
 956                 ack |= AI_START_Interrupt_Ack;
 957         }
 958         if (a_status & AI_STOP_St) {
 959                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 960                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
 961         }
 962         if (ack)
 963                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 964 }
 965
 966 static void handle_a_interrupt(comedi_device * dev, unsigned short status,
 967         unsigned ai_mite_status)
 968 {
 969         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 970
 971         //67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt
 972         if (s->type == COMEDI_SUBD_UNUSED)
 973                 return;
 974
 975 #ifdef DEBUG_INTERRUPT
 976         rt_printk
 977                 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
 978                 status, ai_mite_status);
 979         ni_mio_print_status_a(status);
 980 #endif
 981 #ifdef PCIDMA
 982         if (ai_mite_status & CHSR_LINKC) {
 983                 ni_sync_ai_dma(dev);
 984         }
 985
 986         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
 987                         CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
 988                         CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
 989                 rt_printk
 990                         ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
 991                         ai_mite_status);
 992                 //mite_print_chsr(ai_mite_status);
 993                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 994                 //disable_irq(dev->irq);
 995         }
 996 #endif
 997
 998         /* test for all uncommon interrupt events at the same time */
 999         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1000                         AI_SC_TC_St | AI_START1_St)) {
1001                 if (status == 0xffff) {
1002                         rt_printk
1003                                 ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1004                         /* we probably aren't even running a command now,
1005                          * so it's a good idea to be careful. */
1006                         if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1007                                 s->async->events |=
1008                                         COMEDI_CB_ERROR | COMEDI_CB_EOA;
1009                                 ni_event(dev, s);
1010                         }
1011                         return;
1012                 }
1013                 if (status & (AI_Overrun_St | AI_Overflow_St |
1014                                 AI_SC_TC_Error_St)) {
1015                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
1016                                 status);
1017                         ni_mio_print_status_a(status);
1018
1019                         shutdown_ai_command(dev);
1020
1021                         s->async->events |= COMEDI_CB_ERROR;
1022                         if (status & (AI_Overrun_St | AI_Overflow_St))
1023                                 s->async->events |= COMEDI_CB_OVERFLOW;
1024
1025                         ni_event(dev, s);
1026
1027                         return;
1028                 }
1029                 if (status & AI_SC_TC_St) {
1030 #ifdef DEBUG_INTERRUPT
1031                         rt_printk("ni_mio_common: SC_TC interrupt\n");
1032 #endif
1033                         if (!devpriv->ai_continuous) {
1034                                 shutdown_ai_command(dev);
1035                         }
1036                 }
1037         }
1038 #ifndef PCIDMA
1039         if (status & AI_FIFO_Half_Full_St) {
1040                 int i;
1041                 static const int timeout = 10;
1042                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1043                  *fail to get the fifo less than half full, so loop to be sure.*/
1044                 for (i = 0; i < timeout; ++i) {
1045                         ni_handle_fifo_half_full(dev);
1046                         if ((devpriv->stc_readw(dev,
1047                                                 AI_Status_1_Register) &
1048                                         AI_FIFO_Half_Full_St) == 0)
1049                                 break;
1050                 }
1051         }
1052 #endif // !PCIDMA
1053
1054         if ((status & AI_STOP_St)) {
1055                 ni_handle_eos(dev, s);
1056         }
1057
1058         ni_event(dev, s);
1059
1060 #ifdef DEBUG_INTERRUPT
1061         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1062         if (status & Interrupt_A_St) {
1063                 rt_printk
1064                         ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1065                         status);
1066         }
1067 #endif
1068 }
1069
1070 static void ack_b_interrupt(comedi_device * dev, unsigned short b_status)
1071 {
1072         unsigned short ack = 0;
1073         if (b_status & AO_BC_TC_St) {
1074                 ack |= AO_BC_TC_Interrupt_Ack;
1075         }
1076         if (b_status & AO_Overrun_St) {
1077                 ack |= AO_Error_Interrupt_Ack;
1078         }
1079         if (b_status & AO_START_St) {
1080                 ack |= AO_START_Interrupt_Ack;
1081         }
1082         if (b_status & AO_START1_St) {
1083                 ack |= AO_START1_Interrupt_Ack;
1084         }
1085         if (b_status & AO_UC_TC_St) {
1086                 ack |= AO_UC_TC_Interrupt_Ack;
1087         }
1088         if (b_status & AO_UI2_TC_St) {
1089                 ack |= AO_UI2_TC_Interrupt_Ack;
1090         }
1091         if (b_status & AO_UPDATE_St) {
1092                 ack |= AO_UPDATE_Interrupt_Ack;
1093         }
1094         if (ack)
1095                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1096 }
1097
1098 static void handle_b_interrupt(comedi_device * dev, unsigned short b_status,
1099         unsigned ao_mite_status)
1100 {
1101         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1102         //unsigned short ack=0;
1103 #ifdef DEBUG_INTERRUPT
1104         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1105                 b_status, ao_mite_status);
1106         ni_mio_print_status_b(b_status);
1107 #endif
1108
1109 #ifdef PCIDMA
1110         /* Currently, mite.c requires us to handle LINKC */
1111         if (ao_mite_status & CHSR_LINKC) {
1112                 mite_handle_b_linkc(devpriv->mite, dev);
1113         }
1114
1115         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1116                         CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1117                         CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1118                 rt_printk
1119                         ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1120                         ao_mite_status);
1121                 //mite_print_chsr(ao_mite_status);
1122                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1123         }
1124 #endif
1125
1126         if (b_status == 0xffff)
1127                 return;
1128         if (b_status & AO_Overrun_St) {
1129                 rt_printk
1130                         ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1131                         b_status, devpriv->stc_readw(dev,
1132                                 AO_Status_2_Register));
1133                 s->async->events |= COMEDI_CB_OVERFLOW;
1134         }
1135
1136         if (b_status & AO_BC_TC_St) {
1137                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1138                 s->async->events |= COMEDI_CB_EOA;
1139         }
1140 #ifndef PCIDMA
1141         if (b_status & AO_FIFO_Request_St) {
1142                 int ret;
1143
1144                 ret = ni_ao_fifo_half_empty(dev, s);
1145                 if (!ret) {
1146                         rt_printk("ni_mio_common: AO buffer underrun\n");
1147                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1148                                 AO_FIFO_Interrupt_Enable |
1149                                 AO_Error_Interrupt_Enable, 0);
1150                         s->async->events |= COMEDI_CB_OVERFLOW;
1151                 }
1152         }
1153 #endif
1154
1155         ni_event(dev, s);
1156 }
1157
1158 #ifdef DEBUG_STATUS_A
1159 static const char *const status_a_strings[] = {
1160         "passthru0", "fifo", "G0_gate", "G0_TC",
1161         "stop", "start", "sc_tc", "start1",
1162         "start2", "sc_tc_error", "overflow", "overrun",
1163         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1164 };
1165
1166 static void ni_mio_print_status_a(int status)
1167 {
1168         int i;
1169
1170         rt_printk("A status:");
1171         for (i = 15; i >= 0; i--) {
1172                 if (status & (1 << i)) {
1173                         rt_printk(" %s", status_a_strings[i]);
1174                 }
1175         }
1176         rt_printk("\n");
1177 }
1178 #endif
1179
1180 #ifdef DEBUG_STATUS_B
1181 static const char *const status_b_strings[] = {
1182         "passthru1", "fifo", "G1_gate", "G1_TC",
1183         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1184         "start1", "overrun", "start", "bc_tc_error",
1185         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1186 };
1187
1188 static void ni_mio_print_status_b(int status)
1189 {
1190         int i;
1191
1192         rt_printk("B status:");
1193         for (i = 15; i >= 0; i--) {
1194                 if (status & (1 << i)) {
1195                         rt_printk(" %s", status_b_strings[i]);
1196                 }
1197         }
1198         rt_printk("\n");
1199 }
1200 #endif
1201
1202 #ifndef PCIDMA
1203
1204 static void ni_ao_fifo_load(comedi_device * dev, comedi_subdevice * s, int n)
1205 {
1206         comedi_async *async = s->async;
1207         comedi_cmd *cmd = &async->cmd;
1208         int chan;
1209         int i;
1210         sampl_t d;
1211         u32 packed_data;
1212         int range;
1213         int err = 1;
1214
1215         chan = async->cur_chan;
1216         for (i = 0; i < n; i++) {
1217                 err &= comedi_buf_get(async, &d);
1218                 if (err == 0)
1219                         break;
1220
1221                 range = CR_RANGE(cmd->chanlist[chan]);
1222
1223                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1224                         packed_data = d & 0xffff;
1225                         /* 6711 only has 16 bit wide ao fifo */
1226                         if (boardtype.reg_type != ni_reg_6711) {
1227                                 err &= comedi_buf_get(async, &d);
1228                                 if (err == 0)
1229                                         break;
1230                                 chan++;
1231                                 i++;
1232                                 packed_data |= (d << 16) & 0xffff0000;
1233                         }
1234                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1235                 } else {
1236                         ni_writew(d, DAC_FIFO_Data);
1237                 }
1238                 chan++;
1239                 chan %= cmd->chanlist_len;
1240         }
1241         async->cur_chan = chan;
1242         if (err == 0) {
1243                 async->events |= COMEDI_CB_OVERFLOW;
1244         }
1245 }
1246
1247 /*
1248  *  There's a small problem if the FIFO gets really low and we
1249  *  don't have the data to fill it.  Basically, if after we fill
1250  *  the FIFO with all the data available, the FIFO is _still_
1251  *  less than half full, we never clear the interrupt.  If the
1252  *  IRQ is in edge mode, we never get another interrupt, because
1253  *  this one wasn't cleared.  If in level mode, we get flooded
1254  *  with interrupts that we can't fulfill, because nothing ever
1255  *  gets put into the buffer.
1256  *
1257  *  This kind of situation is recoverable, but it is easier to
1258  *  just pretend we had a FIFO underrun, since there is a good
1259  *  chance it will happen anyway.  This is _not_ the case for
1260  *  RT code, as RT code might purposely be running close to the
1261  *  metal.  Needs to be fixed eventually.
1262  */
1263 static int ni_ao_fifo_half_empty(comedi_device * dev, comedi_subdevice * s)
1264 {
1265         int n;
1266
1267         n = comedi_buf_read_n_available(s->async);
1268         if (n == 0) {
1269                 s->async->events |= COMEDI_CB_OVERFLOW;
1270                 return 0;
1271         }
1272
1273         n /= sizeof(sampl_t);
1274         if (n > boardtype.ao_fifo_depth / 2)
1275                 n = boardtype.ao_fifo_depth / 2;
1276
1277         ni_ao_fifo_load(dev, s, n);
1278
1279         s->async->events |= COMEDI_CB_BLOCK;
1280
1281         return 1;
1282 }
1283
1284 static int ni_ao_prep_fifo(comedi_device * dev, comedi_subdevice * s)
1285 {
1286         int n;
1287
1288         /* reset fifo */
1289         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1290         if (boardtype.reg_type & ni_reg_6xxx_mask)
1291                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1292
1293         /* load some data */
1294         n = comedi_buf_read_n_available(s->async);
1295         if (n == 0)
1296                 return 0;
1297
1298         n /= sizeof(sampl_t);
1299         if (n > boardtype.ao_fifo_depth)
1300                 n = boardtype.ao_fifo_depth;
1301
1302         ni_ao_fifo_load(dev, s, n);
1303
1304         return n;
1305 }
1306
1307 static void ni_ai_fifo_read(comedi_device * dev, comedi_subdevice * s, int n)
1308 {
1309         comedi_async *async = s->async;
1310         int i;
1311
1312         if (boardtype.reg_type == ni_reg_611x) {
1313                 sampl_t data[2];
1314                 u32 dl;
1315
1316                 for (i = 0; i < n / 2; i++) {
1317                         dl = ni_readl(ADC_FIFO_Data_611x);
1318                         /* This may get the hi/lo data in the wrong order */
1319                         data[0] = (dl >> 16) & 0xffff;
1320                         data[1] = dl & 0xffff;
1321                         cfc_write_array_to_buffer(s, data, sizeof(data));
1322                 }
1323                 /* Check if there's a single sample stuck in the FIFO */
1324                 if (n % 2) {
1325                         dl = ni_readl(ADC_FIFO_Data_611x);
1326                         data[0] = dl & 0xffff;
1327                         cfc_write_to_buffer(s, data[0]);
1328                 }
1329         } else if (boardtype.reg_type == ni_reg_6143) {
1330                 sampl_t data[2];
1331                 u32 dl;
1332
1333                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1334                 for (i = 0; i < n / 2; i++) {
1335                         dl = ni_readl(AIFIFO_Data_6143);
1336
1337                         data[0] = (dl >> 16) & 0xffff;
1338                         data[1] = dl & 0xffff;
1339                         cfc_write_array_to_buffer(s, data, sizeof(data));
1340                 }
1341                 if (n % 2) {
1342                         /* Assume there is a single sample stuck in the FIFO */
1343                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1344                         dl = ni_readl(AIFIFO_Data_6143);
1345                         data[0] = (dl >> 16) & 0xffff;
1346                         cfc_write_to_buffer(s, data[0]);
1347                 }
1348         } else {
1349                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1350                         sizeof(devpriv->ai_fifo_buffer[0])) {
1351                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1352                         async->events |= COMEDI_CB_ERROR;
1353                         return;
1354                 }
1355                 for (i = 0; i < n; i++) {
1356                         devpriv->ai_fifo_buffer[i] =
1357                                 ni_readw(ADC_FIFO_Data_Register);
1358                 }
1359                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1360                         n * sizeof(devpriv->ai_fifo_buffer[0]));
1361         }
1362 }
1363
1364 static void ni_handle_fifo_half_full(comedi_device * dev)
1365 {
1366         int n;
1367         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1368
1369         n = boardtype.ai_fifo_depth / 2;
1370
1371         ni_ai_fifo_read(dev, s, n);
1372 }
1373 #endif
1374
1375 #ifdef PCIDMA
1376 static int ni_ai_drain_dma(comedi_device * dev)
1377 {
1378         int i;
1379         static const int timeout = 10000;
1380         unsigned long flags;
1381         int retval = 0;
1382
1383         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1384         if (devpriv->ai_mite_chan) {
1385                 for (i = 0; i < timeout; i++) {
1386                         if ((devpriv->stc_readw(dev,
1387                                                 AI_Status_1_Register) &
1388                                         AI_FIFO_Empty_St)
1389                                 && mite_bytes_in_transit(devpriv->
1390                                         ai_mite_chan) == 0)
1391                                 break;
1392                         comedi_udelay(5);
1393                 }
1394                 if (i == timeout) {
1395                         rt_printk
1396                                 ("ni_mio_common: wait for dma drain timed out\n");
1397                         rt_printk
1398                                 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1399                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
1400                                 devpriv->stc_readw(dev, AI_Status_1_Register));
1401                         retval = -1;
1402                 }
1403         }
1404         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1405
1406         ni_sync_ai_dma(dev);
1407
1408         return retval;
1409 }
1410 #endif
1411 /*
1412    Empties the AI fifo
1413 */
1414 static void ni_handle_fifo_dregs(comedi_device * dev)
1415 {
1416         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1417         sampl_t data[2];
1418         u32 dl;
1419         short fifo_empty;
1420         int i;
1421
1422         if (boardtype.reg_type == ni_reg_611x) {
1423                 while ((devpriv->stc_readw(dev,
1424                                         AI_Status_1_Register) &
1425                                 AI_FIFO_Empty_St) == 0) {
1426                         dl = ni_readl(ADC_FIFO_Data_611x);
1427
1428                         /* This may get the hi/lo data in the wrong order */
1429                         data[0] = (dl >> 16);
1430                         data[1] = (dl & 0xffff);
1431                         cfc_write_array_to_buffer(s, data, sizeof(data));
1432                 }
1433         } else if (boardtype.reg_type == ni_reg_6143) {
1434                 i = 0;
1435                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1436                         dl = ni_readl(AIFIFO_Data_6143);
1437
1438                         /* This may get the hi/lo data in the wrong order */
1439                         data[0] = (dl >> 16);
1440                         data[1] = (dl & 0xffff);
1441                         cfc_write_array_to_buffer(s, data, sizeof(data));
1442                         i += 2;
1443                 }
1444                 // Check if stranded sample is present
1445                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1446                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1447                         dl = ni_readl(AIFIFO_Data_6143);
1448                         data[0] = (dl >> 16) & 0xffff;
1449                         cfc_write_to_buffer(s, data[0]);
1450                 }
1451
1452         } else {
1453                 fifo_empty =
1454                         devpriv->stc_readw(dev,
1455                         AI_Status_1_Register) & AI_FIFO_Empty_St;
1456                 while (fifo_empty == 0) {
1457                         for (i = 0;
1458                                 i <
1459                                 sizeof(devpriv->ai_fifo_buffer) /
1460                                 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1461                                 fifo_empty =
1462                                         devpriv->stc_readw(dev,
1463                                         AI_Status_1_Register) &
1464                                         AI_FIFO_Empty_St;
1465                                 if (fifo_empty)
1466                                         break;
1467                                 devpriv->ai_fifo_buffer[i] =
1468                                         ni_readw(ADC_FIFO_Data_Register);
1469                         }
1470                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1471                                 i * sizeof(devpriv->ai_fifo_buffer[0]));
1472                 }
1473         }
1474 }
1475
1476 static void get_last_sample_611x(comedi_device * dev)
1477 {
1478         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1479         sampl_t data;
1480         u32 dl;
1481
1482         if (boardtype.reg_type != ni_reg_611x)
1483                 return;
1484
1485         /* Check if there's a single sample stuck in the FIFO */
1486         if (ni_readb(XXX_Status) & 0x80) {
1487                 dl = ni_readl(ADC_FIFO_Data_611x);
1488                 data = (dl & 0xffff);
1489                 cfc_write_to_buffer(s, data);
1490         }
1491 }
1492
1493 static void get_last_sample_6143(comedi_device * dev)
1494 {
1495         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1496         sampl_t data;
1497         u32 dl;
1498
1499         if (boardtype.reg_type != ni_reg_6143)
1500                 return;
1501
1502         /* Check if there's a single sample stuck in the FIFO */
1503         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1504                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1505                 dl = ni_readl(AIFIFO_Data_6143);
1506
1507                 /* This may get the hi/lo data in the wrong order */
1508                 data = (dl >> 16) & 0xffff;
1509                 cfc_write_to_buffer(s, data);
1510         }
1511 }
1512
1513 static void ni_ai_munge(comedi_device * dev, comedi_subdevice * s,
1514         void *data, unsigned int num_bytes, unsigned int chan_index)
1515 {
1516         comedi_async *async = s->async;
1517         unsigned int i;
1518         unsigned int length = num_bytes / bytes_per_sample(s);
1519         sampl_t *array = data;
1520         lsampl_t *larray = data;
1521         for (i = 0; i < length; i++) {
1522 #ifdef PCIDMA
1523                 if (s->subdev_flags & SDF_LSAMPL)
1524                         larray[i] = le32_to_cpu(larray[i]);
1525                 else
1526                         array[i] = le16_to_cpu(array[i]);
1527 #endif
1528                 if (s->subdev_flags & SDF_LSAMPL)
1529                         larray[i] += devpriv->ai_offset[chan_index];
1530                 else
1531                         array[i] += devpriv->ai_offset[chan_index];
1532                 chan_index++;
1533                 chan_index %= async->cmd.chanlist_len;
1534         }
1535 }
1536
1537 #ifdef PCIDMA
1538
1539 static int ni_ai_setup_MITE_dma(comedi_device * dev)
1540 {
1541         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1542         int retval;
1543
1544         retval = ni_request_ai_mite_channel(dev);
1545         if (retval)
1546                 return retval;
1547 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1548
1549         /* write alloc the entire buffer */
1550         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1551
1552         switch (boardtype.reg_type) {
1553         case ni_reg_611x:
1554         case ni_reg_6143:
1555                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1556                 break;
1557         case ni_reg_628x:
1558                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1559                 break;
1560         default:
1561                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1562                 break;
1563         };
1564         /*start the MITE */
1565         mite_dma_arm(devpriv->ai_mite_chan);
1566         return 0;
1567 }
1568
1569 static int ni_ao_setup_MITE_dma(comedi_device * dev)
1570 {
1571         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1572         int retval;
1573         unsigned long flags;
1574
1575         retval = ni_request_ao_mite_channel(dev);
1576         if (retval)
1577                 return retval;
1578
1579         /* read alloc the entire buffer */
1580         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1581
1582         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1583         if (devpriv->ao_mite_chan) {
1584                 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1585                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1586                 } else {
1587                         /* doing 32 instead of 16 bit wide transfers from memory
1588                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1589                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1590                 }
1591                 mite_dma_arm(devpriv->ao_mite_chan);
1592         } else
1593                 retval = -EIO;
1594         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1595
1596         return retval;
1597 }
1598
1599 #endif // PCIDMA
1600
1601 /*
1602    used for both cancel ioctl and board initialization
1603
1604    this is pretty harsh for a cancel, but it works...
1605  */
1606
1607 static int ni_ai_reset(comedi_device * dev, comedi_subdevice * s)
1608 {
1609         ni_release_ai_mite_channel(dev);
1610         /* ai configuration */
1611         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1612                 Joint_Reset_Register);
1613
1614         ni_set_bits(dev, Interrupt_A_Enable_Register,
1615                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1616                 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1617                 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1618                 AI_FIFO_Interrupt_Enable, 0);
1619
1620         ni_clear_ai_fifo(dev);
1621
1622         if (boardtype.reg_type != ni_reg_6143)
1623                 ni_writeb(0, Misc_Command);
1624
1625         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1626         devpriv->stc_writew(dev,
1627                 AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */ ,
1628                 AI_Mode_1_Register);
1629         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1630         /* generate FIFO interrupts on non-empty */
1631         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1632         if (boardtype.reg_type == ni_reg_611x) {
1633                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1634                         AI_SOC_Polarity |
1635                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1636                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1637                         AI_EXTMUX_CLK_Output_Select(0) |
1638                         AI_LOCALMUX_CLK_Output_Select(2) |
1639                         AI_SC_TC_Output_Select(3) |
1640                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High),
1641                         AI_Output_Control_Register);
1642         } else if (boardtype.reg_type == ni_reg_6143) {
1643                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1644                         AI_SOC_Polarity |
1645                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1646                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1647                         AI_EXTMUX_CLK_Output_Select(0) |
1648                         AI_LOCALMUX_CLK_Output_Select(2) |
1649                         AI_SC_TC_Output_Select(3) |
1650                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),
1651                         AI_Output_Control_Register);
1652         } else {
1653                 unsigned ai_output_control_bits;
1654                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1655                         AI_SOC_Polarity |
1656                         AI_CONVERT_Pulse_Width |
1657                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1658                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1659                         AI_EXTMUX_CLK_Output_Select(0) |
1660                         AI_LOCALMUX_CLK_Output_Select(2) |
1661                         AI_SC_TC_Output_Select(3);
1662                 if (boardtype.reg_type == ni_reg_622x)
1663                         ai_output_control_bits |=
1664                                 AI_CONVERT_Output_Select
1665                                 (AI_CONVERT_Output_Enable_High);
1666                 else
1667                         ai_output_control_bits |=
1668                                 AI_CONVERT_Output_Select
1669                                 (AI_CONVERT_Output_Enable_Low);
1670                 devpriv->stc_writew(dev, ai_output_control_bits,
1671                         AI_Output_Control_Register);
1672         }
1673         /* the following registers should not be changed, because there
1674          * are no backup registers in devpriv.  If you want to change
1675          * any of these, add a backup register and other appropriate code:
1676          *      AI_Mode_1_Register
1677          *      AI_Mode_3_Register
1678          *      AI_Personal_Register
1679          *      AI_Output_Control_Register
1680          */
1681         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1682
1683         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1684
1685         return 0;
1686 }
1687
1688 static int ni_ai_poll(comedi_device * dev, comedi_subdevice * s)
1689 {
1690         unsigned long flags = 0;
1691         int count;
1692
1693         // lock to avoid race with interrupt handler
1694         if (in_interrupt() == 0)
1695                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1696 #ifndef PCIDMA
1697         ni_handle_fifo_dregs(dev);
1698 #else
1699         ni_sync_ai_dma(dev);
1700 #endif
1701         count = s->async->buf_write_count - s->async->buf_read_count;
1702         if (in_interrupt() == 0)
1703                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1704
1705         return count;
1706 }
1707
1708 static int ni_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
1709         comedi_insn * insn, lsampl_t * data)
1710 {
1711         int i, n;
1712         const unsigned int mask = (1 << boardtype.adbits) - 1;
1713         unsigned signbits;
1714         unsigned short d;
1715         unsigned long dl;
1716
1717         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1718
1719         ni_clear_ai_fifo(dev);
1720
1721         signbits = devpriv->ai_offset[0];
1722         if (boardtype.reg_type == ni_reg_611x) {
1723                 for (n = 0; n < num_adc_stages_611x; n++) {
1724                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1725                                 AI_Command_1_Register);
1726                         comedi_udelay(1);
1727                 }
1728                 for (n = 0; n < insn->n; n++) {
1729                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1730                                 AI_Command_1_Register);
1731                         /* The 611x has screwy 32-bit FIFOs. */
1732                         d = 0;
1733                         for (i = 0; i < NI_TIMEOUT; i++) {
1734                                 if (ni_readb(XXX_Status) & 0x80) {
1735                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1736                                                 & 0xffff;
1737                                         break;
1738                                 }
1739                                 if (!(devpriv->stc_readw(dev,
1740                                                         AI_Status_1_Register) &
1741                                                 AI_FIFO_Empty_St)) {
1742                                         d = ni_readl(ADC_FIFO_Data_611x) &
1743                                                 0xffff;
1744                                         break;
1745                                 }
1746                         }
1747                         if (i == NI_TIMEOUT) {
1748                                 rt_printk
1749                                         ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1750                                 return -ETIME;
1751                         }
1752                         d += signbits;
1753                         data[n] = d;
1754                 }
1755         } else if (boardtype.reg_type == ni_reg_6143) {
1756                 for (n = 0; n < insn->n; n++) {
1757                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1758                                 AI_Command_1_Register);
1759
1760                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1761                         dl = 0;
1762                         for (i = 0; i < NI_TIMEOUT; i++) {
1763                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1764                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1765                                         dl = ni_readl(AIFIFO_Data_6143);
1766                                         break;
1767                                 }
1768                         }
1769                         if (i == NI_TIMEOUT) {
1770                                 rt_printk
1771                                         ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1772                                 return -ETIME;
1773                         }
1774                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1775                 }
1776         } else {
1777                 for (n = 0; n < insn->n; n++) {
1778                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1779                                 AI_Command_1_Register);
1780                         for (i = 0; i < NI_TIMEOUT; i++) {
1781                                 if (!(devpriv->stc_readw(dev,
1782                                                         AI_Status_1_Register) &
1783                                                 AI_FIFO_Empty_St))
1784                                         break;
1785                         }
1786                         if (i == NI_TIMEOUT) {
1787                                 rt_printk
1788                                         ("ni_mio_common: timeout in ni_ai_insn_read\n");
1789                                 return -ETIME;
1790                         }
1791                         if (boardtype.reg_type & ni_reg_m_series_mask) {
1792                                 data[n] =
1793                                         ni_readl(M_Offset_AI_FIFO_Data) & mask;
1794                         } else {
1795                                 d = ni_readw(ADC_FIFO_Data_Register);
1796                                 d += signbits;  /* subtle: needs to be short addition */
1797                                 data[n] = d;
1798                         }
1799                 }
1800         }
1801         return insn->n;
1802 }
1803
1804 void ni_prime_channelgain_list(comedi_device * dev)
1805 {
1806         int i;
1807         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1808         for (i = 0; i < NI_TIMEOUT; ++i) {
1809                 if (!(devpriv->stc_readw(dev,
1810                                         AI_Status_1_Register) &
1811                                 AI_FIFO_Empty_St)) {
1812                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1813                         return;
1814                 }
1815                 comedi_udelay(1);
1816         }
1817         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1818 }
1819
1820 static void ni_m_series_load_channelgain_list(comedi_device * dev,
1821         unsigned int n_chan, unsigned int *list)
1822 {
1823         unsigned int chan, range, aref;
1824         unsigned int i;
1825         unsigned offset;
1826         unsigned int dither;
1827         unsigned range_code;
1828
1829         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1830
1831 //      offset = 1 << (boardtype.adbits - 1);
1832         if ((list[0] & CR_ALT_SOURCE)) {
1833                 unsigned bypass_bits;
1834                 chan = CR_CHAN(list[0]);
1835                 range = CR_RANGE(list[0]);
1836                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1837                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1838                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1839                 bypass_bits |= chan;
1840                 bypass_bits |=
1841                         (devpriv->
1842                         ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1843                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1844                         MSeries_AI_Bypass_Mode_Mux_Mask |
1845                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1846                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1847                 if (dither)
1848                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1849                 // don't use 2's complement encoding
1850                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1851                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1852         } else {
1853                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1854         }
1855         offset = 0;
1856         for (i = 0; i < n_chan; i++) {
1857                 unsigned config_bits = 0;
1858                 chan = CR_CHAN(list[i]);
1859                 aref = CR_AREF(list[i]);
1860                 range = CR_RANGE(list[i]);
1861                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1862
1863                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1864                 devpriv->ai_offset[i] = offset;
1865                 switch (aref) {
1866                 case AREF_DIFF:
1867                         config_bits |=
1868                                 MSeries_AI_Config_Channel_Type_Differential_Bits;
1869                         break;
1870                 case AREF_COMMON:
1871                         config_bits |=
1872                                 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1873                         break;
1874                 case AREF_GROUND:
1875                         config_bits |=
1876                                 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1877                         break;
1878                 case AREF_OTHER:
1879                         break;
1880                 }
1881                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1882                 config_bits |=
1883                         MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1884                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1885                 if (i == n_chan - 1)
1886                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1887                 if (dither)
1888                         config_bits |= MSeries_AI_Config_Dither_Bit;
1889                 // don't use 2's complement encoding
1890                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1891                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1892         }
1893         ni_prime_channelgain_list(dev);
1894 }
1895
1896 /*
1897  * Notes on the 6110 and 6111:
1898  * These boards a slightly different than the rest of the series, since
1899  * they have multiple A/D converters.
1900  * From the driver side, the configuration memory is a
1901  * little different.
1902  * Configuration Memory Low:
1903  *   bits 15-9: same
1904  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1905  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1906  *       1001 gain=0.1 (+/- 50)
1907  *       1010 0.2
1908  *       1011 0.1
1909  *       0001 1
1910  *       0010 2
1911  *       0011 5
1912  *       0100 10
1913  *       0101 20
1914  *       0110 50
1915  * Configuration Memory High:
1916  *   bits 12-14: Channel Type
1917  *       001 for differential
1918  *       000 for calibration
1919  *   bit 11: coupling  (this is not currently handled)
1920  *       1 AC coupling
1921  *       0 DC coupling
1922  *   bits 0-2: channel
1923  *       valid channels are 0-3
1924  */
1925 static void ni_load_channelgain_list(comedi_device * dev, unsigned int n_chan,
1926         unsigned int *list)
1927 {
1928         unsigned int chan, range, aref;
1929         unsigned int i;
1930         unsigned int hi, lo;
1931         unsigned offset;
1932         unsigned int dither;
1933
1934         if (boardtype.reg_type & ni_reg_m_series_mask) {
1935                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1936                 return;
1937         }
1938         if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
1939                 && (boardtype.reg_type != ni_reg_6143)) {
1940                 if (devpriv->changain_state
1941                         && devpriv->changain_spec == list[0]) {
1942                         // ready to go.
1943                         return;
1944                 }
1945                 devpriv->changain_state = 1;
1946                 devpriv->changain_spec = list[0];
1947         } else {
1948                 devpriv->changain_state = 0;
1949         }
1950
1951         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1952
1953         // Set up Calibration mode if required
1954         if (boardtype.reg_type == ni_reg_6143) {
1955                 if ((list[0] & CR_ALT_SOURCE)
1956                         && !devpriv->ai_calib_source_enabled) {
1957                         // Strobe Relay enable bit
1958                         ni_writew(devpriv->
1959                                 ai_calib_source |
1960                                 Calibration_Channel_6143_RelayOn,
1961                                 Calibration_Channel_6143);
1962                         ni_writew(devpriv->ai_calib_source,
1963                                 Calibration_Channel_6143);
1964                         devpriv->ai_calib_source_enabled = 1;
1965                         msleep_interruptible(100);      // Allow relays to change
1966                 } else if (!(list[0] & CR_ALT_SOURCE)
1967                         && devpriv->ai_calib_source_enabled) {
1968                         // Strobe Relay disable bit
1969                         ni_writew(devpriv->
1970                                 ai_calib_source |
1971                                 Calibration_Channel_6143_RelayOff,
1972                                 Calibration_Channel_6143);
1973                         ni_writew(devpriv->ai_calib_source,
1974                                 Calibration_Channel_6143);
1975                         devpriv->ai_calib_source_enabled = 0;
1976                         msleep_interruptible(100);      // Allow relays to change
1977                 }
1978         }
1979
1980         offset = 1 << (boardtype.adbits - 1);
1981         for (i = 0; i < n_chan; i++) {
1982                 if ((boardtype.reg_type != ni_reg_6143)
1983                         && (list[i] & CR_ALT_SOURCE)) {
1984                         chan = devpriv->ai_calib_source;
1985                 } else {
1986                         chan = CR_CHAN(list[i]);
1987                 }
1988                 aref = CR_AREF(list[i]);
1989                 range = CR_RANGE(list[i]);
1990                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1991
1992                 /* fix the external/internal range differences */
1993                 range = ni_gainlkup[boardtype.gainlkup][range];
1994                 if (boardtype.reg_type == ni_reg_611x)
1995                         devpriv->ai_offset[i] = offset;
1996                 else
1997                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1998
1999                 hi = 0;
2000                 if ((list[i] & CR_ALT_SOURCE)) {
2001                         if (boardtype.reg_type == ni_reg_611x)
2002                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2003                                         Calibration_Channel_Select_611x);
2004                 } else {
2005                         if (boardtype.reg_type == ni_reg_611x)
2006                                 aref = AREF_DIFF;
2007                         else if (boardtype.reg_type == ni_reg_6143)
2008                                 aref = AREF_OTHER;
2009                         switch (aref) {
2010                         case AREF_DIFF:
2011                                 hi |= AI_DIFFERENTIAL;
2012                                 break;
2013                         case AREF_COMMON:
2014                                 hi |= AI_COMMON;
2015                                 break;
2016                         case AREF_GROUND:
2017                                 hi |= AI_GROUND;
2018                                 break;
2019                         case AREF_OTHER:
2020                                 break;
2021                         }
2022                 }
2023                 hi |= AI_CONFIG_CHANNEL(chan);
2024
2025                 ni_writew(hi, Configuration_Memory_High);
2026
2027                 if (boardtype.reg_type != ni_reg_6143) {
2028                         lo = range;
2029                         if (i == n_chan - 1)
2030                                 lo |= AI_LAST_CHANNEL;
2031                         if (dither)
2032                                 lo |= AI_DITHER;
2033
2034                         ni_writew(lo, Configuration_Memory_Low);
2035                 }
2036         }
2037
2038         /* prime the channel/gain list */
2039         if ((boardtype.reg_type != ni_reg_611x)
2040                 && (boardtype.reg_type != ni_reg_6143)) {
2041                 ni_prime_channelgain_list(dev);
2042         }
2043 }
2044
2045 static int ni_ns_to_timer(const comedi_device * dev, unsigned nanosec,
2046         int round_mode)
2047 {
2048         int divider;
2049         switch (round_mode) {
2050         case TRIG_ROUND_NEAREST:
2051         default:
2052                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2053                 break;
2054         case TRIG_ROUND_DOWN:
2055                 divider = (nanosec) / devpriv->clock_ns;
2056                 break;
2057         case TRIG_ROUND_UP:
2058                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2059                 break;
2060         }
2061         return divider - 1;
2062 }
2063
2064 static unsigned ni_timer_to_ns(const comedi_device * dev, int timer)
2065 {
2066         return devpriv->clock_ns * (timer + 1);
2067 }
2068
2069 static unsigned ni_min_ai_scan_period_ns(comedi_device * dev,
2070         unsigned num_channels)
2071 {
2072         switch (boardtype.reg_type) {
2073         case ni_reg_611x:
2074         case ni_reg_6143:
2075                 // simultaneously-sampled inputs
2076                 return boardtype.ai_speed;
2077                 break;
2078         default:
2079                 // multiplexed inputs
2080                 break;
2081         };
2082         return boardtype.ai_speed * num_channels;
2083 }
2084
2085 static int ni_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
2086         comedi_cmd * cmd)
2087 {
2088         int err = 0;
2089         int tmp;
2090         int sources;
2091
2092         /* step 1: make sure trigger sources are trivially valid */
2093
2094         if ((cmd->flags & CMDF_WRITE)) {
2095                 cmd->flags &= ~CMDF_WRITE;
2096         }
2097
2098         tmp = cmd->start_src;
2099         cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2100         if (!cmd->start_src || tmp != cmd->start_src)
2101                 err++;
2102
2103         tmp = cmd->scan_begin_src;
2104         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2105         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2106                 err++;
2107
2108         tmp = cmd->convert_src;
2109         sources = TRIG_TIMER | TRIG_EXT;
2110         if ((boardtype.reg_type == ni_reg_611x)
2111                 || (boardtype.reg_type == ni_reg_6143))
2112                 sources |= TRIG_NOW;
2113         cmd->convert_src &= sources;
2114         if (!cmd->convert_src || tmp != cmd->convert_src)
2115                 err++;
2116
2117         tmp = cmd->scan_end_src;
2118         cmd->scan_end_src &= TRIG_COUNT;
2119         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2120                 err++;
2121
2122         tmp = cmd->stop_src;
2123         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2124         if (!cmd->stop_src || tmp != cmd->stop_src)
2125                 err++;
2126
2127         if (err)
2128                 return 1;
2129
2130         /* step 2: make sure trigger sources are unique and mutually compatible */
2131
2132         /* note that mutual compatiblity is not an issue here */
2133         if (cmd->start_src != TRIG_NOW &&
2134                 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2135                 err++;
2136         if (cmd->scan_begin_src != TRIG_TIMER &&
2137                 cmd->scan_begin_src != TRIG_EXT &&
2138                 cmd->scan_begin_src != TRIG_OTHER)
2139                 err++;
2140         if (cmd->convert_src != TRIG_TIMER &&
2141                 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2142                 err++;
2143         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2144                 err++;
2145
2146         if (err)
2147                 return 2;
2148
2149         /* step 3: make sure arguments are trivially compatible */
2150
2151         if (cmd->start_src == TRIG_EXT) {
2152                 /* external trigger */
2153                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2154
2155                 if (tmp > 16)
2156                         tmp = 16;
2157                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2158                 if (cmd->start_arg != tmp) {
2159                         cmd->start_arg = tmp;
2160                         err++;
2161                 }
2162         } else {
2163                 if (cmd->start_arg != 0) {
2164                         /* true for both TRIG_NOW and TRIG_INT */
2165                         cmd->start_arg = 0;
2166                         err++;
2167                 }
2168         }
2169         if (cmd->scan_begin_src == TRIG_TIMER) {
2170                 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2171                                 cmd->chanlist_len)) {
2172                         cmd->scan_begin_arg =
2173                                 ni_min_ai_scan_period_ns(dev,
2174                                 cmd->chanlist_len);
2175                         err++;
2176                 }
2177                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2178                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2179                         err++;
2180                 }
2181         } else if (cmd->scan_begin_src == TRIG_EXT) {
2182                 /* external trigger */
2183                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2184
2185                 if (tmp > 16)
2186                         tmp = 16;
2187                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2188                 if (cmd->scan_begin_arg != tmp) {
2189                         cmd->scan_begin_arg = tmp;
2190                         err++;
2191                 }
2192         } else {                /* TRIG_OTHER */
2193                 if (cmd->scan_begin_arg) {
2194                         cmd->scan_begin_arg = 0;
2195                         err++;
2196                 }
2197         }
2198         if (cmd->convert_src == TRIG_TIMER) {
2199                 if ((boardtype.reg_type == ni_reg_611x)
2200                         || (boardtype.reg_type == ni_reg_6143)) {
2201                         if (cmd->convert_arg != 0) {
2202                                 cmd->convert_arg = 0;
2203                                 err++;
2204                         }
2205                 } else {
2206                         if (cmd->convert_arg < boardtype.ai_speed) {
2207                                 cmd->convert_arg = boardtype.ai_speed;
2208                                 err++;
2209                         }
2210                         if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2211                                 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2212                                 err++;
2213                         }
2214                 }
2215         } else if (cmd->convert_src == TRIG_EXT) {
2216                 /* external trigger */
2217                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2218
2219                 if (tmp > 16)
2220                         tmp = 16;
2221                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2222                 if (cmd->convert_arg != tmp) {
2223                         cmd->convert_arg = tmp;
2224                         err++;
2225                 }
2226         } else if (cmd->convert_src == TRIG_NOW) {
2227                 if (cmd->convert_arg != 0) {
2228                         cmd->convert_arg = 0;
2229                         err++;
2230                 }
2231         }
2232
2233         if (cmd->scan_end_arg != cmd->chanlist_len) {
2234                 cmd->scan_end_arg = cmd->chanlist_len;
2235                 err++;
2236         }
2237         if (cmd->stop_src == TRIG_COUNT) {
2238                 unsigned int max_count = 0x01000000;
2239
2240                 if (boardtype.reg_type == ni_reg_611x)
2241                         max_count -= num_adc_stages_611x;
2242                 if (cmd->stop_arg > max_count) {
2243                         cmd->stop_arg = max_count;
2244                         err++;
2245                 }
2246                 if (cmd->stop_arg < 1) {
2247                         cmd->stop_arg = 1;
2248                         err++;
2249                 }
2250         } else {
2251                 /* TRIG_NONE */
2252                 if (cmd->stop_arg != 0) {
2253                         cmd->stop_arg = 0;
2254                         err++;
2255                 }
2256         }
2257
2258         if (err)
2259                 return 3;
2260
2261         /* step 4: fix up any arguments */
2262
2263         if (cmd->scan_begin_src == TRIG_TIMER) {
2264                 tmp = cmd->scan_begin_arg;
2265                 cmd->scan_begin_arg =
2266                         ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2267                                 cmd->scan_begin_arg,
2268                                 cmd->flags & TRIG_ROUND_MASK));
2269                 if (tmp != cmd->scan_begin_arg)
2270                         err++;
2271         }
2272         if (cmd->convert_src == TRIG_TIMER) {
2273                 if ((boardtype.reg_type != ni_reg_611x)
2274                         && (boardtype.reg_type != ni_reg_6143)) {
2275                         tmp = cmd->convert_arg;
2276                         cmd->convert_arg =
2277                                 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2278                                         cmd->convert_arg,
2279                                         cmd->flags & TRIG_ROUND_MASK));
2280                         if (tmp != cmd->convert_arg)
2281                                 err++;
2282                         if (cmd->scan_begin_src == TRIG_TIMER &&
2283                                 cmd->scan_begin_arg <
2284                                 cmd->convert_arg * cmd->scan_end_arg) {
2285                                 cmd->scan_begin_arg =
2286                                         cmd->convert_arg * cmd->scan_end_arg;
2287                                 err++;
2288                         }
2289                 }
2290         }
2291
2292         if (err)
2293                 return 4;
2294
2295         return 0;
2296 }
2297
2298 static int ni_ai_cmd(comedi_device * dev, comedi_subdevice * s)
2299 {
2300         const comedi_cmd *cmd = &s->async->cmd;
2301         int timer;
2302         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2303         int mode2 = 0;
2304         int start_stop_select = 0;
2305         unsigned int stop_count;
2306         int interrupt_a_enable = 0;
2307
2308         MDPRINTK("ni_ai_cmd\n");
2309         if (dev->irq == 0) {
2310                 comedi_error(dev, "cannot run command without an irq");
2311                 return -EIO;
2312         }
2313         ni_clear_ai_fifo(dev);
2314
2315         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2316
2317         /* start configuration */
2318         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2319
2320         /* disable analog triggering for now, since it
2321          * interferes with the use of pfi0 */
2322         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2323         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2324                 Analog_Trigger_Etc_Register);
2325
2326         switch (cmd->start_src) {
2327         case TRIG_INT:
2328         case TRIG_NOW:
2329                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2330                         AI_START1_Sync | AI_START1_Edge | AI_START1_Select(0),
2331                         AI_Trigger_Select_Register);
2332                 break;
2333         case TRIG_EXT:
2334                 {
2335                         int chan = CR_CHAN(cmd->start_arg);
2336                         unsigned int bits = AI_START2_Select(0) |
2337                                 AI_START1_Sync | AI_START1_Select(chan + 1);
2338
2339                         if (cmd->start_arg & CR_INVERT)
2340                                 bits |= AI_START1_Polarity;
2341                         if (cmd->start_arg & CR_EDGE)
2342                                 bits |= AI_START1_Edge;
2343                         devpriv->stc_writew(dev, bits,
2344                                 AI_Trigger_Select_Register);
2345                         break;
2346                 }
2347         }
2348
2349         mode2 &= ~AI_Pre_Trigger;
2350         mode2 &= ~AI_SC_Initial_Load_Source;
2351         mode2 &= ~AI_SC_Reload_Mode;
2352         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2353
2354         if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2355                 || (boardtype.reg_type == ni_reg_6143)) {
2356                 start_stop_select |= AI_STOP_Polarity;
2357                 start_stop_select |= AI_STOP_Select(31);        // logic low
2358                 start_stop_select |= AI_STOP_Sync;
2359         } else {
2360                 start_stop_select |= AI_STOP_Select(19);        // ai configuration memory
2361         }
2362         devpriv->stc_writew(dev, start_stop_select,
2363                 AI_START_STOP_Select_Register);
2364
2365         devpriv->ai_cmd2 = 0;
2366         switch (cmd->stop_src) {
2367         case TRIG_COUNT:
2368                 stop_count = cmd->stop_arg - 1;
2369
2370                 if (boardtype.reg_type == ni_reg_611x) {
2371                         // have to take 3 stage adc pipeline into account
2372                         stop_count += num_adc_stages_611x;
2373                 }
2374                 /* stage number of scans */
2375                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2376
2377                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2378                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2379                 /* load SC (Scan Count) */
2380                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2381
2382                 devpriv->ai_continuous = 0;
2383                 if (stop_count == 0) {
2384                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2385                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2386                         // this is required to get the last sample for chanlist_len > 1, not sure why
2387                         if (cmd->chanlist_len > 1)
2388                                 start_stop_select |=
2389                                         AI_STOP_Polarity | AI_STOP_Edge;
2390                 }
2391                 break;
2392         case TRIG_NONE:
2393                 /* stage number of scans */
2394                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2395
2396                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2397                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2398
2399                 /* load SC (Scan Count) */
2400                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2401
2402                 devpriv->ai_continuous = 1;
2403
2404                 break;
2405         }
2406
2407         switch (cmd->scan_begin_src) {
2408         case TRIG_TIMER:
2409                 /*
2410                    stop bits for non 611x boards
2411                    AI_SI_Special_Trigger_Delay=0
2412                    AI_Pre_Trigger=0
2413                    AI_START_STOP_Select_Register:
2414                    AI_START_Polarity=0 (?)      rising edge
2415                    AI_START_Edge=1              edge triggered
2416                    AI_START_Sync=1 (?)
2417                    AI_START_Select=0            SI_TC
2418                    AI_STOP_Polarity=0           rising edge
2419                    AI_STOP_Edge=0               level
2420                    AI_STOP_Sync=1
2421                    AI_STOP_Select=19            external pin (configuration mem)
2422                  */
2423                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2424                 devpriv->stc_writew(dev, start_stop_select,
2425                         AI_START_STOP_Select_Register);
2426
2427                 mode2 |= AI_SI_Reload_Mode(0);
2428                 /* AI_SI_Initial_Load_Source=A */
2429                 mode2 &= ~AI_SI_Initial_Load_Source;
2430                 //mode2 |= AI_SC_Reload_Mode;
2431                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2432
2433                 /* load SI */
2434                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2435                         TRIG_ROUND_NEAREST);
2436                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2437                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2438                 break;
2439         case TRIG_EXT:
2440                 if (cmd->scan_begin_arg & CR_EDGE)
2441                         start_stop_select |= AI_START_Edge;
2442                 /* AI_START_Polarity==1 is falling edge */
2443                 if (cmd->scan_begin_arg & CR_INVERT)
2444                         start_stop_select |= AI_START_Polarity;
2445                 if (cmd->scan_begin_src != cmd->convert_src ||
2446                         (cmd->scan_begin_arg & ~CR_EDGE) !=
2447                         (cmd->convert_arg & ~CR_EDGE))
2448                         start_stop_select |= AI_START_Sync;
2449                 start_stop_select |=
2450                         AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2451                 devpriv->stc_writew(dev, start_stop_select,
2452                         AI_START_STOP_Select_Register);
2453                 break;
2454         }
2455
2456         switch (cmd->convert_src) {
2457         case TRIG_TIMER:
2458         case TRIG_NOW:
2459                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2460                         timer = 1;
2461                 else
2462                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2463                                 TRIG_ROUND_NEAREST);
2464                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2465                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2466
2467                 /* AI_SI2_Reload_Mode = alternate */
2468                 /* AI_SI2_Initial_Load_Source = A */
2469                 mode2 &= ~AI_SI2_Initial_Load_Source;
2470                 mode2 |= AI_SI2_Reload_Mode;
2471                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2472
2473                 /* AI_SI2_Load */
2474                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2475
2476                 mode2 |= AI_SI2_Reload_Mode;    // alternate
2477                 mode2 |= AI_SI2_Initial_Load_Source;    // B
2478
2479                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2480                 break;
2481         case TRIG_EXT:
2482                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2483                 if ((cmd->convert_arg & CR_INVERT) == 0)
2484                         mode1 |= AI_CONVERT_Source_Polarity;
2485                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2486
2487                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2488                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2489
2490                 break;
2491         }
2492
2493         if (dev->irq) {
2494
2495                 /* interrupt on FIFO, errors, SC_TC */
2496                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2497                         AI_SC_TC_Interrupt_Enable;
2498
2499 #ifndef PCIDMA
2500                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2501 #endif
2502
2503                 if (cmd->flags & TRIG_WAKE_EOS
2504                         || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2505                         /* wake on end-of-scan */
2506                         devpriv->aimode = AIMODE_SCAN;
2507                 } else {
2508                         devpriv->aimode = AIMODE_HALF_FULL;
2509                 }
2510
2511                 switch (devpriv->aimode) {
2512                 case AIMODE_HALF_FULL:
2513                         /*generate FIFO interrupts and DMA requests on half-full */
2514 #ifdef PCIDMA
2515                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2516                                 AI_Mode_3_Register);
2517 #else
2518                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2519                                 AI_Mode_3_Register);
2520 #endif
2521                         break;
2522                 case AIMODE_SAMPLE:
2523                         /*generate FIFO interrupts on non-empty */
2524                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2525                                 AI_Mode_3_Register);
2526                         break;
2527                 case AIMODE_SCAN:
2528 #ifdef PCIDMA
2529                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2530                                 AI_Mode_3_Register);
2531 #else
2532                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2533                                 AI_Mode_3_Register);
2534 #endif
2535                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2536                         break;
2537                 default:
2538                         break;
2539                 }
2540
2541                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2542
2543                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2544                         interrupt_a_enable, 1);
2545
2546                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2547                         devpriv->int_a_enable_reg);
2548         } else {
2549                 /* interrupt on nothing */
2550                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2551
2552                 /* XXX start polling if necessary */
2553                 MDPRINTK("interrupting on nothing\n");
2554         }
2555
2556         /* end configuration */
2557         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2558
2559         switch (cmd->scan_begin_src) {
2560         case TRIG_TIMER:
2561                 devpriv->stc_writew(dev,
2562                         AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2563                         AI_Command_1_Register);
2564                 break;
2565         case TRIG_EXT:
2566                 /* XXX AI_SI_Arm? */
2567                 devpriv->stc_writew(dev,
2568                         AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2569                         AI_Command_1_Register);
2570                 break;
2571         }
2572
2573 #ifdef PCIDMA
2574         {
2575                 int retval = ni_ai_setup_MITE_dma(dev);
2576                 if (retval)
2577                         return retval;
2578         }
2579         //mite_dump_regs(devpriv->mite);
2580 #endif
2581
2582         switch (cmd->start_src) {
2583         case TRIG_NOW:
2584                 /* AI_START1_Pulse */
2585                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2586                         AI_Command_2_Register);
2587                 s->async->inttrig = NULL;
2588                 break;
2589         case TRIG_EXT:
2590                 s->async->inttrig = NULL;
2591                 break;
2592         case TRIG_INT:
2593                 s->async->inttrig = &ni_ai_inttrig;
2594                 break;
2595         }
2596
2597         MDPRINTK("exit ni_ai_cmd\n");
2598
2599         return 0;
2600 }
2601
2602 static int ni_ai_inttrig(comedi_device * dev, comedi_subdevice * s,
2603         unsigned int trignum)
2604 {
2605         if (trignum != 0)
2606                 return -EINVAL;
2607
2608         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2609                 AI_Command_2_Register);
2610         s->async->inttrig = NULL;
2611
2612         return 1;
2613 }
2614
2615 static int ni_ai_config_analog_trig(comedi_device * dev, comedi_subdevice * s,
2616         comedi_insn * insn, lsampl_t * data);
2617
2618 static int ni_ai_insn_config(comedi_device * dev, comedi_subdevice * s,
2619         comedi_insn * insn, lsampl_t * data)
2620 {
2621         if (insn->n < 1)
2622                 return -EINVAL;
2623
2624         switch (data[0]) {
2625         case INSN_CONFIG_ANALOG_TRIG:
2626                 return ni_ai_config_analog_trig(dev, s, insn, data);
2627         case INSN_CONFIG_ALT_SOURCE:
2628                 if (boardtype.reg_type & ni_reg_m_series_mask) {
2629                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2630                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2631                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2632                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2633                                 return -EINVAL;
2634                         }
2635                         devpriv->ai_calib_source = data[1];
2636                 } else if (boardtype.reg_type == ni_reg_6143) {
2637                         unsigned int calib_source;
2638
2639                         calib_source = data[1] & 0xf;
2640
2641                         if (calib_source > 0xF)
2642                                 return -EINVAL;
2643
2644                         devpriv->ai_calib_source = calib_source;
2645                         ni_writew(calib_source, Calibration_Channel_6143);
2646                 } else {
2647                         unsigned int calib_source;
2648                         unsigned int calib_source_adjust;
2649
2650                         calib_source = data[1] & 0xf;
2651                         calib_source_adjust = (data[1] >> 4) & 0xff;
2652
2653                         if (calib_source >= 8)
2654                                 return -EINVAL;
2655                         devpriv->ai_calib_source = calib_source;
2656                         if (boardtype.reg_type == ni_reg_611x) {
2657                                 ni_writeb(calib_source_adjust,
2658                                         Cal_Gain_Select_611x);
2659                         }
2660                 }
2661                 return 2;
2662         default:
2663                 break;
2664         }
2665
2666         return -EINVAL;
2667 }
2668
2669 static int ni_ai_config_analog_trig(comedi_device * dev, comedi_subdevice * s,
2670         comedi_insn * insn, lsampl_t * data)
2671 {
2672         unsigned int a, b, modebits;
2673         int err = 0;
2674
2675         /* data[1] is flags
2676          * data[2] is analog line
2677          * data[3] is set level
2678          * data[4] is reset level */
2679         if (!boardtype.has_analog_trig)
2680                 return -EINVAL;
2681         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2682                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2683                 err++;
2684         }
2685         if (data[2] >= boardtype.n_adchan) {
2686                 data[2] = boardtype.n_adchan - 1;
2687                 err++;
2688         }
2689         if (data[3] > 255) {    /* a */
2690                 data[3] = 255;
2691                 err++;
2692         }
2693         if (data[4] > 255) {    /* b */
2694                 data[4] = 255;
2695                 err++;
2696         }
2697         /*
2698          * 00 ignore
2699          * 01 set
2700          * 10 reset
2701          *
2702          * modes:
2703          *   1 level:                    +b-   +a-
2704          *     high mode                00 00 01 10
2705          *     low mode                 00 00 10 01
2706          *   2 level: (a<b)
2707          *     hysteresis low mode      10 00 00 01
2708          *     hysteresis high mode     01 00 00 10
2709          *     middle mode              10 01 01 10
2710          */
2711
2712         a = data[3];
2713         b = data[4];
2714         modebits = data[1] & 0xff;
2715         if (modebits & 0xf0) {
2716                 /* two level mode */
2717                 if (b < a) {
2718                         /* swap order */
2719                         a = data[4];
2720                         b = data[3];
2721                         modebits =
2722                                 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >>
2723                                 4);
2724                 }
2725                 devpriv->atrig_low = a;
2726                 devpriv->atrig_high = b;
2727                 switch (modebits) {
2728                 case 0x81:      /* low hysteresis mode */
2729                         devpriv->atrig_mode = 6;
2730                         break;
2731                 case 0x42:      /* high hysteresis mode */
2732                         devpriv->atrig_mode = 3;
2733                         break;
2734                 case 0x96:      /* middle window mode */
2735                         devpriv->atrig_mode = 2;
2736                         break;
2737                 default:
2738                         data[1] &= ~0xff;
2739                         err++;
2740                 }
2741         } else {
2742                 /* one level mode */
2743                 if (b != 0) {
2744                         data[4] = 0;
2745                         err++;
2746                 }
2747                 switch (modebits) {
2748                 case 0x06:      /* high window mode */
2749                         devpriv->atrig_high = a;
2750                         devpriv->atrig_mode = 0;
2751                         break;
2752                 case 0x09:      /* low window mode */
2753                         devpriv->atrig_low = a;
2754                         devpriv->atrig_mode = 1;
2755                         break;
2756                 default:
2757                         data[1] &= ~0xff;
2758                         err++;
2759                 }
2760         }
2761         if (err)
2762                 return -EAGAIN;
2763         return 5;
2764 }
2765
2766 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2767 static void ni_ao_munge(comedi_device * dev, comedi_subdevice * s,
2768         void *data, unsigned int num_bytes, unsigned int chan_index)
2769 {
2770         comedi_async *async = s->async;
2771         unsigned int range;
2772         unsigned int i;
2773         unsigned int offset;
2774         unsigned int length = num_bytes / sizeof(sampl_t);
2775         sampl_t *array = data;
2776
2777         offset = 1 << (boardtype.aobits - 1);
2778         for (i = 0; i < length; i++) {
2779                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2780                 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2781                         array[i] -= offset;
2782 #ifdef PCIDMA
2783                 array[i] = cpu_to_le16(array[i]);
2784 #endif
2785                 chan_index++;
2786                 chan_index %= async->cmd.chanlist_len;
2787         }
2788 }
2789
2790 static int ni_m_series_ao_config_chanlist(comedi_device * dev,
2791         comedi_subdevice * s, unsigned int chanspec[], unsigned int n_chans,
2792         int timed)
2793 {
2794         unsigned int range;
2795         unsigned int chan;
2796         unsigned int conf;
2797         int i;
2798         int invert = 0;
2799
2800         for (i = 0; i < boardtype.n_aochan; ++i) {
2801                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2802         }
2803         for (i = 0; i < n_chans; i++) {
2804                 const comedi_krange *krange;
2805                 chan = CR_CHAN(chanspec[i]);
2806                 range = CR_RANGE(chanspec[i]);
2807                 krange = s->range_table->range + range;
2808                 invert = 0;
2809                 conf = 0;
2810                 switch (krange->max - krange->min) {
2811                 case 20000000:
2812                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2813                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2814                         break;
2815                 case 10000000:
2816                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2817                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2818                         break;
2819                 case 4000000:
2820                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2821                         ni_writeb(MSeries_Attenuate_x5_Bit,
2822                                 M_Offset_AO_Reference_Attenuation(chan));
2823                         break;
2824                 case 2000000:
2825                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2826                         ni_writeb(MSeries_Attenuate_x5_Bit,
2827                                 M_Offset_AO_Reference_Attenuation(chan));
2828                         break;
2829                 default:
2830                         rt_printk("%s: bug! unhandled ao reference voltage\n",
2831                                 __FUNCTION__);
2832                         break;
2833                 }
2834                 switch (krange->max + krange->min) {
2835                 case 0:
2836                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2837                         break;
2838                 case 10000000:
2839                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2840                         break;
2841                 default:
2842                         rt_printk("%s: bug! unhandled ao offset voltage\n",
2843                                 __FUNCTION__);
2844                         break;
2845                 }
2846                 if (timed)
2847                         conf |= MSeries_AO_Update_Timed_Bit;
2848                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2849                 devpriv->ao_conf[chan] = conf;
2850                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2851         }
2852         return invert;
2853 }
2854
2855 static int ni_old_ao_config_chanlist(comedi_device * dev, comedi_subdevice * s,
2856         unsigned int chanspec[], unsigned int n_chans)
2857 {
2858         unsigned int range;
2859         unsigned int chan;
2860         unsigned int conf;
2861         int i;
2862         int invert = 0;
2863
2864         for (i = 0; i < n_chans; i++) {
2865                 chan = CR_CHAN(chanspec[i]);
2866                 range = CR_RANGE(chanspec[i]);
2867                 conf = AO_Channel(chan);
2868
2869                 if (boardtype.ao_unipolar) {
2870                         if ((range & 1) == 0) {
2871                                 conf |= AO_Bipolar;
2872                                 invert = (1 << (boardtype.aobits - 1));
2873                         } else {
2874                                 invert = 0;
2875                         }
2876                         if (range & 2)
2877                                 conf |= AO_Ext_Ref;
2878                 } else {
2879                         conf |= AO_Bipolar;
2880                         invert = (1 << (boardtype.aobits - 1));
2881                 }
2882
2883                 /* not all boards can deglitch, but this shouldn't hurt */
2884                 if (chanspec[i] & CR_DEGLITCH)
2885                         conf |= AO_Deglitch;
2886
2887                 /* analog reference */
2888                 /* AREF_OTHER connects AO ground to AI ground, i think */
2889                 conf |= (CR_AREF(chanspec[i]) ==
2890                         AREF_OTHER) ? AO_Ground_Ref : 0;
2891
2892                 ni_writew(conf, AO_Configuration);
2893                 devpriv->ao_conf[chan] = conf;
2894         }
2895         return invert;
2896 }
2897
2898 static int ni_ao_config_chanlist(comedi_device * dev, comedi_subdevice * s,
2899         unsigned int chanspec[], unsigned int n_chans, int timed)
2900 {
2901         if (boardtype.reg_type & ni_reg_m_series_mask)
2902                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2903                         timed);
2904         else
2905                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2906 }
2907 static int ni_ao_insn_read(comedi_device * dev, comedi_subdevice * s,
2908         comedi_insn * insn, lsampl_t * data)
2909 {
2910         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2911
2912         return 1;
2913 }
2914
2915 static int ni_ao_insn_write(comedi_device * dev, comedi_subdevice * s,
2916         comedi_insn * insn, lsampl_t * data)
2917 {
2918         unsigned int chan = CR_CHAN(insn->chanspec);
2919         unsigned int invert;
2920
2921         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2922
2923         devpriv->ao[chan] = data[0];
2924
2925         if (boardtype.reg_type & ni_reg_m_series_mask) {
2926                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2927         } else
2928                 ni_writew(data[0] ^ invert,
2929                         (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2930
2931         return 1;
2932 }
2933
2934 static int ni_ao_insn_write_671x(comedi_device * dev, comedi_subdevice * s,
2935         comedi_insn * insn, lsampl_t * data)
2936 {
2937         unsigned int chan = CR_CHAN(insn->chanspec);
2938         unsigned int invert;
2939
2940         ao_win_out(1 << chan, AO_Immediate_671x);
2941         invert = 1 << (boardtype.aobits - 1);
2942
2943         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2944
2945         devpriv->ao[chan] = data[0];
2946         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2947
2948         return 1;
2949 }
2950
2951 static int ni_ao_inttrig(comedi_device * dev, comedi_subdevice * s,
2952         unsigned int trignum)
2953 {
2954         int ret;
2955         int interrupt_b_bits;
2956         int i;
2957         static const int timeout = 1000;
2958
2959         if (trignum != 0)
2960                 return -EINVAL;
2961
2962         /* Null trig at beginning prevent ao start trigger from executing more than
2963            once per command (and doing things like trying to allocate the ao dma channel
2964            multiple times) */
2965         s->async->inttrig = NULL;
2966
2967         ni_set_bits(dev, Interrupt_B_Enable_Register,
2968                 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2969         interrupt_b_bits = AO_Error_Interrupt_Enable;
2970 #ifdef PCIDMA
2971         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2972         if (boardtype.reg_type & ni_reg_6xxx_mask)
2973                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2974         ret = ni_ao_setup_MITE_dma(dev);
2975         if (ret)
2976                 return ret;
2977         ret = ni_ao_wait_for_dma_load(dev);
2978         if (ret < 0)
2979                 return ret;
2980 #else
2981         ret = ni_ao_prep_fifo(dev, s);
2982         if (ret == 0)
2983                 return -EPIPE;
2984
2985         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2986 #endif
2987
2988         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
2989                 AO_Mode_3_Register);
2990         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2991         /* wait for DACs to be loaded */
2992         for (i = 0; i < timeout; i++) {
2993                 comedi_udelay(1);
2994                 if ((devpriv->stc_readw(dev,
2995                                         Joint_Status_2_Register) &
2996                                 AO_TMRDACWRs_In_Progress_St) == 0)
2997                         break;
2998         }
2999         if (i == timeout) {
3000                 comedi_error(dev,
3001                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3002                 return -EIO;
3003         }
3004         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
3005         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3006                 Interrupt_B_Ack_Register);
3007
3008         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3009
3010         devpriv->stc_writew(dev,
3011                 devpriv->
3012                 ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3013                 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3014                 AO_Command_1_Register);
3015
3016         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3017                 AO_Command_2_Register);
3018
3019         return 0;
3020 }
3021
3022 static int ni_ao_cmd(comedi_device * dev, comedi_subdevice * s)
3023 {
3024         const comedi_cmd *cmd = &s->async->cmd;
3025         int bits;
3026         int i;
3027         unsigned trigvar;
3028
3029         if (dev->irq == 0) {
3030                 comedi_error(dev, "cannot run command without an irq");
3031                 return -EIO;
3032         }
3033
3034         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3035
3036         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3037
3038         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3039                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3040
3041                 bits = 0;
3042                 for (i = 0; i < cmd->chanlist_len; i++) {
3043                         int chan;
3044
3045                         chan = CR_CHAN(cmd->chanlist[i]);
3046                         bits |= 1 << chan;
3047                         ao_win_out(chan, AO_Waveform_Generation_611x);
3048                 }
3049                 ao_win_out(bits, AO_Timed_611x);
3050         }
3051
3052         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3053
3054         if (cmd->stop_src == TRIG_NONE) {
3055                 devpriv->ao_mode1 |= AO_Continuous;
3056                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3057         } else {
3058                 devpriv->ao_mode1 &= ~AO_Continuous;
3059                 devpriv->ao_mode1 |= AO_Trigger_Once;
3060         }
3061         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3062         devpriv->ao_trigger_select &=
3063                 ~(AO_START1_Polarity | AO_START1_Select(-1));
3064         devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3065         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3066                 AO_Trigger_Select_Register);
3067         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3068         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3069
3070         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3071         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3072         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3073         if (cmd->stop_src == TRIG_NONE) {
3074                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3075         } else {
3076                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3077         }
3078         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3079         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3080         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3081         switch (cmd->stop_src) {
3082         case TRIG_COUNT:
3083                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3084                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3085                 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3086                         AO_UC_Load_A_Register);
3087                 break;
3088         case TRIG_NONE:
3089                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3090                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3091                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3092                 break;
3093         default:
3094                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3095                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3096                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3097         }
3098
3099         devpriv->ao_mode1 &=
3100                 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3101                 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3102         switch (cmd->scan_begin_src) {
3103         case TRIG_TIMER:
3104                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3105                 trigvar =
3106                         ni_ns_to_timer(dev, cmd->scan_begin_arg,
3107                         TRIG_ROUND_NEAREST);
3108                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3109                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3110                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3111                 break;
3112         case TRIG_EXT:
3113                 devpriv->ao_mode1 |=
3114                         AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3115                 if (cmd->scan_begin_arg & CR_INVERT)
3116                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3117                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3118                 break;
3119         default:
3120                 BUG();
3121                 break;
3122         }
3123         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3124         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3125         devpriv->ao_mode2 &=
3126                 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3127         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3128
3129         if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
3130                 if (cmd->scan_end_arg > 1) {
3131                         devpriv->ao_mode1 |= AO_Multiple_Channels;
3132                         devpriv->stc_writew(dev,
3133                                 AO_Number_Of_Channels(cmd->scan_end_arg -
3134                                         1) |
3135                                 AO_UPDATE_Output_Select
3136                                 (AO_Update_Output_High_Z),
3137                                 AO_Output_Control_Register);
3138                 } else {
3139                         unsigned bits;
3140                         devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3141                         bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3142                         if (boardtype.reg_type & ni_reg_m_series_mask) {
3143                                 bits |= AO_Number_Of_Channels(0);
3144                         } else {
3145                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->
3146                                                 chanlist[0]));
3147                         }
3148                         devpriv->stc_writew(dev, bits,
3149                                 AO_Output_Control_Register);
3150                 }
3151                 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3152         }
3153
3154         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3155                 AO_Command_1_Register);
3156
3157         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3158         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3159
3160         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3161 #ifdef PCIDMA
3162         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3163 #else
3164         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3165 #endif
3166         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3167         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3168
3169         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3170                 AO_TMRDACWR_Pulse_Width;
3171         if (boardtype.ao_fifo_depth)
3172                 bits |= AO_FIFO_Enable;
3173         else
3174                 bits |= AO_DMA_PIO_Control;
3175 #if 0
3176         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3177            verified with bus analyzer. */
3178         if (boardtype.reg_type & ni_reg_m_series_mask)
3179                 bits |= AO_Number_Of_DAC_Packages;
3180 #endif
3181         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3182         // enable sending of ao dma requests
3183         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3184
3185         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3186
3187         if (cmd->stop_src == TRIG_COUNT) {
3188                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3189                         Interrupt_B_Ack_Register);
3190                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3191                         AO_BC_TC_Interrupt_Enable, 1);
3192         }
3193
3194         s->async->inttrig = &ni_ao_inttrig;
3195
3196         return 0;
3197 }
3198
3199 static int ni_ao_cmdtest(comedi_device * dev, comedi_subdevice * s,
3200         comedi_cmd * cmd)
3201 {
3202         int err = 0;
3203         int tmp;
3204
3205         /* step 1: make sure trigger sources are trivially valid */
3206
3207         if ((cmd->flags & CMDF_WRITE) == 0) {
3208                 cmd->flags |= CMDF_WRITE;
3209         }
3210
3211         tmp = cmd->start_src;
3212         cmd->start_src &= TRIG_INT;
3213         if (!cmd->start_src || tmp != cmd->start_src)
3214                 err++;
3215
3216         tmp = cmd->scan_begin_src;
3217         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3218         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3219                 err++;
3220
3221         tmp = cmd->convert_src;
3222         cmd->convert_src &= TRIG_NOW;
3223         if (!cmd->convert_src || tmp != cmd->convert_src)
3224                 err++;
3225
3226         tmp = cmd->scan_end_src;
3227         cmd->scan_end_src &= TRIG_COUNT;
3228         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3229                 err++;
3230
3231         tmp = cmd->stop_src;
3232         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3233         if (!cmd->stop_src || tmp != cmd->stop_src)
3234                 err++;
3235
3236         if (err)
3237                 return 1;
3238
3239         /* step 2: make sure trigger sources are unique and mutually compatible */
3240
3241         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3242                 err++;
3243
3244         if (err)
3245                 return 2;
3246
3247         /* step 3: make sure arguments are trivially compatible */
3248
3249         if (cmd->start_arg != 0) {
3250                 cmd->start_arg = 0;
3251                 err++;
3252         }
3253         if (cmd->scan_begin_src == TRIG_TIMER) {
3254                 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3255                         cmd->scan_begin_arg = boardtype.ao_speed;
3256                         err++;
3257                 }
3258                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {       /* XXX check */
3259                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3260                         err++;
3261                 }
3262         }
3263         if (cmd->convert_arg != 0) {
3264                 cmd->convert_arg = 0;
3265                 err++;
3266         }
3267         if (cmd->scan_end_arg != cmd->chanlist_len) {
3268                 cmd->scan_end_arg = cmd->chanlist_len;
3269                 err++;
3270         }
3271         if (cmd->stop_src == TRIG_COUNT) {      /* XXX check */
3272                 if (cmd->stop_arg > 0x00ffffff) {
3273                         cmd->stop_arg = 0x00ffffff;
3274                         err++;
3275                 }
3276         } else {
3277                 /* TRIG_NONE */
3278                 if (cmd->stop_arg != 0) {
3279                         cmd->stop_arg = 0;
3280                         err++;
3281                 }
3282         }
3283
3284         if (err)
3285                 return 3;
3286
3287         /* step 4: fix up any arguments */
3288         if (cmd->scan_begin_src == TRIG_TIMER) {
3289                 tmp = cmd->scan_begin_arg;
3290                 cmd->scan_begin_arg =
3291                         ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3292                                 cmd->scan_begin_arg,
3293                                 cmd->flags & TRIG_ROUND_MASK));
3294                 if (tmp != cmd->scan_begin_arg)
3295                         err++;
3296         }
3297         if (err)
3298                 return 4;
3299
3300         /* step 5: fix up chanlist */
3301
3302         if (err)
3303                 return 5;
3304
3305         return 0;
3306 }
3307
3308 static int ni_ao_reset(comedi_device * dev, comedi_subdevice * s)
3309 {
3310         //devpriv->ao0p=0x0000;
3311         //ni_writew(devpriv->ao0p,AO_Configuration);
3312
3313         //devpriv->ao1p=AO_Channel(1);
3314         //ni_writew(devpriv->ao1p,AO_Configuration);
3315
3316         ni_release_ao_mite_channel(dev);
3317
3318         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3319         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3320         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3321         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3322         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3323         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3324                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3325         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3326         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3327         devpriv->ao_cmd1 = 0;
3328         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3329         devpriv->ao_cmd2 = 0;
3330         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3331         devpriv->ao_mode1 = 0;
3332         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3333         devpriv->ao_mode2 = 0;
3334         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3335         if (boardtype.reg_type & ni_reg_m_series_mask)
3336                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3337         else
3338                 devpriv->ao_mode3 = 0;
3339         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3340         devpriv->ao_trigger_select = 0;
3341         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3342                 AO_Trigger_Select_Register);
3343         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3344                 ao_win_out(0x3, AO_Immediate_671x);
3345                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3346         }
3347         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3348
3349         return 0;
3350 }
3351
3352 // digital io
3353
3354 static int ni_dio_insn_config(comedi_device * dev, comedi_subdevice * s,
3355         comedi_insn * insn, lsampl_t * data)
3356 {
3357 #ifdef DEBUG_DIO
3358         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
3359                 CR_CHAN(insn->chanspec), data[0]);
3360 #endif
3361         switch (data[0]) {
3362         case INSN_CONFIG_DIO_OUTPUT:
3363                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3364                 break;
3365         case INSN_CONFIG_DIO_INPUT:
3366                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3367                 break;
3368         case INSN_CONFIG_DIO_QUERY:
3369                 data[1] =
3370                         (s->io_bits & (1 << CR_CHAN(insn->
3371                                         chanspec))) ? COMEDI_OUTPUT :
3372                         COMEDI_INPUT;
3373                 return insn->n;
3374                 break;
3375         default:
3376                 return -EINVAL;
3377         }
3378
3379         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3380         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3381         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3382
3383         return 1;
3384 }
3385
3386 static int ni_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
3387         comedi_insn * insn, lsampl_t * data)
3388 {
3389 #ifdef DEBUG_DIO
3390         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3391 #endif
3392         if (insn->n != 2)
3393                 return -EINVAL;
3394         if (data[0]) {
3395                 /* Perform check to make sure we're not using the
3396                    serial part of the dio */
3397                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3398                         && devpriv->serial_interval_ns)
3399                         return -EBUSY;
3400
3401                 s->state &= ~data[0];
3402                 s->state |= (data[0] & data[1]);
3403                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3404                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3405                 devpriv->stc_writew(dev, devpriv->dio_output,
3406                         DIO_Output_Register);
3407         }
3408         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3409
3410         return 2;
3411 }
3412
3413 static int ni_m_series_dio_insn_config(comedi_device * dev,
3414         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
3415 {
3416 #ifdef DEBUG_DIO
3417         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3418                 CR_CHAN(insn->chanspec), data[0]);
3419 #endif
3420         switch (data[0]) {
3421         case INSN_CONFIG_DIO_OUTPUT:
3422                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3423                 break;
3424         case INSN_CONFIG_DIO_INPUT:
3425                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3426                 break;
3427         case INSN_CONFIG_DIO_QUERY:
3428                 data[1] =
3429                         (s->io_bits & (1 << CR_CHAN(insn->
3430                                         chanspec))) ? COMEDI_OUTPUT :
3431                         COMEDI_INPUT;
3432                 return insn->n;
3433                 break;
3434         default:
3435                 return -EINVAL;
3436         }
3437
3438         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3439
3440         return 1;
3441 }
3442
3443 static int ni_m_series_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
3444         comedi_insn * insn, lsampl_t * data)
3445 {
3446 #ifdef DEBUG_DIO
3447         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3448                 data[1]);
3449 #endif
3450         if (insn->n != 2)
3451                 return -EINVAL;
3452         if (data[0]) {
3453                 s->state &= ~data[0];
3454                 s->state |= (data[0] & data[1]);
3455                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3456         }
3457         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3458
3459         return 2;
3460 }
3461
3462 static int ni_cdio_cmdtest(comedi_device * dev, comedi_subdevice * s,
3463         comedi_cmd * cmd)
3464 {
3465         int err = 0;
3466         int tmp;
3467         int sources;
3468         unsigned i;
3469
3470         /* step 1: make sure trigger sources are trivially valid */
3471
3472         tmp = cmd->start_src;
3473         sources = TRIG_INT;
3474         cmd->start_src &= sources;
3475         if (!cmd->start_src || tmp != cmd->start_src)
3476                 err++;
3477
3478         tmp = cmd->scan_begin_src;
3479         cmd->scan_begin_src &= TRIG_EXT;
3480         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3481                 err++;
3482
3483         tmp = cmd->convert_src;
3484         cmd->convert_src &= TRIG_NOW;
3485         if (!cmd->convert_src || tmp != cmd->convert_src)
3486                 err++;
3487
3488         tmp = cmd->scan_end_src;
3489         cmd->scan_end_src &= TRIG_COUNT;
3490         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3491                 err++;
3492
3493         tmp = cmd->stop_src;
3494         cmd->stop_src &= TRIG_NONE;
3495         if (!cmd->stop_src || tmp != cmd->stop_src)
3496                 err++;
3497
3498         if (err)
3499                 return 1;
3500
3501         /* step 2: make sure trigger sources are unique... */
3502
3503         if (cmd->start_src != TRIG_INT)
3504                 err++;
3505         if (cmd->scan_begin_src != TRIG_EXT)
3506                 err++;
3507         if (cmd->convert_src != TRIG_NOW)
3508                 err++;
3509         if (cmd->stop_src != TRIG_NONE)
3510                 err++;
3511         /* ... and mutually compatible */
3512
3513         if (err)
3514                 return 2;
3515
3516         /* step 3: make sure arguments are trivially compatible */
3517         if (cmd->start_src == TRIG_INT) {
3518                 if (cmd->start_arg != 0) {
3519                         cmd->start_arg = 0;
3520                         err++;
3521                 }
3522         }
3523         if (cmd->scan_begin_src == TRIG_EXT) {
3524                 tmp = cmd->scan_begin_arg;
3525                 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3526                         CR_INVERT);
3527                 if (tmp != cmd->scan_begin_arg) {
3528                         err++;
3529                 }
3530         }
3531         if (cmd->convert_src == TRIG_NOW) {
3532                 if (cmd->convert_arg) {
3533                         cmd->convert_arg = 0;
3534                         err++;
3535                 }
3536         }
3537
3538         if (cmd->scan_end_arg != cmd->chanlist_len) {
3539                 cmd->scan_end_arg = cmd->chanlist_len;
3540                 err++;
3541         }
3542
3543         if (cmd->stop_src == TRIG_NONE) {
3544                 if (cmd->stop_arg != 0) {
3545                         cmd->stop_arg = 0;
3546                         err++;
3547                 }
3548         }
3549
3550         if (err)
3551                 return 3;
3552
3553         /* step 4: fix up any arguments */
3554
3555         if (err)
3556                 return 4;
3557
3558         /* step 5: check chanlist */
3559
3560         for (i = 0; i < cmd->chanlist_len; ++i) {
3561                 if (cmd->chanlist[i] != i)
3562                         err = 1;
3563         }
3564
3565         if (err)
3566                 return 5;
3567
3568         return 0;
3569 }
3570
3571 static int ni_cdio_cmd(comedi_device * dev, comedi_subdevice * s)
3572 {
3573         const comedi_cmd *cmd = &s->async->cmd;
3574         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3575         int retval;
3576
3577         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3578         switch (cmd->scan_begin_src) {
3579         case TRIG_EXT:
3580                 cdo_mode_bits |=
3581                         CR_CHAN(cmd->
3582                         scan_begin_arg) & CDO_Sample_Source_Select_Mask;
3583                 break;
3584         default:
3585                 BUG();
3586                 break;
3587         }
3588         if (cmd->scan_begin_arg & CR_INVERT)
3589                 cdo_mode_bits |= CDO_Polarity_Bit;
3590         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3591         if (s->io_bits) {
3592                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3593                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3594                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3595         } else {
3596                 comedi_error(dev,
3597                         "attempted to run digital output command with no lines configured as outputs");
3598                 return -EIO;
3599         }
3600         retval = ni_request_cdo_mite_channel(dev);
3601         if (retval < 0) {
3602                 return retval;
3603         }
3604         s->async->inttrig = &ni_cdo_inttrig;
3605         return 0;
3606 }
3607
3608 static int ni_cdo_inttrig(comedi_device * dev, comedi_subdevice * s,
3609         unsigned int trignum)
3610 {
3611         unsigned long flags;
3612         int retval = 0;
3613         unsigned i;
3614         const unsigned timeout = 100;
3615
3616         s->async->inttrig = NULL;
3617
3618         /* read alloc the entire buffer */
3619         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3620
3621         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3622         if (devpriv->cdo_mite_chan) {
3623                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3624                 mite_dma_arm(devpriv->cdo_mite_chan);
3625         } else {
3626                 comedi_error(dev, "BUG: no cdo mite channel?");
3627                 retval = -EIO;
3628         }
3629         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3630         if (retval < 0)
3631                 return retval;
3632 // XXX not sure what interrupt C group does
3633 //      ni_writeb(Interrupt_Group_C_Enable_Bit, M_Offset_Interrupt_C_Enable);
3634         //wait for dma to fill output fifo
3635         for (i = 0; i < timeout; ++i) {
3636                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3637                         break;
3638                 comedi_udelay(10);
3639         }
3640         if (i == timeout) {
3641                 comedi_error(dev, "dma failed to fill cdo fifo!");
3642                 ni_cdio_cancel(dev, s);
3643                 return -EIO;
3644         }
3645         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3646                 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, M_Offset_CDIO_Command);
3647         return 0;
3648 }
3649
3650 static int ni_cdio_cancel(comedi_device * dev, comedi_subdevice * s)
3651 {
3652         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3653                 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3654                 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3655                 M_Offset_CDIO_Command);
3656 // XXX not sure what interrupt C group does
3657 //      ni_writeb(0, M_Offset_Interrupt_C_Enable);
3658         ni_writel(0, M_Offset_CDO_Mask_Enable);
3659         ni_release_cdo_mite_channel(dev);
3660         return 0;
3661 }
3662
3663 static void handle_cdio_interrupt(comedi_device * dev)
3664 {
3665         unsigned cdio_status;
3666         comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3667         unsigned long flags;
3668
3669         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3670                 return;
3671         }
3672         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3673         if (devpriv->cdo_mite_chan) {
3674                 unsigned cdo_mite_status =
3675                         mite_get_status(devpriv->cdo_mite_chan);
3676                 if (cdo_mite_status & CHSR_LINKC) {
3677                         writel(CHOR_CLRLC,
3678                                 devpriv->mite->mite_io_addr +
3679                                 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3680                 }
3681                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3682         }
3683         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3684
3685         cdio_status = ni_readl(M_Offset_CDIO_Status);
3686         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3687 //              rt_printk("cdio error: statux=0x%x\n", cdio_status);
3688                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      // XXX just guessing this is needed and does something useful
3689                 s->async->events |= COMEDI_CB_OVERFLOW;
3690         }
3691         if (cdio_status & CDO_FIFO_Empty_Bit) {
3692 //              rt_printk("cdio fifo empty\n");
3693                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3694                         M_Offset_CDIO_Command);
3695 //              s->async->events |= COMEDI_CB_EOA;
3696         }
3697         ni_event(dev, s);
3698 }
3699
3700 static int ni_serial_insn_config(comedi_device * dev, comedi_subdevice * s,
3701         comedi_insn * insn, lsampl_t * data)
3702 {
3703         int err = insn->n;
3704         unsigned char byte_out, byte_in = 0;
3705
3706         if (insn->n != 2)
3707                 return -EINVAL;
3708
3709         switch (data[0]) {
3710         case INSN_CONFIG_SERIAL_CLOCK:
3711
3712 #ifdef DEBUG_DIO
3713                 rt_printk("SPI serial clock Config cd\n", data[1]);
3714 #endif
3715                 devpriv->serial_hw_mode = 1;
3716                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3717
3718                 if (data[1] == SERIAL_DISABLED) {
3719                         devpriv->serial_hw_mode = 0;
3720                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3721                                 DIO_Software_Serial_Control);
3722                         data[1] = SERIAL_DISABLED;
3723                         devpriv->serial_interval_ns = data[1];
3724                 } else if (data[1] <= SERIAL_600NS) {
3725                         /* Warning: this clock speed is too fast to reliably
3726                            control SCXI. */
3727                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3728                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3729                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3730                         data[1] = SERIAL_600NS;
3731                         devpriv->serial_interval_ns = data[1];
3732                 } else if (data[1] <= SERIAL_1_2US) {
3733                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3734                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3735                                 DIO_Serial_Out_Divide_By_2;
3736                         data[1] = SERIAL_1_2US;
3737                         devpriv->serial_interval_ns = data[1];
3738                 } else if (data[1] <= SERIAL_10US) {
3739                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3740                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3741                                 DIO_Serial_Out_Divide_By_2;
3742                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3743                            600ns/1.2us. If you turn divide_by_2 off with the
3744                            slow clock, you will still get 10us, except then
3745                            all your delays are wrong. */
3746                         data[1] = SERIAL_10US;
3747                         devpriv->serial_interval_ns = data[1];
3748                 } else {
3749                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3750                                 DIO_Software_Serial_Control);
3751                         devpriv->serial_hw_mode = 0;
3752                         data[1] = (data[1] / 1000) * 1000;
3753                         devpriv->serial_interval_ns = data[1];
3754                 }
3755
3756                 devpriv->stc_writew(dev, devpriv->dio_control,
3757                         DIO_Control_Register);
3758                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3759                         Clock_and_FOUT_Register);
3760                 return 1;
3761
3762                 break;
3763
3764         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3765
3766                 if (devpriv->serial_interval_ns == 0) {
3767                         return -EINVAL;
3768                 }
3769
3770                 byte_out = data[1] & 0xFF;
3771
3772                 if (devpriv->serial_hw_mode) {
3773                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3774                                 &byte_in);
3775                 } else if (devpriv->serial_interval_ns > 0) {
3776                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3777                                 &byte_in);
3778                 } else {
3779                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3780                         return -EINVAL;
3781                 }
3782                 if (err < 0)
3783                         return err;
3784                 data[1] = byte_in & 0xFF;
3785                 return insn->n;
3786
3787                 break;
3788         default:
3789                 return -EINVAL;
3790         }
3791
3792 }
3793
3794 static int ni_serial_hw_readwrite8(comedi_device * dev, comedi_subdevice * s,
3795         unsigned char data_out, unsigned char *data_in)
3796 {
3797         unsigned int status1;
3798         int err = 0, count = 20;
3799
3800 #ifdef DEBUG_DIO
3801         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3802 #endif
3803
3804         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3805         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3806         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3807
3808         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3809         if (status1 & DIO_Serial_IO_In_Progress_St) {
3810                 err = -EBUSY;
3811                 goto Error;
3812         }
3813
3814         devpriv->dio_control |= DIO_HW_Serial_Start;
3815         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3816         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3817
3818         /* Wait until STC says we're done, but don't loop infinitely. */
3819         while ((status1 =
3820                         devpriv->stc_readw(dev,
3821                                 Joint_Status_1_Register)) &
3822                 DIO_Serial_IO_In_Progress_St) {
3823                 /* Delay one bit per loop */
3824                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3825                 if (--count < 0) {
3826                         rt_printk
3827                                 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3828                         err = -ETIME;
3829                         goto Error;
3830                 }
3831         }
3832
3833         /* Delay for last bit. This delay is absolutely necessary, because
3834            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3835         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3836
3837         if (data_in != NULL) {
3838                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3839 #ifdef DEBUG_DIO
3840                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3841 #endif
3842         }
3843
3844       Error:
3845         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3846
3847         return err;
3848 }
3849
3850 static int ni_serial_sw_readwrite8(comedi_device * dev, comedi_subdevice * s,
3851         unsigned char data_out, unsigned char *data_in)
3852 {
3853         unsigned char mask, input = 0;
3854
3855 #ifdef DEBUG_DIO
3856         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3857 #endif
3858
3859         /* Wait for one bit before transfer */
3860         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3861
3862         for (mask = 0x80; mask; mask >>= 1) {
3863                 /* Output current bit; note that we cannot touch s->state
3864                    because it is a per-subdevice field, and serial is
3865                    a separate subdevice from DIO. */
3866                 devpriv->dio_output &= ~DIO_SDOUT;
3867                 if (data_out & mask) {
3868                         devpriv->dio_output |= DIO_SDOUT;
3869                 }
3870                 devpriv->stc_writew(dev, devpriv->dio_output,
3871                         DIO_Output_Register);
3872
3873                 /* Assert SDCLK (active low, inverted), wait for half of
3874                    the delay, deassert SDCLK, and wait for the other half. */
3875                 devpriv->dio_control |= DIO_Software_Serial_Control;
3876                 devpriv->stc_writew(dev, devpriv->dio_control,
3877                         DIO_Control_Register);
3878
3879                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3880
3881                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3882                 devpriv->stc_writew(dev, devpriv->dio_control,
3883                         DIO_Control_Register);
3884
3885                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3886
3887                 /* Input current bit */
3888                 if (devpriv->stc_readw(dev,
3889                                 DIO_Parallel_Input_Register) & DIO_SDIN) {
3890 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3891                         input |= mask;
3892                 }
3893         }
3894 #ifdef DEBUG_DIO
3895         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3896 #endif
3897         if (data_in)
3898                 *data_in = input;
3899
3900         return 0;
3901 }
3902
3903 static void mio_common_detach(comedi_device * dev)
3904 {
3905         if (dev->private) {
3906                 if (devpriv->counter_dev) {
3907                         ni_gpct_device_destroy(devpriv->counter_dev);
3908                 }
3909         }
3910         if (dev->subdevices && boardtype.has_8255)
3911                 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
3912 }
3913
3914 static void init_ao_67xx(comedi_device * dev, comedi_subdevice * s)
3915 {
3916         int i;
3917
3918         for (i = 0; i < s->n_chan; i++)
3919                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3920                         AO_Configuration_2_67xx);
3921 }
3922
3923 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3924 {
3925         unsigned stc_register;
3926         switch (reg) {
3927         case NITIO_G0_Autoincrement_Reg:
3928                 stc_register = G_Autoincrement_Register(0);
3929                 break;
3930         case NITIO_G1_Autoincrement_Reg:
3931                 stc_register = G_Autoincrement_Register(1);
3932                 break;
3933         case NITIO_G0_Command_Reg:
3934                 stc_register = G_Command_Register(0);
3935                 break;
3936         case NITIO_G1_Command_Reg:
3937                 stc_register = G_Command_Register(1);
3938                 break;
3939         case NITIO_G0_HW_Save_Reg:
3940                 stc_register = G_HW_Save_Register(0);
3941                 break;
3942         case NITIO_G1_HW_Save_Reg:
3943                 stc_register = G_HW_Save_Register(1);
3944                 break;
3945         case NITIO_G0_SW_Save_Reg:
3946                 stc_register = G_Save_Register(0);
3947                 break;
3948         case NITIO_G1_SW_Save_Reg:
3949                 stc_register = G_Save_Register(1);
3950                 break;
3951         case NITIO_G0_Mode_Reg:
3952                 stc_register = G_Mode_Register(0);
3953                 break;
3954         case NITIO_G1_Mode_Reg:
3955                 stc_register = G_Mode_Register(1);
3956                 break;
3957         case NITIO_G0_LoadA_Reg:
3958                 stc_register = G_Load_A_Register(0);
3959                 break;
3960         case NITIO_G1_LoadA_Reg:
3961                 stc_register = G_Load_A_Register(1);
3962                 break;
3963         case NITIO_G0_LoadB_Reg:
3964                 stc_register = G_Load_B_Register(0);
3965                 break;
3966         case NITIO_G1_LoadB_Reg:
3967                 stc_register = G_Load_B_Register(1);
3968                 break;
3969         case NITIO_G0_Input_Select_Reg:
3970                 stc_register = G_Input_Select_Register(0);
3971                 break;
3972         case NITIO_G1_Input_Select_Reg:
3973                 stc_register = G_Input_Select_Register(1);
3974                 break;
3975         case NITIO_G01_Status_Reg:
3976                 stc_register = G_Status_Register;
3977                 break;
3978         case NITIO_G01_Joint_Reset_Reg:
3979                 stc_register = Joint_Reset_Register;
3980                 break;
3981         case NITIO_G01_Joint_Status1_Reg:
3982                 stc_register = Joint_Status_1_Register;
3983                 break;
3984         case NITIO_G01_Joint_Status2_Reg:
3985                 stc_register = Joint_Status_2_Register;
3986                 break;
3987         case NITIO_G0_Interrupt_Acknowledge_Reg:
3988                 stc_register = Interrupt_A_Ack_Register;
3989                 break;
3990         case NITIO_G1_Interrupt_Acknowledge_Reg:
3991                 stc_register = Interrupt_B_Ack_Register;
3992                 break;
3993         case NITIO_G0_Status_Reg:
3994                 stc_register = AI_Status_1_Register;
3995                 break;
3996         case NITIO_G1_Status_Reg:
3997                 stc_register = AO_Status_1_Register;
3998                 break;
3999         case NITIO_G0_Interrupt_Enable_Reg:
4000                 stc_register = Interrupt_A_Enable_Register;
4001                 break;
4002         case NITIO_G1_Interrupt_Enable_Reg:
4003                 stc_register = Interrupt_B_Enable_Register;
4004                 break;
4005         default:
4006                 rt_printk("%s: unhandled register 0x%x in switch.\n",
4007                         __FUNCTION__, reg);
4008                 BUG();
4009                 return 0;
4010                 break;
4011         }
4012         return stc_register;
4013 }
4014
4015 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4016         enum ni_gpct_register reg)
4017 {
4018         comedi_device *dev = counter->counter_dev->dev;
4019         unsigned stc_register;
4020         /* bits in the join reset register which are relevant to counters */
4021         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4022         static const unsigned gpct_interrupt_a_enable_mask =
4023                 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4024         static const unsigned gpct_interrupt_b_enable_mask =
4025                 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4026
4027         switch (reg) {
4028                 /* m-series-only registers */
4029         case NITIO_G0_Counting_Mode_Reg:
4030                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4031                 break;
4032         case NITIO_G1_Counting_Mode_Reg:
4033                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4034                 break;
4035         case NITIO_G0_Second_Gate_Reg:
4036                 ni_writew(bits, M_Offset_G0_Second_Gate);
4037                 break;
4038         case NITIO_G1_Second_Gate_Reg:
4039                 ni_writew(bits, M_Offset_G1_Second_Gate);
4040                 break;
4041         case NITIO_G0_DMA_Config_Reg:
4042                 ni_writew(bits, M_Offset_G0_DMA_Config);
4043                 break;
4044         case NITIO_G1_DMA_Config_Reg:
4045                 ni_writew(bits, M_Offset_G1_DMA_Config);
4046                 break;
4047         case NITIO_G0_ABZ_Reg:
4048                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4049                 break;
4050         case NITIO_G1_ABZ_Reg:
4051                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4052                 break;
4053
4054                 /* 32 bit registers */
4055         case NITIO_G0_LoadA_Reg:
4056         case NITIO_G1_LoadA_Reg:
4057         case NITIO_G0_LoadB_Reg:
4058         case NITIO_G1_LoadB_Reg:
4059                 stc_register = ni_gpct_to_stc_register(reg);
4060                 devpriv->stc_writel(dev, bits, stc_register);
4061                 break;
4062
4063                 /* 16 bit registers */
4064         case NITIO_G0_Interrupt_Enable_Reg:
4065                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4066                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4067                         gpct_interrupt_a_enable_mask, bits);
4068                 break;
4069         case NITIO_G1_Interrupt_Enable_Reg:
4070                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4071                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4072                         gpct_interrupt_b_enable_mask, bits);
4073                 break;
4074         case NITIO_G01_Joint_Reset_Reg:
4075                 BUG_ON(bits & ~gpct_joint_reset_mask);
4076                 /* fall-through */
4077         default:
4078                 stc_register = ni_gpct_to_stc_register(reg);
4079                 devpriv->stc_writew(dev, bits, stc_register);
4080         }
4081 }
4082
4083 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4084         enum ni_gpct_register reg)
4085 {
4086         comedi_device *dev = counter->counter_dev->dev;
4087         unsigned stc_register;
4088         switch (reg) {
4089                 /* m-series only registers */
4090         case NITIO_G0_DMA_Status_Reg:
4091                 return ni_readw(M_Offset_G0_DMA_Status);
4092                 break;
4093         case NITIO_G1_DMA_Status_Reg:
4094                 return ni_readw(M_Offset_G1_DMA_Status);
4095                 break;
4096
4097                 /* 32 bit registers */
4098         case NITIO_G0_HW_Save_Reg:
4099         case NITIO_G1_HW_Save_Reg:
4100         case NITIO_G0_SW_Save_Reg:
4101         case NITIO_G1_SW_Save_Reg:
4102                 stc_register = ni_gpct_to_stc_register(reg);
4103                 return devpriv->stc_readl(dev, stc_register);
4104                 break;
4105
4106                 /* 16 bit registers */
4107         default:
4108                 stc_register = ni_gpct_to_stc_register(reg);
4109                 return devpriv->stc_readw(dev, stc_register);
4110                 break;
4111         }
4112         return 0;
4113 }
4114
4115 static int ni_freq_out_insn_read(comedi_device * dev,
4116         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4117 {
4118         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4119         return 1;
4120 }
4121
4122 static int ni_freq_out_insn_write(comedi_device * dev,
4123         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4124 {
4125         devpriv->clock_and_fout &= ~FOUT_Enable;
4126         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4127                 Clock_and_FOUT_Register);
4128         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4129         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4130         devpriv->clock_and_fout |= FOUT_Enable;
4131         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4132                 Clock_and_FOUT_Register);
4133         return insn->n;
4134 }
4135
4136 static int ni_set_freq_out_clock(comedi_device * dev, lsampl_t clock_source)
4137 {
4138         switch (clock_source) {
4139         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4140                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4141                 break;
4142         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4143                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4144                 break;
4145         default:
4146                 return -EINVAL;
4147         }
4148         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4149                 Clock_and_FOUT_Register);
4150         return 3;
4151 }
4152
4153 static void ni_get_freq_out_clock(comedi_device * dev, lsampl_t * clock_source,
4154         lsampl_t * clock_period_ns)
4155 {
4156         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4157                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4158                 *clock_period_ns = TIMEBASE_2_NS;
4159         } else {
4160                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4161                 *clock_period_ns = TIMEBASE_1_NS * 2;
4162         }
4163 }
4164
4165 static int ni_freq_out_insn_config(comedi_device * dev, comedi_subdevice * s,
4166         comedi_insn * insn, lsampl_t * data)
4167 {
4168         switch (data[0]) {
4169         case INSN_CONFIG_SET_CLOCK_SRC:
4170                 return ni_set_freq_out_clock(dev, data[1]);
4171                 break;
4172         case INSN_CONFIG_GET_CLOCK_SRC:
4173                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4174                 return 3;
4175         default:
4176                 break;
4177         }
4178         return -EINVAL;
4179 }
4180
4181 static int ni_alloc_private(comedi_device * dev)
4182 {
4183         int ret;
4184
4185         ret = alloc_private(dev, sizeof(ni_private));
4186         if (ret < 0)
4187                 return ret;
4188
4189         spin_lock_init(&devpriv->window_lock);
4190         spin_lock_init(&devpriv->soft_reg_copy_lock);
4191         spin_lock_init(&devpriv->mite_channel_lock);
4192
4193         return 0;
4194 };
4195
4196 static int ni_E_init(comedi_device * dev, comedi_devconfig * it)
4197 {
4198         comedi_subdevice *s;
4199         unsigned j;
4200         enum ni_gpct_variant counter_variant;
4201
4202         if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4203                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4204                 return -EINVAL;
4205         }
4206
4207         if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4208                 return -ENOMEM;
4209
4210         /* analog input subdevice */
4211
4212         s = dev->subdevices + NI_AI_SUBDEV;
4213         dev->read_subdev = s;
4214         if (boardtype.n_adchan) {
4215                 s->type = COMEDI_SUBD_AI;
4216                 s->subdev_flags =
4217                         SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4218                 if (boardtype.reg_type != ni_reg_611x)
4219                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4220                 if (boardtype.adbits > 16)
4221                         s->subdev_flags |= SDF_LSAMPL;
4222                 if (boardtype.reg_type & ni_reg_m_series_mask)
4223                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4224                 s->n_chan = boardtype.n_adchan;
4225                 s->len_chanlist = 512;
4226                 s->maxdata = (1 << boardtype.adbits) - 1;
4227                 s->range_table = ni_range_lkup[boardtype.gainlkup];
4228                 s->insn_read = &ni_ai_insn_read;
4229                 s->insn_config = &ni_ai_insn_config;
4230                 s->do_cmdtest = &ni_ai_cmdtest;
4231                 s->do_cmd = &ni_ai_cmd;
4232                 s->cancel = &ni_ai_reset;
4233                 s->poll = &ni_ai_poll;
4234                 s->munge = &ni_ai_munge;
4235 #ifdef PCIDMA
4236                 s->async_dma_dir = DMA_FROM_DEVICE;
4237 #endif
4238         } else {
4239                 s->type = COMEDI_SUBD_UNUSED;
4240         }
4241
4242         /* analog output subdevice */
4243
4244         s = dev->subdevices + NI_AO_SUBDEV;
4245         if (boardtype.n_aochan) {
4246                 s->type = COMEDI_SUBD_AO;
4247                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4248                 if (boardtype.reg_type & ni_reg_m_series_mask)
4249                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4250                 s->n_chan = boardtype.n_aochan;
4251                 s->maxdata = (1 << boardtype.aobits) - 1;
4252                 s->range_table = boardtype.ao_range_table;
4253                 s->insn_read = &ni_ao_insn_read;
4254                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4255                         s->insn_write = &ni_ao_insn_write_671x;
4256                 } else {
4257                         s->insn_write = &ni_ao_insn_write;
4258                 }
4259 #ifdef PCIDMA
4260                 if (boardtype.n_aochan) {
4261                         s->async_dma_dir = DMA_TO_DEVICE;
4262 #else
4263                 if (boardtype.ao_fifo_depth) {
4264 #endif
4265                         dev->write_subdev = s;
4266                         s->subdev_flags |= SDF_CMD_WRITE;
4267                         s->do_cmd = &ni_ao_cmd;
4268                         s->do_cmdtest = &ni_ao_cmdtest;
4269                         s->len_chanlist = boardtype.n_aochan;
4270                         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4271                                 s->munge = ni_ao_munge;
4272                 }
4273                 s->cancel = &ni_ao_reset;
4274         } else {
4275                 s->type = COMEDI_SUBD_UNUSED;
4276         }
4277         if ((boardtype.reg_type & ni_reg_67xx_mask))
4278                 init_ao_67xx(dev, s);
4279
4280         /* digital i/o subdevice */
4281
4282         s = dev->subdevices + NI_DIO_SUBDEV;
4283         s->type = COMEDI_SUBD_DIO;
4284         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4285         s->maxdata = 1;
4286         s->io_bits = 0;         /* all bits input */
4287         s->range_table = &range_digital;
4288         s->n_chan = boardtype.num_p0_dio_channels;
4289         if (boardtype.reg_type & ni_reg_m_series_mask) {
4290                 s->subdev_flags |=
4291                         SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4292                 s->insn_bits = &ni_m_series_dio_insn_bits;
4293                 s->insn_config = &ni_m_series_dio_insn_config;
4294                 s->do_cmd = &ni_cdio_cmd;
4295                 s->do_cmdtest = &ni_cdio_cmdtest;
4296                 s->cancel = &ni_cdio_cancel;
4297                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4298                 s->len_chanlist = s->n_chan;
4299
4300                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4301                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4302         } else {
4303                 s->insn_bits = &ni_dio_insn_bits;
4304                 s->insn_config = &ni_dio_insn_config;
4305                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4306                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4307         }
4308
4309         /* 8255 device */
4310         s = dev->subdevices + NI_8255_DIO_SUBDEV;
4311         if (boardtype.has_8255) {
4312                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4313         } else {
4314                 s->type = COMEDI_SUBD_UNUSED;
4315         }
4316
4317         /* formerly general purpose counter/timer device, but no longer used */
4318         s = dev->subdevices + NI_UNUSED_SUBDEV;
4319         s->type = COMEDI_SUBD_UNUSED;
4320
4321         /* calibration subdevice -- ai and ao */
4322         s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4323         s->type = COMEDI_SUBD_CALIB;
4324         if (boardtype.reg_type & ni_reg_m_series_mask) {
4325                 // internal PWM analog output used for AI nonlinearity calibration
4326                 s->subdev_flags = SDF_INTERNAL;
4327                 s->insn_config = &ni_m_series_pwm_config;
4328                 s->n_chan = 1;
4329                 s->maxdata = 0;
4330                 ni_writel(0x0, M_Offset_Cal_PWM);
4331         } else if (boardtype.reg_type == ni_reg_6143) {
4332                 // internal PWM analog output used for AI nonlinearity calibration
4333                 s->subdev_flags = SDF_INTERNAL;
4334                 s->insn_config = &ni_6143_pwm_config;
4335                 s->n_chan = 1;
4336                 s->maxdata = 0;
4337         } else {
4338                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4339                 s->insn_read = &ni_calib_insn_read;
4340                 s->insn_write = &ni_calib_insn_write;
4341                 caldac_setup(dev, s);
4342         }
4343
4344         /* EEPROM */
4345         s = dev->subdevices + NI_EEPROM_SUBDEV;
4346         s->type = COMEDI_SUBD_MEMORY;
4347         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4348         s->maxdata = 0xff;
4349         if (boardtype.reg_type & ni_reg_m_series_mask) {
4350                 s->n_chan = M_SERIES_EEPROM_SIZE;
4351                 s->insn_read = &ni_m_series_eeprom_insn_read;
4352         } else {
4353                 s->n_chan = 512;
4354                 s->insn_read = &ni_eeprom_insn_read;
4355         }
4356
4357         /* PFI */
4358         s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4359         s->type = COMEDI_SUBD_DIO;
4360         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4361         if (boardtype.reg_type & ni_reg_m_series_mask) {
4362                 unsigned i;
4363                 s->n_chan = 16;
4364                 ni_writew(s->state, M_Offset_PFI_DO);
4365                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4366                         ni_writew(devpriv->pfi_output_select_reg[i],
4367                                 M_Offset_PFI_Output_Select(i + 1));
4368                 }
4369         } else {
4370                 s->n_chan = 10;
4371         }
4372         s->maxdata = 1;
4373         if (boardtype.reg_type & ni_reg_m_series_mask) {
4374                 s->insn_bits = &ni_pfi_insn_bits;
4375         }
4376         s->insn_config = &ni_pfi_insn_config;
4377         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4378
4379         /* cs5529 calibration adc */
4380         s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4381         if (boardtype.reg_type & ni_reg_67xx_mask) {
4382                 s->type = COMEDI_SUBD_AI;
4383                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4384                 // one channel for each analog output channel
4385                 s->n_chan = boardtype.n_aochan;
4386                 s->maxdata = (1 << 16) - 1;
4387                 s->range_table = &range_unknown;        /* XXX */
4388                 s->insn_read = cs5529_ai_insn_read;
4389                 s->insn_config = NULL;
4390                 init_cs5529(dev);
4391         } else {
4392                 s->type = COMEDI_SUBD_UNUSED;
4393         }
4394
4395         /* Serial */
4396         s = dev->subdevices + NI_SERIAL_SUBDEV;
4397         s->type = COMEDI_SUBD_SERIAL;
4398         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4399         s->n_chan = 1;
4400         s->maxdata = 0xff;
4401         s->insn_config = ni_serial_insn_config;
4402         devpriv->serial_interval_ns = 0;
4403         devpriv->serial_hw_mode = 0;
4404
4405         /* RTSI */
4406         s = dev->subdevices + NI_RTSI_SUBDEV;
4407         s->type = COMEDI_SUBD_DIO;
4408         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4409         s->n_chan = 8;
4410         s->maxdata = 1;
4411         s->insn_bits = ni_rtsi_insn_bits;
4412         s->insn_config = ni_rtsi_insn_config;
4413         ni_rtsi_init(dev);
4414
4415         if (boardtype.reg_type & ni_reg_m_series_mask) {
4416                 counter_variant = ni_gpct_variant_m_series;
4417         } else {
4418                 counter_variant = ni_gpct_variant_e_series;
4419         }
4420         devpriv->counter_dev = ni_gpct_device_construct(dev,
4421                 &ni_gpct_write_register, &ni_gpct_read_register,
4422                 counter_variant, NUM_GPCT);
4423         /* General purpose counters */
4424         for (j = 0; j < NUM_GPCT; ++j) {
4425                 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4426                 s->type = COMEDI_SUBD_COUNTER;
4427                 s->subdev_flags =
4428                         SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4429                         /* | SDF_CMD_WRITE */ ;
4430                 s->n_chan = 3;
4431                 if (boardtype.reg_type & ni_reg_m_series_mask)
4432                         s->maxdata = 0xffffffff;
4433                 else
4434                         s->maxdata = 0xffffff;
4435                 s->insn_read = &ni_gpct_insn_read;
4436                 s->insn_write = &ni_gpct_insn_write;
4437                 s->insn_config = &ni_gpct_insn_config;
4438                 s->do_cmd = &ni_gpct_cmd;
4439                 s->len_chanlist = 1;
4440                 s->do_cmdtest = &ni_gpct_cmdtest;
4441                 s->cancel = &ni_gpct_cancel;
4442                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4443                 s->private = &devpriv->counter_dev->counters[j];
4444
4445                 devpriv->counter_dev->counters[j].chip_index = 0;
4446                 devpriv->counter_dev->counters[j].counter_index = j;
4447                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4448         }
4449
4450         /* Frequency output */
4451         s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4452         s->type = COMEDI_SUBD_COUNTER;
4453         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4454         s->n_chan = 1;
4455         s->maxdata = 0xf;
4456         s->insn_read = &ni_freq_out_insn_read;
4457         s->insn_write = &ni_freq_out_insn_write;
4458         s->insn_config = &ni_freq_out_insn_config;
4459
4460         /* ai configuration */
4461         ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV);
4462         if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4463                 // BEAM is this needed for PCI-6143 ??
4464                 devpriv->clock_and_fout =
4465                         Slow_Internal_Time_Divide_By_2 |
4466                         Slow_Internal_Timebase |
4467                         Clock_To_Board_Divide_By_2 |
4468                         Clock_To_Board |
4469                         AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4470         } else {
4471                 devpriv->clock_and_fout =
4472                         Slow_Internal_Time_Divide_By_2 |
4473                         Slow_Internal_Timebase |
4474                         Clock_To_Board_Divide_By_2 | Clock_To_Board;
4475         }
4476         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4477                 Clock_and_FOUT_Register);
4478
4479         /* analog output configuration */
4480         ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV);
4481
4482         if (dev->irq) {
4483                 devpriv->stc_writew(dev,
4484                         (IRQ_POLARITY ? Interrupt_Output_Polarity : 0) |
4485                         (Interrupt_Output_On_3_Pins & 0) | Interrupt_A_Enable |
4486                         Interrupt_B_Enable |
4487                         Interrupt_A_Output_Select(interrupt_pin(dev->
4488                                         irq)) |
4489                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
4490                         Interrupt_Control_Register);
4491         }
4492
4493         /* DMA setup */
4494         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4495         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4496
4497         if (boardtype.reg_type & ni_reg_6xxx_mask) {
4498                 ni_writeb(0, Magic_611x);
4499         } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4500                 int channel;
4501                 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4502                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4503                         ni_writeb(0x0,
4504                                 M_Offset_AO_Reference_Attenuation(channel));
4505                 }
4506                 ni_writeb(0x0, M_Offset_AO_Calibration);
4507         }
4508
4509         printk("\n");
4510         return 0;
4511 }
4512
4513 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4514 {
4515         comedi_device *dev = (comedi_device *) arg;
4516
4517         if (dir) {
4518                 ni_writeb(data, Port_A + 2 * port);
4519                 return 0;
4520         } else {
4521                 return ni_readb(Port_A + 2 * port);
4522         }
4523 }
4524
4525 /*
4526         presents the EEPROM as a subdevice
4527 */
4528
4529 static int ni_eeprom_insn_read(comedi_device * dev, comedi_subdevice * s,
4530         comedi_insn * insn, lsampl_t * data)
4531 {
4532         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4533
4534         return 1;
4535 }
4536
4537 /*
4538         reads bytes out of eeprom
4539 */
4540
4541 static int ni_read_eeprom(comedi_device * dev, int addr)
4542 {
4543         int bit;
4544         int bitstring;
4545
4546         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4547         ni_writeb(0x04, Serial_Command);
4548         for (bit = 0x8000; bit; bit >>= 1) {
4549                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4550                         Serial_Command);
4551                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4552                         Serial_Command);
4553         }
4554         bitstring = 0;
4555         for (bit = 0x80; bit; bit >>= 1) {
4556                 ni_writeb(0x04, Serial_Command);
4557                 ni_writeb(0x05, Serial_Command);
4558                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4559         }
4560         ni_writeb(0x00, Serial_Command);
4561
4562         return bitstring;
4563 }
4564
4565 static int ni_m_series_eeprom_insn_read(comedi_device * dev,
4566         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4567 {
4568         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4569
4570         return 1;
4571 }
4572
4573 static int ni_get_pwm_config(comedi_device * dev, lsampl_t * data)
4574 {
4575         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4576         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4577         return 3;
4578 }
4579
4580 static int ni_m_series_pwm_config(comedi_device * dev, comedi_subdevice * s,
4581         comedi_insn * insn, lsampl_t * data)
4582 {
4583         unsigned up_count, down_count;
4584         switch (data[0]) {
4585         case INSN_CONFIG_PWM_OUTPUT:
4586                 switch (data[1]) {
4587                 case TRIG_ROUND_NEAREST:
4588                         up_count =
4589                                 (data[2] +
4590                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4591                         break;
4592                 case TRIG_ROUND_DOWN:
4593                         up_count = data[2] / devpriv->clock_ns;
4594                         break;
4595                 case TRIG_ROUND_UP:
4596                         up_count =
4597                                 (data[2] + devpriv->clock_ns -
4598                                 1) / devpriv->clock_ns;
4599                         break;
4600                 default:
4601                         return -EINVAL;
4602                         break;
4603                 }
4604                 switch (data[3]) {
4605                 case TRIG_ROUND_NEAREST:
4606                         down_count =
4607                                 (data[4] +
4608                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4609                         break;
4610                 case TRIG_ROUND_DOWN:
4611                         down_count = data[4] / devpriv->clock_ns;
4612                         break;
4613                 case TRIG_ROUND_UP:
4614                         down_count =
4615                                 (data[4] + devpriv->clock_ns -
4616                                 1) / devpriv->clock_ns;
4617                         break;
4618                 default:
4619                         return -EINVAL;
4620                         break;
4621                 }
4622                 if (up_count * devpriv->clock_ns != data[2] ||
4623                         down_count * devpriv->clock_ns != data[4]) {
4624                         data[2] = up_count * devpriv->clock_ns;
4625                         data[4] = down_count * devpriv->clock_ns;
4626                         return -EAGAIN;
4627                 }
4628                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4629                         MSeries_Cal_PWM_Low_Time_Bits(down_count),
4630                         M_Offset_Cal_PWM);
4631                 devpriv->pwm_up_count = up_count;
4632                 devpriv->pwm_down_count = down_count;
4633                 return 5;
4634                 break;
4635         case INSN_CONFIG_GET_PWM_OUTPUT:
4636                 return ni_get_pwm_config(dev, data);
4637                 break;
4638         default:
4639                 return -EINVAL;
4640                 break;
4641         }
4642         return 0;
4643 }
4644
4645 static int ni_6143_pwm_config(comedi_device * dev, comedi_subdevice * s,
4646         comedi_insn * insn, lsampl_t * data)
4647 {
4648         unsigned up_count, down_count;
4649         switch (data[0]) {
4650         case INSN_CONFIG_PWM_OUTPUT:
4651                 switch (data[1]) {
4652                 case TRIG_ROUND_NEAREST:
4653                         up_count =
4654                                 (data[2] +
4655                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4656                         break;
4657                 case TRIG_ROUND_DOWN:
4658                         up_count = data[2] / devpriv->clock_ns;
4659                         break;
4660                 case TRIG_ROUND_UP:
4661                         up_count =
4662                                 (data[2] + devpriv->clock_ns -
4663                                 1) / devpriv->clock_ns;
4664                         break;
4665                 default:
4666                         return -EINVAL;
4667                         break;
4668                 }
4669                 switch (data[3]) {
4670                 case TRIG_ROUND_NEAREST:
4671                         down_count =
4672                                 (data[4] +
4673                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4674                         break;
4675                 case TRIG_ROUND_DOWN:
4676                         down_count = data[4] / devpriv->clock_ns;
4677                         break;
4678                 case TRIG_ROUND_UP:
4679                         down_count =
4680                                 (data[4] + devpriv->clock_ns -
4681                                 1) / devpriv->clock_ns;
4682                         break;
4683                 default:
4684                         return -EINVAL;
4685                         break;
4686                 }
4687                 if (up_count * devpriv->clock_ns != data[2] ||
4688                         down_count * devpriv->clock_ns != data[4]) {
4689                         data[2] = up_count * devpriv->clock_ns;
4690                         data[4] = down_count * devpriv->clock_ns;
4691                         return -EAGAIN;
4692                 }
4693                 ni_writel(up_count, Calibration_HighTime_6143);
4694                 devpriv->pwm_up_count = up_count;
4695                 ni_writel(down_count, Calibration_LowTime_6143);
4696                 devpriv->pwm_down_count = down_count;
4697                 return 5;
4698                 break;
4699         case INSN_CONFIG_GET_PWM_OUTPUT:
4700                 return ni_get_pwm_config(dev, data);
4701         default:
4702                 return -EINVAL;
4703                 break;
4704         }
4705         return 0;
4706 }
4707
4708 static void ni_write_caldac(comedi_device * dev, int addr, int val);
4709 /*
4710         calibration subdevice
4711 */
4712 static int ni_calib_insn_write(comedi_device * dev, comedi_subdevice * s,
4713         comedi_insn * insn, lsampl_t * data)
4714 {
4715         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4716
4717         return 1;
4718 }
4719
4720 static int ni_calib_insn_read(comedi_device * dev, comedi_subdevice * s,
4721         comedi_insn * insn, lsampl_t * data)
4722 {
4723         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4724
4725         return 1;
4726 }
4727
4728 static int pack_mb88341(int addr, int val, int *bitstring);
4729 static int pack_dac8800(int addr, int val, int *bitstring);
4730 static int pack_dac8043(int addr, int val, int *bitstring);
4731 static int pack_ad8522(int addr, int val, int *bitstring);
4732 static int pack_ad8804(int addr, int val, int *bitstring);
4733 static int pack_ad8842(int addr, int val, int *bitstring);
4734
4735 struct caldac_struct {
4736         int n_chans;
4737         int n_bits;
4738         int (*packbits) (int, int, int *);
4739 };
4740
4741 static struct caldac_struct caldacs[] = {
4742         [mb88341] = {12, 8, pack_mb88341},
4743         [dac8800] = {8, 8, pack_dac8800},
4744         [dac8043] = {1, 12, pack_dac8043},
4745         [ad8522] = {2, 12, pack_ad8522},
4746         [ad8804] = {12, 8, pack_ad8804},
4747         [ad8842] = {8, 8, pack_ad8842},
4748         [ad8804_debug] = {16, 8, pack_ad8804},
4749 };
4750
4751 static void caldac_setup(comedi_device * dev, comedi_subdevice * s)
4752 {
4753         int i, j;
4754         int n_dacs;
4755         int n_chans = 0;
4756         int n_bits;
4757         int diffbits = 0;
4758         int type;
4759         int chan;
4760
4761         type = boardtype.caldac[0];
4762         if (type == caldac_none)
4763                 return;
4764         n_bits = caldacs[type].n_bits;
4765         for (i = 0; i < 3; i++) {
4766                 type = boardtype.caldac[i];
4767                 if (type == caldac_none)
4768                         break;
4769                 if (caldacs[type].n_bits != n_bits)
4770                         diffbits = 1;
4771                 n_chans += caldacs[type].n_chans;
4772         }
4773         n_dacs = i;
4774         s->n_chan = n_chans;
4775
4776         if (diffbits) {
4777                 unsigned int *maxdata_list;
4778
4779                 if (n_chans > MAX_N_CALDACS) {
4780                         printk("BUG! MAX_N_CALDACS too small\n");
4781                 }
4782                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4783                 chan = 0;
4784                 for (i = 0; i < n_dacs; i++) {
4785                         type = boardtype.caldac[i];
4786                         for (j = 0; j < caldacs[type].n_chans; j++) {
4787                                 maxdata_list[chan] =
4788                                         (1 << caldacs[type].n_bits) - 1;
4789                                 chan++;
4790                         }
4791                 }
4792
4793                 for (chan = 0; chan < s->n_chan; chan++)
4794                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4795         } else {
4796                 type = boardtype.caldac[0];
4797                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4798
4799                 for (chan = 0; chan < s->n_chan; chan++)
4800                         ni_write_caldac(dev, i, s->maxdata / 2);
4801         }
4802 }
4803
4804 static void ni_write_caldac(comedi_device * dev, int addr, int val)
4805 {
4806         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4807         int i;
4808         int type;
4809
4810         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4811         if (devpriv->caldacs[addr] == val)
4812                 return;
4813         devpriv->caldacs[addr] = val;
4814
4815         for (i = 0; i < 3; i++) {
4816                 type = boardtype.caldac[i];
4817                 if (type == caldac_none)
4818                         break;
4819                 if (addr < caldacs[type].n_chans) {
4820                         bits = caldacs[type].packbits(addr, val, &bitstring);
4821                         loadbit = SerDacLd(i);
4822                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4823                         break;
4824                 }
4825                 addr -= caldacs[type].n_chans;
4826         }
4827
4828         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4829                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4830                 comedi_udelay(1);
4831                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4832                 comedi_udelay(1);
4833         }
4834         ni_writeb(loadbit, Serial_Command);
4835         comedi_udelay(1);
4836         ni_writeb(0, Serial_Command);
4837 }
4838
4839 static int pack_mb88341(int addr, int val, int *bitstring)
4840 {
4841         /*
4842            Fujitsu MB 88341
4843            Note that address bits are reversed.  Thanks to
4844            Ingo Keen for noticing this.
4845
4846            Note also that the 88341 expects address values from
4847            1-12, whereas we use channel numbers 0-11.  The NI
4848            docs use 1-12, also, so be careful here.
4849          */
4850         addr++;
4851         *bitstring = ((addr & 0x1) << 11) |
4852                 ((addr & 0x2) << 9) |
4853                 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4854         return 12;
4855 }
4856
4857 static int pack_dac8800(int addr, int val, int *bitstring)
4858 {
4859         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4860         return 11;
4861 }
4862
4863 static int pack_dac8043(int addr, int val, int *bitstring)
4864 {
4865         *bitstring = val & 0xfff;
4866         return 12;
4867 }
4868
4869 static int pack_ad8522(int addr, int val, int *bitstring)
4870 {
4871         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4872         return 16;
4873 }
4874
4875 static int pack_ad8804(int addr, int val, int *bitstring)
4876 {
4877         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4878         return 12;
4879 }
4880
4881 static int pack_ad8842(int addr, int val, int *bitstring)
4882 {
4883         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4884         return 12;
4885 }
4886
4887 #if 0
4888 /*
4889  *      Read the GPCTs current value.
4890  */
4891 static int GPCT_G_Watch(comedi_device * dev, int chan)
4892 {
4893         unsigned int hi1, hi2, lo;
4894
4895         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4896         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4897                 G_Command_Register(chan));
4898
4899         devpriv->gpct_command[chan] |= G_Save_Trace;
4900         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4901                 G_Command_Register(chan));
4902
4903         /* This procedure is used because the two registers cannot
4904          * be read atomically. */
4905         do {
4906                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4907                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4908                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4909         } while (hi1 != hi2);
4910
4911         return (hi1 << 16) | lo;
4912 }
4913
4914 static void GPCT_Reset(comedi_device * dev, int chan)
4915 {
4916         int temp_ack_reg = 0;
4917
4918         //printk("GPCT_Reset...");
4919         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4920
4921         switch (chan) {
4922         case 0:
4923                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
4924                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4925                         G0_TC_Interrupt_Enable, 0);
4926                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4927                         G0_Gate_Interrupt_Enable, 0);
4928                 temp_ack_reg |= G0_Gate_Error_Confirm;
4929                 temp_ack_reg |= G0_TC_Error_Confirm;
4930                 temp_ack_reg |= G0_TC_Interrupt_Ack;
4931                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
4932                 devpriv->stc_writew(dev, temp_ack_reg,
4933                         Interrupt_A_Ack_Register);
4934
4935                 //problem...this interferes with the other ctr...
4936                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4937                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4938                         Analog_Trigger_Etc_Register);
4939                 break;
4940         case 1:
4941                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
4942                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4943                         G1_TC_Interrupt_Enable, 0);
4944                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4945                         G0_Gate_Interrupt_Enable, 0);
4946                 temp_ack_reg |= G1_Gate_Error_Confirm;
4947                 temp_ack_reg |= G1_TC_Error_Confirm;
4948                 temp_ack_reg |= G1_TC_Interrupt_Ack;
4949                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
4950                 devpriv->stc_writew(dev, temp_ack_reg,
4951                         Interrupt_B_Ack_Register);
4952
4953                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4954                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4955                         Analog_Trigger_Etc_Register);
4956                 break;
4957         };
4958
4959         devpriv->gpct_mode[chan] = 0;
4960         devpriv->gpct_input_select[chan] = 0;
4961         devpriv->gpct_command[chan] = 0;
4962
4963         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4964
4965         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
4966                 G_Mode_Register(chan));
4967         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
4968                 G_Input_Select_Register(chan));
4969         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
4970
4971         //printk("exit GPCT_Reset\n");
4972 }
4973
4974 #endif
4975
4976 static int ni_gpct_insn_config(comedi_device * dev, comedi_subdevice * s,
4977         comedi_insn * insn, lsampl_t * data)
4978 {
4979         struct ni_gpct *counter = s->private;
4980         return ni_tio_insn_config(counter, insn, data);
4981 }
4982
4983 static int ni_gpct_insn_read(comedi_device * dev, comedi_subdevice * s,
4984         comedi_insn * insn, lsampl_t * data)
4985 {
4986         struct ni_gpct *counter = s->private;
4987         return ni_tio_rinsn(counter, insn, data);
4988 }
4989
4990 static int ni_gpct_insn_write(comedi_device * dev, comedi_subdevice * s,
4991         comedi_insn * insn, lsampl_t * data)
4992 {
4993         struct ni_gpct *counter = s->private;
4994         return ni_tio_winsn(counter, insn, data);
4995 }
4996
4997 static int ni_gpct_cmd(comedi_device * dev, comedi_subdevice * s)
4998 {
4999         int retval;
5000 #ifdef PCIDMA
5001         struct ni_gpct *counter = s->private;
5002 //      const comedi_cmd *cmd = &s->async->cmd;
5003
5004         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5005                 COMEDI_INPUT);
5006         if (retval) {
5007                 comedi_error(dev,
5008                         "no dma channel available for use by counter");
5009                 return retval;
5010         }
5011         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5012         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5013         retval = ni_tio_cmd(counter, s->async);
5014 #else
5015         retval = -ENOTSUPP;
5016 #endif
5017         return retval;
5018 }
5019
5020 static int ni_gpct_cmdtest(comedi_device * dev, comedi_subdevice * s,
5021         comedi_cmd * cmd)
5022 {
5023         struct ni_gpct *counter = s->private;
5024
5025         return ni_tio_cmdtest(counter, cmd);
5026 }
5027
5028 static int ni_gpct_cancel(comedi_device * dev, comedi_subdevice * s)
5029 {
5030         struct ni_gpct *counter = s->private;
5031         int retval;
5032
5033         retval = ni_tio_cancel(counter);
5034         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5035         ni_release_gpct_mite_channel(dev, counter->counter_index);
5036         return retval;
5037 }
5038
5039 /*
5040  *
5041  *  Programmable Function Inputs
5042  *
5043  */
5044
5045 static int ni_m_series_set_pfi_routing(comedi_device * dev, unsigned chan,
5046         unsigned source)
5047 {
5048         unsigned pfi_reg_index;
5049         unsigned array_offset;
5050         if ((source & 0x1f) != source)
5051                 return -EINVAL;
5052         pfi_reg_index = 1 + chan / 3;
5053         array_offset = pfi_reg_index - 1;
5054         devpriv->pfi_output_select_reg[array_offset] &=
5055                 ~MSeries_PFI_Output_Select_Mask(chan);
5056         devpriv->pfi_output_select_reg[array_offset] |=
5057                 MSeries_PFI_Output_Select_Bits(chan, source);
5058         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5059                 M_Offset_PFI_Output_Select(pfi_reg_index));
5060         return 2;
5061 }
5062
5063 static int ni_old_set_pfi_routing(comedi_device * dev, unsigned chan,
5064         unsigned source)
5065 {
5066         // pre-m-series boards have fixed signals on pfi pins
5067         if (source != ni_old_get_pfi_routing(dev, chan))
5068                 return -EINVAL;
5069         return 2;
5070 }
5071
5072 static int ni_set_pfi_routing(comedi_device * dev, unsigned chan,
5073         unsigned source)
5074 {
5075         if (boardtype.reg_type & ni_reg_m_series_mask)
5076                 return ni_m_series_set_pfi_routing(dev, chan, source);
5077         else
5078                 return ni_old_set_pfi_routing(dev, chan, source);
5079 }
5080
5081 static unsigned ni_m_series_get_pfi_routing(comedi_device * dev, unsigned chan)
5082 {
5083         const unsigned array_offset = chan / 3;
5084         return MSeries_PFI_Output_Select_Source(chan,
5085                 devpriv->pfi_output_select_reg[array_offset]);
5086 }
5087
5088 static unsigned ni_old_get_pfi_routing(comedi_device * dev, unsigned chan)
5089 {
5090         // pre-m-series boards have fixed signals on pfi pins
5091         switch (chan) {
5092         case 0:
5093                 return NI_PFI_OUTPUT_AI_START1;
5094                 break;
5095         case 1:
5096                 return NI_PFI_OUTPUT_AI_START2;
5097                 break;
5098         case 2:
5099                 return NI_PFI_OUTPUT_AI_CONVERT;
5100                 break;
5101         case 3:
5102                 return NI_PFI_OUTPUT_G_SRC1;
5103                 break;
5104         case 4:
5105                 return NI_PFI_OUTPUT_G_GATE1;
5106                 break;
5107         case 5:
5108                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5109                 break;
5110         case 6:
5111                 return NI_PFI_OUTPUT_AO_START1;
5112                 break;
5113         case 7:
5114                 return NI_PFI_OUTPUT_AI_START_PULSE;
5115                 break;
5116         case 8:
5117                 return NI_PFI_OUTPUT_G_SRC0;
5118                 break;
5119         case 9:
5120                 return NI_PFI_OUTPUT_G_GATE0;
5121                 break;
5122         default:
5123                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
5124                 break;
5125         }
5126         return 0;
5127 }
5128
5129 static unsigned ni_get_pfi_routing(comedi_device * dev, unsigned chan)
5130 {
5131         if (boardtype.reg_type & ni_reg_m_series_mask)
5132                 return ni_m_series_get_pfi_routing(dev, chan);
5133         else
5134                 return ni_old_get_pfi_routing(dev, chan);
5135 }
5136
5137 static int ni_config_filter(comedi_device * dev, unsigned pfi_channel,
5138         enum ni_pfi_filter_select filter)
5139 {
5140         unsigned bits;
5141         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5142                 return -ENOTSUPP;
5143         }
5144         bits = ni_readl(M_Offset_PFI_Filter);
5145         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5146         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5147         ni_writel(bits, M_Offset_PFI_Filter);
5148         return 0;
5149 }
5150
5151 static int ni_pfi_insn_bits(comedi_device * dev, comedi_subdevice * s,
5152         comedi_insn * insn, lsampl_t * data)
5153 {
5154         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5155                 return -ENOTSUPP;
5156         }
5157         if (data[0]) {
5158                 s->state &= ~data[0];
5159                 s->state |= (data[0] & data[1]);
5160                 ni_writew(s->state, M_Offset_PFI_DO);
5161         }
5162         data[1] = ni_readw(M_Offset_PFI_DI);
5163         return 2;
5164 }
5165
5166 static int ni_pfi_insn_config(comedi_device * dev, comedi_subdevice * s,
5167         comedi_insn * insn, lsampl_t * data)
5168 {
5169         unsigned int chan;
5170
5171         if (insn->n < 1)
5172                 return -EINVAL;
5173
5174         chan = CR_CHAN(insn->chanspec);
5175
5176         switch (data[0]) {
5177         case COMEDI_OUTPUT:
5178                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5179                 break;
5180         case COMEDI_INPUT:
5181                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5182                 break;
5183         case INSN_CONFIG_DIO_QUERY:
5184                 data[1] =
5185                         (devpriv->
5186                         io_bidirection_pin_reg & (1 << chan)) ? COMEDI_OUTPUT :
5187                         COMEDI_INPUT;
5188                 return 0;
5189                 break;
5190         case INSN_CONFIG_SET_ROUTING:
5191                 return ni_set_pfi_routing(dev, chan, data[1]);
5192                 break;
5193         case INSN_CONFIG_GET_ROUTING:
5194                 data[1] = ni_get_pfi_routing(dev, chan);
5195                 break;
5196         case INSN_CONFIG_FILTER:
5197                 return ni_config_filter(dev, chan, data[1]);
5198                 break;
5199         default:
5200                 return -EINVAL;
5201         }
5202         return 0;
5203 }
5204
5205 /*
5206  *
5207  *  NI RTSI Bus Functions
5208  *
5209  */
5210 static void ni_rtsi_init(comedi_device * dev)
5211 {
5212         // Initialises the RTSI bus signal switch to a default state
5213
5214         // Set clock mode to internal
5215         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5216         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5217                 rt_printk("ni_set_master_clock failed, bug?");
5218         }
5219         // default internal lines routing to RTSI bus lines
5220         devpriv->rtsi_trig_a_output_reg =
5221                 RTSI_Trig_Output_Bits(0,
5222                 NI_RTSI_OUTPUT_ADR_START1) | RTSI_Trig_Output_Bits(1,
5223                 NI_RTSI_OUTPUT_ADR_START2) | RTSI_Trig_Output_Bits(2,
5224                 NI_RTSI_OUTPUT_SCLKG) | RTSI_Trig_Output_Bits(3,
5225                 NI_RTSI_OUTPUT_DACUPDN);
5226         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5227                 RTSI_Trig_A_Output_Register);
5228         devpriv->rtsi_trig_b_output_reg =
5229                 RTSI_Trig_Output_Bits(4,
5230                 NI_RTSI_OUTPUT_DA_START1) | RTSI_Trig_Output_Bits(5,
5231                 NI_RTSI_OUTPUT_G_SRC0) | RTSI_Trig_Output_Bits(6,
5232                 NI_RTSI_OUTPUT_G_GATE0);
5233         if (boardtype.reg_type & ni_reg_m_series_mask)
5234                 devpriv->rtsi_trig_b_output_reg |=
5235                         RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5236         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5237                 RTSI_Trig_B_Output_Register);
5238
5239         // Sets the source and direction of the 4 on board lines
5240 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5241 }
5242
5243 static int ni_rtsi_insn_bits(comedi_device * dev, comedi_subdevice * s,
5244         comedi_insn * insn, lsampl_t * data)
5245 {
5246         if (insn->n != 2)
5247                 return -EINVAL;
5248
5249         data[1] = 0;
5250
5251         return 2;
5252 }
5253
5254 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5255  * given an arbitrary frequency input clock */
5256 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5257         unsigned *freq_divider, unsigned *freq_multiplier,
5258         unsigned *actual_period_ns)
5259 {
5260         unsigned div;
5261         unsigned best_div = 1;
5262         static const unsigned max_div = 0x10;
5263         unsigned mult;
5264         unsigned best_mult = 1;
5265         static const unsigned max_mult = 0x100;
5266         static const unsigned pico_per_nano = 1000;
5267
5268         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5269         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5270          * 20 MHz for most timing clocks */
5271         static const unsigned target_picosec = 12500;
5272         static const unsigned fudge_factor_80_to_20Mhz = 4;
5273         int best_period_picosec = 0;
5274         for (div = 1; div <= max_div; ++div) {
5275                 for (mult = 1; mult <= max_mult; ++mult) {
5276                         unsigned new_period_ps =
5277                                 (reference_picosec * div) / mult;
5278                         if (abs(new_period_ps - target_picosec) <
5279                                 abs(best_period_picosec - target_picosec)) {
5280                                 best_period_picosec = new_period_ps;
5281                                 best_div = div;
5282                                 best_mult = mult;
5283                         }
5284                 }
5285         }
5286         if (best_period_picosec == 0) {
5287                 rt_printk("%s: bug, failed to find pll parameters\n",
5288                         __FUNCTION__);
5289                 return -EIO;
5290         }
5291         *freq_divider = best_div;
5292         *freq_multiplier = best_mult;
5293         *actual_period_ns =
5294                 (best_period_picosec * fudge_factor_80_to_20Mhz +
5295                 (pico_per_nano / 2)) / pico_per_nano;
5296         return 0;
5297 }
5298
5299 static inline unsigned num_configurable_rtsi_channels(comedi_device * dev)
5300 {
5301         if (boardtype.reg_type & ni_reg_m_series_mask)
5302                 return 8;
5303         else
5304                 return 7;
5305 }
5306
5307 static int ni_mseries_set_pll_master_clock(comedi_device * dev, unsigned source,
5308         unsigned period_ns)
5309 {
5310         static const unsigned min_period_ns = 50;
5311         static const unsigned max_period_ns = 1000;
5312         static const unsigned timeout = 1000;
5313         unsigned pll_control_bits;
5314         unsigned freq_divider;
5315         unsigned freq_multiplier;
5316         unsigned i;
5317         int retval;
5318         if (source == NI_MIO_PLL_PXI10_CLOCK)
5319                 period_ns = 100;
5320         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
5321         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5322                 rt_printk
5323                         ("%s: you must specify an input clock frequency between %i and %i nanosec "
5324                         "for the phased-lock loop.\n", __FUNCTION__,
5325                         min_period_ns, max_period_ns);
5326                 return -EINVAL;
5327         }
5328         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5329         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5330                 RTSI_Trig_Direction_Register);
5331         pll_control_bits =
5332                 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5333         devpriv->clock_and_fout2 |=
5334                 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5335         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5336         switch (source) {
5337         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5338                 devpriv->clock_and_fout2 |=
5339                         MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5340                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5341                         &freq_multiplier, &devpriv->clock_ns);
5342                 if (retval < 0)
5343                         return retval;
5344                 break;
5345         case NI_MIO_PLL_PXI10_CLOCK:
5346                 /* pxi clock is 10MHz */
5347                 devpriv->clock_and_fout2 |=
5348                         MSeries_PLL_In_Source_Select_PXI_Clock10;
5349                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5350                         &freq_multiplier, &devpriv->clock_ns);
5351                 if (retval < 0)
5352                         return retval;
5353                 break;
5354         default:
5355                 {
5356                         unsigned rtsi_channel;
5357                         static const unsigned max_rtsi_channel = 7;
5358                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5359                                 ++rtsi_channel) {
5360                                 if (source ==
5361                                         NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5362                                         devpriv->clock_and_fout2 |=
5363                                                 MSeries_PLL_In_Source_Select_RTSI_Bits
5364                                                 (rtsi_channel);
5365                                         break;
5366                                 }
5367                         }
5368                         if (rtsi_channel > max_rtsi_channel)
5369                                 return -EINVAL;
5370                         retval = ni_mseries_get_pll_parameters(period_ns,
5371                                 &freq_divider, &freq_multiplier,
5372                                 &devpriv->clock_ns);
5373                         if (retval < 0)
5374                                 return retval;
5375                 }
5376                 break;
5377         }
5378         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5379         pll_control_bits |=
5380                 MSeries_PLL_Divisor_Bits(freq_divider) |
5381                 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5382 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
5383 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
5384         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5385         devpriv->clock_source = source;
5386         /* it seems to typically take a few hundred microseconds for PLL to lock */
5387         for (i = 0; i < timeout; ++i) {
5388                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5389                         break;
5390                 }
5391                 udelay(1);
5392         }
5393         if (i == timeout) {
5394                 rt_printk
5395                         ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5396                         __FUNCTION__, source, period_ns);
5397                 return -ETIMEDOUT;
5398         }
5399         return 3;
5400 }
5401
5402 static int ni_set_master_clock(comedi_device * dev, unsigned source,
5403         unsigned period_ns)
5404 {
5405         if (source == NI_MIO_INTERNAL_CLOCK) {
5406                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5407                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5408                         RTSI_Trig_Direction_Register);
5409                 devpriv->clock_ns = TIMEBASE_1_NS;
5410                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5411                         devpriv->clock_and_fout2 &=
5412                                 ~(MSeries_Timebase1_Select_Bit |
5413                                 MSeries_Timebase3_Select_Bit);
5414                         ni_writew(devpriv->clock_and_fout2,
5415                                 M_Offset_Clock_and_Fout2);
5416                         ni_writew(0, M_Offset_PLL_Control);
5417                 }
5418                 devpriv->clock_source = source;
5419         } else {
5420                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5421                         return ni_mseries_set_pll_master_clock(dev, source,
5422                                 period_ns);
5423                 } else {
5424                         if (source == NI_MIO_RTSI_CLOCK) {
5425                                 devpriv->rtsi_trig_direction_reg |=
5426                                         Use_RTSI_Clock_Bit;
5427                                 devpriv->stc_writew(dev,
5428                                         devpriv->rtsi_trig_direction_reg,
5429                                         RTSI_Trig_Direction_Register);
5430                                 if (devpriv->clock_ns == 0) {
5431                                         rt_printk
5432                                                 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5433                                                 __FUNCTION__);
5434                                         return -EINVAL;
5435                                 } else {
5436                                         devpriv->clock_ns = period_ns;
5437                                 }
5438                                 devpriv->clock_source = source;
5439                         } else
5440                                 return -EINVAL;
5441                 }
5442         }
5443         return 3;
5444 }
5445
5446 static int ni_valid_rtsi_output_source(comedi_device * dev, unsigned chan,
5447         unsigned source)
5448 {
5449         if (chan >= num_configurable_rtsi_channels(dev)) {
5450                 if (chan == old_RTSI_clock_channel) {
5451                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5452                                 return 1;
5453                         else {
5454                                 rt_printk
5455                                         ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5456                                         __FUNCTION__, chan,
5457                                         old_RTSI_clock_channel);
5458                                 return 0;
5459                         }
5460                 }
5461                 return 0;
5462         }
5463         switch (source) {
5464         case NI_RTSI_OUTPUT_ADR_START1:
5465         case NI_RTSI_OUTPUT_ADR_START2:
5466         case NI_RTSI_OUTPUT_SCLKG:
5467         case NI_RTSI_OUTPUT_DACUPDN:
5468         case NI_RTSI_OUTPUT_DA_START1:
5469         case NI_RTSI_OUTPUT_G_SRC0:
5470         case NI_RTSI_OUTPUT_G_GATE0:
5471         case NI_RTSI_OUTPUT_RGOUT0:
5472         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5473                 return 1;
5474                 break;
5475         case NI_RTSI_OUTPUT_RTSI_OSC:
5476                 if (boardtype.reg_type & ni_reg_m_series_mask)
5477                         return 1;
5478                 else
5479                         return 0;
5480                 break;
5481         default:
5482                 return 0;
5483                 break;
5484         }
5485 }
5486
5487 static int ni_set_rtsi_routing(comedi_device * dev, unsigned chan,
5488         unsigned source)
5489 {
5490         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5491                 return -EINVAL;
5492         if (chan < 4) {
5493                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5494                 devpriv->rtsi_trig_a_output_reg |=
5495                         RTSI_Trig_Output_Bits(chan, source);
5496                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5497                         RTSI_Trig_A_Output_Register);
5498         } else if (chan < 8) {
5499                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5500                 devpriv->rtsi_trig_b_output_reg |=
5501                         RTSI_Trig_Output_Bits(chan, source);
5502                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5503                         RTSI_Trig_B_Output_Register);
5504         }
5505         return 2;
5506 }
5507
5508 static unsigned ni_get_rtsi_routing(comedi_device * dev, unsigned chan)
5509 {
5510         if (chan < 4) {
5511                 return RTSI_Trig_Output_Source(chan,
5512                         devpriv->rtsi_trig_a_output_reg);
5513         } else if (chan < num_configurable_rtsi_channels(dev)) {
5514                 return RTSI_Trig_Output_Source(chan,
5515                         devpriv->rtsi_trig_b_output_reg);
5516         } else {
5517                 if (chan == old_RTSI_clock_channel)
5518                         return NI_RTSI_OUTPUT_RTSI_OSC;
5519                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
5520                 return 0;
5521         }
5522 }
5523
5524 static int ni_rtsi_insn_config(comedi_device * dev, comedi_subdevice * s,
5525         comedi_insn * insn, lsampl_t * data)
5526 {
5527         unsigned int chan = CR_CHAN(insn->chanspec);
5528         switch (data[0]) {
5529         case INSN_CONFIG_DIO_OUTPUT:
5530                 if (chan < num_configurable_rtsi_channels(dev)) {
5531                         devpriv->rtsi_trig_direction_reg |=
5532                                 RTSI_Output_Bit(chan,
5533                                 (boardtype.reg_type & ni_reg_m_series_mask) !=
5534                                 0);
5535                 } else if (chan == old_RTSI_clock_channel) {
5536                         devpriv->rtsi_trig_direction_reg |=
5537                                 Drive_RTSI_Clock_Bit;
5538                 }
5539                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5540                         RTSI_Trig_Direction_Register);
5541                 break;
5542         case INSN_CONFIG_DIO_INPUT:
5543                 if (chan < num_configurable_rtsi_channels(dev)) {
5544                         devpriv->rtsi_trig_direction_reg &=
5545                                 ~RTSI_Output_Bit(chan,
5546                                 (boardtype.reg_type & ni_reg_m_series_mask) !=
5547                                 0);
5548                 } else if (chan == old_RTSI_clock_channel) {
5549                         devpriv->rtsi_trig_direction_reg &=
5550                                 ~Drive_RTSI_Clock_Bit;
5551                 }
5552                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5553                         RTSI_Trig_Direction_Register);
5554                 break;
5555         case INSN_CONFIG_DIO_QUERY:
5556                 if (chan < num_configurable_rtsi_channels(dev)) {
5557                         data[1] =
5558                                 (devpriv->
5559                                 rtsi_trig_direction_reg & RTSI_Output_Bit(chan,
5560                                         (boardtype.
5561                                                 reg_type & ni_reg_m_series_mask)
5562                                         !=
5563                                         0)) ? INSN_CONFIG_DIO_OUTPUT :
5564                                 INSN_CONFIG_DIO_INPUT;
5565                 } else if (chan == old_RTSI_clock_channel) {
5566                         data[1] =
5567                                 (devpriv->
5568                                 rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit)
5569                                 ? INSN_CONFIG_DIO_OUTPUT :
5570                                 INSN_CONFIG_DIO_INPUT;
5571                 }
5572                 return 2;
5573                 break;
5574         case INSN_CONFIG_SET_CLOCK_SRC:
5575                 return ni_set_master_clock(dev, data[1], data[2]);
5576                 break;
5577         case INSN_CONFIG_GET_CLOCK_SRC:
5578                 data[1] = devpriv->clock_source;
5579                 data[2] = devpriv->clock_ns;
5580                 return 3;
5581                 break;
5582         case INSN_CONFIG_SET_ROUTING:
5583                 return ni_set_rtsi_routing(dev, chan, data[1]);
5584                 break;
5585         case INSN_CONFIG_GET_ROUTING:
5586                 data[1] = ni_get_rtsi_routing(dev, chan);
5587                 return 2;
5588                 break;
5589         default:
5590                 return -EINVAL;
5591                 break;
5592         }
5593         return 1;
5594 }
5595
5596 static int cs5529_wait_for_idle(comedi_device * dev)
5597 {
5598         unsigned short status;
5599         const int timeout = HZ;
5600         int i;
5601
5602         for (i = 0; i < timeout; i++) {
5603                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5604                 if ((status & CSS_ADC_BUSY) == 0) {
5605                         break;
5606                 }
5607                 set_current_state(TASK_INTERRUPTIBLE);
5608                 if (schedule_timeout(1)) {
5609                         return -EIO;
5610                 }
5611         }
5612 //printk("looped %i times waiting for idle\n", i);
5613         if (i == timeout) {
5614                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
5615                 return -ETIME;
5616         }
5617         return 0;
5618 }
5619
5620 static void cs5529_command(comedi_device * dev, unsigned short value)
5621 {
5622         static const int timeout = 100;
5623         int i;
5624
5625         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5626         /* give time for command to start being serially clocked into cs5529.
5627          * this insures that the CSS_ADC_BUSY bit will get properly
5628          * set before we exit this function.
5629          */
5630         for (i = 0; i < timeout; i++) {
5631                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5632                         break;
5633                 comedi_udelay(1);
5634         }
5635 //printk("looped %i times writing command to cs5529\n", i);
5636         if (i == timeout) {
5637                 comedi_error(dev, "possible problem - never saw adc go busy?");
5638         }
5639 }
5640
5641 /* write to cs5529 register */
5642 static void cs5529_config_write(comedi_device * dev, unsigned int value,
5643         unsigned int reg_select_bits)
5644 {
5645         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5646                 CAL_ADC_Config_Data_High_Word_67xx);
5647         ni_ao_win_outw(dev, (value & 0xffff),
5648                 CAL_ADC_Config_Data_Low_Word_67xx);
5649         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5650         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5651         if (cs5529_wait_for_idle(dev))
5652                 comedi_error(dev, "time or signal in cs5529_config_write()");
5653 }
5654
5655 /* read from cs5529 register */
5656 static unsigned int cs5529_config_read(comedi_device * dev,
5657         unsigned int reg_select_bits)
5658 {
5659         unsigned int value;
5660
5661         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5662         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5663         if (cs5529_wait_for_idle(dev))
5664                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5665         value = (ni_ao_win_inw(dev,
5666                         CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
5667         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5668         return value;
5669 }
5670
5671 static int cs5529_do_conversion(comedi_device * dev, unsigned short *data)
5672 {
5673         int retval;
5674         unsigned short status;
5675
5676         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5677         retval = cs5529_wait_for_idle(dev);
5678         if (retval) {
5679                 comedi_error(dev,
5680                         "timeout or signal in cs5529_do_conversion()");
5681                 return -ETIME;
5682         }
5683         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5684         if (status & CSS_OSC_DETECT) {
5685                 rt_printk
5686                         ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5687                 return -EIO;
5688         }
5689         if (status & CSS_OVERRANGE) {
5690                 rt_printk
5691                         ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5692         }
5693         if (data) {
5694                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5695                 /* cs5529 returns 16 bit signed data in bipolar mode */
5696                 *data ^= (1 << 15);
5697         }
5698         return 0;
5699 }
5700
5701 static int cs5529_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
5702         comedi_insn * insn, lsampl_t * data)
5703 {
5704         int n, retval;
5705         unsigned short sample;
5706         unsigned int channel_select;
5707         const unsigned int INTERNAL_REF = 0x1000;
5708
5709         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5710          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5711          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5712         if (insn->chanspec & CR_ALT_SOURCE)
5713                 channel_select = INTERNAL_REF;
5714         else
5715                 channel_select = CR_CHAN(insn->chanspec);
5716         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5717
5718         for (n = 0; n < insn->n; n++) {
5719                 retval = cs5529_do_conversion(dev, &sample);
5720                 if (retval < 0)
5721                         return retval;
5722                 data[n] = sample;
5723         }
5724         return insn->n;
5725 }
5726
5727 static int init_cs5529(comedi_device * dev)
5728 {
5729         unsigned int config_bits =
5730                 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5731
5732 #if 1
5733         /* do self-calibration */
5734         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5735                 CSCMD_CONFIG_REGISTER);
5736         /* need to force a conversion for calibration to run */
5737         cs5529_do_conversion(dev, NULL);
5738 #else
5739         /* force gain calibration to 1 */
5740         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5741         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5742                 CSCMD_CONFIG_REGISTER);
5743         if (cs5529_wait_for_idle(dev))
5744                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5745 #endif
5746 #if 0
5747         rt_printk("config: 0x%x\n", cs5529_config_read(dev,
5748                 CSCMD_CONFIG_REGISTER));
5749         rt_printk("gain: 0x%x\n", cs5529_config_read(dev,
5750                 CSCMD_GAIN_REGISTER));
5751         rt_printk("offset: 0x%x\n", cs5529_config_read(dev,
5752                 CSCMD_OFFSET_REGISTER));
5753 #endif
5754         return 0;
5755 }