comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static const short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static const comedi_lrange range_ni_E_ai={      16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static const comedi_lrange range_ni_E_ai_limited={      8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static const comedi_lrange range_ni_E_ai_limited14={    14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static const comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static const comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static const comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static const comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static const comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static const comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static const comedi_lrange * const ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200 static int ni_cdio_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 201 static int ni_cdio_cmd(comedi_device *dev,comedi_subdevice *s);
 202 static int ni_cdio_cancel(comedi_device *dev,comedi_subdevice *s);
 203 static void handle_cdio_interrupt(comedi_device *dev);
 204 static int ni_cdo_inttrig(comedi_device *dev,comedi_subdevice *s,
 205         unsigned int trignum);
 206
 207 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 208         comedi_insn *insn,lsampl_t *data);
 209 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 210         unsigned char data_out, unsigned char *data_in);
 211 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 212         unsigned char data_out, unsigned char *data_in);
 213
 214 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 215         comedi_insn *insn,lsampl_t *data);
 216 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 217         comedi_insn *insn,lsampl_t *data);
 218
 219 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 220         comedi_insn *insn,lsampl_t *data);
 221 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 222         comedi_insn *insn,lsampl_t *data);
 223
 224 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 225         comedi_insn *insn,lsampl_t *data);
 226 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 227         comedi_insn *insn,lsampl_t *data);
 228 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 229
 230 static void ni_rtsi_init(comedi_device *dev);
 231 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 232         comedi_insn *insn,lsampl_t *data);
 233 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 234         comedi_insn *insn,lsampl_t *data);
 235
 236 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 237 static int ni_read_eeprom(comedi_device *dev,int addr);
 238
 239 #ifdef DEBUG_STATUS_A
 240 static void ni_mio_print_status_a(int status);
 241 #else
 242 #define ni_mio_print_status_a(a)
 243 #endif
 244 #ifdef DEBUG_STATUS_B
 245 static void ni_mio_print_status_b(int status);
 246 #else
 247 #define ni_mio_print_status_b(a)
 248 #endif
 249
 250 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 251 #ifndef PCIDMA
 252 static void ni_handle_fifo_half_full(comedi_device *dev);
 253 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 254 #endif
 255 static void ni_handle_fifo_dregs(comedi_device *dev);
 256 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 259         unsigned int *list);
 260 static void shutdown_ai_command( comedi_device *dev );
 261
 262 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 263         unsigned int trignum);
 264
 265 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 266
 267 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 268
 269 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 270         comedi_insn *insn,lsampl_t *data);
 271 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 272         comedi_insn *insn,lsampl_t *data);
 273 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 274         comedi_insn *insn,lsampl_t *data);
 275 static int ni_gpct_cmd(comedi_device *dev,comedi_subdevice *s);
 276 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 277 static int ni_gpct_cancel(comedi_device *dev,comedi_subdevice *s);
 278 static void handle_gpct_interrupt(comedi_device *dev, unsigned short counter_index);
 279
 280 static int init_cs5529(comedi_device *dev);
 281 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 282 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 283 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 284 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 285
 286 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 287         comedi_insn *insn,lsampl_t *data);
 288 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 289         comedi_insn *insn, lsampl_t *data);
 290
 291 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 292 static void ack_a_interrupt(comedi_device *dev, unsigned short a_status);
 293 static void ack_b_interrupt(comedi_device *dev, unsigned short b_status);
 294
 295 enum aimodes
 296 {
 297         AIMODE_NONE = 0,
 298         AIMODE_HALF_FULL = 1,
 299         AIMODE_SCAN = 2,
 300         AIMODE_SAMPLE = 3,
 301 };
 302
 303 enum ni_common_subdevices
 304 {
 305         NI_AI_SUBDEV,
 306         NI_AO_SUBDEV,
 307         NI_DIO_SUBDEV,
 308         NI_8255_DIO_SUBDEV,
 309         NI_UNUSED_SUBDEV,
 310         NI_CALIBRATION_SUBDEV,
 311         NI_EEPROM_SUBDEV,
 312         NI_PFI_DIO_SUBDEV,
 313         NI_CS5529_CALIBRATION_SUBDEV,
 314         NI_SERIAL_SUBDEV,
 315         NI_RTSI_SUBDEV,
 316         NI_GPCT0_SUBDEV,
 317         NI_GPCT1_SUBDEV,
 318         NI_FREQ_OUT_SUBDEV,
 319         NI_NUM_SUBDEVICES
 320 };
 321 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 322 {
 323         switch(counter_index)
 324         {
 325         case 0: return NI_GPCT0_SUBDEV;
 326                 break;
 327         case 1: return NI_GPCT1_SUBDEV;
 328                 break;
 329         default:
 330                 break;
 331         }
 332         BUG();
 333         return NI_GPCT0_SUBDEV;
 334 }
 335
 336 enum timebase_nanoseconds
 337 {
 338         TIMEBASE_1_NS = 50,
 339         TIMEBASE_2_NS = 10000
 340 };
 341
 342 #define SERIAL_DISABLED         0
 343 #define SERIAL_600NS            600
 344 #define SERIAL_1_2US            1200
 345 #define SERIAL_10US                     10000
 346
 347 static const int num_adc_stages_611x = 3;
 348
 349 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 350         unsigned ai_mite_status);
 351 static void handle_b_interrupt(comedi_device *dev, unsigned short status,
 352         unsigned ao_mite_status);
 353 static void get_last_sample_611x( comedi_device *dev );
 354 static void get_last_sample_6143( comedi_device *dev );
 355 #ifdef PCIDMA
 356 static int ni_ai_drain_dma(comedi_device *dev );
 357 static inline void ni_set_bitfield(comedi_device *dev, int reg, unsigned bit_mask, unsigned bit_values);
 358
 359 /* DMA channel setup */
 360
 361 // negative channel means no channel
 362 static inline void ni_set_ai_dma_channel(comedi_device *dev, int channel)
 363 {
 364         unsigned bitfield;
 365
 366         if(channel >= 0)
 367         {
 368                 bitfield = (ni_stc_dma_channel_select_bitfield(channel) << AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 369         }else
 370         {
 371                 bitfield = 0;
 372         }
 373         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 374 }
 375
 376 // negative channel means no channel
 377 static inline void ni_set_ao_dma_channel(comedi_device *dev, int channel)
 378 {
 379         unsigned bitfield;
 380
 381         if(channel >= 0)
 382         {
 383                 bitfield = (ni_stc_dma_channel_select_bitfield(channel) << AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 384         }else
 385         {
 386                 bitfield = 0;
 387         }
 388         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 389 }
 390
 391 // negative mite_channel means no channel
 392 static inline void ni_set_gpct_dma_channel(comedi_device *dev, unsigned gpct_index, int mite_channel)
 393 {
 394         unsigned bitfield;
 395
 396         if(mite_channel >= 0)
 397         {
 398                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 399         }else
 400         {
 401                 bitfield = 0;
 402         }
 403         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index), bitfield);
 404 }
 405
 406 // negative mite_channel means no channel
 407 static inline void ni_set_cdo_dma_channel(comedi_device *dev, int mite_channel)
 408 {
 409         unsigned long flags;
 410
 411         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 412         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 413         if(mite_channel >= 0)
 414         {
 415                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 416                 under the assumption the cdio dma selection works just like ai/ao/gpct.
 417                 Definitely works for dma channels 0 and 1.*/
 418                 devpriv->cdio_dma_select_reg |= (ni_stc_dma_channel_select_bitfield(mite_channel) << CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 419         }
 420         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 421         mmiowb();
 422         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 423 }
 424
 425 static int ni_request_ai_mite_channel(comedi_device *dev)
 426 {
 427         unsigned long flags;
 428
 429         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 430         BUG_ON(devpriv->ai_mite_chan);
 431         devpriv->ai_mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 432         if(devpriv->ai_mite_chan == NULL)
 433         {
 434                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 435                 comedi_error(dev, "failed to reserve mite dma channel for analog input.");
 436                 return -EBUSY;
 437         }
 438         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 439         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 440         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 441         return 0;
 442 }
 443
 444 static int ni_request_ao_mite_channel(comedi_device *dev)
 445 {
 446         unsigned long flags;
 447
 448         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 449         BUG_ON(devpriv->ao_mite_chan);
 450         devpriv->ao_mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 451         if(devpriv->ao_mite_chan == NULL)
 452         {
 453                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 454                 comedi_error(dev, "failed to reserve mite dma channel for analog outut.");
 455                 return -EBUSY;
 456         }
 457         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 458         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 459         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 460         return 0;
 461 }
 462
 463 static int ni_request_gpct_mite_channel(comedi_device *dev, unsigned gpct_index, enum comedi_io_direction direction)
 464 {
 465         unsigned long flags;
 466         struct mite_channel *mite_chan;
 467
 468         BUG_ON(gpct_index >= NUM_GPCT);
 469         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 470         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 471         mite_chan = mite_request_channel(devpriv->mite, devpriv->gpct_mite_ring[gpct_index]);
 472         if(mite_chan == NULL)
 473         {
 474                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 475                 comedi_error(dev, "failed to reserve mite dma channel for counter.");
 476                 return -EBUSY;
 477         }
 478         mite_chan->dir = direction;
 479         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], mite_chan);
 480         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 481         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 482         return 0;
 483 }
 484
 485 #endif  // PCIDMA
 486
 487 static int ni_request_cdo_mite_channel(comedi_device *dev)
 488 {
 489 #ifdef PCIDMA
 490         unsigned long flags;
 491
 492         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 493         BUG_ON(devpriv->cdo_mite_chan);
 494         devpriv->cdo_mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 495         if(devpriv->cdo_mite_chan == NULL)
 496         {
 497                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 498                 comedi_error(dev, "failed to reserve mite dma channel for correlated digital outut.");
 499                 return -EBUSY;
 500         }
 501         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 502         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 503         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 504 #endif  // PCIDMA
 505         return 0;
 506 }
 507
 508
 509 static void ni_release_ai_mite_channel(comedi_device *dev)
 510 {
 511 #ifdef PCIDMA
 512         unsigned long flags;
 513
 514         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 515         if(devpriv->ai_mite_chan)
 516         {
 517                 ni_set_ai_dma_channel(dev, -1);
 518                 mite_release_channel(devpriv->ai_mite_chan);
 519                 devpriv->ai_mite_chan = NULL;
 520         }
 521         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 522 #endif  // PCIDMA
 523 }
 524
 525 static void ni_release_ao_mite_channel(comedi_device *dev)
 526 {
 527 #ifdef PCIDMA
 528         unsigned long flags;
 529
 530         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 531         if(devpriv->ao_mite_chan)
 532         {
 533                 ni_set_ao_dma_channel(dev, -1);
 534                 mite_release_channel(devpriv->ao_mite_chan);
 535                 devpriv->ao_mite_chan = NULL;
 536         }
 537         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 538 #endif  // PCIDMA
 539 }
 540
 541 void ni_release_gpct_mite_channel(comedi_device *dev, unsigned gpct_index)
 542 {
 543 #ifdef PCIDMA
 544         unsigned long flags;
 545
 546         BUG_ON(gpct_index >= NUM_GPCT);
 547         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 548         if(devpriv->counter_dev->counters[gpct_index].mite_chan)
 549         {
 550                 struct mite_channel *mite_chan = devpriv->counter_dev->counters[gpct_index].mite_chan;
 551
 552                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 553                 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], NULL);
 554                 mite_release_channel(mite_chan);
 555         }
 556         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 557 #endif  // PCIDMA
 558 }
 559
 560 static void ni_release_cdo_mite_channel(comedi_device *dev)
 561 {
 562 #ifdef PCIDMA
 563         unsigned long flags;
 564
 565         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 566         if(devpriv->cdo_mite_chan)
 567         {
 568                 ni_set_cdo_dma_channel(dev, -1);
 569                 mite_release_channel(devpriv->cdo_mite_chan);
 570                 devpriv->cdo_mite_chan = NULL;
 571         }
 572         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 573 #endif  // PCIDMA
 574 }
 575
 576 // e-series boards use the second irq signals to generate dma requests for their counters
 577 static void ni_e_series_enable_second_irq(comedi_device *dev, unsigned gpct_index, short enable)
 578 {
 579         if(boardtype.reg_type & ni_reg_m_series_mask) return;
 580         switch(gpct_index)
 581         {
 582         case 0:
 583                 if(enable)
 584                 {
 585                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable, Second_IRQ_A_Enable_Register);
 586                 }else
 587                 {
 588                         devpriv->stc_writew(dev, 0, Second_IRQ_A_Enable_Register);
 589                 }
 590                 break;
 591         case 1:
 592                 if(enable)
 593                 {
 594                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable, Second_IRQ_B_Enable_Register);
 595                 }else
 596                 {
 597                         devpriv->stc_writew(dev, 0, Second_IRQ_B_Enable_Register);
 598                 }
 599                 break;
 600         default:
 601                 BUG();
 602                 break;
 603         }
 604 }
 605
 606 static void ni_clear_ai_fifo(comedi_device *dev){
 607         if(boardtype.reg_type == ni_reg_6143){
 608                 // Flush the 6143 data FIFO
 609                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 610                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 611                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 612         }else {
 613                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 614                 if(boardtype.reg_type == ni_reg_625x)
 615                 {
 616                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 617                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 618 #if 0
 619                 /* the NI example code does 3 convert pulses for 625x boards,
 620                 but that appears to be wrong in practice. */
 621                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 622                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 623                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 624 #endif
 625                 }
 626         }
 627 }
 628
 629 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 630 {
 631         devpriv->stc_writew(dev, data >> 16, reg);
 632         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 633 }
 634
 635 static uint32_t win_in2(comedi_device *dev, int reg)
 636 {
 637         uint32_t bits;
 638         bits = devpriv->stc_readw(dev, reg) << 16;
 639         bits |= devpriv->stc_readw(dev, reg + 1);
 640         return bits;
 641 }
 642
 643 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 644 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 645 {
 646         unsigned long flags;
 647
 648         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 649         ni_writew(addr,AO_Window_Address_611x);
 650         ni_writew(data,AO_Window_Data_611x);
 651         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 652 }
 653
 654 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 655 {
 656         unsigned long flags;
 657
 658         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 659         ni_writew(addr,AO_Window_Address_611x);
 660         ni_writel(data,AO_Window_Data_611x);
 661         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 662 }
 663
 664 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 665 {
 666         unsigned long flags;
 667         unsigned short data;
 668
 669         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 670         ni_writew(addr, AO_Window_Address_611x);
 671         data = ni_readw(AO_Window_Data_611x);
 672         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 673         return data;
 674 }
 675
 676 static inline void ni_set_bitfield(comedi_device *dev, int reg, unsigned bit_mask, unsigned bit_values)
 677 {
 678         unsigned long flags;
 679
 680         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 681         switch (reg){
 682                 case Interrupt_A_Enable_Register:
 683                         devpriv->int_a_enable_reg &= ~bit_mask;
 684                         devpriv->int_a_enable_reg |=  bit_values & bit_mask;
 685                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg, Interrupt_A_Enable_Register);
 686                         break;
 687                 case Interrupt_B_Enable_Register:
 688                         devpriv->int_b_enable_reg &= ~bit_mask;
 689                         devpriv->int_b_enable_reg |=  bit_values & bit_mask;
 690                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg, Interrupt_B_Enable_Register);
 691                         break;
 692                 case IO_Bidirection_Pin_Register:
 693                         devpriv->io_bidirection_pin_reg &= ~bit_mask;
 694                         devpriv->io_bidirection_pin_reg |=  bit_values & bit_mask;
 695                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg, IO_Bidirection_Pin_Register);
 696                         break;
 697                 case AI_AO_Select:
 698                         devpriv->ai_ao_select_reg &= ~bit_mask;
 699                         devpriv->ai_ao_select_reg |=  bit_values & bit_mask;
 700                         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 701                         break;
 702                 case G0_G1_Select:
 703                         devpriv->g0_g1_select_reg &= ~bit_mask;
 704                         devpriv->g0_g1_select_reg |=  bit_values & bit_mask;
 705                         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 706                         break;
 707                 default:
 708                         rt_printk("Warning %s() called with invalid register\n", __FUNCTION__);
 709                         rt_printk("reg is %d\n", reg);
 710                         break;
 711         }
 712         mmiowb();
 713         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags );
 714 }
 715
 716 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 717 * share registers (such as Interrupt_A_Register) without interfering with
 718 * each other.
 719 *
 720 * NOTE: the switch/case statements are optimized out for a constant argument
 721 * so this is actually quite fast---  If you must wrap another function around this
 722 * make it inline to avoid a large speed penalty.
 723 *
 724 * value should only be 1 or 0.
 725 */
 726 static inline void ni_set_bits(comedi_device *dev, int reg, unsigned bits, unsigned value)
 727 {
 728         unsigned bit_values;
 729
 730         if(value)
 731                 bit_values = bits;
 732         else
 733                 bit_values = 0;
 734         ni_set_bitfield(dev, reg, bits, bit_values);
 735 }
 736
 737 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 738 {
 739         comedi_device *dev=d;
 740         unsigned short a_status;
 741         unsigned short b_status;
 742         unsigned int ai_mite_status = 0;
 743         unsigned int ao_mite_status = 0;
 744         unsigned long flags;
 745         struct mite_struct *mite = devpriv->mite;
 746
 747         if(dev->attached == 0) return IRQ_NONE;
 748         smp_mb();       // make sure dev->attached is checked before handler does anything else.
 749
 750         // lock to avoid race with comedi_poll
 751         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 752         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 753         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 754         if(mite)
 755         {
 756                 unsigned long flags_too;
 757
 758                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 759                 if(devpriv->ai_mite_chan)
 760                 {
 761                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 762                         if(ai_mite_status & CHSR_LINKC)
 763                                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 764                 }
 765                 if(devpriv->ao_mite_chan)
 766                 {
 767                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 768                         if(ao_mite_status & CHSR_LINKC)
 769                                 writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 770                 }
 771                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 772         }
 773         ack_a_interrupt(dev, a_status);
 774         ack_b_interrupt(dev, b_status);
 775         if((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 776                 handle_a_interrupt(dev, a_status, ai_mite_status);
 777         if((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 778                 handle_b_interrupt(dev, b_status, ao_mite_status);
 779         handle_gpct_interrupt(dev, 0);
 780         handle_gpct_interrupt(dev, 1);
 781         handle_cdio_interrupt(dev);
 782
 783         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 784         return IRQ_HANDLED;
 785 }
 786
 787 #ifdef PCIDMA
 788 static void ni_sync_ai_dma(comedi_device *dev)
 789 {
 790         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 791         unsigned long flags;
 792
 793         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 794         if(devpriv->ai_mite_chan)
 795                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 796         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 797 }
 798
 799 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 800 {
 801         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
 802         unsigned long flags;
 803
 804         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 805         if(devpriv->ao_mite_chan)
 806         {
 807                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 808         }
 809         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 810 }
 811
 812 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 813 {
 814         static const int timeout = 10000;
 815         int i;
 816         for(i = 0; i < timeout; i++)
 817         {
 818                 unsigned short b_status;
 819
 820                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 821                 if( b_status & AO_FIFO_Half_Full_St )
 822                         break;
 823                 /* if we poll too often, the pci bus activity seems
 824                  to slow the dma transfer down */
 825                 comedi_udelay(10);
 826         }
 827         if( i == timeout )
 828         {
 829                 comedi_error(dev, "timed out waiting for dma load");
 830                 return -EPIPE;
 831         }
 832         return 0;
 833 }
 834
 835 #endif //PCIDMA
 836 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 837 {
 838         if(devpriv->aimode == AIMODE_SCAN)
 839         {
 840 #ifdef PCIDMA
 841                 static const int timeout = 10;
 842                 int i;
 843
 844                 for(i = 0; i < timeout; i++)
 845                 {
 846                         ni_sync_ai_dma(dev);
 847                         if((s->async->events & COMEDI_CB_EOS)) break;
 848                         comedi_udelay(1);
 849                 }
 850 #else
 851                 ni_handle_fifo_dregs(dev);
 852                 s->async->events |= COMEDI_CB_EOS;
 853 #endif
 854         }
 855         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 856         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 857                 shutdown_ai_command( dev );
 858         }
 859 }
 860
 861 static void shutdown_ai_command( comedi_device *dev )
 862 {
 863         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 864
 865 #ifdef PCIDMA
 866         ni_ai_drain_dma( dev );
 867 #endif
 868         ni_handle_fifo_dregs(dev);
 869         get_last_sample_611x(dev);
 870         get_last_sample_6143(dev);
 871
 872         s->async->events |= COMEDI_CB_EOA;
 873 }
 874
 875 static void ni_event(comedi_device *dev, comedi_subdevice *s)
 876 {
 877         if(s->async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
 878         {
 879                 switch(dev->subdevices - s)
 880                 {
 881                 case    NI_AI_SUBDEV:
 882                         ni_ai_reset(dev, s);
 883                         break;
 884                 case NI_AO_SUBDEV:
 885                         ni_ao_reset(dev, s);
 886                         break;
 887                 case NI_GPCT0_SUBDEV:
 888                 case NI_GPCT1_SUBDEV:
 889                         ni_gpct_cancel(dev, s);
 890                         break;
 891                 case NI_DIO_SUBDEV:
 892                         ni_cdio_cancel(dev, s);
 893                         break;
 894                 default:
 895                         break;
 896                 }
 897         }
 898         comedi_event(dev, s);
 899 }
 900
 901 static void handle_gpct_interrupt(comedi_device *dev, unsigned short counter_index)
 902 {
 903         comedi_subdevice *s = dev->subdevices + NI_GPCT_SUBDEV(counter_index);
 904
 905         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], s);
 906         if(s->async->events)
 907                 ni_event(dev, s);
 908 }
 909
 910 static void ack_a_interrupt(comedi_device *dev, unsigned short a_status)
 911 {
 912         unsigned short ack = 0;
 913
 914         if(a_status & AI_SC_TC_St)
 915         {
 916                 ack |= AI_SC_TC_Interrupt_Ack;
 917         }
 918         if(a_status & AI_START1_St)
 919         {
 920                         ack |= AI_START1_Interrupt_Ack;
 921         }
 922         if(a_status & AI_START_St)
 923         {
 924                 ack |= AI_START_Interrupt_Ack;
 925         }
 926         if(a_status & AI_STOP_St)
 927         {
 928                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 929                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack*/;
 930         }
 931         if(ack) devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 932 }
 933
 934 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 935         unsigned ai_mite_status)
 936 {
 937         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 938
 939         //67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt
 940         if(s->type == COMEDI_SUBD_UNUSED) return;
 941
 942 #ifdef DEBUG_INTERRUPT
 943         rt_printk("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
 944                 status, ai_mite_status);
 945         ni_mio_print_status_a(status);
 946 #endif
 947 #ifdef PCIDMA
 948         if(ai_mite_status & CHSR_LINKC){
 949                 ni_sync_ai_dma(dev);
 950         }
 951
 952         if(ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 953                 rt_printk("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", ai_mite_status);
 954                 //mite_print_chsr(ai_mite_status);
 955                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 956                 //disable_irq(dev->irq);
 957         }
 958 #endif
 959
 960         /* test for all uncommon interrupt events at the same time */
 961         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 962                 if(status==0xffff){
 963                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 964                         /* we probably aren't even running a command now,
 965                          * so it's a good idea to be careful. */
 966                         if(comedi_get_subdevice_runflags(s) & SRF_RUNNING){
 967                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 968                                 ni_event(dev, s);
 969                         }
 970                         return;
 971                 }
 972                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 973                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 974                                 status);
 975                         ni_mio_print_status_a(status);
 976
 977                         shutdown_ai_command( dev );
 978
 979                         s->async->events |= COMEDI_CB_ERROR;
 980                         if(status & (AI_Overrun_St | AI_Overflow_St))
 981                                 s->async->events |= COMEDI_CB_OVERFLOW;
 982
 983                         ni_event(dev, s);
 984
 985                         return;
 986                 }
 987                 if(status&AI_SC_TC_St){
 988 #ifdef DEBUG_INTERRUPT
 989                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 990 #endif
 991                         if(!devpriv->ai_continuous){
 992                                 shutdown_ai_command(dev);
 993                         }
 994                 }
 995         }
 996 #ifndef PCIDMA
 997         if(status&AI_FIFO_Half_Full_St){
 998                 int i;
 999                 static const int timeout = 10;
1000                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1001                  *fail to get the fifo less than half full, so loop to be sure.*/
1002                 for(i = 0; i < timeout; ++i)
1003                 {
1004                         ni_handle_fifo_half_full(dev);
1005                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
1006                                 break;
1007                 }
1008         }
1009 #endif // !PCIDMA
1010
1011         if( (status & AI_STOP_St) ){
1012                 ni_handle_eos(dev, s);
1013         }
1014
1015         ni_event(dev, s);
1016
1017 #ifdef DEBUG_INTERRUPT
1018         status=devpriv->stc_readw(dev, AI_Status_1_Register);
1019         if(status&Interrupt_A_St){
1020                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
1021         }
1022 #endif
1023 }
1024
1025 static void ack_b_interrupt(comedi_device *dev, unsigned short b_status)
1026 {
1027         unsigned short ack = 0;
1028         if(b_status & AO_BC_TC_St)
1029         {
1030                 ack |= AO_BC_TC_Interrupt_Ack;
1031         }
1032         if(b_status & AO_Overrun_St)
1033         {
1034                 ack |= AO_Error_Interrupt_Ack;
1035         }
1036         if(b_status & AO_START_St)
1037         {
1038                 ack |= AO_START_Interrupt_Ack;
1039         }
1040         if(b_status & AO_START1_St)
1041         {
1042                 ack |= AO_START1_Interrupt_Ack;
1043         }
1044         if(b_status & AO_UC_TC_St)
1045         {
1046                 ack |= AO_UC_TC_Interrupt_Ack;
1047         }
1048         if(b_status & AO_UI2_TC_St)
1049         {
1050                 ack |= AO_UI2_TC_Interrupt_Ack;
1051         }
1052         if(b_status & AO_UPDATE_St)
1053         {
1054                 ack |= AO_UPDATE_Interrupt_Ack;
1055         }
1056         if(ack) devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1057 }
1058
1059 static void handle_b_interrupt(comedi_device *dev, unsigned short b_status,
1060         unsigned ao_mite_status)
1061 {
1062         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1063         //unsigned short ack=0;
1064 #ifdef DEBUG_INTERRUPT
1065         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1066                 b_status,ao_mite_status);
1067         ni_mio_print_status_b(b_status);
1068 #endif
1069
1070 #ifdef PCIDMA
1071         /* Currently, mite.c requires us to handle LINKC */
1072         if(ao_mite_status & CHSR_LINKC){
1073                 mite_handle_b_linkc(devpriv->mite, dev);
1074         }
1075
1076         if(ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
1077                 rt_printk("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", ao_mite_status);
1078                 //mite_print_chsr(ao_mite_status);
1079                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1080         }
1081 #endif
1082
1083         if(b_status == 0xffff)return;
1084         if(b_status & AO_Overrun_St){
1085                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
1086                 s->async->events |= COMEDI_CB_OVERFLOW;
1087         }
1088
1089         if(b_status & AO_BC_TC_St){
1090                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
1091                 s->async->events |= COMEDI_CB_EOA;
1092         }
1093
1094 #ifndef PCIDMA
1095         if(b_status & AO_FIFO_Request_St){
1096                 int ret;
1097
1098                 ret = ni_ao_fifo_half_empty(dev, s);
1099                 if(!ret){
1100                         rt_printk("ni_mio_common: AO buffer underrun\n");
1101                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1102                                 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
1103                         s->async->events |= COMEDI_CB_OVERFLOW;
1104                 }
1105         }
1106 #endif
1107
1108         ni_event(dev, s);
1109 }
1110
1111 #ifdef DEBUG_STATUS_A
1112 static const char * const status_a_strings[]={
1113         "passthru0","fifo","G0_gate","G0_TC",
1114         "stop","start","sc_tc","start1",
1115         "start2","sc_tc_error","overflow","overrun",
1116         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
1117 };
1118
1119 static void ni_mio_print_status_a(int status)
1120 {
1121         int i;
1122
1123         rt_printk("A status:");
1124         for(i=15;i>=0;i--){
1125                 if(status&(1<<i)){
1126                         rt_printk(" %s",status_a_strings[i]);
1127                 }
1128         }
1129         rt_printk("\n");
1130 }
1131 #endif
1132
1133 #ifdef DEBUG_STATUS_B
1134 static const char * const status_b_strings[]={
1135         "passthru1","fifo","G1_gate","G1_TC",
1136         "UI2_TC","UPDATE","UC_TC","BC_TC",
1137         "start1","overrun","start","bc_tc_error",
1138         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
1139 };
1140
1141 static void ni_mio_print_status_b(int status)
1142 {
1143         int i;
1144
1145         rt_printk("B status:");
1146         for(i=15;i>=0;i--){
1147                 if(status&(1<<i)){
1148                         rt_printk(" %s",status_b_strings[i]);
1149                 }
1150         }
1151         rt_printk("\n");
1152 }
1153 #endif
1154
1155 #ifndef PCIDMA
1156
1157 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
1158 {
1159         comedi_async *async = s->async;
1160         comedi_cmd *cmd = &async->cmd;
1161         int chan;
1162         int i;
1163         sampl_t d;
1164         u32 packed_data;
1165         int range;
1166         int err = 1;
1167
1168         chan = async->cur_chan;
1169         for(i=0;i<n;i++){
1170                 err &= comedi_buf_get(async, &d);
1171                 if(err == 0) break;
1172
1173                 range = CR_RANGE(cmd->chanlist[chan]);
1174
1175                 if(boardtype.reg_type & ni_reg_6xxx_mask)
1176                 {
1177                         packed_data = d & 0xffff;
1178                         /* 6711 only has 16 bit wide ao fifo */
1179                         if(boardtype.reg_type != ni_reg_6711)
1180                         {
1181                                 err &= comedi_buf_get(async, &d);
1182                                 if(err == 0) break;
1183                                 chan++;
1184                                 i++;
1185                                 packed_data |= ( d << 16 ) & 0xffff0000;
1186                         }
1187                         ni_writel( packed_data, DAC_FIFO_Data_611x );
1188                 }else{
1189                         ni_writew(d, DAC_FIFO_Data);
1190                 }
1191                 chan++;
1192                 chan %= cmd->chanlist_len;
1193         }
1194         async->cur_chan = chan;
1195         if(err==0){
1196                 async->events |= COMEDI_CB_OVERFLOW;
1197         }
1198 }
1199
1200 /*
1201  *  There's a small problem if the FIFO gets really low and we
1202  *  don't have the data to fill it.  Basically, if after we fill
1203  *  the FIFO with all the data available, the FIFO is _still_
1204  *  less than half full, we never clear the interrupt.  If the
1205  *  IRQ is in edge mode, we never get another interrupt, because
1206  *  this one wasn't cleared.  If in level mode, we get flooded
1207  *  with interrupts that we can't fulfill, because nothing ever
1208  *  gets put into the buffer.
1209  *
1210  *  This kind of situation is recoverable, but it is easier to
1211  *  just pretend we had a FIFO underrun, since there is a good
1212  *  chance it will happen anyway.  This is _not_ the case for
1213  *  RT code, as RT code might purposely be running close to the
1214  *  metal.  Needs to be fixed eventually.
1215  */
1216 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
1217 {
1218         int n;
1219
1220         n = comedi_buf_read_n_available(s->async);
1221         if(n==0){
1222                 s->async->events |= COMEDI_CB_OVERFLOW;
1223                 return 0;
1224         }
1225
1226         n /= sizeof(sampl_t);
1227         if(n > boardtype.ao_fifo_depth / 2)
1228                 n = boardtype.ao_fifo_depth / 2;
1229
1230         ni_ao_fifo_load(dev,s,n);
1231
1232         s->async->events |= COMEDI_CB_BLOCK;
1233
1234         return 1;
1235 }
1236
1237 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
1238 {
1239         int n;
1240
1241         /* reset fifo */
1242         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
1243         if(boardtype.reg_type & ni_reg_6xxx_mask)
1244                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1245
1246         /* load some data */
1247         n = comedi_buf_read_n_available(s->async);
1248         if(n==0)return 0;
1249
1250         n /= sizeof(sampl_t);
1251         if(n > boardtype.ao_fifo_depth)
1252                 n = boardtype.ao_fifo_depth;
1253
1254         ni_ao_fifo_load(dev,s,n);
1255
1256         return n;
1257 }
1258
1259 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
1260         int n)
1261 {
1262         comedi_async *async = s->async;
1263         int i;
1264
1265         if(boardtype.reg_type == ni_reg_611x){
1266                 sampl_t data[2];
1267                 u32 dl;
1268
1269                 for( i = 0; i < n / 2; i++ ){
1270                         dl=ni_readl(ADC_FIFO_Data_611x);
1271                         /* This may get the hi/lo data in the wrong order */
1272                         data[0] = (dl>>16) & 0xffff;
1273                         data[1] = dl & 0xffff;
1274                         cfc_write_array_to_buffer(s, data, sizeof(data));
1275                 }
1276                 /* Check if there's a single sample stuck in the FIFO */
1277                 if( n % 2){
1278                         dl=ni_readl(ADC_FIFO_Data_611x);
1279                         data[0] = dl & 0xffff;
1280                         cfc_write_to_buffer(s, data[0]);
1281                 }
1282         } else if(boardtype.reg_type == ni_reg_6143){
1283                 sampl_t data[2];
1284                 u32     dl;
1285
1286                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1287                 for(i = 0; i < n / 2; i++){
1288                         dl = ni_readl(AIFIFO_Data_6143);
1289
1290                         data[0] = (dl >> 16) & 0xffff;
1291                         data[1] = dl & 0xffff;
1292                         cfc_write_array_to_buffer(s, data, sizeof(data));
1293                 }
1294                 if(n % 2){
1295                         /* Assume there is a single sample stuck in the FIFO */
1296                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1297                         dl = ni_readl(AIFIFO_Data_6143);
1298                         data[0] = (dl >> 16) & 0xffff;
1299                         cfc_write_to_buffer(s, data[0]);
1300                 }
1301         } else{
1302                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1303                 {
1304                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1305                         async->events |= COMEDI_CB_ERROR;
1306                         return;
1307                 }
1308                 for(i = 0; i < n; i++){
1309                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1310                 }
1311                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1312                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1313         }
1314 }
1315
1316 static void ni_handle_fifo_half_full(comedi_device *dev)
1317 {
1318         int n;
1319         comedi_subdevice *s=dev->subdevices + NI_AI_SUBDEV;
1320
1321         n=boardtype.ai_fifo_depth/2;
1322
1323         ni_ai_fifo_read(dev,s,n);
1324 }
1325 #endif
1326
1327 #ifdef PCIDMA
1328 static int ni_ai_drain_dma(comedi_device *dev )
1329 {
1330         int i;
1331         static const int timeout = 10000;
1332         unsigned long flags;
1333         int retval = 0;
1334
1335         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1336         if(devpriv->ai_mite_chan)
1337         {
1338                 for(i = 0; i < timeout; i++)
1339                 {
1340                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1341                                 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
1342                                 break;
1343                         comedi_udelay(5);
1344                 }
1345                 if(i == timeout)
1346                 {
1347                         rt_printk("ni_mio_common: wait for dma drain timed out\n");
1348                         rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1349                                 mite_bytes_in_transit(devpriv->ai_mite_chan), devpriv->stc_readw(dev, AI_Status_1_Register));
1350                         retval = -1;
1351                 }
1352         }
1353         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1354
1355         ni_sync_ai_dma(dev);
1356
1357         return retval;
1358 }
1359 #endif
1360 /*
1361    Empties the AI fifo
1362 */
1363 static void ni_handle_fifo_dregs(comedi_device *dev)
1364 {
1365         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1366         sampl_t data[2];
1367         u32 dl;
1368         short fifo_empty;
1369         int i;
1370
1371         if(boardtype.reg_type == ni_reg_611x){
1372                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1373                         dl=ni_readl(ADC_FIFO_Data_611x);
1374
1375                         /* This may get the hi/lo data in the wrong order */
1376                         data[0] = (dl>>16);
1377                         data[1] = (dl&0xffff);
1378                         cfc_write_array_to_buffer(s, data, sizeof(data));
1379                 }
1380         }else if(boardtype.reg_type == ni_reg_6143){
1381                 i = 0;
1382                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1383                         dl = ni_readl(AIFIFO_Data_6143);
1384
1385                         /* This may get the hi/lo data in the wrong order */
1386                         data[0] = (dl >> 16);
1387                         data[1] = (dl & 0xffff);
1388                         cfc_write_array_to_buffer(s, data, sizeof(data));
1389                         i += 2;
1390                 }
1391                 // Check if stranded sample is present
1392                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1393                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1394                         dl = ni_readl(AIFIFO_Data_6143);
1395                         data[0] = (dl >> 16) & 0xffff;
1396                         cfc_write_to_buffer(s, data[0]);
1397                 }
1398
1399         }else{
1400                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1401                 while(fifo_empty == 0)
1402                 {
1403                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1404                         {
1405                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1406                                 if(fifo_empty) break;
1407                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1408                         }
1409                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1410                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1411                 }
1412         }
1413 }
1414
1415 static void get_last_sample_611x( comedi_device *dev )
1416 {
1417         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1418         sampl_t data;
1419         u32 dl;
1420
1421         if(boardtype.reg_type != ni_reg_611x) return;
1422
1423         /* Check if there's a single sample stuck in the FIFO */
1424         if(ni_readb(XXX_Status)&0x80){
1425                 dl=ni_readl(ADC_FIFO_Data_611x);
1426                 data = (dl&0xffff);
1427                 cfc_write_to_buffer(s, data);
1428         }
1429 }
1430
1431 static void get_last_sample_6143(comedi_device* dev)
1432 {
1433         comedi_subdevice*       s = dev->subdevices + NI_AI_SUBDEV;
1434         sampl_t                 data;
1435         u32                     dl;
1436
1437         if(boardtype.reg_type != ni_reg_6143) return;
1438
1439         /* Check if there's a single sample stuck in the FIFO */
1440         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1441                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1442                 dl = ni_readl(AIFIFO_Data_6143);
1443
1444                 /* This may get the hi/lo data in the wrong order */
1445                 data = (dl >> 16) & 0xffff;
1446                 cfc_write_to_buffer(s, data);
1447         }
1448 }
1449
1450 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1451         void *data, unsigned int num_bytes, unsigned int chan_index )
1452 {
1453         comedi_async *async = s->async;
1454         unsigned int i;
1455         unsigned int length = num_bytes / bytes_per_sample(s);
1456         sampl_t *array = data;
1457         lsampl_t *larray = data;
1458         for(i = 0; i < length; i++)
1459         {
1460 #ifdef PCIDMA
1461                 if(s->subdev_flags & SDF_LSAMPL)
1462                         larray[i] = le32_to_cpu(larray[i]);
1463                 else
1464                         array[i] = le16_to_cpu(array[i]);
1465 #endif
1466                 if(s->subdev_flags & SDF_LSAMPL)
1467                         larray[i] += devpriv->ai_offset[chan_index];
1468                 else
1469                         array[i] += devpriv->ai_offset[chan_index];
1470                 chan_index++;
1471                 chan_index %= async->cmd.chanlist_len;
1472         }
1473 }
1474
1475 #ifdef PCIDMA
1476
1477 static int ni_ai_setup_MITE_dma(comedi_device *dev)
1478 {
1479         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1480         int retval;
1481
1482         retval = ni_request_ai_mite_channel(dev);
1483         if(retval) return retval;
1484 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1485
1486         /* write alloc the entire buffer */
1487         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1488
1489         switch(boardtype.reg_type)
1490         {
1491         case ni_reg_611x:
1492         case ni_reg_6143:
1493                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1494                 break;
1495         case ni_reg_628x:
1496                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1497                 break;
1498         default:
1499                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1500                 break;
1501         };
1502         /*start the MITE*/
1503         mite_dma_arm(devpriv->ai_mite_chan);
1504         return 0;
1505 }
1506
1507 static int ni_ao_setup_MITE_dma(comedi_device *dev)
1508 {
1509         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1510         int retval;
1511         unsigned long flags;
1512
1513         retval = ni_request_ao_mite_channel(dev);
1514         if(retval) return retval;
1515
1516         /* read alloc the entire buffer */
1517         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1518
1519         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1520         if(devpriv->ao_mite_chan)
1521         {
1522                 if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1523                 {
1524                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1525                 }else
1526                 {
1527                         /* doing 32 instead of 16 bit wide transfers from memory
1528                         makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1529                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1530                 }
1531                 mite_dma_arm(devpriv->ao_mite_chan);
1532         }else
1533                 retval = -EIO;
1534         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1535
1536         return retval;
1537 }
1538
1539 #endif // PCIDMA
1540
1541 /*
1542    used for both cancel ioctl and board initialization
1543
1544    this is pretty harsh for a cancel, but it works...
1545  */
1546
1547 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1548 {
1549         ni_release_ai_mite_channel(dev);
1550         /* ai configuration */
1551         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1552
1553         ni_set_bits(dev, Interrupt_A_Enable_Register,
1554                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1555                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1556                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1557                 AI_FIFO_Interrupt_Enable,0);
1558
1559         ni_clear_ai_fifo(dev);
1560
1561         if(boardtype.reg_type != ni_reg_6143)
1562                 ni_writeb(0, Misc_Command);
1563
1564         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1565         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1566                 AI_Mode_1_Register);
1567         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1568         /* generate FIFO interrupts on non-empty */
1569         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1570         if(boardtype.reg_type == ni_reg_611x){
1571                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1572                         AI_SOC_Polarity |
1573                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1574                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1575                         AI_EXTMUX_CLK_Output_Select(0) |
1576                         AI_LOCALMUX_CLK_Output_Select(2) |
1577                         AI_SC_TC_Output_Select(3) |
1578                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High), AI_Output_Control_Register);
1579         }else if(boardtype.reg_type == ni_reg_6143){
1580                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1581                         AI_SOC_Polarity |
1582                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1583                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1584                         AI_EXTMUX_CLK_Output_Select(0) |
1585                         AI_LOCALMUX_CLK_Output_Select(2) |
1586                         AI_SC_TC_Output_Select(3) |
1587                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),AI_Output_Control_Register);
1588         }else{
1589                 unsigned ai_output_control_bits;
1590                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1591                         AI_SOC_Polarity |
1592                         AI_CONVERT_Pulse_Width |
1593                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1594                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1595                         AI_EXTMUX_CLK_Output_Select(0) |
1596                         AI_LOCALMUX_CLK_Output_Select(2) |
1597                         AI_SC_TC_Output_Select(3);
1598                 if(boardtype.reg_type == ni_reg_622x)
1599                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High);
1600                 else
1601                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low);
1602                 devpriv->stc_writew(dev, ai_output_control_bits, AI_Output_Control_Register);
1603         }
1604         /* the following registers should not be changed, because there
1605          * are no backup registers in devpriv.  If you want to change
1606          * any of these, add a backup register and other appropriate code:
1607          *      AI_Mode_1_Register
1608          *      AI_Mode_3_Register
1609          *      AI_Personal_Register
1610          *      AI_Output_Control_Register
1611         */
1612         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1613                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1614                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1615                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1616
1617         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1618
1619         return 0;
1620 }
1621
1622 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1623 {
1624         unsigned long flags = 0;
1625         int count;
1626
1627         // lock to avoid race with interrupt handler
1628         if(in_interrupt() == 0)
1629                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1630 #ifndef PCIDMA
1631         ni_handle_fifo_dregs(dev);
1632 #else
1633         ni_sync_ai_dma(dev);
1634 #endif
1635         count = s->async->buf_write_count - s->async->buf_read_count;
1636         if(in_interrupt() == 0)
1637                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1638
1639         return count;
1640 }
1641
1642
1643 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1644 {
1645         int i,n;
1646         const unsigned int mask = (1 << boardtype.adbits) - 1;
1647         unsigned signbits;
1648         unsigned short d;
1649         unsigned long dl;
1650
1651         ni_load_channelgain_list(dev,1,&insn->chanspec);
1652
1653         ni_clear_ai_fifo(dev);
1654
1655         signbits=devpriv->ai_offset[0];
1656         if(boardtype.reg_type == ni_reg_611x){
1657                 for(n=0; n < num_adc_stages_611x; n++){
1658                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1659                         comedi_udelay(1);
1660                 }
1661                 for(n=0; n<insn->n; n++){
1662                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1663                         /* The 611x has screwy 32-bit FIFOs. */
1664                         d = 0;
1665                         for(i=0; i<NI_TIMEOUT; i++){
1666                                 if(ni_readb(XXX_Status)&0x80)
1667                                 {
1668                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1669                                         break;
1670                                 }
1671                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1672                                 {
1673                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1674                                         break;
1675                                 }
1676                         }
1677                         if(i==NI_TIMEOUT){
1678                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1679                                 return -ETIME;
1680                         }
1681                         d += signbits;
1682                         data[ n ] = d;
1683                 }
1684         }else if(boardtype.reg_type == ni_reg_6143){
1685                 for(n = 0; n < insn->n; n++){
1686                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1687
1688                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1689                         dl = 0;
1690                         for(i = 0; i < NI_TIMEOUT; i++){
1691                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1692                                 {
1693                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1694                                         dl = ni_readl(AIFIFO_Data_6143);
1695                                         break;
1696                                 }
1697                         }
1698                         if(i == NI_TIMEOUT){
1699                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1700                                 return -ETIME;
1701                         }
1702                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1703                 }
1704         }else{
1705                 for(n = 0; n < insn->n; n++){
1706                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1707                         for(i = 0; i < NI_TIMEOUT; i++){
1708                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1709                                         break;
1710                         }
1711                         if(i == NI_TIMEOUT){
1712                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1713                                 return -ETIME;
1714                         }
1715                         if(boardtype.reg_type & ni_reg_m_series_mask)
1716                         {
1717                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1718                         }else
1719                         {
1720                                 d = ni_readw(ADC_FIFO_Data_Register);
1721                                 d += signbits; /* subtle: needs to be short addition */
1722                                 data[n] = d;
1723                         }
1724                 }
1725         }
1726         return insn->n;
1727 }
1728
1729 void ni_prime_channelgain_list(comedi_device *dev)
1730 {
1731         int i;
1732         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1733         for(i = 0; i < NI_TIMEOUT; ++i)
1734         {
1735                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1736                 {
1737                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1738                         return;
1739                 }
1740                 comedi_udelay(1);
1741         }
1742         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1743 }
1744
1745 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1746         unsigned int *list)
1747 {
1748         unsigned int chan, range, aref;
1749         unsigned int i;
1750         unsigned offset;
1751         unsigned int dither;
1752         unsigned range_code;
1753
1754         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1755
1756 //      offset = 1 << (boardtype.adbits - 1);
1757         if((list[0] & CR_ALT_SOURCE))
1758         {
1759                 unsigned bypass_bits;
1760                 chan = CR_CHAN(list[0]);
1761                 range = CR_RANGE(list[0]);
1762                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1763                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1764                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1765                 bypass_bits |= chan;
1766                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1767                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1768                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1769                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1770                 if(dither)
1771                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1772                 // don't use 2's complement encoding
1773                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1774                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1775         }else
1776         {
1777                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1778         }
1779         offset = 0;
1780         for(i = 0; i < n_chan; i++)
1781         {
1782                 unsigned config_bits = 0;
1783                 chan = CR_CHAN(list[i]);
1784                 aref = CR_AREF(list[i]);
1785                 range = CR_RANGE(list[i]);
1786                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1787
1788                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1789                 devpriv->ai_offset[i] = offset;
1790                 switch( aref )
1791                 {
1792                         case AREF_DIFF:
1793                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1794                                 break;
1795                         case AREF_COMMON:
1796                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1797                                 break;
1798                         case AREF_GROUND:
1799                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1800                                 break;
1801                         case AREF_OTHER:
1802                                 break;
1803                 }
1804                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1805                 config_bits |= MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1806                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1807                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1808                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1809                 // don't use 2's complement encoding
1810                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1811                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1812         }
1813         ni_prime_channelgain_list(dev);
1814 }
1815
1816 /*
1817  * Notes on the 6110 and 6111:
1818  * These boards a slightly different than the rest of the series, since
1819  * they have multiple A/D converters.
1820  * From the driver side, the configuration memory is a
1821  * little different.
1822  * Configuration Memory Low:
1823  *   bits 15-9: same
1824  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1825  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1826  *       1001 gain=0.1 (+/- 50)
1827  *       1010 0.2
1828  *       1011 0.1
1829  *       0001 1
1830  *       0010 2
1831  *       0011 5
1832  *       0100 10
1833  *       0101 20
1834  *       0110 50
1835  * Configuration Memory High:
1836  *   bits 12-14: Channel Type
1837  *       001 for differential
1838  *       000 for calibration
1839  *   bit 11: coupling  (this is not currently handled)
1840  *       1 AC coupling
1841  *       0 DC coupling
1842  *   bits 0-2: channel
1843  *       valid channels are 0-3
1844  */
1845 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1846         unsigned int *list)
1847 {
1848         unsigned int chan,range,aref;
1849         unsigned int i;
1850         unsigned int hi,lo;
1851         unsigned offset;
1852         unsigned int dither;
1853
1854         if(boardtype.reg_type & ni_reg_m_series_mask)
1855         {
1856                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1857                 return;
1858         }
1859         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1860                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1861                         // ready to go.
1862                         return;
1863                 }
1864                 devpriv->changain_state=1;
1865                 devpriv->changain_spec=list[0];
1866         }else{
1867                 devpriv->changain_state=0;
1868         }
1869
1870         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1871
1872         // Set up Calibration mode if required
1873         if(boardtype.reg_type == ni_reg_6143){
1874                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1875                         // Strobe Relay enable bit
1876                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1877                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1878                         devpriv->ai_calib_source_enabled = 1;
1879                         msleep_interruptible(100);      // Allow relays to change
1880                 }
1881                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1882                         // Strobe Relay disable bit
1883                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1884                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1885                         devpriv->ai_calib_source_enabled = 0;
1886                         msleep_interruptible(100);      // Allow relays to change
1887                 }
1888         }
1889
1890         offset=1<<(boardtype.adbits-1);
1891         for(i=0;i<n_chan;i++){
1892                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1893                         chan=devpriv->ai_calib_source;
1894                 }else{
1895                         chan=CR_CHAN(list[i]);
1896                 }
1897                 aref=CR_AREF(list[i]);
1898                 range=CR_RANGE(list[i]);
1899                 dither=((list[i]&CR_ALT_FILTER)!=0);
1900
1901                 /* fix the external/internal range differences */
1902                 range = ni_gainlkup[boardtype.gainlkup][range];
1903                 if(boardtype.reg_type == ni_reg_611x)
1904                         devpriv->ai_offset[i] = offset;
1905                 else
1906                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1907
1908                 hi = 0;
1909                 if( ( list[i] & CR_ALT_SOURCE ) )
1910                 {
1911                         if(boardtype.reg_type == ni_reg_611x)
1912                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1913                 }else
1914                 {
1915                         if(boardtype.reg_type == ni_reg_611x)
1916                                 aref = AREF_DIFF;
1917                         else if(boardtype.reg_type == ni_reg_6143)
1918                                 aref = AREF_OTHER;
1919                         switch( aref )
1920                         {
1921                                 case AREF_DIFF:
1922                                         hi |= AI_DIFFERENTIAL;
1923                                         break;
1924                                 case AREF_COMMON:
1925                                         hi |= AI_COMMON;
1926                                         break;
1927                                 case AREF_GROUND:
1928                                         hi |= AI_GROUND;
1929                                         break;
1930                                 case AREF_OTHER:
1931                                         break;
1932                         }
1933                 }
1934                 hi |= AI_CONFIG_CHANNEL( chan );
1935
1936                 ni_writew(hi,Configuration_Memory_High);
1937
1938                 if(boardtype.reg_type != ni_reg_6143){
1939                         lo = range;
1940                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1941                         if( dither ) lo |= AI_DITHER;
1942
1943                         ni_writew(lo,Configuration_Memory_Low);
1944                 }
1945         }
1946
1947         /* prime the channel/gain list */
1948         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1949                 ni_prime_channelgain_list(dev);
1950         }
1951 }
1952
1953 static int ni_ns_to_timer(const comedi_device *dev, unsigned nanosec, int round_mode)
1954 {
1955         int divider;
1956         switch(round_mode)
1957         {
1958         case TRIG_ROUND_NEAREST:
1959         default:
1960                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1961                 break;
1962         case TRIG_ROUND_DOWN:
1963                 divider = (nanosec) / devpriv->clock_ns;
1964                 break;
1965         case TRIG_ROUND_UP:
1966                 divider=(nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1967                 break;
1968         }
1969         return divider - 1;
1970 }
1971
1972 static unsigned ni_timer_to_ns(const comedi_device *dev, int timer)
1973 {
1974         return devpriv->clock_ns * (timer + 1);
1975 }
1976
1977 static unsigned ni_min_ai_scan_period_ns(comedi_device *dev, unsigned num_channels)
1978 {
1979         switch(boardtype.reg_type)
1980         {
1981         case ni_reg_611x:
1982         case ni_reg_6143:
1983         // simultaneously-sampled inputs
1984                 return boardtype.ai_speed;
1985                 break;
1986         default:
1987         // multiplexed inputs
1988                 break;
1989         };
1990         return boardtype.ai_speed * num_channels;
1991 }
1992
1993 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1994 {
1995         int err=0;
1996         int tmp;
1997         int sources;
1998
1999         /* step 1: make sure trigger sources are trivially valid */
2000
2001         if((cmd->flags & CMDF_WRITE))
2002         {
2003                 cmd->flags &= ~CMDF_WRITE;
2004         }
2005
2006         tmp=cmd->start_src;
2007         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
2008         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2009
2010         tmp=cmd->scan_begin_src;
2011         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
2012         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2013
2014         tmp=cmd->convert_src;
2015         sources = TRIG_TIMER | TRIG_EXT;
2016         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
2017         cmd->convert_src &= sources;
2018         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2019
2020         tmp=cmd->scan_end_src;
2021         cmd->scan_end_src &= TRIG_COUNT;
2022         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2023
2024         tmp=cmd->stop_src;
2025         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2026         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2027
2028         if(err)return 1;
2029
2030         /* step 2: make sure trigger sources are unique and mutually compatible */
2031
2032         /* note that mutual compatiblity is not an issue here */
2033         if(cmd->start_src!=TRIG_NOW &&
2034            cmd->start_src!=TRIG_INT &&
2035            cmd->start_src!=TRIG_EXT)err++;
2036         if(cmd->scan_begin_src!=TRIG_TIMER &&
2037            cmd->scan_begin_src!=TRIG_EXT &&
2038            cmd->scan_begin_src!=TRIG_OTHER)err++;
2039         if(cmd->convert_src!=TRIG_TIMER &&
2040            cmd->convert_src!=TRIG_EXT &&
2041            cmd->convert_src!=TRIG_NOW)err++;
2042         if(cmd->stop_src!=TRIG_COUNT &&
2043            cmd->stop_src!=TRIG_NONE)err++;
2044
2045         if(err)return 2;
2046
2047         /* step 3: make sure arguments are trivially compatible */
2048
2049         if(cmd->start_src==TRIG_EXT){
2050                 /* external trigger */
2051                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2052
2053                 if(tmp > 16) tmp = 16;
2054                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2055                 if(cmd->start_arg != tmp){
2056                         cmd->start_arg = tmp;
2057                         err++;
2058                 }
2059         }else{
2060                 if(cmd->start_arg!=0){
2061                         /* true for both TRIG_NOW and TRIG_INT */
2062                         cmd->start_arg=0;
2063                         err++;
2064                 }
2065         }
2066         if(cmd->scan_begin_src==TRIG_TIMER){
2067                 if(cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, cmd->chanlist_len))
2068                 {
2069                         cmd->scan_begin_arg = ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
2070                         err++;
2071                 }
2072                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
2073                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2074                         err++;
2075                 }
2076         }else if(cmd->scan_begin_src==TRIG_EXT){
2077                 /* external trigger */
2078                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2079
2080                 if(tmp>16)tmp=16;
2081                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2082                 if(cmd->scan_begin_arg!=tmp){
2083                         cmd->scan_begin_arg = tmp;
2084                         err++;
2085                 }
2086         }else{ /* TRIG_OTHER */
2087                 if(cmd->scan_begin_arg){
2088                         cmd->scan_begin_arg=0;
2089                         err++;
2090                 }
2091         }
2092         if(cmd->convert_src==TRIG_TIMER){
2093                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
2094                         if(cmd->convert_arg != 0){
2095                                 cmd->convert_arg = 0;
2096                                 err++;
2097                         }
2098                 }else{
2099                         if(cmd->convert_arg<boardtype.ai_speed){
2100                                 cmd->convert_arg=boardtype.ai_speed;
2101                                 err++;
2102                         }
2103                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
2104                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
2105                                 err++;
2106                         }
2107                 }
2108         }else if(cmd->convert_src == TRIG_EXT){
2109                 /* external trigger */
2110                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2111
2112                 if(tmp>16)tmp=16;
2113                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
2114                 if(cmd->convert_arg!=tmp){
2115                         cmd->convert_arg = tmp;
2116                         err++;
2117                 }
2118         }else if(cmd->convert_src == TRIG_NOW){
2119                 if(cmd->convert_arg != 0){
2120                         cmd->convert_arg = 0;
2121                         err++;
2122                 }
2123         }
2124
2125         if(cmd->scan_end_arg!=cmd->chanlist_len){
2126                 cmd->scan_end_arg=cmd->chanlist_len;
2127                 err++;
2128         }
2129         if(cmd->stop_src==TRIG_COUNT){
2130                 unsigned int max_count = 0x01000000;
2131
2132                 if(boardtype.reg_type == ni_reg_611x )
2133                         max_count -= num_adc_stages_611x;
2134                 if(cmd->stop_arg > max_count){
2135                         cmd->stop_arg = max_count;
2136                         err++;
2137                 }
2138                 if(cmd->stop_arg < 1){
2139                         cmd->stop_arg = 1;
2140                         err++;
2141                 }
2142         }else{
2143                 /* TRIG_NONE */
2144                 if(cmd->stop_arg!=0){
2145                         cmd->stop_arg=0;
2146                         err++;
2147                 }
2148         }
2149
2150         if(err)return 3;
2151
2152         /* step 4: fix up any arguments */
2153
2154         if(cmd->scan_begin_src==TRIG_TIMER){
2155                 tmp=cmd->scan_begin_arg;
2156                 cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags & TRIG_ROUND_MASK));
2157                 if(tmp!=cmd->scan_begin_arg)err++;
2158         }
2159         if(cmd->convert_src==TRIG_TIMER){
2160                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
2161                         tmp=cmd->convert_arg;
2162                         cmd->convert_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->convert_arg, cmd->flags & TRIG_ROUND_MASK));
2163                         if(tmp!=cmd->convert_arg)err++;
2164                         if(cmd->scan_begin_src==TRIG_TIMER &&
2165                                 cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg)
2166                         {
2167                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
2168                                 err++;
2169                         }
2170                 }
2171         }
2172
2173         if(err)return 4;
2174
2175         return 0;
2176 }
2177
2178 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
2179 {
2180         const comedi_cmd *cmd=&s->async->cmd;
2181         int timer;
2182         int mode1=0; /* mode1 is needed for both stop and convert */
2183         int mode2=0;
2184         int start_stop_select=0;
2185         unsigned int stop_count;
2186         int interrupt_a_enable=0;
2187
2188         MDPRINTK("ni_ai_cmd\n");
2189         if(dev->irq == 0)
2190         {
2191                 comedi_error(dev, "cannot run command without an irq");
2192                 return -EIO;
2193         }
2194         ni_clear_ai_fifo(dev);
2195
2196         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
2197
2198         /* start configuration */
2199         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
2200
2201         /* disable analog triggering for now, since it
2202          * interferes with the use of pfi0 */
2203         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2204         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
2205
2206         switch(cmd->start_src){
2207                 case TRIG_INT:
2208                 case TRIG_NOW:
2209                         devpriv->stc_writew(dev, AI_START2_Select(0)|
2210                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
2211                                 AI_Trigger_Select_Register);
2212                         break;
2213                 case TRIG_EXT:
2214                 {
2215                         int chan = CR_CHAN(cmd->start_arg);
2216                         unsigned int bits = AI_START2_Select(0)|
2217                                 AI_START1_Sync |
2218                                 AI_START1_Select(chan + 1);
2219
2220                         if(cmd->start_arg & CR_INVERT)
2221                                 bits |= AI_START1_Polarity;
2222                         if(cmd->start_arg & CR_EDGE)
2223                                 bits |= AI_START1_Edge;
2224                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
2225                         break;
2226                 }
2227         }
2228
2229         mode2 &= ~AI_Pre_Trigger;
2230         mode2 &= ~AI_SC_Initial_Load_Source;
2231         mode2 &= ~AI_SC_Reload_Mode;
2232         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2233
2234         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
2235                 start_stop_select |= AI_STOP_Polarity;
2236                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
2237                 start_stop_select |= AI_STOP_Sync;
2238         }else
2239         {
2240                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
2241         }
2242         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2243
2244         devpriv->ai_cmd2 = 0;
2245         switch(cmd->stop_src){
2246         case TRIG_COUNT:
2247                 stop_count = cmd->stop_arg - 1;
2248
2249                 if(boardtype.reg_type == ni_reg_611x){
2250                         // have to take 3 stage adc pipeline into account
2251                         stop_count += num_adc_stages_611x;
2252                 }
2253                 /* stage number of scans */
2254                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
2255
2256                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2257                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2258                 /* load SC (Scan Count) */
2259                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2260
2261                 devpriv->ai_continuous = 0;
2262                 if( stop_count == 0 ){
2263                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2264                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2265                         // this is required to get the last sample for chanlist_len > 1, not sure why
2266                         if(cmd->chanlist_len > 1)
2267                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
2268                 }
2269                 break;
2270         case TRIG_NONE:
2271                 /* stage number of scans */
2272                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
2273
2274                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2275                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2276
2277                 /* load SC (Scan Count) */
2278                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2279
2280                 devpriv->ai_continuous = 1;
2281
2282                 break;
2283         }
2284
2285         switch(cmd->scan_begin_src){
2286         case TRIG_TIMER:
2287                 /*
2288                         stop bits for non 611x boards
2289                         AI_SI_Special_Trigger_Delay=0
2290                         AI_Pre_Trigger=0
2291                         AI_START_STOP_Select_Register:
2292                         AI_START_Polarity=0 (?) rising edge
2293                         AI_START_Edge=1         edge triggered
2294                         AI_START_Sync=1 (?)
2295                         AI_START_Select=0               SI_TC
2296                         AI_STOP_Polarity=0              rising edge
2297                         AI_STOP_Edge=0          level
2298                         AI_STOP_Sync=1
2299                         AI_STOP_Select=19               external pin (configuration mem)
2300                  */
2301                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2302                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2303
2304                 mode2 |= AI_SI_Reload_Mode(0);
2305                 /* AI_SI_Initial_Load_Source=A */
2306                 mode2 &= ~AI_SI_Initial_Load_Source;
2307                 //mode2 |= AI_SC_Reload_Mode;
2308                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2309
2310                 /* load SI */
2311                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2312                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
2313                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
2314                 break;
2315         case TRIG_EXT:
2316                 if( cmd->scan_begin_arg & CR_EDGE )
2317                         start_stop_select |= AI_START_Edge;
2318                 /* AI_START_Polarity==1 is falling edge */
2319                 if( cmd->scan_begin_arg & CR_INVERT )
2320                         start_stop_select |= AI_START_Polarity;
2321                 if( cmd->scan_begin_src != cmd->convert_src ||
2322                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
2323                         start_stop_select |= AI_START_Sync;
2324                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2325                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2326                 break;
2327         }
2328
2329         switch(cmd->convert_src){
2330         case TRIG_TIMER:
2331         case TRIG_NOW:
2332                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
2333                         timer = 1;
2334                 else
2335                         timer = ni_ns_to_timer(dev, cmd->convert_arg, TRIG_ROUND_NEAREST);
2336                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
2337                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
2338
2339                 /* AI_SI2_Reload_Mode = alternate */
2340                 /* AI_SI2_Initial_Load_Source = A */
2341                 mode2 &= ~AI_SI2_Initial_Load_Source;
2342                 mode2 |= AI_SI2_Reload_Mode;
2343                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2344
2345                 /* AI_SI2_Load */
2346                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2347
2348                 mode2 |= AI_SI2_Reload_Mode; // alternate
2349                 mode2 |= AI_SI2_Initial_Load_Source; // B
2350
2351                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2352                 break;
2353         case TRIG_EXT:
2354                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2355                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2356                         mode1 |= AI_CONVERT_Source_Polarity;
2357                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2358
2359                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2360                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2361
2362                 break;
2363         }
2364
2365         if(dev->irq){
2366
2367                 /* interrupt on FIFO, errors, SC_TC */
2368                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2369                         AI_SC_TC_Interrupt_Enable;
2370
2371 #ifndef PCIDMA
2372                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2373 #endif
2374
2375                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2376                         /* wake on end-of-scan */
2377                         devpriv->aimode=AIMODE_SCAN;
2378                 }else{
2379                         devpriv->aimode=AIMODE_HALF_FULL;
2380                 }
2381
2382                 switch(devpriv->aimode){
2383                 case AIMODE_HALF_FULL:
2384                         /*generate FIFO interrupts and DMA requests on half-full */
2385 #ifdef PCIDMA
2386                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2387 #else
2388                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2389 #endif
2390                         break;
2391                 case AIMODE_SAMPLE:
2392                         /*generate FIFO interrupts on non-empty */
2393                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2394                         break;
2395                 case AIMODE_SCAN:
2396 #ifdef PCIDMA
2397                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2398 #else
2399                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2400 #endif
2401                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2402                         break;
2403                 default:
2404                         break;
2405                 }
2406
2407                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack |
2408                         AI_STOP_Interrupt_Ack |
2409                         AI_START_Interrupt_Ack |
2410                         AI_START2_Interrupt_Ack |
2411                         AI_START1_Interrupt_Ack |
2412                         AI_SC_TC_Interrupt_Ack |
2413                         AI_SC_TC_Error_Confirm,
2414                         Interrupt_A_Ack_Register); /* clear interrupts */
2415
2416                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2417
2418                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2419         }else{
2420                 /* interrupt on nothing */
2421                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2422
2423                 /* XXX start polling if necessary */
2424                 MDPRINTK("interrupting on nothing\n");
2425         }
2426
2427         /* end configuration */
2428         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2429
2430         switch(cmd->scan_begin_src){
2431         case TRIG_TIMER:
2432                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2433                         AI_Command_1_Register);
2434                 break;
2435         case TRIG_EXT:
2436                 /* XXX AI_SI_Arm? */
2437                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2438                         AI_Command_1_Register);
2439                 break;
2440         }
2441
2442 #ifdef PCIDMA
2443         {
2444                 int retval = ni_ai_setup_MITE_dma(dev);
2445                 if(retval) return retval;
2446         }
2447         //mite_dump_regs(devpriv->mite);
2448 #endif
2449
2450         switch(cmd->start_src){
2451         case TRIG_NOW:
2452                 /* AI_START1_Pulse */
2453                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2454                 s->async->inttrig=NULL;
2455                 break;
2456         case TRIG_EXT:
2457                 s->async->inttrig=NULL;
2458                 break;
2459         case TRIG_INT:
2460                 s->async->inttrig = &ni_ai_inttrig;
2461                 break;
2462         }
2463
2464         MDPRINTK("exit ni_ai_cmd\n");
2465
2466         return 0;
2467 }
2468
2469 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2470         unsigned int trignum)
2471 {
2472         if(trignum!=0)return -EINVAL;
2473
2474         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2475         s->async->inttrig=NULL;
2476
2477         return 1;
2478 }
2479
2480 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2481         comedi_insn *insn, lsampl_t *data);
2482
2483 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2484         comedi_insn *insn, lsampl_t *data)
2485 {
2486         if(insn->n<1)return -EINVAL;
2487
2488         switch(data[0]){
2489         case INSN_CONFIG_ANALOG_TRIG:
2490                 return ni_ai_config_analog_trig(dev,s,insn,data);
2491         case INSN_CONFIG_ALT_SOURCE:
2492                 if(boardtype.reg_type & ni_reg_m_series_mask)
2493                 {
2494                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2495                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2496                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2497                         {
2498                                 return -EINVAL;
2499                         }
2500                         devpriv->ai_calib_source = data[1];
2501                 } else if(boardtype.reg_type == ni_reg_6143)
2502                 {
2503                         unsigned int calib_source;
2504
2505                         calib_source = data[1] & 0xf;
2506
2507
2508                         if(calib_source > 0xF)
2509                                 return -EINVAL;
2510
2511                         devpriv->ai_calib_source = calib_source;
2512                         ni_writew(calib_source, Calibration_Channel_6143);
2513                 }else
2514                 {
2515                         unsigned int calib_source;
2516                         unsigned int calib_source_adjust;
2517
2518                         calib_source = data[1] & 0xf;
2519                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2520
2521                         if(calib_source >= 8)
2522                                 return -EINVAL;
2523                         devpriv->ai_calib_source = calib_source;
2524                         if(boardtype.reg_type == ni_reg_611x){
2525                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2526                         }
2527                 }
2528                 return 2;
2529         default:
2530                 break;
2531         }
2532
2533         return -EINVAL;
2534 }
2535
2536 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2537         comedi_insn *insn, lsampl_t *data)
2538 {
2539         unsigned int a,b,modebits;
2540         int err=0;
2541
2542         /* data[1] is flags
2543          * data[2] is analog line
2544          * data[3] is set level
2545          * data[4] is reset level */
2546         if(!boardtype.has_analog_trig)return -EINVAL;
2547         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2548                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2549                 err++;
2550         }
2551         if(data[2]>=boardtype.n_adchan){
2552                 data[2]=boardtype.n_adchan-1;
2553                 err++;
2554         }
2555         if(data[3]>255){ /* a */
2556                 data[3]=255;
2557                 err++;
2558         }
2559         if(data[4]>255){ /* b */
2560                 data[4]=255;
2561                 err++;
2562         }
2563         /*
2564          * 00 ignore
2565          * 01 set
2566          * 10 reset
2567          *
2568          * modes:
2569          *   1 level:                    +b-   +a-
2570          *     high mode                00 00 01 10
2571          *     low mode                 00 00 10 01
2572          *   2 level: (a<b)
2573          *     hysteresis low mode      10 00 00 01
2574          *     hysteresis high mode     01 00 00 10
2575          *     middle mode              10 01 01 10
2576          */
2577
2578         a=data[3];
2579         b=data[4];
2580         modebits=data[1]&0xff;
2581         if(modebits&0xf0){
2582                 /* two level mode */
2583                 if(b<a){
2584                         /* swap order */
2585                         a=data[4];
2586                         b=data[3];
2587                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2588                 }
2589                 devpriv->atrig_low = a;
2590                 devpriv->atrig_high = b;
2591                 switch(modebits){
2592                 case 0x81:      /* low hysteresis mode */
2593                         devpriv->atrig_mode = 6;
2594                         break;
2595                 case 0x42:      /* high hysteresis mode */
2596                         devpriv->atrig_mode = 3;
2597                         break;
2598                 case 0x96:      /* middle window mode */
2599                         devpriv->atrig_mode = 2;
2600                         break;
2601                 default:
2602                         data[1]&=~0xff;
2603                         err++;
2604                 }
2605         }else{
2606                 /* one level mode */
2607                 if(b!=0){
2608                         data[4]=0;
2609                         err++;
2610                 }
2611                 switch(modebits){
2612                 case 0x06:      /* high window mode */
2613                         devpriv->atrig_high = a;
2614                         devpriv->atrig_mode = 0;
2615                         break;
2616                 case 0x09:      /* low window mode */
2617                         devpriv->atrig_low = a;
2618                         devpriv->atrig_mode = 1;
2619                         break;
2620                 default:
2621                         data[1]&=~0xff;
2622                         err++;
2623                 }
2624         }
2625         if(err)return -EAGAIN;
2626         return 5;
2627 }
2628
2629 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2630 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2631         void *data, unsigned int num_bytes, unsigned int chan_index )
2632 {
2633         comedi_async *async = s->async;
2634         unsigned int range;
2635         unsigned int i;
2636         unsigned int offset;
2637         unsigned int length = num_bytes / sizeof( sampl_t );
2638         sampl_t *array = data;
2639
2640         offset = 1 << (boardtype.aobits - 1);
2641         for(i = 0; i < length; i++)
2642         {
2643                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2644                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2645                         array[i] -= offset;
2646 #ifdef PCIDMA
2647                 array[i] = cpu_to_le16( array[i] );
2648 #endif
2649                 chan_index++;
2650                 chan_index %= async->cmd.chanlist_len;
2651         }
2652 }
2653
2654 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2655         unsigned int chanspec[], unsigned int n_chans, int timed)
2656 {
2657         unsigned int range;
2658         unsigned int chan;
2659         unsigned int conf;
2660         int i;
2661         int invert = 0;
2662
2663         for(i = 0; i < boardtype.n_aochan; ++i)
2664         {
2665                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2666         }
2667         for(i=0;i<n_chans;i++)
2668         {
2669                 const comedi_krange *krange;
2670                 chan = CR_CHAN(chanspec[i]);
2671                 range = CR_RANGE(chanspec[i]);
2672                 krange = s->range_table->range + range;
2673                 invert = 0;
2674                 conf = 0;
2675                 switch(krange->max - krange->min)
2676                 {
2677                 case 20000000:
2678                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2679                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2680                         break;
2681                 case 10000000:
2682                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2683                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2684                         break;
2685                 case 4000000:
2686                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2687                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2688                         break;
2689                 case 2000000:
2690                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2691                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2692                         break;
2693                 default:
2694                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2695                         break;
2696                 }
2697                 switch(krange->max + krange->min)
2698                 {
2699                 case 0:
2700                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2701                         break;
2702                 case 10000000:
2703                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2704                         break;
2705                 default:
2706                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2707                         break;
2708                 }
2709                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2710                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2711                 devpriv->ao_conf[chan] = conf;
2712                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2713         }
2714         return invert;
2715 }
2716
2717 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2718         unsigned int chanspec[], unsigned int n_chans)
2719 {
2720         unsigned int range;
2721         unsigned int chan;
2722         unsigned int conf;
2723         int i;
2724         int invert = 0;
2725
2726         for(i=0;i<n_chans;i++)
2727         {
2728                 chan = CR_CHAN(chanspec[i]);
2729                 range = CR_RANGE(chanspec[i]);
2730                 conf = AO_Channel(chan);
2731
2732                 if(boardtype.ao_unipolar){
2733                         if((range&1) == 0){
2734                                 conf |= AO_Bipolar;
2735                                 invert = (1<<(boardtype.aobits-1));
2736                         }else{
2737                                 invert = 0;
2738                         }
2739                         if(range&2)
2740                                 conf |= AO_Ext_Ref;
2741                 }else{
2742                         conf |= AO_Bipolar;
2743                         invert = (1<<(boardtype.aobits-1));
2744                 }
2745
2746                 /* not all boards can deglitch, but this shouldn't hurt */
2747                 if(chanspec[i] & CR_DEGLITCH)
2748                         conf |= AO_Deglitch;
2749
2750                 /* analog reference */
2751                 /* AREF_OTHER connects AO ground to AI ground, i think */
2752                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2753
2754                 ni_writew(conf,AO_Configuration);
2755                 devpriv->ao_conf[chan] = conf;
2756         }
2757         return invert;
2758 }
2759
2760 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2761         unsigned int chanspec[], unsigned int n_chans, int timed)
2762 {
2763         if(boardtype.reg_type & ni_reg_m_series_mask)
2764                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2765         else
2766                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2767 }
2768 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2769         comedi_insn *insn,lsampl_t *data)
2770 {
2771         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2772
2773         return 1;
2774 }
2775
2776 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2777         comedi_insn *insn,lsampl_t *data)
2778 {
2779         unsigned int chan = CR_CHAN(insn->chanspec);
2780         unsigned int invert;
2781
2782         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2783
2784         devpriv->ao[chan] = data[0];
2785
2786         if(boardtype.reg_type & ni_reg_m_series_mask)
2787         {
2788                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2789         }
2790         else
2791                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2792
2793         return 1;
2794 }
2795
2796 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2797         comedi_insn *insn,lsampl_t *data)
2798 {
2799         unsigned int chan = CR_CHAN(insn->chanspec);
2800         unsigned int invert;
2801
2802         ao_win_out(1 << chan, AO_Immediate_671x);
2803         invert = 1 << (boardtype.aobits - 1);
2804
2805         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2806
2807         devpriv->ao[chan] = data[0];
2808         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2809
2810         return 1;
2811 }
2812
2813 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2814         unsigned int trignum)
2815 {
2816         int ret;
2817         int interrupt_b_bits;
2818         int i;
2819         static const int timeout = 1000;
2820
2821         if(trignum!=0) return -EINVAL;
2822
2823         /* Null trig at beginning prevent ao start trigger from executing more than
2824         once per command (and doing things like trying to allocate the ao dma channel
2825         multiple times) */
2826         s->async->inttrig = NULL;
2827
2828         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2829         interrupt_b_bits = AO_Error_Interrupt_Enable;
2830 #ifdef PCIDMA
2831         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2832         if(boardtype.reg_type & ni_reg_6xxx_mask)
2833                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2834         ret = ni_ao_setup_MITE_dma(dev);
2835         if(ret) return ret;
2836         ret = ni_ao_wait_for_dma_load(dev);
2837         if(ret < 0) return ret;
2838 #else
2839         ret = ni_ao_prep_fifo(dev,s);
2840         if(ret==0)return -EPIPE;
2841
2842         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2843 #endif
2844
2845         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2846         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2847         /* wait for DACs to be loaded */
2848         for(i = 0; i < timeout; i++)
2849         {
2850                 comedi_udelay(1);
2851                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2852                         break;
2853         }
2854         if(i == timeout)
2855         {
2856                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2857                 return -EIO;
2858         }
2859         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2860         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2861
2862         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2863
2864         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2865                 AO_Command_1_Register);
2866
2867         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2868
2869         return 0;
2870 }
2871
2872 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2873 {
2874         const comedi_cmd *cmd = &s->async->cmd;
2875         int bits;
2876         int i;
2877         unsigned trigvar;
2878
2879         if(dev->irq == 0)
2880         {
2881                 comedi_error(dev, "cannot run command without an irq");
2882                 return -EIO;
2883         }
2884
2885         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2886
2887         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2888
2889         if(boardtype.reg_type & ni_reg_6xxx_mask)
2890         {
2891                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2892
2893                 bits = 0;
2894                 for(i = 0; i < cmd->chanlist_len; i++)
2895                 {
2896                         int chan;
2897
2898                         chan = CR_CHAN(cmd->chanlist[i]);
2899                         bits |= 1 << chan;
2900                         ao_win_out(chan, AO_Waveform_Generation_611x);
2901                 }
2902                 ao_win_out(bits, AO_Timed_611x);
2903         }
2904
2905         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2906
2907         if(cmd->stop_src==TRIG_NONE){
2908                 devpriv->ao_mode1|=AO_Continuous;
2909                 devpriv->ao_mode1&=~AO_Trigger_Once;
2910         }else{
2911                 devpriv->ao_mode1&=~AO_Continuous;
2912                 devpriv->ao_mode1|=AO_Trigger_Once;
2913         }
2914         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2915         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2916         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2917         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2918         devpriv->ao_mode3&=~AO_Trigger_Length;
2919         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2920
2921         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2922         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2923         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2924         if(cmd->stop_src==TRIG_NONE){
2925                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2926         }else{
2927                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2928         }
2929         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2930         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2931         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2932         switch(cmd->stop_src){
2933         case TRIG_COUNT:
2934                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2935                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2936                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2937                 break;
2938         case TRIG_NONE:
2939                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2940                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2941                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2942                 break;
2943         default:
2944                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2945                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2946                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2947         }
2948
2949         devpriv->ao_mode1 &= ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
2950                 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
2951         switch(cmd->scan_begin_src)
2952         {
2953         case TRIG_TIMER:
2954                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
2955                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2956                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
2957                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
2958                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
2959                 break;
2960         case TRIG_EXT:
2961                 devpriv->ao_mode1 |= AO_UPDATE_Source_Select(cmd->scan_begin_arg);
2962                 if(cmd->scan_begin_arg & CR_INVERT)
2963                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
2964                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
2965                 break;
2966         default:
2967                 BUG();
2968                 break;
2969         }
2970         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2971         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2972         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2973         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2974
2975         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2976                 if(cmd->scan_end_arg>1){
2977                         devpriv->ao_mode1|=AO_Multiple_Channels;
2978                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2979                                 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
2980                                 AO_Output_Control_Register);
2981                 }else{
2982                         unsigned bits;
2983                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2984                         bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
2985                         if(boardtype.reg_type & ni_reg_m_series_mask)
2986                         {
2987                                 bits |= AO_Number_Of_Channels(0);
2988                         }else
2989                         {
2990                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2991                         }
2992                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2993                 }
2994                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2995         }
2996
2997         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2998
2999         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
3000         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
3001
3002         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3003 #ifdef PCIDMA
3004         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3005 #else
3006         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3007 #endif
3008         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3009         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
3010
3011         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3012                 AO_TMRDACWR_Pulse_Width;
3013         if( boardtype.ao_fifo_depth )
3014                 bits |= AO_FIFO_Enable;
3015         else
3016                 bits |= AO_DMA_PIO_Control;
3017 #if 0
3018         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3019         verified with bus analyzer. */
3020         if(boardtype.reg_type & ni_reg_m_series_mask)
3021                 bits |= AO_Number_Of_DAC_Packages;
3022 #endif
3023         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3024         // enable sending of ao dma requests
3025         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3026
3027         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
3028
3029         if(cmd->stop_src==TRIG_COUNT) {
3030                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
3031                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3032                         AO_BC_TC_Interrupt_Enable, 1);
3033         }
3034
3035         s->async->inttrig = &ni_ao_inttrig;
3036
3037         return 0;
3038 }
3039
3040 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
3041 {
3042         int err=0;
3043         int tmp;
3044
3045         /* step 1: make sure trigger sources are trivially valid */
3046
3047         if((cmd->flags & CMDF_WRITE) == 0)
3048         {
3049                 cmd->flags |= CMDF_WRITE;
3050         }
3051
3052         tmp=cmd->start_src;
3053         cmd->start_src &= TRIG_INT;
3054         if(!cmd->start_src || tmp!=cmd->start_src)err++;
3055
3056         tmp=cmd->scan_begin_src;
3057         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3058         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
3059
3060         tmp=cmd->convert_src;
3061         cmd->convert_src &= TRIG_NOW;
3062         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
3063
3064         tmp=cmd->scan_end_src;
3065         cmd->scan_end_src &= TRIG_COUNT;
3066         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
3067
3068         tmp=cmd->stop_src;
3069         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
3070         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
3071
3072         if(err)return 1;
3073
3074         /* step 2: make sure trigger sources are unique and mutually compatible */
3075
3076         if(cmd->stop_src!=TRIG_COUNT &&
3077            cmd->stop_src!=TRIG_NONE)err++;
3078
3079         if(err)return 2;
3080
3081         /* step 3: make sure arguments are trivially compatible */
3082
3083         if(cmd->start_arg!=0){
3084                 cmd->start_arg=0;
3085                 err++;
3086         }
3087         if(cmd->scan_begin_src == TRIG_TIMER)
3088         {
3089                 if(cmd->scan_begin_arg < boardtype.ao_speed){
3090                         cmd->scan_begin_arg = boardtype.ao_speed;
3091                         err++;
3092                 }
3093                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){ /* XXX check */
3094                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3095                         err++;
3096                 }
3097         }
3098         if(cmd->convert_arg!=0){
3099                 cmd->convert_arg=0;
3100                 err++;
3101         }
3102         if(cmd->scan_end_arg!=cmd->chanlist_len){
3103                 cmd->scan_end_arg=cmd->chanlist_len;
3104                 err++;
3105         }
3106         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
3107                 if(cmd->stop_arg>0x00ffffff){
3108                         cmd->stop_arg=0x00ffffff;
3109                         err++;
3110                 }
3111         }else{
3112                 /* TRIG_NONE */
3113                 if(cmd->stop_arg!=0){
3114                         cmd->stop_arg=0;
3115                         err++;
3116                 }
3117         }
3118
3119         if(err)return 3;
3120
3121         /* step 4: fix up any arguments */
3122         if(cmd->scan_begin_src == TRIG_TIMER)
3123         {
3124                 tmp = cmd->scan_begin_arg;
3125                 cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK));
3126                 if(tmp!=cmd->scan_begin_arg)err++;
3127         }
3128         if(err)return 4;
3129
3130         /* step 5: fix up chanlist */
3131
3132         if(err)return 5;
3133
3134         return 0;
3135 }
3136
3137
3138 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
3139 {
3140         //devpriv->ao0p=0x0000;
3141         //ni_writew(devpriv->ao0p,AO_Configuration);
3142
3143         //devpriv->ao1p=AO_Channel(1);
3144         //ni_writew(devpriv->ao1p,AO_Configuration);
3145
3146         ni_release_ao_mite_channel(dev);
3147
3148         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
3149         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
3150         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
3151         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3152         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
3153         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3154                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3155         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
3156         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
3157         devpriv->ao_cmd1=0;
3158         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
3159         devpriv->ao_cmd2=0;
3160         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3161         devpriv->ao_mode1=0;
3162         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3163         devpriv->ao_mode2=0;
3164         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3165         if(boardtype.reg_type & ni_reg_m_series_mask)
3166                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3167         else
3168                 devpriv->ao_mode3 = 0;
3169         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3170         devpriv->ao_trigger_select = 0;
3171         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
3172         if(boardtype.reg_type & ni_reg_6xxx_mask){
3173                 ao_win_out(0x3, AO_Immediate_671x);
3174                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3175         }
3176         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3177
3178         return 0;
3179 }
3180
3181 // digital io
3182
3183 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
3184         comedi_insn *insn,lsampl_t *data)
3185 {
3186 #ifdef DEBUG_DIO
3187         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
3188                 CR_CHAN(insn->chanspec),data[0]);
3189 #endif
3190         switch(data[0]){
3191         case INSN_CONFIG_DIO_OUTPUT:
3192                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
3193                 break;
3194         case INSN_CONFIG_DIO_INPUT:
3195                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
3196                 break;
3197         case INSN_CONFIG_DIO_QUERY:
3198                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
3199                 return insn->n;
3200                 break;
3201         default:
3202                 return -EINVAL;
3203         }
3204
3205         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3206         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3207         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3208
3209         return 1;
3210 }
3211
3212 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3213         comedi_insn *insn,lsampl_t *data)
3214 {
3215 #ifdef DEBUG_DIO
3216         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3217 #endif
3218         if(insn->n!=2)return -EINVAL;
3219         if(data[0]){
3220                 /* Perform check to make sure we're not using the
3221                    serial part of the dio */
3222                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3223                         return -EBUSY;
3224
3225                 s->state &= ~data[0];
3226                 s->state |= (data[0]&data[1]);
3227                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3228                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3229                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3230         }
3231         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3232
3233         return 2;
3234 }
3235
3236 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
3237         comedi_insn *insn, lsampl_t *data)
3238 {
3239 #ifdef DEBUG_DIO
3240         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3241                 CR_CHAN(insn->chanspec), data[0]);
3242 #endif
3243         switch(data[0])
3244         {
3245         case INSN_CONFIG_DIO_OUTPUT:
3246                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3247                 break;
3248         case INSN_CONFIG_DIO_INPUT:
3249                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3250                 break;
3251         case INSN_CONFIG_DIO_QUERY:
3252                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
3253                 return insn->n;
3254                 break;
3255         default:
3256                 return -EINVAL;
3257         }
3258
3259         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3260
3261         return 1;
3262 }
3263
3264 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3265         comedi_insn *insn, lsampl_t *data)
3266 {
3267 #ifdef DEBUG_DIO
3268         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3269 #endif
3270         if(insn->n!=2)return -EINVAL;
3271         if(data[0]){
3272                 s->state &= ~data[0];
3273                 s->state |= (data[0] & data[1]);
3274                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3275         }
3276         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3277
3278         return 2;
3279 }
3280
3281 static int ni_cdio_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
3282 {
3283         int err=0;
3284         int tmp;
3285         int sources;
3286         unsigned i;
3287
3288         /* step 1: make sure trigger sources are trivially valid */
3289
3290         tmp = cmd->start_src;
3291         sources = TRIG_INT;
3292         cmd->start_src &= sources;
3293         if(!cmd->start_src || tmp != cmd->start_src) err++;
3294
3295         tmp = cmd->scan_begin_src;
3296         cmd->scan_begin_src &= TRIG_EXT;
3297         if(!cmd->scan_begin_src || tmp != cmd->scan_begin_src) err++;
3298
3299         tmp = cmd->convert_src;
3300         cmd->convert_src &= TRIG_NOW;
3301         if(!cmd->convert_src || tmp != cmd->convert_src) err++;
3302
3303         tmp = cmd->scan_end_src;
3304         cmd->scan_end_src &= TRIG_COUNT;
3305         if(!cmd->scan_end_src || tmp != cmd->scan_end_src) err++;
3306
3307         tmp = cmd->stop_src;
3308         cmd->stop_src &= TRIG_NONE;
3309         if(!cmd->stop_src || tmp != cmd->stop_src) err++;
3310
3311         if(err) return 1;
3312
3313         /* step 2: make sure trigger sources are unique...*/
3314
3315         if(cmd->start_src != TRIG_INT) err++;
3316         if(cmd->scan_begin_src != TRIG_EXT) err++;
3317         if(cmd->convert_src != TRIG_NOW) err++;
3318         if(cmd->stop_src != TRIG_NONE) err++;
3319         /* ... and mutually compatible */
3320
3321         if(err) return 2;
3322
3323         /* step 3: make sure arguments are trivially compatible */
3324         if(cmd->start_src == TRIG_INT)
3325         {
3326                 if(cmd->start_arg != 0)
3327                 {
3328                         cmd->start_arg = 0;
3329                         err++;
3330                 }
3331         }
3332         if(cmd->scan_begin_src == TRIG_EXT)
3333         {
3334                 tmp = cmd->scan_begin_arg;
3335                 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3336                 if(tmp != cmd->scan_begin_arg)
3337                 {
3338                         err++;
3339                 }
3340         }
3341         if(cmd->convert_src == TRIG_NOW)
3342         {
3343                 if(cmd->convert_arg)
3344                 {
3345                         cmd->convert_arg = 0;
3346                         err++;
3347                 }
3348         }
3349
3350         if(cmd->scan_end_arg != cmd->chanlist_len)
3351         {
3352                 cmd->scan_end_arg = cmd->chanlist_len;
3353                 err++;
3354         }
3355
3356         if(cmd->stop_src == TRIG_NONE)
3357         {
3358                 if(cmd->stop_arg != 0)
3359                 {
3360                         cmd->stop_arg = 0;
3361                         err++;
3362                 }
3363         }
3364
3365         if(err) return 3;
3366
3367         /* step 4: fix up any arguments */
3368
3369         if(err) return 4;
3370
3371         /* step 5: check chanlist */
3372
3373         for(i = 0; i < cmd->chanlist_len; ++i)
3374         {
3375                 if(cmd->chanlist[i] != i) err = 1;
3376         }
3377
3378         if(err) return 5;
3379
3380         return 0;
3381 }
3382
3383 static int ni_cdio_cmd(comedi_device *dev, comedi_subdevice *s)
3384 {
3385         const comedi_cmd *cmd = &s->async->cmd;
3386         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3387         int retval;
3388
3389         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3390         switch(cmd->scan_begin_src)
3391         {
3392         case TRIG_EXT:
3393                 cdo_mode_bits |= CR_CHAN(cmd->scan_begin_arg) & CDO_Sample_Source_Select_Mask;
3394                 break;
3395         default:
3396                 BUG();
3397                 break;
3398         }
3399         if(cmd->scan_begin_arg & CR_INVERT)
3400                 cdo_mode_bits |= CDO_Polarity_Bit;
3401         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3402         if(s->io_bits)
3403         {
3404                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3405                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3406                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3407         }else
3408         {
3409                 comedi_error(dev, "attempted to run digital output command with no lines configured as outputs");
3410                 return -EIO;
3411         }
3412         retval = ni_request_cdo_mite_channel(dev);
3413         if(retval < 0)
3414         {
3415                 return retval;
3416         }
3417         s->async->inttrig = &ni_cdo_inttrig;
3418         return 0;
3419 }
3420
3421 static int ni_cdo_inttrig(comedi_device *dev,comedi_subdevice *s,
3422         unsigned int trignum)
3423 {
3424         unsigned long flags;
3425         int retval = 0;
3426         unsigned i;
3427         const unsigned timeout = 100;
3428
3429         s->async->inttrig = NULL;
3430
3431         /* read alloc the entire buffer */
3432         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3433
3434         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3435         if(devpriv->cdo_mite_chan)
3436         {
3437                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3438                 mite_dma_arm(devpriv->cdo_mite_chan);
3439         }else
3440         {
3441                 comedi_error(dev, "BUG: no cdo mite channel?");
3442                 retval = -EIO;
3443         }
3444         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3445         if(retval < 0) return retval;
3446 // XXX not sure what interrupt C group does
3447 //      ni_writeb(Interrupt_Group_C_Enable_Bit, M_Offset_Interrupt_C_Enable);
3448         //wait for dma to fill output fifo
3449         for(i = 0; i < timeout; ++i)
3450         {
3451                 if(ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) break;
3452                 comedi_udelay(10);
3453         }
3454         if(i == timeout)
3455         {
3456                 comedi_error(dev, "dma failed to fill cdo fifo!");
3457                 ni_cdio_cancel(dev, s);
3458                 return -EIO;
3459         }
3460         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3461                 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3462                 M_Offset_CDIO_Command);
3463         return 0;
3464 }
3465
3466 static int ni_cdio_cancel(comedi_device *dev, comedi_subdevice *s)
3467 {
3468         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3469                 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3470                 M_Offset_CDIO_Command);
3471 // XXX not sure what interrupt C group does
3472 //      ni_writeb(0, M_Offset_Interrupt_C_Enable);
3473         ni_writel(0, M_Offset_CDO_Mask_Enable);
3474         ni_release_cdo_mite_channel(dev);
3475         return 0;
3476 }
3477
3478 static void handle_cdio_interrupt(comedi_device *dev)
3479 {
3480         unsigned cdio_status;
3481         comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3482         unsigned long flags;
3483
3484         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
3485         {
3486                 return;
3487         }
3488         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3489         if(devpriv->cdo_mite_chan)
3490         {
3491                 unsigned cdo_mite_status = mite_get_status(devpriv->cdo_mite_chan);
3492                 if(cdo_mite_status & CHSR_LINKC)
3493                 {
3494                         writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->cdo_mite_chan->channel));
3495                 }
3496                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3497         }
3498         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3499
3500         cdio_status = ni_readl(M_Offset_CDIO_Status);
3501         if(cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit))
3502         {
3503 //              rt_printk("cdio error: statux=0x%x\n", cdio_status);
3504                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      // XXX just guessing this is needed and does something useful
3505                 s->async->events |= COMEDI_CB_OVERFLOW;
3506         }
3507         if(cdio_status & CDO_FIFO_Empty_Bit)
3508         {
3509 //              rt_printk("cdio fifo empty\n");
3510                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, M_Offset_CDIO_Command);
3511 //              s->async->events |= COMEDI_CB_EOA;
3512         }
3513         ni_event(dev, s);
3514 }
3515
3516 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
3517                                  comedi_insn *insn,lsampl_t *data)
3518 {
3519         int err = insn->n;
3520         unsigned char byte_out, byte_in = 0;
3521
3522         if(insn->n!=2)return -EINVAL;
3523
3524         switch(data[0]) {
3525         case INSN_CONFIG_SERIAL_CLOCK:
3526
3527 #ifdef DEBUG_DIO
3528                 rt_printk("SPI serial clock Config cd\n", data[1]);
3529 #endif
3530                 devpriv->serial_hw_mode = 1;
3531                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3532
3533                 if(data[1] == SERIAL_DISABLED) {
3534                         devpriv->serial_hw_mode = 0;
3535                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3536                                                   DIO_Software_Serial_Control);
3537                         data[1] = SERIAL_DISABLED;
3538                         devpriv->serial_interval_ns = data[1];
3539                 }
3540                 else if(data[1] <= SERIAL_600NS) {
3541                         /* Warning: this clock speed is too fast to reliably
3542                         control SCXI. */
3543                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3544                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3545                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3546                         data[1] = SERIAL_600NS;
3547                         devpriv->serial_interval_ns = data[1];
3548                 }
3549                 else if(data[1] <= SERIAL_1_2US) {
3550                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3551                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3552                                 DIO_Serial_Out_Divide_By_2;
3553                         data[1] = SERIAL_1_2US;
3554                         devpriv->serial_interval_ns = data[1];
3555                 }
3556                 else if(data[1] <= SERIAL_10US) {
3557                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3558                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3559                                 DIO_Serial_Out_Divide_By_2;
3560                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3561                         600ns/1.2us. If you turn divide_by_2 off with the
3562                         slow clock, you will still get 10us, except then
3563                         all your delays are wrong. */
3564                         data[1] = SERIAL_10US;
3565                         devpriv->serial_interval_ns = data[1];
3566                 }
3567                 else {
3568                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3569                                                   DIO_Software_Serial_Control);
3570                         devpriv->serial_hw_mode = 0;
3571                         data[1] = (data[1] / 1000) * 1000;
3572                         devpriv->serial_interval_ns = data[1];
3573                 }
3574
3575                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3576                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
3577                 return 1;
3578
3579         break;
3580
3581         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3582
3583                 if(devpriv->serial_interval_ns == 0) {
3584                         return -EINVAL;
3585                 }
3586
3587                 byte_out = data[1] & 0xFF;
3588
3589                 if(devpriv->serial_hw_mode) {
3590                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
3591                 } else if(devpriv->serial_interval_ns > 0) {
3592                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
3593                 } else {
3594                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3595                         return -EINVAL;
3596                 }
3597                 if(err < 0) return err;
3598                 data[1] = byte_in & 0xFF;
3599                 return insn->n;
3600
3601         break;
3602         default:
3603                 return -EINVAL;
3604         }
3605
3606 }
3607
3608 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3609                                    unsigned char data_out,
3610                                    unsigned char *data_in)
3611 {
3612         unsigned int status1;
3613         int err = 0, count = 20;
3614
3615 #ifdef DEBUG_DIO
3616         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3617 #endif
3618
3619         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3620         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3621         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3622
3623         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3624         if(status1 & DIO_Serial_IO_In_Progress_St) {
3625                 err = -EBUSY;
3626                 goto Error;
3627         }
3628
3629         devpriv->dio_control |= DIO_HW_Serial_Start;
3630         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3631         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3632
3633         /* Wait until STC says we're done, but don't loop infinitely. */
3634         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3635                 /* Delay one bit per loop */
3636                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3637                 if(--count < 0) {
3638                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3639                         err = -ETIME;
3640                         goto Error;
3641                 }
3642         }
3643
3644         /* Delay for last bit. This delay is absolutely necessary, because
3645            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3646         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3647
3648         if(data_in != NULL) {
3649                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3650 #ifdef DEBUG_DIO
3651                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3652 #endif
3653         }
3654
3655  Error:
3656         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3657
3658         return err;
3659 }
3660
3661 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3662                                    unsigned char data_out,
3663                                    unsigned char *data_in)
3664 {
3665         unsigned char mask, input = 0;
3666
3667 #ifdef DEBUG_DIO
3668         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3669 #endif
3670
3671         /* Wait for one bit before transfer */
3672         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3673
3674         for(mask = 0x80; mask; mask >>= 1) {
3675                 /* Output current bit; note that we cannot touch s->state
3676            because it is a per-subdevice field, and serial is
3677                    a separate subdevice from DIO. */
3678                 devpriv->dio_output &= ~DIO_SDOUT;
3679                 if(data_out & mask) {
3680                         devpriv->dio_output |= DIO_SDOUT;
3681                 }
3682                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3683
3684                 /* Assert SDCLK (active low, inverted), wait for half of
3685                    the delay, deassert SDCLK, and wait for the other half. */
3686                 devpriv->dio_control |= DIO_Software_Serial_Control;
3687                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3688
3689                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3690
3691                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3692                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3693
3694                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3695
3696                 /* Input current bit */
3697                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3698 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3699                         input |= mask;
3700                 }
3701         }
3702 #ifdef DEBUG_DIO
3703         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3704 #endif
3705         if(data_in) *data_in = input;
3706
3707         return 0;
3708 }
3709
3710 static void mio_common_detach(comedi_device *dev)
3711 {
3712         if(dev->private)
3713         {
3714                 if(devpriv->counter_dev)
3715                 {
3716                         ni_gpct_device_destroy(devpriv->counter_dev);
3717                 }
3718         }
3719         if(dev->subdevices && boardtype.has_8255)
3720                 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
3721 }
3722
3723 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3724 {
3725         int i;
3726
3727         for(i = 0; i < s->n_chan; i++)
3728                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3729 }
3730
3731 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3732 {
3733         unsigned stc_register;
3734         switch(reg)
3735         {
3736         case NITIO_G0_Autoincrement_Reg:
3737                 stc_register = G_Autoincrement_Register(0);
3738                 break;
3739         case NITIO_G1_Autoincrement_Reg:
3740                 stc_register = G_Autoincrement_Register(1);
3741                 break;
3742         case NITIO_G0_Command_Reg:
3743                 stc_register = G_Command_Register(0);
3744                 break;
3745         case NITIO_G1_Command_Reg:
3746                 stc_register = G_Command_Register(1);
3747                 break;
3748         case NITIO_G0_HW_Save_Reg:
3749                 stc_register = G_HW_Save_Register(0);
3750                 break;
3751         case NITIO_G1_HW_Save_Reg:
3752                 stc_register = G_HW_Save_Register(1);
3753                 break;
3754         case NITIO_G0_SW_Save_Reg:
3755                 stc_register = G_Save_Register(0);
3756                 break;
3757         case NITIO_G1_SW_Save_Reg:
3758                 stc_register = G_Save_Register(1);
3759                 break;
3760         case NITIO_G0_Mode_Reg:
3761                 stc_register = G_Mode_Register(0);
3762                 break;
3763         case NITIO_G1_Mode_Reg:
3764                 stc_register = G_Mode_Register(1);
3765                 break;
3766         case NITIO_G0_LoadA_Reg:
3767                 stc_register = G_Load_A_Register(0);
3768                 break;
3769         case NITIO_G1_LoadA_Reg:
3770                 stc_register = G_Load_A_Register(1);
3771                 break;
3772         case NITIO_G0_LoadB_Reg:
3773                 stc_register = G_Load_B_Register(0);
3774                 break;
3775         case NITIO_G1_LoadB_Reg:
3776                 stc_register = G_Load_B_Register(1);
3777                 break;
3778         case NITIO_G0_Input_Select_Reg:
3779                 stc_register = G_Input_Select_Register(0);
3780                 break;
3781         case NITIO_G1_Input_Select_Reg:
3782                 stc_register = G_Input_Select_Register(1);
3783                 break;
3784         case NITIO_G01_Status_Reg:
3785                 stc_register = G_Status_Register;
3786                 break;
3787         case NITIO_G01_Joint_Reset_Reg:
3788                 stc_register = Joint_Reset_Register;
3789                 break;
3790         case NITIO_G01_Joint_Status1_Reg:
3791                 stc_register = Joint_Status_1_Register;
3792                 break;
3793         case NITIO_G01_Joint_Status2_Reg:
3794                 stc_register = Joint_Status_2_Register;
3795                 break;
3796         case NITIO_G0_Interrupt_Acknowledge_Reg:
3797                 stc_register = Interrupt_A_Ack_Register;
3798                 break;
3799         case NITIO_G1_Interrupt_Acknowledge_Reg:
3800                 stc_register = Interrupt_B_Ack_Register;
3801                 break;
3802         case NITIO_G0_Status_Reg:
3803                 stc_register = AI_Status_1_Register;
3804                 break;
3805         case NITIO_G1_Status_Reg:
3806                 stc_register = AO_Status_1_Register;
3807                 break;
3808         case NITIO_G0_Interrupt_Enable_Reg:
3809                 stc_register = Interrupt_A_Enable_Register;
3810                 break;
3811         case NITIO_G1_Interrupt_Enable_Reg:
3812                 stc_register = Interrupt_B_Enable_Register;
3813                 break;
3814         default:
3815                 rt_printk("%s: unhandled register 0x%x in switch.\n", __FUNCTION__, reg);
3816                 BUG();
3817                 return 0;
3818                 break;
3819         }
3820         return stc_register;
3821 }
3822
3823 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg)
3824 {
3825         comedi_device *dev = counter->counter_dev->dev;
3826         unsigned stc_register;
3827         /* bits in the join reset register which are relevant to counters */
3828         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3829         static const unsigned gpct_interrupt_a_enable_mask = G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3830         static const unsigned gpct_interrupt_b_enable_mask = G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3831
3832         switch(reg)
3833         {
3834         /* m-series-only registers */
3835         case NITIO_G0_Counting_Mode_Reg:
3836                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3837                 break;
3838         case NITIO_G1_Counting_Mode_Reg:
3839                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3840                 break;
3841         case NITIO_G0_Second_Gate_Reg:
3842                 ni_writew(bits, M_Offset_G0_Second_Gate);
3843                 break;
3844         case NITIO_G1_Second_Gate_Reg:
3845                 ni_writew(bits, M_Offset_G1_Second_Gate);
3846                 break;
3847         case NITIO_G0_DMA_Config_Reg:
3848                 ni_writew(bits, M_Offset_G0_DMA_Config);
3849                 break;
3850         case NITIO_G1_DMA_Config_Reg:
3851                 ni_writew(bits, M_Offset_G1_DMA_Config);
3852                 break;
3853         case NITIO_G0_ABZ_Reg:
3854                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
3855                 break;
3856         case NITIO_G1_ABZ_Reg:
3857                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
3858                 break;
3859
3860         /* 32 bit registers */
3861         case NITIO_G0_LoadA_Reg:
3862         case NITIO_G1_LoadA_Reg:
3863         case NITIO_G0_LoadB_Reg:
3864         case NITIO_G1_LoadB_Reg:
3865                 stc_register = ni_gpct_to_stc_register(reg);
3866                 devpriv->stc_writel(dev, bits, stc_register);
3867                 break;
3868
3869         /* 16 bit registers */
3870         case NITIO_G0_Interrupt_Enable_Reg:
3871                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3872                 ni_set_bitfield(dev, Interrupt_A_Enable_Register, gpct_interrupt_a_enable_mask, bits);
3873                 break;
3874         case NITIO_G1_Interrupt_Enable_Reg:
3875                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3876                 ni_set_bitfield(dev, Interrupt_B_Enable_Register, gpct_interrupt_b_enable_mask, bits);
3877                 break;
3878         case NITIO_G01_Joint_Reset_Reg:
3879                 BUG_ON(bits & ~gpct_joint_reset_mask);
3880                 /* fall-through */
3881         default:
3882                 stc_register = ni_gpct_to_stc_register(reg);
3883                 devpriv->stc_writew(dev, bits, stc_register);
3884         }
3885 }
3886
3887 static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg)
3888 {
3889         comedi_device *dev = counter->counter_dev->dev;
3890         unsigned stc_register;
3891         switch(reg)
3892         {
3893         /* m-series only registers */
3894         case NITIO_G0_DMA_Status_Reg:
3895                 return ni_readw(M_Offset_G0_DMA_Status);
3896                 break;
3897         case NITIO_G1_DMA_Status_Reg:
3898                 return ni_readw(M_Offset_G1_DMA_Status);
3899                 break;
3900
3901         /* 32 bit registers */
3902         case NITIO_G0_HW_Save_Reg:
3903         case NITIO_G1_HW_Save_Reg:
3904         case NITIO_G0_SW_Save_Reg:
3905         case NITIO_G1_SW_Save_Reg:
3906                 stc_register = ni_gpct_to_stc_register(reg);
3907                 return devpriv->stc_readl(dev, stc_register);
3908                 break;
3909
3910         /* 16 bit registers */
3911         default:
3912                 stc_register = ni_gpct_to_stc_register(reg);
3913                 return devpriv->stc_readw(dev, stc_register);
3914                 break;
3915         }
3916         return 0;
3917 }
3918
3919 static int ni_freq_out_insn_read(comedi_device *dev,
3920         comedi_subdevice *s, comedi_insn *insn, lsampl_t *data)
3921 {
3922         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
3923         return 1;
3924 }
3925
3926 static int ni_freq_out_insn_write(comedi_device *dev,
3927         comedi_subdevice *s, comedi_insn *insn, lsampl_t *data)
3928 {
3929         devpriv->clock_and_fout &= ~FOUT_Enable;
3930         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3931         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
3932         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
3933         devpriv->clock_and_fout |= FOUT_Enable;
3934         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3935         return insn->n;
3936 }
3937
3938 static int ni_set_freq_out_clock(comedi_device *dev, lsampl_t clock_source)
3939 {
3940         switch(clock_source)
3941         {
3942         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3943                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
3944                 break;
3945         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3946                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
3947                 break;
3948         default:
3949                 return -EINVAL;
3950         }
3951         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3952         return 3;
3953 }
3954
3955 static void ni_get_freq_out_clock(comedi_device *dev, lsampl_t *clock_source, lsampl_t *clock_period_ns)
3956 {
3957         if(devpriv->clock_and_fout & FOUT_Timebase_Select)
3958         {
3959                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3960                 *clock_period_ns = TIMEBASE_2_NS;
3961         }else
3962         {
3963                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3964                 *clock_period_ns = TIMEBASE_1_NS * 2;
3965         }
3966 }
3967
3968 static int ni_freq_out_insn_config(comedi_device *dev, comedi_subdevice *s,
3969         comedi_insn *insn, lsampl_t *data)
3970 {
3971         switch(data[0])
3972         {
3973         case INSN_CONFIG_SET_CLOCK_SRC:
3974                 return ni_set_freq_out_clock(dev, data[1]);
3975                 break;
3976         case INSN_CONFIG_GET_CLOCK_SRC:
3977                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
3978                 return 3;
3979         default:
3980                 break;
3981         }
3982         return -EINVAL;
3983 }
3984
3985 static int ni_alloc_private(comedi_device *dev)
3986 {
3987         int ret;
3988
3989         ret = alloc_private(dev, sizeof(ni_private));
3990         if(ret < 0) return ret;
3991
3992         spin_lock_init(&devpriv->window_lock);
3993         spin_lock_init(&devpriv->soft_reg_copy_lock);
3994         spin_lock_init(&devpriv->mite_channel_lock);
3995
3996         return 0;
3997 };
3998
3999 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
4000 {
4001         comedi_subdevice *s;
4002         unsigned j;
4003         enum ni_gpct_variant counter_variant;
4004
4005         if(boardtype.n_aochan > MAX_N_AO_CHAN)
4006         {
4007                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4008                 return -EINVAL;
4009         }
4010
4011         if(alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4012                 return -ENOMEM;
4013
4014         /* analog input subdevice */
4015
4016         s = dev->subdevices + NI_AI_SUBDEV;
4017         dev->read_subdev=s;
4018         if(boardtype.n_adchan){
4019                 s->type=COMEDI_SUBD_AI;
4020                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4021                 if(boardtype.reg_type != ni_reg_611x)
4022                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4023                 if(boardtype.adbits > 16)
4024                         s->subdev_flags |= SDF_LSAMPL;
4025                 if(boardtype.reg_type & ni_reg_m_series_mask)
4026                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4027                 s->n_chan=boardtype.n_adchan;
4028                 s->len_chanlist=512;
4029                 s->maxdata=(1<<boardtype.adbits)-1;
4030                 s->range_table=ni_range_lkup[boardtype.gainlkup];
4031                 s->insn_read = &ni_ai_insn_read;
4032                 s->insn_config = &ni_ai_insn_config;
4033                 s->do_cmdtest = &ni_ai_cmdtest;
4034                 s->do_cmd = &ni_ai_cmd;
4035                 s->cancel = &ni_ai_reset;
4036                 s->poll = &ni_ai_poll;
4037                 s->munge = &ni_ai_munge;
4038 #ifdef PCIDMA
4039                 s->async_dma_dir = DMA_FROM_DEVICE;
4040 #endif
4041         }else{
4042                 s->type=COMEDI_SUBD_UNUSED;
4043         }
4044
4045         /* analog output subdevice */
4046
4047         s = dev->subdevices + NI_AO_SUBDEV;
4048         if(boardtype.n_aochan){
4049                 s->type = COMEDI_SUBD_AO;
4050                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4051                 if(boardtype.reg_type & ni_reg_m_series_mask)
4052                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4053                 s->n_chan = boardtype.n_aochan;
4054                 s->maxdata = (1 << boardtype.aobits) - 1;
4055                 s->range_table = boardtype.ao_range_table;
4056                 s->insn_read = &ni_ao_insn_read;
4057                 if(boardtype.reg_type & ni_reg_6xxx_mask){
4058                         s->insn_write = &ni_ao_insn_write_671x;
4059                 }else{
4060                         s->insn_write = &ni_ao_insn_write;
4061                 }
4062 #ifdef PCIDMA
4063                 if(boardtype.n_aochan){
4064                         s->async_dma_dir = DMA_TO_DEVICE;
4065 #else
4066                 if(boardtype.ao_fifo_depth){
4067 #endif
4068                         dev->write_subdev=s;
4069                         s->subdev_flags |= SDF_CMD_WRITE;
4070                         s->do_cmd = &ni_ao_cmd;
4071                         s->do_cmdtest = &ni_ao_cmdtest;
4072                         s->len_chanlist = boardtype.n_aochan;
4073                         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4074                                 s->munge=ni_ao_munge;
4075                 }
4076                 s->cancel = &ni_ao_reset;
4077         }else{
4078                 s->type = COMEDI_SUBD_UNUSED;
4079         }
4080         if((boardtype.reg_type & ni_reg_67xx_mask))
4081                 init_ao_67xx(dev, s);
4082
4083         /* digital i/o subdevice */
4084
4085         s = dev->subdevices + NI_DIO_SUBDEV;
4086         s->type=COMEDI_SUBD_DIO;
4087         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4088         s->maxdata=1;
4089         s->io_bits=0;           /* all bits input */
4090         s->range_table=&range_digital;
4091         s->n_chan = boardtype.num_p0_dio_channels;
4092         if(boardtype.reg_type & ni_reg_m_series_mask)
4093         {
4094                 s->subdev_flags |= SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;
4095                 s->insn_bits = &ni_m_series_dio_insn_bits;
4096                 s->insn_config = &ni_m_series_dio_insn_config;
4097                 s->do_cmd = &ni_cdio_cmd;
4098                 s->do_cmdtest = &ni_cdio_cmdtest;
4099                 s->cancel = &ni_cdio_cancel;
4100                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4101                 s->len_chanlist = s->n_chan;
4102
4103                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4104                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4105         }else
4106         {
4107                 s->insn_bits = &ni_dio_insn_bits;
4108                 s->insn_config = &ni_dio_insn_config;
4109                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4110                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4111         }
4112
4113         /* 8255 device */
4114         s = dev->subdevices + NI_8255_DIO_SUBDEV;
4115         if(boardtype.has_8255){
4116                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
4117         }else{
4118                 s->type=COMEDI_SUBD_UNUSED;
4119         }
4120
4121         /* formerly general purpose counter/timer device, but no longer used */
4122         s = dev->subdevices + NI_UNUSED_SUBDEV;
4123         s->type = COMEDI_SUBD_UNUSED;
4124
4125         /* calibration subdevice -- ai and ao */
4126         s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4127         s->type=COMEDI_SUBD_CALIB;
4128         if(boardtype.reg_type & ni_reg_m_series_mask)
4129         {
4130                 // internal PWM analog output used for AI nonlinearity calibration
4131                 s->subdev_flags = SDF_INTERNAL;
4132                 s->insn_config = &ni_m_series_pwm_config;
4133                 s->n_chan = 1;
4134                 s->maxdata = 0;
4135                 ni_writel(0x0, M_Offset_Cal_PWM);
4136         } else if(boardtype.reg_type == ni_reg_6143)
4137         {
4138                 // internal PWM analog output used for AI nonlinearity calibration
4139                 s->subdev_flags = SDF_INTERNAL;
4140                 s->insn_config = &ni_6143_pwm_config;
4141                 s->n_chan = 1;
4142                 s->maxdata = 0;
4143         }else
4144         {
4145                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4146                 s->insn_read = &ni_calib_insn_read;
4147                 s->insn_write = &ni_calib_insn_write;
4148                 caldac_setup(dev, s);
4149         }
4150
4151         /* EEPROM */
4152         s = dev->subdevices + NI_EEPROM_SUBDEV;
4153         s->type=COMEDI_SUBD_MEMORY;
4154         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
4155         s->maxdata=0xff;
4156         if(boardtype.reg_type & ni_reg_m_series_mask)
4157         {
4158                 s->n_chan = M_SERIES_EEPROM_SIZE;
4159                 s->insn_read = &ni_m_series_eeprom_insn_read;
4160         }else
4161         {
4162                 s->n_chan = 512;
4163                 s->insn_read = &ni_eeprom_insn_read;
4164         }
4165
4166         /* PFI */
4167         s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4168         s->type = COMEDI_SUBD_DIO;
4169         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4170         if(boardtype.reg_type & ni_reg_m_series_mask)
4171         {
4172                 unsigned i;
4173                 s->n_chan = 16;
4174                 ni_writew(s->state, M_Offset_PFI_DO);
4175                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
4176                 {
4177                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
4178                 }
4179         }else
4180         {
4181                 s->n_chan = 10;
4182         }
4183         s->maxdata = 1;
4184         if(boardtype.reg_type & ni_reg_m_series_mask)
4185         {
4186                 s->insn_bits = &ni_pfi_insn_bits;
4187         }
4188         s->insn_config = &ni_pfi_insn_config;
4189         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4190
4191         /* cs5529 calibration adc */
4192         s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4193         if(boardtype.reg_type & ni_reg_67xx_mask)
4194         {
4195                 s->type = COMEDI_SUBD_AI;
4196                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4197                 // one channel for each analog output channel
4198                 s->n_chan = boardtype.n_aochan;
4199                 s->maxdata = (1 << 16) - 1;
4200                 s->range_table = &range_unknown; /* XXX */
4201                 s->insn_read=cs5529_ai_insn_read;
4202                 s->insn_config=NULL;
4203                 init_cs5529(dev);
4204         }else
4205         {
4206                 s->type=COMEDI_SUBD_UNUSED;
4207         }
4208
4209         /* Serial */
4210         s = dev->subdevices + NI_SERIAL_SUBDEV;
4211         s->type=COMEDI_SUBD_SERIAL;
4212         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
4213         s->n_chan=1;
4214         s->maxdata=0xff;
4215         s->insn_config = ni_serial_insn_config;
4216         devpriv->serial_interval_ns = 0;
4217         devpriv->serial_hw_mode = 0;
4218
4219         /* RTSI */
4220         s = dev->subdevices + NI_RTSI_SUBDEV;
4221         s->type = COMEDI_SUBD_DIO;
4222         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4223         s->n_chan = 8;
4224         s->maxdata = 1;
4225         s->insn_bits = ni_rtsi_insn_bits;
4226         s->insn_config = ni_rtsi_insn_config;
4227         ni_rtsi_init(dev);
4228
4229         if(boardtype.reg_type & ni_reg_m_series_mask)
4230         {
4231                 counter_variant = ni_gpct_variant_m_series;
4232         }else
4233         {
4234                 counter_variant = ni_gpct_variant_e_series;
4235         }
4236         devpriv->counter_dev = ni_gpct_device_construct(dev,
4237                 &ni_gpct_write_register, &ni_gpct_read_register,
4238                 counter_variant, NUM_GPCT);
4239         /* General purpose counters */
4240         for(j = 0; j < NUM_GPCT; ++j)
4241         {
4242                 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4243                 s->type = COMEDI_SUBD_COUNTER;
4244                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ /* | SDF_CMD_WRITE */;
4245                 s->n_chan = 3;
4246                 if(boardtype.reg_type & ni_reg_m_series_mask)
4247                         s->maxdata = 0xffffffff;
4248                 else
4249                         s->maxdata = 0xffffff;
4250                 s->insn_read = &ni_gpct_insn_read;
4251                 s->insn_write = &ni_gpct_insn_write;
4252                 s->insn_config = &ni_gpct_insn_config;
4253                 s->do_cmd = &ni_gpct_cmd;
4254                 s->len_chanlist = 1;
4255                 s->do_cmdtest = &ni_gpct_cmdtest;
4256                 s->cancel = &ni_gpct_cancel;
4257                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4258                 s->private = &devpriv->counter_dev->counters[j];
4259
4260                 devpriv->counter_dev->counters[j].chip_index = 0;
4261                 devpriv->counter_dev->counters[j].counter_index = j;
4262                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4263         }
4264
4265         /* Frequency output */
4266         s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4267         s->type = COMEDI_SUBD_COUNTER;
4268         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4269         s->n_chan = 1;
4270         s->maxdata = 0xf;
4271         s->insn_read = &ni_freq_out_insn_read;
4272         s->insn_write = &ni_freq_out_insn_write;
4273         s->insn_config = &ni_freq_out_insn_config;
4274
4275         /* ai configuration */
4276         ni_ai_reset(dev,dev->subdevices + NI_AI_SUBDEV);
4277         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
4278                 // BEAM is this needed for PCI-6143 ??
4279                 devpriv->clock_and_fout =
4280                         Slow_Internal_Time_Divide_By_2 |
4281                         Slow_Internal_Timebase |
4282                         Clock_To_Board_Divide_By_2 |
4283                         Clock_To_Board |
4284                         AI_Output_Divide_By_2 |
4285                         AO_Output_Divide_By_2;
4286         }else{
4287                 devpriv->clock_and_fout =
4288                         Slow_Internal_Time_Divide_By_2 |
4289                         Slow_Internal_Timebase |
4290                         Clock_To_Board_Divide_By_2 |
4291                         Clock_To_Board;
4292         }
4293         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
4294
4295         /* analog output configuration */
4296         ni_ao_reset(dev,dev->subdevices + NI_AO_SUBDEV);
4297
4298         if(dev->irq){
4299                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
4300                         (Interrupt_Output_On_3_Pins&0) |
4301                         Interrupt_A_Enable |
4302                         Interrupt_B_Enable |
4303                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
4304                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
4305                         Interrupt_Control_Register
4306                 );
4307         }
4308
4309         /* DMA setup */
4310         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4311         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4312
4313         if(boardtype.reg_type & ni_reg_6xxx_mask)
4314         {
4315                 ni_writeb( 0, Magic_611x );
4316         }else if(boardtype.reg_type & ni_reg_m_series_mask)
4317         {
4318                 int channel;
4319                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
4320                 {
4321                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4322                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
4323                 }
4324                 ni_writeb(0x0, M_Offset_AO_Calibration);
4325         }
4326
4327         printk("\n");
4328         return 0;
4329 }
4330
4331
4332
4333 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
4334 {
4335         comedi_device *dev=(comedi_device *)arg;
4336
4337         if(dir){
4338                 ni_writeb(data,Port_A+2*port);
4339                 return 0;
4340         }else{
4341                 return ni_readb(Port_A+2*port);
4342         }
4343 }
4344
4345 /*
4346         presents the EEPROM as a subdevice
4347 */
4348
4349 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
4350         comedi_insn *insn,lsampl_t *data)
4351 {
4352         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
4353
4354         return 1;
4355 }
4356
4357 /*
4358         reads bytes out of eeprom
4359 */
4360
4361 static int ni_read_eeprom(comedi_device *dev,int addr)
4362 {
4363         int bit;
4364         int bitstring;
4365
4366         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
4367         ni_writeb(0x04,Serial_Command);
4368         for(bit=0x8000;bit;bit>>=1){
4369                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
4370                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
4371         }
4372         bitstring=0;
4373         for(bit=0x80;bit;bit>>=1){
4374                 ni_writeb(0x04,Serial_Command);
4375                 ni_writeb(0x05,Serial_Command);
4376                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
4377         }
4378         ni_writeb(0x00,Serial_Command);
4379
4380         return bitstring;
4381 }
4382
4383 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
4384         comedi_insn *insn,lsampl_t *data)
4385 {
4386         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4387
4388         return 1;
4389 }
4390
4391 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
4392 {
4393         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4394         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4395         return 3;
4396 }
4397
4398 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
4399         comedi_insn *insn, lsampl_t *data)
4400 {
4401         unsigned up_count, down_count;
4402         switch(data[0])
4403         {
4404         case INSN_CONFIG_PWM_OUTPUT:
4405                 switch(data[1])
4406                 {
4407                 case TRIG_ROUND_NEAREST:
4408                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
4409                         break;
4410                 case TRIG_ROUND_DOWN:
4411                         up_count = data[2] / devpriv->clock_ns;
4412                         break;
4413                 case TRIG_ROUND_UP:
4414                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
4415                         break;
4416                 default:
4417                         return -EINVAL;
4418                         break;
4419                 }
4420                 switch(data[3])
4421                 {
4422                 case TRIG_ROUND_NEAREST:
4423                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
4424                         break;
4425                 case TRIG_ROUND_DOWN:
4426                         down_count = data[4] / devpriv->clock_ns;
4427                         break;
4428                 case TRIG_ROUND_UP:
4429                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
4430                         break;
4431                 default:
4432                         return -EINVAL;
4433                         break;
4434                 }
4435                 if(up_count * devpriv->clock_ns != data[2] ||
4436                         down_count * devpriv->clock_ns != data[4])
4437                 {
4438                         data[2] = up_count * devpriv->clock_ns;
4439                         data[4] = down_count * devpriv->clock_ns;
4440                         return -EAGAIN;
4441                 }
4442                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
4443                 devpriv->pwm_up_count = up_count;
4444                 devpriv->pwm_down_count = down_count;
4445                 return 5;
4446                 break;
4447         case INSN_CONFIG_GET_PWM_OUTPUT:
4448                 return ni_get_pwm_config(dev, data);
4449                 break;
4450         default:
4451                 return -EINVAL;
4452                 break;
4453         }
4454         return 0;
4455 }
4456
4457 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
4458         comedi_insn *insn, lsampl_t *data)
4459 {
4460         unsigned up_count, down_count;
4461         switch(data[0])
4462         {
4463         case INSN_CONFIG_PWM_OUTPUT:
4464                 switch(data[1])
4465                 {
4466                 case TRIG_ROUND_NEAREST:
4467                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
4468                         break;
4469                 case TRIG_ROUND_DOWN:
4470                         up_count = data[2] / devpriv->clock_ns;
4471                         break;
4472                 case TRIG_ROUND_UP:
4473                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
4474                         break;
4475                 default:
4476                         return -EINVAL;
4477                         break;
4478                 }
4479                 switch(data[3])
4480                 {
4481                 case TRIG_ROUND_NEAREST:
4482                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
4483                         break;
4484                 case TRIG_ROUND_DOWN:
4485                         down_count = data[4] / devpriv->clock_ns;
4486                         break;
4487                 case TRIG_ROUND_UP:
4488                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
4489                         break;
4490                 default:
4491                         return -EINVAL;
4492                         break;
4493                 }
4494                 if(up_count * devpriv->clock_ns != data[2] ||
4495                         down_count * devpriv->clock_ns != data[4])
4496                 {
4497                         data[2] = up_count * devpriv->clock_ns;
4498                         data[4] = down_count * devpriv->clock_ns;
4499                         return -EAGAIN;
4500                 }
4501                 ni_writel(up_count, Calibration_HighTime_6143);
4502                 devpriv->pwm_up_count = up_count;
4503                 ni_writel(down_count, Calibration_LowTime_6143);
4504                 devpriv->pwm_down_count = down_count;
4505                 return 5;
4506                 break;
4507         case INSN_CONFIG_GET_PWM_OUTPUT:
4508                 return ni_get_pwm_config(dev, data);
4509         default:
4510                 return -EINVAL;
4511                 break;
4512         }
4513         return 0;
4514 }
4515
4516 static void ni_write_caldac(comedi_device *dev,int addr,int val);
4517 /*
4518         calibration subdevice
4519 */
4520 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
4521         comedi_insn *insn,lsampl_t *data)
4522 {
4523         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
4524
4525         return 1;
4526 }
4527
4528 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
4529         comedi_insn *insn,lsampl_t *data)
4530 {
4531         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4532
4533         return 1;
4534 }
4535
4536 static int pack_mb88341(int addr,int val,int *bitstring);
4537 static int pack_dac8800(int addr,int val,int *bitstring);
4538 static int pack_dac8043(int addr,int val,int *bitstring);
4539 static int pack_ad8522(int addr,int val,int *bitstring);
4540 static int pack_ad8804(int addr,int val,int *bitstring);
4541 static int pack_ad8842(int addr,int val,int *bitstring);
4542
4543 struct caldac_struct{
4544         int n_chans;
4545         int n_bits;
4546         int (*packbits)(int,int,int *);
4547 };
4548
4549 static struct caldac_struct caldacs[] = {
4550         [mb88341] = { 12, 8, pack_mb88341 },
4551         [dac8800] = { 8, 8, pack_dac8800 },
4552         [dac8043] = { 1, 12, pack_dac8043 },
4553         [ad8522]  = { 2, 12, pack_ad8522 },
4554         [ad8804] = { 12, 8, pack_ad8804 },
4555         [ad8842] = { 8, 8, pack_ad8842 },
4556         [ad8804_debug] = { 16, 8, pack_ad8804 },
4557 };
4558
4559 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
4560 {
4561         int i,j;
4562         int n_dacs;
4563         int n_chans=0;
4564         int n_bits;
4565         int diffbits=0;
4566         int type;
4567         int chan;
4568
4569         type = boardtype.caldac[0];
4570         if(type==caldac_none)return;
4571         n_bits=caldacs[type].n_bits;
4572         for(i=0;i<3;i++){
4573                 type = boardtype.caldac[i];
4574                 if(type==caldac_none)break;
4575                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
4576                 n_chans+=caldacs[type].n_chans;
4577         }
4578         n_dacs=i;
4579         s->n_chan=n_chans;
4580
4581         if(diffbits){
4582                 unsigned int *maxdata_list;
4583
4584                 if(n_chans>MAX_N_CALDACS){
4585                         printk("BUG! MAX_N_CALDACS too small\n");
4586                 }
4587                 s->maxdata_list=maxdata_list=devpriv->caldac_maxdata_list;
4588                 chan=0;
4589                 for(i=0;i<n_dacs;i++){
4590                         type = boardtype.caldac[i];
4591                         for(j=0;j<caldacs[type].n_chans;j++){
4592                                 maxdata_list[chan]=
4593                                         (1<<caldacs[type].n_bits)-1;
4594                                 chan++;
4595                         }
4596                 }
4597
4598                 for( chan = 0; chan < s->n_chan; chan++ )
4599                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
4600         }else{
4601                 type = boardtype.caldac[0];
4602                 s->maxdata=(1<<caldacs[type].n_bits)-1;
4603
4604                 for( chan = 0; chan < s->n_chan; chan++ )
4605                         ni_write_caldac( dev, i, s->maxdata / 2 );
4606         }
4607 }
4608
4609 static void ni_write_caldac(comedi_device *dev,int addr,int val)
4610 {
4611         unsigned int loadbit=0,bits=0,bit,bitstring=0;
4612         int i;
4613         int type;
4614
4615         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4616         if( devpriv->caldacs[ addr ] == val ) return;
4617         devpriv->caldacs[ addr ] = val;
4618
4619         for(i=0;i<3;i++){
4620                 type = boardtype.caldac[i];
4621                 if(type==caldac_none)break;
4622                 if(addr<caldacs[type].n_chans){
4623                         bits=caldacs[type].packbits(addr,val,&bitstring);
4624                         loadbit=SerDacLd(i);
4625                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4626                         break;
4627                 }
4628                 addr-=caldacs[type].n_chans;
4629         }
4630
4631         for(bit=1<<(bits-1);bit;bit>>=1){
4632                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
4633                 comedi_udelay(1);
4634                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
4635                 comedi_udelay(1);
4636         }
4637         ni_writeb(loadbit,Serial_Command);
4638         comedi_udelay(1);
4639         ni_writeb(0,Serial_Command);
4640 }
4641
4642
4643
4644 static int pack_mb88341(int addr,int val,int *bitstring)
4645 {
4646         /*
4647            Fujitsu MB 88341
4648            Note that address bits are reversed.  Thanks to
4649            Ingo Keen for noticing this.
4650
4651            Note also that the 88341 expects address values from
4652            1-12, whereas we use channel numbers 0-11.  The NI
4653            docs use 1-12, also, so be careful here.
4654         */
4655         addr++;
4656         *bitstring=((addr&0x1)<<11) |
4657                   ((addr&0x2)<<9)  |
4658                   ((addr&0x4)<<7)  |
4659                   ((addr&0x8)<<5)  |
4660                   (val&0xff);
4661         return 12;
4662 }
4663
4664 static int pack_dac8800(int addr,int val,int *bitstring)
4665 {
4666         *bitstring=((addr&0x7)<<8)|(val&0xff);
4667         return 11;
4668 }
4669
4670 static int pack_dac8043(int addr,int val,int *bitstring)
4671 {
4672         *bitstring=val&0xfff;
4673         return 12;
4674 }
4675
4676 static int pack_ad8522(int addr,int val,int *bitstring)
4677 {
4678         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
4679         return 16;
4680 }
4681
4682 static int pack_ad8804(int addr,int val,int *bitstring)
4683 {
4684         *bitstring=((addr&0xf)<<8) | (val&0xff);
4685         return 12;
4686 }
4687
4688 static int pack_ad8842(int addr,int val,int *bitstring)
4689 {
4690         *bitstring=((addr+1)<<8) | (val&0xff);
4691         return 12;
4692 }
4693
4694
4695 #if 0
4696 /*
4697  *      Read the GPCTs current value.
4698  */
4699 static int GPCT_G_Watch(comedi_device *dev, int chan)
4700 {
4701         unsigned int hi1,hi2,lo;
4702
4703         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4704         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4705
4706         devpriv->gpct_command[chan] |= G_Save_Trace;
4707         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
4708
4709         /* This procedure is used because the two registers cannot
4710          * be read atomically. */
4711         do{
4712                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4713                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4714                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4715         }while(hi1!=hi2);
4716
4717         return (hi1<<16)|lo;
4718 }
4719
4720 static void GPCT_Reset(comedi_device *dev, int chan)
4721 {
4722         int temp_ack_reg=0;
4723
4724         //printk("GPCT_Reset...");
4725         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4726
4727         switch (chan) {
4728                 case 0:
4729                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4730                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4731                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4732                         temp_ack_reg |= G0_Gate_Error_Confirm;
4733                         temp_ack_reg |= G0_TC_Error_Confirm;
4734                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4735                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4736                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4737
4738                         //problem...this interferes with the other ctr...
4739                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4740                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4741                         break;
4742                 case 1:
4743                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4744                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4745                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4746                         temp_ack_reg |= G1_Gate_Error_Confirm;
4747                         temp_ack_reg |= G1_TC_Error_Confirm;
4748                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4749                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4750                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4751
4752                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4753                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4754                         break;
4755         };
4756
4757         devpriv->gpct_mode[chan] = 0;
4758         devpriv->gpct_input_select[chan] = 0;
4759         devpriv->gpct_command[chan] = 0;
4760
4761         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4762
4763         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4764         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4765         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4766
4767         //printk("exit GPCT_Reset\n");
4768 }
4769
4770 #endif
4771
4772 static int ni_gpct_insn_config(comedi_device *dev, comedi_subdevice *s,
4773         comedi_insn *insn, lsampl_t *data)
4774 {
4775         struct ni_gpct *counter = s->private;
4776         return ni_tio_insn_config(counter, insn, data);
4777 }
4778
4779 static int ni_gpct_insn_read(comedi_device *dev, comedi_subdevice *s,
4780         comedi_insn *insn,lsampl_t *data)
4781 {
4782         struct ni_gpct *counter = s->private;
4783         return ni_tio_rinsn(counter, insn, data);
4784 }
4785
4786 static int ni_gpct_insn_write(comedi_device *dev, comedi_subdevice *s,
4787         comedi_insn *insn, lsampl_t *data)
4788 {
4789         struct ni_gpct *counter = s->private;
4790         return ni_tio_winsn(counter, insn, data);
4791 }
4792
4793 static int ni_gpct_cmd(comedi_device *dev, comedi_subdevice *s)
4794 {
4795         int retval;
4796 #ifdef PCIDMA
4797         struct ni_gpct *counter = s->private;
4798 //      const comedi_cmd *cmd = &s->async->cmd;
4799
4800         retval = ni_request_gpct_mite_channel(dev, counter->counter_index, COMEDI_INPUT);
4801         if(retval)
4802         {
4803                 comedi_error(dev, "no dma channel available for use by counter");
4804                 return retval;
4805         }
4806         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
4807         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4808         retval = ni_tio_cmd(counter, s->async);
4809 #else
4810         retval = -ENOTSUPP;
4811 #endif
4812         return retval;
4813 }
4814
4815 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
4816 {
4817         struct ni_gpct *counter = s->private;
4818
4819         return ni_tio_cmdtest(counter, cmd);
4820 }
4821
4822 static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s)
4823 {
4824         struct ni_gpct *counter = s->private;
4825         int retval;
4826
4827         retval = ni_tio_cancel(counter);
4828         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4829         ni_release_gpct_mite_channel(dev, counter->counter_index);
4830         return retval;
4831 }
4832
4833 /*
4834  *
4835  *  Programmable Function Inputs
4836  *
4837  */
4838
4839 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4840 {
4841         unsigned pfi_reg_index;
4842         unsigned array_offset;
4843         if((source & 0x1f) != source) return -EINVAL;
4844         pfi_reg_index = 1 + chan / 3;
4845         array_offset = pfi_reg_index - 1;
4846         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4847         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4848         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4849         return 2;
4850 }
4851
4852 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4853 {
4854         // pre-m-series boards have fixed signals on pfi pins
4855         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4856         return 2;
4857 }
4858
4859 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4860 {
4861         if(boardtype.reg_type & ni_reg_m_series_mask)
4862                 return ni_m_series_set_pfi_routing(dev, chan, source);
4863         else
4864                 return ni_old_set_pfi_routing(dev, chan, source);
4865 }
4866
4867 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4868 {
4869         const unsigned array_offset = chan / 3;
4870         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4871 }
4872
4873 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4874 {
4875         // pre-m-series boards have fixed signals on pfi pins
4876         switch(chan)
4877         {
4878         case 0:
4879                 return NI_PFI_OUTPUT_AI_START1;
4880                 break;
4881         case 1:
4882                 return NI_PFI_OUTPUT_AI_START2;
4883                 break;
4884         case 2:
4885                 return NI_PFI_OUTPUT_AI_CONVERT;
4886                 break;
4887         case 3:
4888                 return NI_PFI_OUTPUT_G_SRC1;
4889                 break;
4890         case 4:
4891                 return NI_PFI_OUTPUT_G_GATE1;
4892                 break;
4893         case 5:
4894                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4895                 break;
4896         case 6:
4897                 return NI_PFI_OUTPUT_AO_START1;
4898                 break;
4899         case 7:
4900                 return NI_PFI_OUTPUT_AI_START_PULSE;
4901                 break;
4902         case 8:
4903                 return NI_PFI_OUTPUT_G_SRC0;
4904                 break;
4905         case 9:
4906                 return NI_PFI_OUTPUT_G_GATE0;
4907                 break;
4908         default:
4909                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4910                 break;
4911         }
4912         return 0;
4913 }
4914
4915 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4916 {
4917         if(boardtype.reg_type & ni_reg_m_series_mask)
4918                 return ni_m_series_get_pfi_routing(dev, chan);
4919         else
4920                 return ni_old_get_pfi_routing(dev, chan);
4921 }
4922
4923 static int ni_config_filter(comedi_device *dev, unsigned pfi_channel, enum ni_pfi_filter_select filter)
4924 {
4925         unsigned bits;
4926         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4927         {
4928                 return -ENOTSUPP;
4929         }
4930         bits = ni_readl(M_Offset_PFI_Filter);
4931         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
4932         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
4933         ni_writel(bits, M_Offset_PFI_Filter);
4934         return 0;
4935 }
4936
4937 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4938         comedi_insn *insn,lsampl_t *data)
4939 {
4940         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4941         {
4942                 return -ENOTSUPP;
4943         }
4944         if(data[0])
4945         {
4946                 s->state &= ~data[0];
4947                 s->state |= (data[0] & data[1]);
4948                 ni_writew(s->state, M_Offset_PFI_DO);
4949         }
4950         data[1] = ni_readw(M_Offset_PFI_DI);
4951         return 2;
4952 }
4953
4954 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4955         comedi_insn *insn,lsampl_t *data)
4956 {
4957         unsigned int chan;
4958
4959         if(insn->n < 1)return -EINVAL;
4960
4961         chan = CR_CHAN(insn->chanspec);
4962
4963         switch(data[0]){
4964         case COMEDI_OUTPUT:
4965                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4966                 break;
4967         case COMEDI_INPUT:
4968                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4969                 break;
4970         case INSN_CONFIG_DIO_QUERY:
4971                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4972                 return 0;
4973                 break;
4974         case INSN_CONFIG_SET_ROUTING:
4975                 return ni_set_pfi_routing(dev, chan, data[1]);
4976                 break;
4977         case INSN_CONFIG_GET_ROUTING:
4978                 data[1] = ni_get_pfi_routing(dev, chan);
4979                 break;
4980         case INSN_CONFIG_FILTER:
4981                 return ni_config_filter(dev, chan, data[1]);
4982                 break;
4983         default:
4984                 return -EINVAL;
4985         }
4986         return 0;
4987 }
4988
4989 /*
4990  *
4991  *  NI RTSI Bus Functions
4992  *
4993  */
4994 static void ni_rtsi_init(comedi_device *dev)
4995 {
4996         // Initialises the RTSI bus signal switch to a default state
4997
4998         // Set clock mode to internal
4999         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5000         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5001         {
5002                 rt_printk("ni_set_master_clock failed, bug?");
5003         }
5004         // default internal lines routing to RTSI bus lines
5005         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
5006                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
5007                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
5008                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5009         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5010                 RTSI_Trig_A_Output_Register);
5011         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
5012                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
5013                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5014         if(boardtype.reg_type & ni_reg_m_series_mask)
5015                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5016         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5017                 RTSI_Trig_B_Output_Register);
5018
5019         // Sets the source and direction of the 4 on board lines
5020 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5021 }
5022
5023 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
5024         comedi_insn *insn,lsampl_t *data)
5025 {
5026         if(insn->n != 2) return -EINVAL;
5027
5028         data[1] = 0;
5029
5030         return 2;
5031 }
5032
5033 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5034  * given an arbitrary frequency input clock */
5035 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5036         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
5037 {
5038         unsigned div;
5039         unsigned best_div = 1;
5040         static const unsigned max_div = 0x10;
5041         unsigned mult;
5042         unsigned best_mult = 1;
5043         static const unsigned max_mult = 0x100;
5044         static const unsigned pico_per_nano = 1000;
5045
5046         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5047         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5048          * 20 MHz for most timing clocks */
5049         static const unsigned target_picosec = 12500;
5050         static const unsigned fudge_factor_80_to_20Mhz = 4;
5051         int best_period_picosec = 0;
5052         for(div = 1; div <= max_div; ++div)
5053         {
5054                 for(mult = 1; mult <= max_mult; ++mult)
5055                 {
5056                         unsigned new_period_ps = (reference_picosec * div) / mult;
5057                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
5058                         {
5059                                 best_period_picosec = new_period_ps;
5060                                 best_div = div;
5061                                 best_mult = mult;
5062                         }
5063                 }
5064         }
5065         if(best_period_picosec == 0)
5066         {
5067                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
5068                 return -EIO;
5069         }
5070         *freq_divider = best_div;
5071         *freq_multiplier = best_mult;
5072         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
5073         return 0;
5074 }
5075
5076 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
5077 {
5078         if(boardtype.reg_type & ni_reg_m_series_mask) return 8;
5079         else return 7;
5080 }
5081
5082 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
5083 {
5084         static const unsigned min_period_ns = 50;
5085         static const unsigned max_period_ns = 1000;
5086         static const unsigned timeout = 1000;
5087         unsigned pll_control_bits;
5088         unsigned freq_divider;
5089         unsigned freq_multiplier;
5090         unsigned i;
5091         int retval;
5092         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
5093         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
5094         if(period_ns < min_period_ns || period_ns > max_period_ns)
5095         {
5096                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
5097                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
5098                 return -EINVAL;
5099         }
5100         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5101         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
5102         pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5103         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5104         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5105         switch(source)
5106         {
5107         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5108                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5109                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5110                         &freq_multiplier, &devpriv->clock_ns);
5111                 if(retval < 0) return retval;
5112                 break;
5113         case NI_MIO_PLL_PXI10_CLOCK:
5114                 /* pxi clock is 10MHz */
5115                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
5116                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5117                         &freq_multiplier, &devpriv->clock_ns);
5118                 if(retval < 0) return retval;
5119                 break;
5120         default:
5121                 {
5122                         unsigned rtsi_channel;
5123                         static const unsigned max_rtsi_channel = 7;
5124                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
5125                         {
5126                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
5127                                 {
5128                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
5129                                         break;
5130                                 }
5131                         }
5132                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
5133                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5134                                 &freq_multiplier, &devpriv->clock_ns);
5135                         if(retval < 0) return retval;
5136                 }
5137                 break;
5138         }
5139         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5140         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
5141 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
5142 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
5143         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5144         devpriv->clock_source = source;
5145         /* it seems to typically take a few hundred microseconds for PLL to lock */
5146         for(i = 0; i < timeout; ++i)
5147         {
5148                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
5149                 {
5150                         break;
5151                 }
5152                 udelay(1);
5153         }
5154         if(i == timeout)
5155         {
5156                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5157                         __FUNCTION__, source, period_ns);
5158                 return -ETIMEDOUT;
5159         }
5160         return 3;
5161 }
5162
5163 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
5164 {
5165         if(source == NI_MIO_INTERNAL_CLOCK)
5166         {
5167                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5168                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
5169                 devpriv->clock_ns = TIMEBASE_1_NS;
5170                 if(boardtype.reg_type & ni_reg_m_series_mask)
5171                 {
5172                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
5173                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5174                         ni_writew(0, M_Offset_PLL_Control);
5175                 }
5176                 devpriv->clock_source = source;
5177         }else
5178         {
5179                 if(boardtype.reg_type & ni_reg_m_series_mask)
5180                 {
5181                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
5182                 }else
5183                 {
5184                         if(source == NI_MIO_RTSI_CLOCK)
5185                         {
5186                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
5187                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
5188                                 if(devpriv->clock_ns == 0)
5189                                 {
5190                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5191                                                 __FUNCTION__);
5192                                         return -EINVAL;
5193                                 }else
5194                                 {
5195                                         devpriv->clock_ns = period_ns;
5196                                 }
5197                                 devpriv->clock_source = source;
5198                         }else
5199                                 return -EINVAL;
5200                 }
5201         }
5202         return 3;
5203 }
5204
5205 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
5206 {
5207         if(chan >= num_configurable_rtsi_channels(dev))
5208         {
5209                 if(chan == old_RTSI_clock_channel)
5210                 {
5211                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
5212                         else
5213                         {
5214                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5215                                         __FUNCTION__, chan, old_RTSI_clock_channel);
5216                                 return 0;
5217                         }
5218                 }
5219                 return 0;
5220         }
5221         switch(source)
5222         {
5223         case NI_RTSI_OUTPUT_ADR_START1:
5224         case NI_RTSI_OUTPUT_ADR_START2:
5225         case NI_RTSI_OUTPUT_SCLKG:
5226         case NI_RTSI_OUTPUT_DACUPDN:
5227         case NI_RTSI_OUTPUT_DA_START1:
5228         case NI_RTSI_OUTPUT_G_SRC0:
5229         case NI_RTSI_OUTPUT_G_GATE0:
5230         case NI_RTSI_OUTPUT_RGOUT0:
5231         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5232                 return 1;
5233                 break;
5234         case NI_RTSI_OUTPUT_RTSI_OSC:
5235                 if(boardtype.reg_type & ni_reg_m_series_mask)
5236                         return 1;
5237                 else return 0;
5238                 break;
5239         default:
5240                 return 0;
5241                 break;
5242         }
5243 }
5244
5245 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
5246 {
5247         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
5248         if(chan < 4)
5249         {
5250                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5251                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
5252                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5253                         RTSI_Trig_A_Output_Register);
5254         }else if(chan < 8)
5255         {
5256                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5257                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
5258                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5259                         RTSI_Trig_B_Output_Register);
5260         }
5261         return 2;
5262 }
5263
5264 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
5265 {
5266         if(chan < 4)
5267         {
5268                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
5269         }else if(chan < num_configurable_rtsi_channels(dev))
5270         {
5271                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
5272         }else
5273         {
5274                 if(chan == old_RTSI_clock_channel)
5275                         return NI_RTSI_OUTPUT_RTSI_OSC;
5276                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
5277                 return 0;
5278         }
5279 }
5280
5281 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
5282         comedi_insn *insn,lsampl_t *data)
5283 {
5284         unsigned int chan = CR_CHAN(insn->chanspec);
5285         switch(data[0]){
5286         case INSN_CONFIG_DIO_OUTPUT:
5287                 if(chan < num_configurable_rtsi_channels(dev))
5288                 {
5289                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
5290                 }else if(chan == old_RTSI_clock_channel)
5291                 {
5292                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
5293                 }
5294                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
5295                 break;
5296         case INSN_CONFIG_DIO_INPUT:
5297                 if(chan < num_configurable_rtsi_channels(dev))
5298                 {
5299                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
5300                 }else if(chan == old_RTSI_clock_channel)
5301                 {
5302                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
5303                 }
5304                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
5305                 break;
5306         case INSN_CONFIG_DIO_QUERY:
5307                 if(chan < num_configurable_rtsi_channels(dev))
5308                 {
5309                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0)) ?
5310                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5311                 }else if(chan == old_RTSI_clock_channel)
5312                 {
5313                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5314                 }
5315                 return 2;
5316                 break;
5317         case INSN_CONFIG_SET_CLOCK_SRC:
5318                 return ni_set_master_clock(dev, data[1], data[2]);
5319                 break;
5320         case INSN_CONFIG_GET_CLOCK_SRC:
5321                 data[1] = devpriv->clock_source;
5322                 data[2] = devpriv->clock_ns;
5323                 return 3;
5324                 break;
5325         case INSN_CONFIG_SET_ROUTING:
5326                 return ni_set_rtsi_routing(dev, chan, data[1]);
5327                 break;
5328         case INSN_CONFIG_GET_ROUTING:
5329                 data[1] = ni_get_rtsi_routing(dev, chan);
5330                 return 2;
5331                 break;
5332         default:
5333                 return -EINVAL;
5334                 break;
5335         }
5336         return 1;
5337 }
5338
5339 static int cs5529_wait_for_idle(comedi_device *dev)
5340 {
5341         unsigned short status;
5342         const int timeout = HZ;
5343         int i;
5344
5345         for(i = 0; i < timeout; i++)
5346         {
5347                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5348                 if((status & CSS_ADC_BUSY) == 0)
5349                 {
5350                         break;
5351                 }
5352                 set_current_state(TASK_INTERRUPTIBLE);
5353                 if(schedule_timeout(1))
5354                 {
5355                         return -EIO;
5356                 }
5357         }
5358 //printk("looped %i times waiting for idle\n", i);
5359         if(i == timeout)
5360         {
5361                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
5362                 return -ETIME;
5363         }
5364         return 0;
5365 }
5366
5367 static void cs5529_command(comedi_device *dev, unsigned short value)
5368 {
5369         static const int timeout = 100;
5370         int i;
5371
5372         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5373         /* give time for command to start being serially clocked into cs5529.
5374          * this insures that the CSS_ADC_BUSY bit will get properly
5375          * set before we exit this function.
5376         */
5377         for(i = 0; i < timeout; i++)
5378         {
5379                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5380                         break;
5381                 comedi_udelay(1);
5382         }
5383 //printk("looped %i times writing command to cs5529\n", i);
5384         if(i == timeout)
5385         {
5386                 comedi_error(dev, "possible problem - never saw adc go busy?");
5387         }
5388 }
5389
5390 /* write to cs5529 register */
5391 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
5392 {
5393         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
5394         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
5395         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5396         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5397         if(cs5529_wait_for_idle(dev))
5398                 comedi_error(dev, "time or signal in cs5529_config_write()");
5399 }
5400
5401 /* read from cs5529 register */
5402 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
5403 {
5404         unsigned int value;
5405
5406         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5407         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5408         if(cs5529_wait_for_idle(dev))
5409                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5410         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
5411         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5412         return value;
5413 }
5414
5415 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
5416 {
5417         int retval;
5418         unsigned short status;
5419
5420         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5421         retval = cs5529_wait_for_idle(dev);
5422         if(retval)
5423         {
5424                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
5425                 return -ETIME;
5426         }
5427         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5428         if(status & CSS_OSC_DETECT)
5429         {
5430                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5431                 return -EIO;
5432         }
5433         if(status & CSS_OVERRANGE)
5434         {
5435                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5436         }
5437         if(data)
5438         {
5439                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5440                 /* cs5529 returns 16 bit signed data in bipolar mode */
5441                 *data ^= (1 << 15);
5442         }
5443         return 0;
5444 }
5445
5446 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
5447 {
5448         int n, retval;
5449         unsigned short sample;
5450         unsigned int channel_select;
5451         const unsigned int INTERNAL_REF = 0x1000;
5452
5453         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5454          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5455          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5456         if(insn->chanspec & CR_ALT_SOURCE)
5457                 channel_select = INTERNAL_REF;
5458         else
5459                 channel_select = CR_CHAN(insn->chanspec);
5460         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5461
5462         for(n = 0; n < insn->n; n++)
5463         {
5464                 retval = cs5529_do_conversion(dev, &sample);
5465                 if(retval < 0) return retval;
5466                 data[n] = sample;
5467         }
5468         return insn->n;
5469 }
5470
5471 static int init_cs5529(comedi_device *dev)
5472 {
5473         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5474
5475 #if 1
5476         /* do self-calibration */
5477         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
5478         /* need to force a conversion for calibration to run */
5479         cs5529_do_conversion(dev, NULL);
5480 #else
5481         /* force gain calibration to 1 */
5482         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5483         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
5484         if(cs5529_wait_for_idle(dev))
5485                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5486 #endif
5487         if(0)
5488         {
5489                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
5490                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5491                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
5492         }
5493         return 0;
5494 }
5495
5496