comedi/drivers/ni_labpc.c

   1 /*
   2     comedi/drivers/ni_labpc.c
   3     Driver for National Instruments Lab-PC series boards and compatibles
   4     Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 ************************************************************************
  21 */
  22 /*
  23 Driver: ni_labpc
  24 Description: National Instruments Lab-PC (& compatibles)
  25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
  27   Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (pci-1200)
  28 Status: works
  29
  30 Tested with lab-pc-1200.  For the older Lab-PC+, not all input ranges
  31 and analog references will work, the available ranges/arefs will
  32 depend on how you have configured the jumpers on your board
  33 (see your owner's manual).
  34
  35 Kernel-level ISA plug-and-play support for the lab-pc-1200
  36 boards has not
  37 yet been added to the driver, mainly due to the fact that
  38 I don't know the device id numbers.  If you have one
  39 of these boards,
  40 please file a bug report at https://bugs.comedi.org/
  41 so I can get the necessary information from you.
  42
  43 The 1200 series boards have onboard calibration dacs for correcting
  44 analog input/output offsets and gains.  The proper settings for these
  45 caldacs are stored on the board's eeprom.  To read the caldac values
  46 from the eeprom and store them into a file that can be then be used by
  47 comedilib, use the comedi_calibrate program.
  48
  49 Configuration options - ISA boards:
  50   [0] - I/O port base address
  51   [1] - IRQ (optional, required for timed or externally triggered conversions)
  52   [2] - DMA channel (optional)
  53
  54 Configuration options - PCI boards:
  55   [0] - bus (optional)
  56   [1] - slot (optional)
  57
  58 The Lab-pc+ has quirky chanlist requirements
  59 when scanning multiple channels.  Multiple channel scan
  60 sequence must start at highest channel, then decrement down to
  61 channel 0.  The rest of the cards can scan down like lab-pc+ or scan
  62 up from channel zero.  Chanlists consisting of all one channel
  63 are also legal, and allow you to pace conversions in bursts.
  64
  65 */
  66
  67 /*
  68
  69 NI manuals:
  70 341309a (labpc-1200 register manual)
  71 340914a (pci-1200)
  72 320502b (lab-pc+)
  73
  74 */
  75
  76 #undef LABPC_DEBUG
  77 //#define LABPC_DEBUG   // enable debugging messages
  78
  79 #include <linux/comedidev.h>
  80
  81 #include <linux/delay.h>
  82 #include <asm/dma.h>
  83
  84 #include "8253.h"
  85 #include "8255.h"
  86 #include "mite.h"
  87 #include "comedi_fc.h"
  88 #include "ni_labpc.h"
  89
  90 #define LABPC_SIZE           32 // size of io region used by board
  91 #define LABPC_TIMER_BASE            500 // 2 MHz master clock
  92
  93 /* Registers for the lab-pc+ */
  94
  95 //write-only registers
  96 #define COMMAND1_REG    0x0
  97 #define   ADC_GAIN_MASK (0x7 << 4)
  98 #define   ADC_CHAN_BITS(x)      ((x) & 0x7)
  99 #define   ADC_SCAN_EN_BIT       0x80    // enables multi channel scans
 100 #define COMMAND2_REG    0x1
 101 #define   PRETRIG_BIT   0x1     // enable pretriggering (used in conjunction with SWTRIG)
 102 #define   HWTRIG_BIT    0x2     // enable paced conversions on external trigger
 103 #define   SWTRIG_BIT    0x4     // enable paced conversions
 104 #define   CASCADE_BIT   0x8     // use two cascaded counters for pacing
 105 #define   DAC_PACED_BIT(channel)        (0x40 << ((channel) & 0x1))
 106 #define COMMAND3_REG    0x2
 107 #define   DMA_EN_BIT    0x1     // enable dma transfers
 108 #define   DIO_INTR_EN_BIT       0x2     // enable interrupts for 8255
 109 #define   DMATC_INTR_EN_BIT     0x4     // enable dma terminal count interrupt
 110 #define   TIMER_INTR_EN_BIT     0x8     // enable timer interrupt
 111 #define   ERR_INTR_EN_BIT       0x10    // enable error interrupt
 112 #define   ADC_FNE_INTR_EN_BIT   0x20    // enable fifo not empty interrupt
 113 #define ADC_CONVERT_REG 0x3
 114 #define DAC_LSB_REG(channel)    (0x4 + 2 * ((channel) & 0x1))
 115 #define DAC_MSB_REG(channel)    (0x5 + 2 * ((channel) & 0x1))
 116 #define ADC_CLEAR_REG   0x8
 117 #define DMATC_CLEAR_REG 0xa
 118 #define TIMER_CLEAR_REG 0xc
 119 #define COMMAND6_REG    0xe     // 1200 boards only
 120 #define   ADC_COMMON_BIT        0x1     // select ground or common-mode reference
 121 #define   ADC_UNIP_BIT  0x2     // adc unipolar
 122 #define   DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))      // dac unipolar
 123 #define   ADC_FHF_INTR_EN_BIT   0x20    // enable fifo half full interrupt
 124 #define   A1_INTR_EN_BIT        0x40    // enable interrupt on end of hardware count
 125 #define   ADC_SCAN_UP_BIT 0x80  // scan up from channel zero instead of down to zero
 126 #define COMMAND4_REG    0xf
 127 #define   INTERVAL_SCAN_EN_BIT  0x1     // enables 'interval' scanning
 128 #define   EXT_SCAN_EN_BIT       0x2     // enables external signal on counter b1 output to trigger scan
 129 #define   EXT_CONVERT_OUT_BIT   0x4     // chooses direction (output or input) for EXTCONV* line
 130 #define   ADC_DIFF_BIT  0x8     // chooses differential inputs for adc (in conjunction with board jumper)
 131 #define   EXT_CONVERT_DISABLE_BIT       0x10
 132 #define COMMAND5_REG    0x1c    // 1200 boards only, calibration stuff
 133 #define   EEPROM_WRITE_UNPROTECT_BIT    0x4     // enable eeprom for write
 134 #define   DITHER_EN_BIT 0x8     // enable dithering
 135 #define   CALDAC_LOAD_BIT       0x10    // load calibration dac
 136 #define   SCLOCK_BIT    0x20    // serial clock - rising edge writes, falling edge reads
 137 #define   SDATA_BIT     0x40    // serial data bit for writing to eeprom or calibration dacs
 138 #define   EEPROM_EN_BIT 0x80    // enable eeprom for read/write
 139 #define INTERVAL_COUNT_REG      0x1e
 140 #define INTERVAL_LOAD_REG       0x1f
 141 #define   INTERVAL_LOAD_BITS    0x1
 142
 143 // read-only registers
 144 #define STATUS1_REG     0x0
 145 #define   DATA_AVAIL_BIT        0x1     // data is available in fifo
 146 #define   OVERRUN_BIT   0x2     // overrun has occurred
 147 #define   OVERFLOW_BIT  0x4     // fifo overflow
 148 #define   TIMER_BIT     0x8     // timer interrupt has occured
 149 #define   DMATC_BIT     0x10    // dma terminal count has occured
 150 #define   EXT_TRIG_BIT  0x40    // external trigger has occured
 151 #define STATUS2_REG     0x1d    // 1200 boards only
 152 #define   EEPROM_OUT_BIT        0x1     // programmable eeprom serial output
 153 #define   A1_TC_BIT     0x2     // counter A1 terminal count
 154 #define   FNHF_BIT      0x4     // fifo not half full
 155 #define ADC_FIFO_REG    0xa
 156
 157 #define DIO_BASE_REG    0x10
 158 #define COUNTER_A_BASE_REG      0x14
 159 #define COUNTER_A_CONTROL_REG   (COUNTER_A_BASE_REG + 0x3)
 160 #define   INIT_A0_BITS  0x14    // check modes put conversion pacer output in harmless state (a0 mode 2)
 161 #define   INIT_A1_BITS  0x70    // put hardware conversion counter output in harmless state (a1 mode 0)
 162 #define COUNTER_B_BASE_REG      0x18
 163
 164 static int labpc_attach(comedi_device * dev, comedi_devconfig * it);
 165 static int labpc_cancel(comedi_device * dev, comedi_subdevice * s);
 166 static irqreturn_t labpc_interrupt(int irq, void *d PT_REGS_ARG);
 167 static int labpc_drain_fifo(comedi_device * dev);
 168 static void labpc_drain_dma(comedi_device * dev);
 169 static void handle_isa_dma(comedi_device * dev);
 170 static void labpc_drain_dregs(comedi_device * dev);
 171 static int labpc_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
 172         comedi_cmd * cmd);
 173 static int labpc_ai_cmd(comedi_device * dev, comedi_subdevice * s);
 174 static int labpc_ai_rinsn(comedi_device * dev, comedi_subdevice * s,
 175         comedi_insn * insn, lsampl_t * data);
 176 static int labpc_ao_winsn(comedi_device * dev, comedi_subdevice * s,
 177         comedi_insn * insn, lsampl_t * data);
 178 static int labpc_ao_rinsn(comedi_device * dev, comedi_subdevice * s,
 179         comedi_insn * insn, lsampl_t * data);
 180 static int labpc_calib_read_insn(comedi_device * dev, comedi_subdevice * s,
 181         comedi_insn * insn, lsampl_t * data);
 182 static int labpc_calib_write_insn(comedi_device * dev, comedi_subdevice * s,
 183         comedi_insn * insn, lsampl_t * data);
 184 static int labpc_eeprom_read_insn(comedi_device * dev, comedi_subdevice * s,
 185         comedi_insn * insn, lsampl_t * data);
 186 static int labpc_eeprom_write_insn(comedi_device * dev, comedi_subdevice * s,
 187         comedi_insn * insn, lsampl_t * data);
 188 static unsigned int labpc_suggest_transfer_size(comedi_cmd cmd);
 189 static void labpc_adc_timing(comedi_device * dev, comedi_cmd * cmd);
 190 static struct mite_struct *labpc_find_device(int bus, int slot);
 191 static int labpc_dio_mem_callback(int dir, int port, int data,
 192         unsigned long arg);
 193 static void labpc_serial_out(comedi_device * dev, unsigned int value,
 194         unsigned int num_bits);
 195 static unsigned int labpc_serial_in(comedi_device * dev);
 196 static unsigned int labpc_eeprom_read(comedi_device * dev,
 197         unsigned int address);
 198 static unsigned int labpc_eeprom_read_status(comedi_device * dev);
 199 static unsigned int labpc_eeprom_write(comedi_device * dev,
 200         unsigned int address, unsigned int value);
 201 static void write_caldac(comedi_device * dev, unsigned int channel,
 202         unsigned int value);
 203
 204 enum scan_mode {
 205         MODE_SINGLE_CHAN,
 206         MODE_SINGLE_CHAN_INTERVAL,
 207         MODE_MULT_CHAN_UP,
 208         MODE_MULT_CHAN_DOWN,
 209 };
 210
 211 //analog input ranges
 212 #define NUM_LABPC_PLUS_AI_RANGES 16
 213 // indicates unipolar ranges
 214 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
 215         0,
 216         0,
 217         0,
 218         0,
 219         0,
 220         0,
 221         0,
 222         0,
 223         1,
 224         1,
 225         1,
 226         1,
 227         1,
 228         1,
 229         1,
 230         1,
 231 };
 232
 233 // map range index to gain bits
 234 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
 235         0x00,
 236         0x10,
 237         0x20,
 238         0x30,
 239         0x40,
 240         0x50,
 241         0x60,
 242         0x70,
 243         0x00,
 244         0x10,
 245         0x20,
 246         0x30,
 247         0x40,
 248         0x50,
 249         0x60,
 250         0x70,
 251 };
 252 static const comedi_lrange range_labpc_plus_ai = {
 253         NUM_LABPC_PLUS_AI_RANGES,
 254         {
 255                         BIP_RANGE(5),
 256                         BIP_RANGE(4),
 257                         BIP_RANGE(2.5),
 258                         BIP_RANGE(1),
 259                         BIP_RANGE(0.5),
 260                         BIP_RANGE(0.25),
 261                         BIP_RANGE(0.1),
 262                         BIP_RANGE(0.05),
 263                         UNI_RANGE(10),
 264                         UNI_RANGE(8),
 265                         UNI_RANGE(5),
 266                         UNI_RANGE(2),
 267                         UNI_RANGE(1),
 268                         UNI_RANGE(0.5),
 269                         UNI_RANGE(0.2),
 270                         UNI_RANGE(0.1),
 271                 }
 272 };
 273
 274 #define NUM_LABPC_1200_AI_RANGES 14
 275 // indicates unipolar ranges
 276 static const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
 277         0,
 278         0,
 279         0,
 280         0,
 281         0,
 282         0,
 283         0,
 284         1,
 285         1,
 286         1,
 287         1,
 288         1,
 289         1,
 290         1,
 291 };
 292
 293 // map range index to gain bits
 294 static const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
 295         0x00,
 296         0x20,
 297         0x30,
 298         0x40,
 299         0x50,
 300         0x60,
 301         0x70,
 302         0x00,
 303         0x20,
 304         0x30,
 305         0x40,
 306         0x50,
 307         0x60,
 308         0x70,
 309 };
 310 static const comedi_lrange range_labpc_1200_ai = {
 311         NUM_LABPC_1200_AI_RANGES,
 312         {
 313                         BIP_RANGE(5),
 314                         BIP_RANGE(2.5),
 315                         BIP_RANGE(1),
 316                         BIP_RANGE(0.5),
 317                         BIP_RANGE(0.25),
 318                         BIP_RANGE(0.1),
 319                         BIP_RANGE(0.05),
 320                         UNI_RANGE(10),
 321                         UNI_RANGE(5),
 322                         UNI_RANGE(2),
 323                         UNI_RANGE(1),
 324                         UNI_RANGE(0.5),
 325                         UNI_RANGE(0.2),
 326                         UNI_RANGE(0.1),
 327                 }
 328 };
 329
 330 //analog output ranges
 331 #define AO_RANGE_IS_UNIPOLAR 0x1
 332 static const comedi_lrange range_labpc_ao = {
 333         2,
 334         {
 335                         BIP_RANGE(5),
 336                         UNI_RANGE(10),
 337                 }
 338 };
 339
 340 /* functions that do inb/outb and readb/writeb so we can use
 341  * function pointers to decide which to use */
 342 static inline unsigned int labpc_inb(unsigned long address)
 343 {
 344         return inb(address);
 345 }
 346 static inline void labpc_outb(unsigned int byte, unsigned long address)
 347 {
 348         outb(byte, address);
 349 }
 350 static inline unsigned int labpc_readb(unsigned long address)
 351 {
 352         return readb((void *)address);
 353 }
 354 static inline void labpc_writeb(unsigned int byte, unsigned long address)
 355 {
 356         writeb(byte, (void *)address);
 357 }
 358
 359 static const labpc_board labpc_boards[] = {
 360         {
 361               name:     "lab-pc-1200",
 362               ai_speed:10000,
 363               bustype:  isa_bustype,
 364               register_layout:labpc_1200_layout,
 365               has_ao:   1,
 366               ai_range_table:&range_labpc_1200_ai,
 367               ai_range_code:labpc_1200_ai_gain_bits,
 368               ai_range_is_unipolar:labpc_1200_is_unipolar,
 369               ai_scan_up:1,
 370               memory_mapped_io:0,
 371                 },
 372         {
 373               name:     "lab-pc-1200ai",
 374               ai_speed:10000,
 375               bustype:  isa_bustype,
 376               register_layout:labpc_1200_layout,
 377               has_ao:   0,
 378               ai_range_table:&range_labpc_1200_ai,
 379               ai_range_code:labpc_1200_ai_gain_bits,
 380               ai_range_is_unipolar:labpc_1200_is_unipolar,
 381               ai_scan_up:1,
 382               memory_mapped_io:0,
 383                 },
 384         {
 385               name:     "lab-pc+",
 386               ai_speed:12000,
 387               bustype:  isa_bustype,
 388               register_layout:labpc_plus_layout,
 389               has_ao:   1,
 390               ai_range_table:&range_labpc_plus_ai,
 391               ai_range_code:labpc_plus_ai_gain_bits,
 392               ai_range_is_unipolar:labpc_plus_is_unipolar,
 393               ai_scan_up:0,
 394               memory_mapped_io:0,
 395                 },
 396         {
 397               name:     "pci-1200",
 398               device_id:0x161,
 399               ai_speed:10000,
 400               bustype:  pci_bustype,
 401               register_layout:labpc_1200_layout,
 402               has_ao:   1,
 403               ai_range_table:&range_labpc_1200_ai,
 404               ai_range_code:labpc_1200_ai_gain_bits,
 405               ai_range_is_unipolar:labpc_1200_is_unipolar,
 406               ai_scan_up:1,
 407               memory_mapped_io:1,
 408                 },
 409 };
 410
 411 const labpc_board labpc_cs_boards[NUM_LABPC_CS_BOARDS] = {
 412         {
 413               name:     "daqcard-1200",
 414               device_id:0x103,  // 0x10b is manufacturer id, 0x103 is device id
 415               ai_speed:10000,
 416               bustype:  pcmcia_bustype,
 417               register_layout:labpc_1200_layout,
 418               has_ao:   1,
 419               ai_range_table:&range_labpc_1200_ai,
 420               ai_range_code:labpc_1200_ai_gain_bits,
 421               ai_range_is_unipolar:labpc_1200_is_unipolar,
 422               ai_scan_up:0,
 423               memory_mapped_io:0,
 424                 },
 425         /* duplicate entry, to support using alternate name */
 426         {
 427               name:     "ni_labpc_cs",
 428               device_id:0x103,
 429               ai_speed:10000,
 430               bustype:  pcmcia_bustype,
 431               register_layout:labpc_1200_layout,
 432               has_ao:   1,
 433               ai_range_table:&range_labpc_1200_ai,
 434               ai_range_code:labpc_1200_ai_gain_bits,
 435               ai_range_is_unipolar:labpc_1200_is_unipolar,
 436               ai_scan_up:0,
 437               memory_mapped_io:0,
 438                 },
 439 };
 440
 441 /*
 442  * Useful for shorthand access to the particular board structure
 443  */
 444 #define thisboard ((labpc_board *)dev->board_ptr)
 445
 446 static const int dma_buffer_size = 0xff00;      // size in bytes of dma buffer
 447 static const int sample_size = 2;       // 2 bytes per sample
 448
 449 #define devpriv ((labpc_private *)dev->private)
 450
 451 static comedi_driver driver_labpc = {
 452       driver_name:"ni_labpc",
 453       module:THIS_MODULE,
 454       attach:labpc_attach,
 455       detach:labpc_common_detach,
 456       num_names:sizeof(labpc_boards) / sizeof(labpc_board),
 457       board_name:&labpc_boards[0].name,
 458       offset:sizeof(labpc_board),
 459 };
 460
 461 static struct pci_device_id labpc_pci_table[] __devinitdata = {
 462         {PCI_VENDOR_ID_NATINST, 0x161, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 463         {0}
 464 };
 465
 466 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
 467
 468 static inline int labpc_counter_load(comedi_device * dev,
 469         unsigned long base_address, unsigned int counter_number,
 470         unsigned int count, unsigned int mode)
 471 {
 472         if (thisboard->memory_mapped_io)
 473                 return i8254_mm_load((void *)base_address, 0, counter_number,
 474                         count, mode);
 475         else
 476                 return i8254_load(base_address, 0, counter_number, count, mode);
 477 }
 478
 479 int labpc_common_attach(comedi_device * dev, unsigned long iobase,
 480         unsigned int irq, unsigned int dma_chan)
 481 {
 482         comedi_subdevice *s;
 483         int i;
 484         unsigned long dma_flags, isr_flags;
 485         short lsb, msb;
 486
 487         printk("comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, thisboard->name,
 488                 iobase);
 489         if (irq) {
 490                 printk(", irq %u", irq);
 491         }
 492         if (dma_chan) {
 493                 printk(", dma %u", dma_chan);
 494         }
 495         printk("\n");
 496
 497         if (iobase == 0) {
 498                 printk("io base address is zero!\n");
 499                 return -EINVAL;
 500         }
 501         // request io regions for isa boards
 502         if (thisboard->bustype == isa_bustype) {
 503                 /* check if io addresses are available */
 504                 if (!request_region(iobase, LABPC_SIZE,
 505                                 driver_labpc.driver_name)) {
 506                         printk("I/O port conflict\n");
 507                         return -EIO;
 508                 }
 509         }
 510         dev->iobase = iobase;
 511
 512         if (thisboard->memory_mapped_io) {
 513                 devpriv->read_byte = labpc_readb;
 514                 devpriv->write_byte = labpc_writeb;
 515         } else {
 516                 devpriv->read_byte = labpc_inb;
 517                 devpriv->write_byte = labpc_outb;
 518         }
 519         // initialize board's command registers
 520         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
 521         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 522         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 523         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
 524         if (thisboard->register_layout == labpc_1200_layout) {
 525                 devpriv->write_byte(devpriv->command5_bits,
 526                         dev->iobase + COMMAND5_REG);
 527                 devpriv->write_byte(devpriv->command6_bits,
 528                         dev->iobase + COMMAND6_REG);
 529         }
 530
 531         /* grab our IRQ */
 532         if (irq) {
 533                 isr_flags = 0;
 534                 if (thisboard->bustype == pci_bustype)
 535                         isr_flags |= IRQF_SHARED;
 536                 if (comedi_request_irq(irq, labpc_interrupt, isr_flags,
 537                                 driver_labpc.driver_name, dev)) {
 538                         printk("unable to allocate irq %u\n", irq);
 539                         return -EINVAL;
 540                 }
 541         }
 542         dev->irq = irq;
 543
 544         // grab dma channel
 545         if (dma_chan > 3) {
 546                 printk(" invalid dma channel %u\n", dma_chan);
 547                 return -EINVAL;
 548         } else if (dma_chan) {
 549                 // allocate dma buffer
 550                 devpriv->dma_buffer =
 551                         kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
 552                 if (devpriv->dma_buffer == NULL) {
 553                         printk(" failed to allocate dma buffer\n");
 554                         return -ENOMEM;
 555                 }
 556                 if (request_dma(dma_chan, driver_labpc.driver_name)) {
 557                         printk(" failed to allocate dma channel %u\n",
 558                                 dma_chan);
 559                         return -EINVAL;
 560                 }
 561                 devpriv->dma_chan = dma_chan;
 562                 dma_flags = claim_dma_lock();
 563                 disable_dma(devpriv->dma_chan);
 564                 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
 565                 release_dma_lock(dma_flags);
 566         }
 567
 568         dev->board_name = thisboard->name;
 569
 570         if (alloc_subdevices(dev, 5) < 0)
 571                 return -ENOMEM;
 572
 573         /* analog input subdevice */
 574         s = dev->subdevices + 0;
 575         dev->read_subdev = s;
 576         s->type = COMEDI_SUBD_AI;
 577         s->subdev_flags =
 578                 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF |
 579                 SDF_CMD_READ;
 580         s->n_chan = 8;
 581         s->len_chanlist = 8;
 582         s->maxdata = (1 << 12) - 1;     // 12 bit resolution
 583         s->range_table = thisboard->ai_range_table;
 584         s->do_cmd = labpc_ai_cmd;
 585         s->do_cmdtest = labpc_ai_cmdtest;
 586         s->insn_read = labpc_ai_rinsn;
 587         s->cancel = labpc_cancel;
 588
 589         /* analog output */
 590         s = dev->subdevices + 1;
 591         if (thisboard->has_ao) {
 592 /* Could provide command support, except it only has a one sample
 593  * hardware buffer for analog output and no underrun flag. */
 594                 s->type = COMEDI_SUBD_AO;
 595                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
 596                 s->n_chan = NUM_AO_CHAN;
 597                 s->maxdata = (1 << 12) - 1;     // 12 bit resolution
 598                 s->range_table = &range_labpc_ao;
 599                 s->insn_read = labpc_ao_rinsn;
 600                 s->insn_write = labpc_ao_winsn;
 601                 /* initialize analog outputs to a known value */
 602                 for (i = 0; i < s->n_chan; i++) {
 603                         devpriv->ao_value[i] = s->maxdata / 2;
 604                         lsb = devpriv->ao_value[i] & 0xff;
 605                         msb = (devpriv->ao_value[i] >> 8) & 0xff;
 606                         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
 607                         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
 608                 }
 609         } else {
 610                 s->type = COMEDI_SUBD_UNUSED;
 611         }
 612
 613         /* 8255 dio */
 614         s = dev->subdevices + 2;
 615         // if board uses io memory we have to give a custom callback function to the 8255 driver
 616         if (thisboard->memory_mapped_io)
 617                 subdev_8255_init(dev, s, labpc_dio_mem_callback,
 618                         (unsigned long)(dev->iobase + DIO_BASE_REG));
 619         else
 620                 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
 621
 622         // calibration subdevices for boards that have one
 623         s = dev->subdevices + 3;
 624         if (thisboard->register_layout == labpc_1200_layout) {
 625                 s->type = COMEDI_SUBD_CALIB;
 626                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 627                 s->n_chan = 16;
 628                 s->maxdata = 0xff;
 629                 s->insn_read = labpc_calib_read_insn;
 630                 s->insn_write = labpc_calib_write_insn;
 631
 632                 for (i = 0; i < s->n_chan; i++)
 633                         write_caldac(dev, i, s->maxdata / 2);
 634         } else
 635                 s->type = COMEDI_SUBD_UNUSED;
 636
 637         /* EEPROM */
 638         s = dev->subdevices + 4;
 639         if (thisboard->register_layout == labpc_1200_layout) {
 640                 s->type = COMEDI_SUBD_MEMORY;
 641                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 642                 s->n_chan = EEPROM_SIZE;
 643                 s->maxdata = 0xff;
 644                 s->insn_read = labpc_eeprom_read_insn;
 645                 s->insn_write = labpc_eeprom_write_insn;
 646
 647                 for (i = 0; i < EEPROM_SIZE; i++) {
 648                         devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
 649                 }
 650 #ifdef LABPC_DEBUG
 651                 printk(" eeprom:");
 652                 for (i = 0; i < EEPROM_SIZE; i++) {
 653                         printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
 654                 }
 655                 printk("\n");
 656 #endif
 657         } else
 658                 s->type = COMEDI_SUBD_UNUSED;
 659
 660         return 0;
 661 }
 662
 663 static int labpc_attach(comedi_device * dev, comedi_devconfig * it)
 664 {
 665         unsigned long iobase = 0;
 666         unsigned int irq = 0;
 667         unsigned int dma_chan = 0;
 668         int ret;
 669
 670         /* allocate and initialize dev->private */
 671         if (alloc_private(dev, sizeof(labpc_private)) < 0)
 672                 return -ENOMEM;
 673
 674         // get base address, irq etc. based on bustype
 675         switch (thisboard->bustype) {
 676         case isa_bustype:
 677                 iobase = it->options[0];
 678                 irq = it->options[1];
 679                 dma_chan = it->options[2];
 680                 break;
 681         case pci_bustype:
 682                 devpriv->mite =
 683                         labpc_find_device(it->options[0], it->options[1]);
 684                 if (devpriv->mite == NULL) {
 685                         return -EIO;
 686                 }
 687                 if (thisboard->device_id != mite_device_id(devpriv->mite)) {    // this should never happen since this driver only supports one type of pci board
 688                         printk("bug! mite device id does not match boardtype definition\n");
 689                         return -EINVAL;
 690                 }
 691                 ret = mite_setup(devpriv->mite);
 692                 if (ret < 0)
 693                         return ret;
 694                 iobase = (unsigned long)devpriv->mite->daq_io_addr;
 695                 irq = mite_irq(devpriv->mite);
 696                 break;
 697         case pcmcia_bustype:
 698                 printk(" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
 699                 return -EINVAL;
 700                 break;
 701         default:
 702                 printk("bug! couldn't determine board type\n");
 703                 return -EINVAL;
 704                 break;
 705         }
 706
 707         return labpc_common_attach(dev, iobase, irq, dma_chan);
 708 }
 709
 710 // adapted from ni_pcimio for finding mite based boards (pc-1200)
 711 static struct mite_struct *labpc_find_device(int bus, int slot)
 712 {
 713         struct mite_struct *mite;
 714         int i;
 715         for (mite = mite_devices; mite; mite = mite->next) {
 716                 if (mite->used)
 717                         continue;
 718                 // if bus/slot are specified then make sure we have the right bus/slot
 719                 if (bus || slot) {
 720                         if (bus != mite->pcidev->bus->number
 721                                 || slot != PCI_SLOT(mite->pcidev->devfn))
 722                                 continue;
 723                 }
 724                 for (i = 0; i < driver_labpc.num_names; i++) {
 725                         if (labpc_boards[i].bustype != pci_bustype)
 726                                 continue;
 727                         if (mite_device_id(mite) == labpc_boards[i].device_id) {
 728                                 return mite;
 729                         }
 730                 }
 731         }
 732         printk("no device found\n");
 733         mite_list_devices();
 734         return NULL;
 735 }
 736
 737 int labpc_common_detach(comedi_device * dev)
 738 {
 739         printk("comedi%d: ni_labpc: detach\n", dev->minor);
 740
 741         if (dev->subdevices)
 742                 subdev_8255_cleanup(dev, dev->subdevices + 2);
 743
 744         /* only free stuff if it has been allocated by _attach */
 745         if (devpriv->dma_buffer)
 746                 kfree(devpriv->dma_buffer);
 747         if (devpriv->dma_chan)
 748                 free_dma(devpriv->dma_chan);
 749         if (dev->irq)
 750                 comedi_free_irq(dev->irq, dev);
 751         if (thisboard->bustype == isa_bustype && dev->iobase)
 752                 release_region(dev->iobase, LABPC_SIZE);
 753         if (devpriv->mite)
 754                 mite_unsetup(devpriv->mite);
 755
 756         return 0;
 757 };
 758
 759 static void labpc_clear_adc_fifo(const comedi_device * dev)
 760 {
 761         devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
 762         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 763         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 764 }
 765
 766 static int labpc_cancel(comedi_device * dev, comedi_subdevice * s)
 767 {
 768         unsigned long flags;
 769
 770         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 771         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
 772         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 773         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 774
 775         devpriv->command3_bits = 0;
 776         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 777
 778         return 0;
 779 }
 780
 781 static enum scan_mode labpc_ai_scan_mode(const comedi_cmd * cmd)
 782 {
 783         if (cmd->chanlist_len == 1)
 784                 return MODE_SINGLE_CHAN;
 785
 786         /* chanlist may be NULL during cmdtest. */
 787         if (cmd->chanlist == NULL)
 788                 return MODE_MULT_CHAN_UP;
 789
 790         if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
 791                 return MODE_SINGLE_CHAN_INTERVAL;
 792
 793         if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
 794                 return MODE_MULT_CHAN_UP;
 795
 796         if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
 797                 return MODE_MULT_CHAN_DOWN;
 798
 799         rt_printk("ni_labpc: bug! this should never happen\n");
 800
 801         return 0;
 802 }
 803
 804 static int labpc_ai_chanlist_invalid(const comedi_device * dev,
 805         const comedi_cmd * cmd)
 806 {
 807         int mode, channel, range, aref, i;
 808
 809         if (cmd->chanlist == NULL)
 810                 return 0;
 811
 812         mode = labpc_ai_scan_mode(cmd);
 813
 814         if (mode == MODE_SINGLE_CHAN)
 815                 return 0;
 816
 817         if (mode == MODE_SINGLE_CHAN_INTERVAL) {
 818                 if (cmd->chanlist_len > 0xff) {
 819                         comedi_error(dev,
 820                                 "ni_labpc: chanlist too long for single channel interval mode\n");
 821                         return 1;
 822                 }
 823         }
 824
 825         channel = CR_CHAN(cmd->chanlist[0]);
 826         range = CR_RANGE(cmd->chanlist[0]);
 827         aref = CR_AREF(cmd->chanlist[0]);
 828
 829         for (i = 0; i < cmd->chanlist_len; i++) {
 830
 831                 switch (mode) {
 832                 case MODE_SINGLE_CHAN_INTERVAL:
 833                         if (CR_CHAN(cmd->chanlist[i]) != channel) {
 834                                 comedi_error(dev,
 835                                         "channel scanning order specified in chanlist is not supported by hardware.\n");
 836                                 return 1;
 837                         }
 838                         break;
 839                 case MODE_MULT_CHAN_UP:
 840                         if (CR_CHAN(cmd->chanlist[i]) != i) {
 841                                 comedi_error(dev,
 842                                         "channel scanning order specified in chanlist is not supported by hardware.\n");
 843                                 return 1;
 844                         }
 845                         break;
 846                 case MODE_MULT_CHAN_DOWN:
 847                         if (CR_CHAN(cmd->chanlist[i]) !=
 848                                 cmd->chanlist_len - i - 1) {
 849                                 comedi_error(dev,
 850                                         "channel scanning order specified in chanlist is not supported by hardware.\n");
 851                                 return 1;
 852                         }
 853                         break;
 854                 default:
 855                         rt_printk("ni_labpc: bug! in chanlist check\n");
 856                         return 1;
 857                         break;
 858                 }
 859
 860                 if (CR_RANGE(cmd->chanlist[i]) != range) {
 861                         comedi_error(dev,
 862                                 "entries in chanlist must all have the same range\n");
 863                         return 1;
 864                 }
 865
 866                 if (CR_AREF(cmd->chanlist[i]) != aref) {
 867                         comedi_error(dev,
 868                                 "entries in chanlist must all have the same reference\n");
 869                         return 1;
 870                 }
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int labpc_use_continuous_mode(const comedi_cmd * cmd)
 877 {
 878         if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
 879                 return 1;
 880
 881         if (cmd->scan_begin_src == TRIG_FOLLOW)
 882                 return 1;
 883
 884         return 0;
 885 }
 886
 887 static unsigned int labpc_ai_convert_period(const comedi_cmd * cmd)
 888 {
 889         if (cmd->convert_src != TRIG_TIMER)
 890                 return 0;
 891
 892         if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
 893                 cmd->scan_begin_src == TRIG_TIMER)
 894                 return cmd->scan_begin_arg;
 895
 896         return cmd->convert_arg;
 897 }
 898
 899 static void labpc_set_ai_convert_period(comedi_cmd * cmd, unsigned int ns)
 900 {
 901         if (cmd->convert_src != TRIG_TIMER)
 902                 return;
 903
 904         if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
 905                 cmd->scan_begin_src == TRIG_TIMER) {
 906                 cmd->scan_begin_arg = ns;
 907                 if (cmd->convert_arg > cmd->scan_begin_arg)
 908                         cmd->convert_arg = cmd->scan_begin_arg;
 909         } else
 910                 cmd->convert_arg = ns;
 911 }
 912
 913 static unsigned int labpc_ai_scan_period(const comedi_cmd * cmd)
 914 {
 915         if (cmd->scan_begin_src != TRIG_TIMER)
 916                 return 0;
 917
 918         if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
 919                 cmd->convert_src == TRIG_TIMER)
 920                 return 0;
 921
 922         return cmd->scan_begin_arg;
 923 }
 924
 925 static void labpc_set_ai_scan_period(comedi_cmd * cmd, unsigned int ns)
 926 {
 927         if (cmd->scan_begin_src != TRIG_TIMER)
 928                 return;
 929
 930         if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
 931                 cmd->convert_src == TRIG_TIMER)
 932                 return;
 933
 934         cmd->scan_begin_arg = ns;
 935 }
 936
 937 static int labpc_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
 938         comedi_cmd * cmd)
 939 {
 940         int err = 0;
 941         int tmp, tmp2;
 942         int stop_mask;
 943
 944         /* step 1: make sure trigger sources are trivially valid */
 945
 946         tmp = cmd->start_src;
 947         cmd->start_src &= TRIG_NOW | TRIG_EXT;
 948         if (!cmd->start_src || tmp != cmd->start_src)
 949                 err++;
 950
 951         tmp = cmd->scan_begin_src;
 952         cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
 953         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
 954                 err++;
 955
 956         tmp = cmd->convert_src;
 957         cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
 958         if (!cmd->convert_src || tmp != cmd->convert_src)
 959                 err++;
 960
 961         tmp = cmd->scan_end_src;
 962         cmd->scan_end_src &= TRIG_COUNT;
 963         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
 964                 err++;
 965
 966         tmp = cmd->stop_src;
 967         stop_mask = TRIG_COUNT | TRIG_NONE;
 968         if (thisboard->register_layout == labpc_1200_layout)
 969                 stop_mask |= TRIG_EXT;
 970         cmd->stop_src &= stop_mask;
 971         if (!cmd->stop_src || tmp != cmd->stop_src)
 972                 err++;
 973
 974         if (err)
 975                 return 1;
 976
 977         /* step 2: make sure trigger sources are unique and mutually compatible */
 978
 979         if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
 980                 err++;
 981         if (cmd->scan_begin_src != TRIG_TIMER &&
 982                 cmd->scan_begin_src != TRIG_FOLLOW &&
 983                 cmd->scan_begin_src != TRIG_EXT)
 984                 err++;
 985         if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
 986                 err++;
 987         if (cmd->stop_src != TRIG_COUNT &&
 988                 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
 989                 err++;
 990
 991         // can't have external stop and start triggers at once
 992         if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
 993                 err++;
 994
 995         if (err)
 996                 return 2;
 997
 998         /* step 3: make sure arguments are trivially compatible */
 999
1000         if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1001                 cmd->start_arg = 0;
1002                 err++;
1003         }
1004
1005         if (!cmd->chanlist_len) {
1006                 err++;
1007         }
1008         if (cmd->scan_end_arg != cmd->chanlist_len) {
1009                 cmd->scan_end_arg = cmd->chanlist_len;
1010                 err++;
1011         }
1012
1013         if (cmd->convert_src == TRIG_TIMER) {
1014                 if (cmd->convert_arg < thisboard->ai_speed) {
1015                         cmd->convert_arg = thisboard->ai_speed;
1016                         err++;
1017                 }
1018         }
1019         // make sure scan timing is not too fast
1020         if (cmd->scan_begin_src == TRIG_TIMER) {
1021                 if (cmd->convert_src == TRIG_TIMER &&
1022                         cmd->scan_begin_arg <
1023                         cmd->convert_arg * cmd->chanlist_len) {
1024                         cmd->scan_begin_arg =
1025                                 cmd->convert_arg * cmd->chanlist_len;
1026                         err++;
1027                 }
1028                 if (cmd->scan_begin_arg <
1029                         thisboard->ai_speed * cmd->chanlist_len) {
1030                         cmd->scan_begin_arg =
1031                                 thisboard->ai_speed * cmd->chanlist_len;
1032                         err++;
1033                 }
1034         }
1035         // stop source
1036         switch (cmd->stop_src) {
1037         case TRIG_COUNT:
1038                 if (!cmd->stop_arg) {
1039                         cmd->stop_arg = 1;
1040                         err++;
1041                 }
1042                 break;
1043         case TRIG_NONE:
1044                 if (cmd->stop_arg != 0) {
1045                         cmd->stop_arg = 0;
1046                         err++;
1047                 }
1048                 break;
1049                 // TRIG_EXT doesn't care since it doesn't trigger off a numbered channel
1050         default:
1051                 break;
1052         }
1053
1054         if (err)
1055                 return 3;
1056
1057         /* step 4: fix up any arguments */
1058
1059         tmp = cmd->convert_arg;
1060         tmp2 = cmd->scan_begin_arg;
1061         labpc_adc_timing(dev, cmd);
1062         if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1063                 err++;
1064
1065         if (err)
1066                 return 4;
1067
1068         if (labpc_ai_chanlist_invalid(dev, cmd))
1069                 return 5;
1070
1071         return 0;
1072 }
1073
1074 static int labpc_ai_cmd(comedi_device * dev, comedi_subdevice * s)
1075 {
1076         int channel, range, aref;
1077         unsigned long irq_flags;
1078         int ret;
1079         comedi_async *async = s->async;
1080         comedi_cmd *cmd = &async->cmd;
1081         enum transfer_type xfer;
1082         unsigned long flags;
1083
1084         if (!dev->irq) {
1085                 comedi_error(dev, "no irq assigned, cannot perform command");
1086                 return -1;
1087         }
1088
1089         range = CR_RANGE(cmd->chanlist[0]);
1090         aref = CR_AREF(cmd->chanlist[0]);
1091
1092         // make sure board is disabled before setting up aquisition
1093         comedi_spin_lock_irqsave(&dev->spinlock, flags);
1094         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1095         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1096         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1097
1098         devpriv->command3_bits = 0;
1099         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1100
1101         // initialize software conversion count
1102         if (cmd->stop_src == TRIG_COUNT) {
1103                 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1104         }
1105         // setup hardware conversion counter
1106         if (cmd->stop_src == TRIG_EXT) {
1107                 // load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0
1108                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1109                         1, 3, 0);
1110                 if (ret < 0) {
1111                         comedi_error(dev, "error loading counter a1");
1112                         return -1;
1113                 }
1114         } else                  // otherwise, just put a1 in mode 0 with no count to set its output low
1115                 devpriv->write_byte(INIT_A1_BITS,
1116                         dev->iobase + COUNTER_A_CONTROL_REG);
1117
1118         // figure out what method we will use to transfer data
1119         if (devpriv->dma_chan &&        // need a dma channel allocated
1120                 // dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for
1121                 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1122                 // only available on the isa boards
1123                 thisboard->bustype == isa_bustype) {
1124                 xfer = isa_dma_transfer;
1125         } else if (thisboard->register_layout == labpc_1200_layout &&   // pc-plus has no fifo-half full interrupt
1126                 // wake-end-of-scan should interrupt on fifo not empty
1127                 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1128                 // make sure we are taking more than just a few points
1129                 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1130                 xfer = fifo_half_full_transfer;
1131         } else
1132                 xfer = fifo_not_empty_transfer;
1133         devpriv->current_transfer = xfer;
1134
1135         // setup command6 register for 1200 boards
1136         if (thisboard->register_layout == labpc_1200_layout) {
1137                 // reference inputs to ground or common?
1138                 if (aref != AREF_GROUND)
1139                         devpriv->command6_bits |= ADC_COMMON_BIT;
1140                 else
1141                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1142                 // bipolar or unipolar range?
1143                 if (thisboard->ai_range_is_unipolar[range])
1144                         devpriv->command6_bits |= ADC_UNIP_BIT;
1145                 else
1146                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1147                 // interrupt on fifo half full?
1148                 if (xfer == fifo_half_full_transfer)
1149                         devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1150                 else
1151                         devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1152                 // enable interrupt on counter a1 terminal count?
1153                 if (cmd->stop_src == TRIG_EXT)
1154                         devpriv->command6_bits |= A1_INTR_EN_BIT;
1155                 else
1156                         devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1157                 // are we scanning up or down through channels?
1158                 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1159                         devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1160                 else
1161                         devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1162                 // write to register
1163                 devpriv->write_byte(devpriv->command6_bits,
1164                         dev->iobase + COMMAND6_REG);
1165         }
1166
1167         /* setup channel list, etc (command1 register) */
1168         devpriv->command1_bits = 0;
1169         if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1170                 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1171         else
1172                 channel = CR_CHAN(cmd->chanlist[0]);
1173         // munge channel bits for differential / scan disabled mode
1174         if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1175                 channel *= 2;
1176         devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1177         devpriv->command1_bits |= thisboard->ai_range_code[range];
1178         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1179         // manual says to set scan enable bit on second pass
1180         if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
1181                 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
1182                 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1183                 /* need a brief delay before enabling scan, or scan list will get screwed when you switch
1184                  * between scan up to scan down mode - dunno why */
1185                 comedi_udelay(1);
1186                 devpriv->write_byte(devpriv->command1_bits,
1187                         dev->iobase + COMMAND1_REG);
1188         }
1189         // setup any external triggering/pacing (command4 register)
1190         devpriv->command4_bits = 0;
1191         if (cmd->convert_src != TRIG_EXT)
1192                 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1193         /* XXX should discard first scan when using interval scanning
1194          * since manual says it is not synced with scan clock */
1195         if (labpc_use_continuous_mode(cmd) == 0) {
1196                 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1197                 if (cmd->scan_begin_src == TRIG_EXT)
1198                         devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1199         }
1200         // single-ended/differential
1201         if (aref == AREF_DIFF)
1202                 devpriv->command4_bits |= ADC_DIFF_BIT;
1203         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1204
1205         devpriv->write_byte(cmd->chanlist_len,
1206                 dev->iobase + INTERVAL_COUNT_REG);
1207         // load count
1208         devpriv->write_byte(INTERVAL_LOAD_BITS,
1209                 dev->iobase + INTERVAL_LOAD_REG);
1210
1211         if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1212                 // set up pacing
1213                 labpc_adc_timing(dev, cmd);
1214                 // load counter b0 in mode 3
1215                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1216                         0, devpriv->divisor_b0, 3);
1217                 if (ret < 0) {
1218                         comedi_error(dev, "error loading counter b0");
1219                         return -1;
1220                 }
1221         }
1222         // set up conversion pacing
1223         if (labpc_ai_convert_period(cmd)) {
1224                 // load counter a0 in mode 2
1225                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1226                         0, devpriv->divisor_a0, 2);
1227                 if (ret < 0) {
1228                         comedi_error(dev, "error loading counter a0");
1229                         return -1;
1230                 }
1231         } else
1232                 devpriv->write_byte(INIT_A0_BITS,
1233                         dev->iobase + COUNTER_A_CONTROL_REG);
1234
1235         // set up scan pacing
1236         if (labpc_ai_scan_period(cmd)) {
1237                 // load counter b1 in mode 2
1238                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1239                         1, devpriv->divisor_b1, 2);
1240                 if (ret < 0) {
1241                         comedi_error(dev, "error loading counter b1");
1242                         return -1;
1243                 }
1244         }
1245
1246         labpc_clear_adc_fifo(dev);
1247
1248         // set up dma transfer
1249         if (xfer == isa_dma_transfer) {
1250                 irq_flags = claim_dma_lock();
1251                 disable_dma(devpriv->dma_chan);
1252                 /* clear flip-flop to make sure 2-byte registers for
1253                  * count and address get set correctly */
1254                 clear_dma_ff(devpriv->dma_chan);
1255                 set_dma_addr(devpriv->dma_chan,
1256                         virt_to_bus(devpriv->dma_buffer));
1257                 // set appropriate size of transfer
1258                 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1259                 if (cmd->stop_src == TRIG_COUNT &&
1260                         devpriv->count * sample_size <
1261                         devpriv->dma_transfer_size) {
1262                         devpriv->dma_transfer_size =
1263                                 devpriv->count * sample_size;
1264                 }
1265                 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1266                 enable_dma(devpriv->dma_chan);
1267                 release_dma_lock(irq_flags);
1268                 // enable board's dma
1269                 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1270         } else
1271                 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1272
1273         // enable error interrupts
1274         devpriv->command3_bits |= ERR_INTR_EN_BIT;
1275         // enable fifo not empty interrupt?
1276         if (xfer == fifo_not_empty_transfer)
1277                 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1278         else
1279                 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1280         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1281
1282         // startup aquisition
1283
1284         // command2 reg
1285         // use 2 cascaded counters for pacing
1286         comedi_spin_lock_irqsave(&dev->spinlock, flags);
1287         devpriv->command2_bits |= CASCADE_BIT;
1288         switch (cmd->start_src) {
1289         case TRIG_EXT:
1290                 devpriv->command2_bits |= HWTRIG_BIT;
1291                 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1292                 break;
1293         case TRIG_NOW:
1294                 devpriv->command2_bits |= SWTRIG_BIT;
1295                 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1296                 break;
1297         default:
1298                 comedi_error(dev, "bug with start_src");
1299                 return -1;
1300                 break;
1301         }
1302         switch (cmd->stop_src) {
1303         case TRIG_EXT:
1304                 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1305                 break;
1306         case TRIG_COUNT:
1307         case TRIG_NONE:
1308                 break;
1309         default:
1310                 comedi_error(dev, "bug with stop_src");
1311                 return -1;
1312         }
1313         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1314         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1315
1316         return 0;
1317 }
1318
1319 /* interrupt service routine */
1320 static irqreturn_t labpc_interrupt(int irq, void *d PT_REGS_ARG)
1321 {
1322         comedi_device *dev = d;
1323         comedi_subdevice *s = dev->read_subdev;
1324         comedi_async *async;
1325         comedi_cmd *cmd;
1326
1327         if (dev->attached == 0) {
1328                 comedi_error(dev, "premature interrupt");
1329                 return IRQ_HANDLED;
1330         }
1331
1332         async = s->async;
1333         cmd = &async->cmd;
1334         async->events = 0;
1335
1336         // read board status
1337         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1338         if (thisboard->register_layout == labpc_1200_layout)
1339                 devpriv->status2_bits =
1340                         devpriv->read_byte(dev->iobase + STATUS2_REG);
1341
1342         if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1343                                 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1344                 && (devpriv->status2_bits & A1_TC_BIT) == 0
1345                 && (devpriv->status2_bits & FNHF_BIT)) {
1346                 return IRQ_NONE;
1347         }
1348
1349         if (devpriv->status1_bits & OVERRUN_BIT) {
1350                 // clear error interrupt
1351                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1352                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1353                 comedi_event(dev, s);
1354                 comedi_error(dev, "overrun");
1355                 return IRQ_HANDLED;
1356         }
1357
1358         if (devpriv->current_transfer == isa_dma_transfer) {
1359                 // if a dma terminal count of external stop trigger has occurred
1360                 if (devpriv->status1_bits & DMATC_BIT ||
1361                         (thisboard->register_layout == labpc_1200_layout
1362                                 && devpriv->status2_bits & A1_TC_BIT)) {
1363                         handle_isa_dma(dev);
1364                 }
1365         } else
1366                 labpc_drain_fifo(dev);
1367
1368         if (devpriv->status1_bits & TIMER_BIT) {
1369                 comedi_error(dev, "handled timer interrupt?");
1370                 // clear it
1371                 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1372         }
1373
1374         if (devpriv->status1_bits & OVERFLOW_BIT) {
1375                 // clear error interrupt
1376                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1377                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1378                 comedi_event(dev, s);
1379                 comedi_error(dev, "overflow");
1380                 return IRQ_HANDLED;
1381         }
1382         // handle external stop trigger
1383         if (cmd->stop_src == TRIG_EXT) {
1384                 if (devpriv->status2_bits & A1_TC_BIT) {
1385                         labpc_drain_dregs(dev);
1386                         labpc_cancel(dev, s);
1387                         async->events |= COMEDI_CB_EOA;
1388                 }
1389         }
1390
1391         /* TRIG_COUNT end of acquisition */
1392         if (cmd->stop_src == TRIG_COUNT) {
1393                 if (devpriv->count == 0) {
1394                         labpc_cancel(dev, s);
1395                         async->events |= COMEDI_CB_EOA;
1396                 }
1397         }
1398
1399         comedi_event(dev, s);
1400         return IRQ_HANDLED;
1401 }
1402
1403 // read all available samples from ai fifo
1404 static int labpc_drain_fifo(comedi_device * dev)
1405 {
1406         unsigned int lsb, msb;
1407         sampl_t data;
1408         comedi_async *async = dev->read_subdev->async;
1409         const int timeout = 10000;
1410         unsigned int i;
1411
1412         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1413
1414         for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1415                 i++) {
1416                 // quit if we have all the data we want
1417                 if (async->cmd.stop_src == TRIG_COUNT) {
1418                         if (devpriv->count == 0)
1419                                 break;
1420                         devpriv->count--;
1421                 }
1422                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1423                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1424                 data = (msb << 8) | lsb;
1425                 cfc_write_to_buffer(dev->read_subdev, data);
1426                 devpriv->status1_bits =
1427                         devpriv->read_byte(dev->iobase + STATUS1_REG);
1428         }
1429         if (i == timeout) {
1430                 comedi_error(dev, "ai timeout, fifo never empties");
1431                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1432                 return -1;
1433         }
1434
1435         return 0;
1436 }
1437
1438 static void labpc_drain_dma(comedi_device * dev)
1439 {
1440         comedi_subdevice *s = dev->read_subdev;
1441         comedi_async *async = s->async;
1442         int status;
1443         unsigned long flags;
1444         unsigned int max_points, num_points, residue, leftover;
1445         int i;
1446
1447         status = devpriv->status1_bits;
1448
1449         flags = claim_dma_lock();
1450         disable_dma(devpriv->dma_chan);
1451         /* clear flip-flop to make sure 2-byte registers for
1452          * count and address get set correctly */
1453         clear_dma_ff(devpriv->dma_chan);
1454
1455         // figure out how many points to read
1456         max_points = devpriv->dma_transfer_size / sample_size;
1457         /* residue is the number of points left to be done on the dma
1458          * transfer.  It should always be zero at this point unless
1459          * the stop_src is set to external triggering.
1460          */
1461         residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1462         num_points = max_points - residue;
1463         if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1464                 num_points = devpriv->count;
1465
1466         // figure out how many points will be stored next time
1467         leftover = 0;
1468         if (async->cmd.stop_src != TRIG_COUNT) {
1469                 leftover = devpriv->dma_transfer_size / sample_size;
1470         } else if (devpriv->count > num_points) {
1471                 leftover = devpriv->count - num_points;
1472                 if (leftover > max_points)
1473                         leftover = max_points;
1474         }
1475
1476         /* write data to comedi buffer */
1477         for (i = 0; i < num_points; i++) {
1478                 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1479         }
1480         if (async->cmd.stop_src == TRIG_COUNT)
1481                 devpriv->count -= num_points;
1482
1483         // set address and count for next transfer
1484         set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1485         set_dma_count(devpriv->dma_chan, leftover * sample_size);
1486         release_dma_lock(flags);
1487
1488         async->events |= COMEDI_CB_BLOCK;
1489 }
1490
1491 static void handle_isa_dma(comedi_device * dev)
1492 {
1493         labpc_drain_dma(dev);
1494
1495         enable_dma(devpriv->dma_chan);
1496
1497         // clear dma tc interrupt
1498         devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1499 }
1500
1501 /* makes sure all data aquired by board is transfered to comedi (used
1502  * when aquisition is terminated by stop_src == TRIG_EXT). */
1503 static void labpc_drain_dregs(comedi_device * dev)
1504 {
1505         if (devpriv->current_transfer == isa_dma_transfer)
1506                 labpc_drain_dma(dev);
1507
1508         labpc_drain_fifo(dev);
1509 }
1510
1511 static int labpc_ai_rinsn(comedi_device * dev, comedi_subdevice * s,
1512         comedi_insn * insn, lsampl_t * data)
1513 {
1514         int i, n;
1515         int chan, range;
1516         int lsb, msb;
1517         int timeout = 1000;
1518         unsigned long flags;
1519
1520         // disable timed conversions
1521         comedi_spin_lock_irqsave(&dev->spinlock, flags);
1522         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1523         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1524         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1525
1526         // disable interrupt generation and dma
1527         devpriv->command3_bits = 0;
1528         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1529
1530         /* set gain and channel */
1531         devpriv->command1_bits = 0;
1532         chan = CR_CHAN(insn->chanspec);
1533         range = CR_RANGE(insn->chanspec);
1534         devpriv->command1_bits |= thisboard->ai_range_code[range];
1535         // munge channel bits for differential/scan disabled mode
1536         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1537                 chan *= 2;
1538         devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1539         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1540
1541         // setup command6 register for 1200 boards
1542         if (thisboard->register_layout == labpc_1200_layout) {
1543                 // reference inputs to ground or common?
1544                 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1545                         devpriv->command6_bits |= ADC_COMMON_BIT;
1546                 else
1547                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1548                 // bipolar or unipolar range?
1549                 if (thisboard->ai_range_is_unipolar[range])
1550                         devpriv->command6_bits |= ADC_UNIP_BIT;
1551                 else
1552                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1553                 // don't interrupt on fifo half full
1554                 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1555                 // don't enable interrupt on counter a1 terminal count?
1556                 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1557                 // write to register
1558                 devpriv->write_byte(devpriv->command6_bits,
1559                         dev->iobase + COMMAND6_REG);
1560         }
1561         // setup command4 register
1562         devpriv->command4_bits = 0;
1563         devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1564         // single-ended/differential
1565         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1566                 devpriv->command4_bits |= ADC_DIFF_BIT;
1567         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1568
1569         // initialize pacer counter output to make sure it doesn't cause any problems
1570         devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1571
1572         labpc_clear_adc_fifo(dev);
1573
1574         for (n = 0; n < insn->n; n++) {
1575                 /* trigger conversion */
1576                 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1577
1578                 for (i = 0; i < timeout; i++) {
1579                         if (devpriv->read_byte(dev->iobase +
1580                                         STATUS1_REG) & DATA_AVAIL_BIT)
1581                                 break;
1582                         comedi_udelay(1);
1583                 }
1584                 if (i == timeout) {
1585                         comedi_error(dev, "timeout");
1586                         return -ETIME;
1587                 }
1588                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1589                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1590                 data[n] = (msb << 8) | lsb;
1591         }
1592
1593         return n;
1594 }
1595
1596 // analog output insn
1597 static int labpc_ao_winsn(comedi_device * dev, comedi_subdevice * s,
1598         comedi_insn * insn, lsampl_t * data)
1599 {
1600         int channel, range;
1601         unsigned long flags;
1602         int lsb, msb;
1603
1604         channel = CR_CHAN(insn->chanspec);
1605
1606         // turn off pacing of analog output channel
1607         /* note: hardware bug in daqcard-1200 means pacing cannot
1608          * be independently enabled/disabled for its the two channels */
1609         comedi_spin_lock_irqsave(&dev->spinlock, flags);
1610         devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1611         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1612         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1613
1614         // set range
1615         if (thisboard->register_layout == labpc_1200_layout) {
1616                 range = CR_RANGE(insn->chanspec);
1617                 if (range & AO_RANGE_IS_UNIPOLAR)
1618                         devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1619                 else
1620                         devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1621                 // write to register
1622                 devpriv->write_byte(devpriv->command6_bits,
1623                         dev->iobase + COMMAND6_REG);
1624         }
1625         // send data
1626         lsb = data[0] & 0xff;
1627         msb = (data[0] >> 8) & 0xff;
1628         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1629         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1630
1631         // remember value for readback
1632         devpriv->ao_value[channel] = data[0];
1633
1634         return 1;
1635 }
1636
1637 // analog output readback insn
1638 static int labpc_ao_rinsn(comedi_device * dev, comedi_subdevice * s,
1639         comedi_insn * insn, lsampl_t * data)
1640 {
1641         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1642
1643         return 1;
1644 }
1645
1646 static int labpc_calib_read_insn(comedi_device * dev, comedi_subdevice * s,
1647         comedi_insn * insn, lsampl_t * data)
1648 {
1649         data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1650
1651         return 1;
1652 }
1653
1654 static int labpc_calib_write_insn(comedi_device * dev, comedi_subdevice * s,
1655         comedi_insn * insn, lsampl_t * data)
1656 {
1657         int channel = CR_CHAN(insn->chanspec);
1658
1659         write_caldac(dev, channel, data[0]);
1660         return 1;
1661 }
1662
1663 static int labpc_eeprom_read_insn(comedi_device * dev, comedi_subdevice * s,
1664         comedi_insn * insn, lsampl_t * data)
1665 {
1666         data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1667
1668         return 1;
1669 }
1670
1671 static int labpc_eeprom_write_insn(comedi_device * dev, comedi_subdevice * s,
1672         comedi_insn * insn, lsampl_t * data)
1673 {
1674         int channel = CR_CHAN(insn->chanspec);
1675         int ret;
1676
1677         // only allow writes to user area of eeprom
1678         if (channel < 16 || channel > 127) {
1679                 printk("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
1680                 return -EINVAL;
1681         }
1682
1683         ret = labpc_eeprom_write(dev, channel, data[0]);
1684         if (ret < 0)
1685                 return ret;
1686
1687         return 1;
1688 }
1689
1690 // utility function that suggests a dma transfer size in bytes
1691 static unsigned int labpc_suggest_transfer_size(comedi_cmd cmd)
1692 {
1693         unsigned int size;
1694         unsigned int freq;
1695
1696         if (cmd.convert_src == TRIG_TIMER)
1697                 freq = 1000000000 / cmd.convert_arg;
1698         // return some default value
1699         else
1700                 freq = 0xffffffff;
1701
1702         // make buffer fill in no more than 1/3 second
1703         size = (freq / 3) * sample_size;
1704
1705         // set a minimum and maximum size allowed
1706         if (size > dma_buffer_size)
1707                 size = dma_buffer_size - dma_buffer_size % sample_size;
1708         else if (size < sample_size)
1709                 size = sample_size;
1710
1711         return size;
1712 }
1713
1714 // figures out what counter values to use based on command
1715 static void labpc_adc_timing(comedi_device * dev, comedi_cmd * cmd)
1716 {
1717         const int max_counter_value = 0x10000;  // max value for 16 bit counter in mode 2
1718         const int min_counter_value = 2;        // min value for 16 bit counter in mode 2
1719         unsigned int base_period;
1720
1721         // if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0
1722         if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
1723                 // pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters)
1724                 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
1725                         (LABPC_TIMER_BASE * max_counter_value) + 1;
1726                 if (devpriv->divisor_b0 < min_counter_value)
1727                         devpriv->divisor_b0 = min_counter_value;
1728                 if (devpriv->divisor_b0 > max_counter_value)
1729                         devpriv->divisor_b0 = max_counter_value;
1730
1731                 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1732
1733                 // set a0 for conversion frequency and b1 for scan frequency
1734                 switch (cmd->flags & TRIG_ROUND_MASK) {
1735                 default:
1736                 case TRIG_ROUND_NEAREST:
1737                         devpriv->divisor_a0 =
1738                                 (labpc_ai_convert_period(cmd) +
1739                                 (base_period / 2)) / base_period;
1740                         devpriv->divisor_b1 =
1741                                 (labpc_ai_scan_period(cmd) +
1742                                 (base_period / 2)) / base_period;
1743                         break;
1744                 case TRIG_ROUND_UP:
1745                         devpriv->divisor_a0 =
1746                                 (labpc_ai_convert_period(cmd) + (base_period -
1747                                         1)) / base_period;
1748                         devpriv->divisor_b1 =
1749                                 (labpc_ai_scan_period(cmd) + (base_period -
1750                                         1)) / base_period;
1751                         break;
1752                 case TRIG_ROUND_DOWN:
1753                         devpriv->divisor_a0 =
1754                                 labpc_ai_convert_period(cmd) / base_period;
1755                         devpriv->divisor_b1 =
1756                                 labpc_ai_scan_period(cmd) / base_period;
1757                         break;
1758                 }
1759                 // make sure a0 and b1 values are acceptable
1760                 if (devpriv->divisor_a0 < min_counter_value)
1761                         devpriv->divisor_a0 = min_counter_value;
1762                 if (devpriv->divisor_a0 > max_counter_value)
1763                         devpriv->divisor_a0 = max_counter_value;
1764                 if (devpriv->divisor_b1 < min_counter_value)
1765                         devpriv->divisor_b1 = min_counter_value;
1766                 if (devpriv->divisor_b1 > max_counter_value)
1767                         devpriv->divisor_b1 = max_counter_value;
1768                 // write corrected timings to command
1769                 labpc_set_ai_convert_period(cmd,
1770                         base_period * devpriv->divisor_a0);
1771                 labpc_set_ai_scan_period(cmd,
1772                         base_period * devpriv->divisor_b1);
1773                 // if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions
1774         } else if (labpc_ai_scan_period(cmd)) {
1775                 unsigned int scan_period;
1776
1777                 scan_period = labpc_ai_scan_period(cmd);
1778                 /* calculate cascaded counter values that give desired scan timing */
1779                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1780                         &(devpriv->divisor_b1), &(devpriv->divisor_b0),
1781                         &scan_period, cmd->flags & TRIG_ROUND_MASK);
1782                 labpc_set_ai_scan_period(cmd, scan_period);
1783         } else if (labpc_ai_convert_period(cmd)) {
1784                 unsigned int convert_period;
1785
1786                 convert_period = labpc_ai_convert_period(cmd);
1787                 /* calculate cascaded counter values that give desired conversion timing */
1788                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1789                         &(devpriv->divisor_a0), &(devpriv->divisor_b0),
1790                         &convert_period, cmd->flags & TRIG_ROUND_MASK);
1791                 labpc_set_ai_convert_period(cmd, convert_period);
1792         }
1793 }
1794
1795 static int labpc_dio_mem_callback(int dir, int port, int data,
1796         unsigned long iobase)
1797 {
1798         if (dir) {
1799                 writeb(data, (void *)(iobase + port));
1800                 return 0;
1801         } else {
1802                 return readb((void *)(iobase + port));
1803         }
1804 }
1805
1806 // lowlevel write to eeprom/dac
1807 static void labpc_serial_out(comedi_device * dev, unsigned int value,
1808         unsigned int value_width)
1809 {
1810         int i;
1811
1812         for (i = 1; i <= value_width; i++) {
1813                 // clear serial clock
1814                 devpriv->command5_bits &= ~SCLOCK_BIT;
1815                 // send bits most significant bit first
1816                 if (value & (1 << (value_width - i)))
1817                         devpriv->command5_bits |= SDATA_BIT;
1818                 else
1819                         devpriv->command5_bits &= ~SDATA_BIT;
1820                 comedi_udelay(1);
1821                 devpriv->write_byte(devpriv->command5_bits,
1822                         dev->iobase + COMMAND5_REG);
1823                 // set clock to load bit
1824                 devpriv->command5_bits |= SCLOCK_BIT;
1825                 comedi_udelay(1);
1826                 devpriv->write_byte(devpriv->command5_bits,
1827                         dev->iobase + COMMAND5_REG);
1828         }
1829 }
1830
1831 // lowlevel read from eeprom
1832 static unsigned int labpc_serial_in(comedi_device * dev)
1833 {
1834         unsigned int value = 0;
1835         int i;
1836         const int value_width = 8;      // number of bits wide values are
1837
1838         for (i = 1; i <= value_width; i++) {
1839                 // set serial clock
1840                 devpriv->command5_bits |= SCLOCK_BIT;
1841                 comedi_udelay(1);
1842                 devpriv->write_byte(devpriv->command5_bits,
1843                         dev->iobase + COMMAND5_REG);
1844                 // clear clock bit
1845                 devpriv->command5_bits &= ~SCLOCK_BIT;
1846                 comedi_udelay(1);
1847                 devpriv->write_byte(devpriv->command5_bits,
1848                         dev->iobase + COMMAND5_REG);
1849                 // read bits most significant bit first
1850                 comedi_udelay(1);
1851                 devpriv->status2_bits =
1852                         devpriv->read_byte(dev->iobase + STATUS2_REG);
1853                 if (devpriv->status2_bits & EEPROM_OUT_BIT) {
1854                         value |= 1 << (value_width - i);
1855                 }
1856         }
1857
1858         return value;
1859 }
1860
1861 static unsigned int labpc_eeprom_read(comedi_device * dev, unsigned int address)
1862 {
1863         unsigned int value;
1864         const int read_instruction = 0x3;       // bits to tell eeprom to expect a read
1865         const int write_length = 8;     // 8 bit write lengths to eeprom
1866
1867         // enable read/write to eeprom
1868         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1869         comedi_udelay(1);
1870         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1871         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1872         comedi_udelay(1);
1873         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1874
1875         // send read instruction
1876         labpc_serial_out(dev, read_instruction, write_length);
1877         // send 8 bit address to read from
1878         labpc_serial_out(dev, address, write_length);
1879         // read result
1880         value = labpc_serial_in(dev);
1881
1882         // disable read/write to eeprom
1883         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1884         comedi_udelay(1);
1885         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1886
1887         return value;
1888 }
1889
1890 static unsigned int labpc_eeprom_write(comedi_device * dev,
1891         unsigned int address, unsigned int value)
1892 {
1893         const int write_enable_instruction = 0x6;
1894         const int write_instruction = 0x2;
1895         const int write_length = 8;     // 8 bit write lengths to eeprom
1896         const int write_in_progress_bit = 0x1;
1897         const int timeout = 10000;
1898         int i;
1899
1900         // make sure there isn't already a write in progress
1901         for (i = 0; i < timeout; i++) {
1902                 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1903                         0)
1904                         break;
1905         }
1906         if (i == timeout) {
1907                 comedi_error(dev, "eeprom write timed out");
1908                 return -ETIME;
1909         }
1910         // update software copy of eeprom
1911         devpriv->eeprom_data[address] = value;
1912
1913         // enable read/write to eeprom
1914         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1915         comedi_udelay(1);
1916         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1917         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1918         comedi_udelay(1);
1919         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1920
1921         // send write_enable instruction
1922         labpc_serial_out(dev, write_enable_instruction, write_length);
1923         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1924         comedi_udelay(1);
1925         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1926
1927         // send write instruction
1928         devpriv->command5_bits |= EEPROM_EN_BIT;
1929         comedi_udelay(1);
1930         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1931         labpc_serial_out(dev, write_instruction, write_length);
1932         // send 8 bit address to write to
1933         labpc_serial_out(dev, address, write_length);
1934         // write value
1935         labpc_serial_out(dev, value, write_length);
1936         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1937         comedi_udelay(1);
1938         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1939
1940         // disable read/write to eeprom
1941         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1942         comedi_udelay(1);
1943         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1944
1945         return 0;
1946 }
1947
1948 static unsigned int labpc_eeprom_read_status(comedi_device * dev)
1949 {
1950         unsigned int value;
1951         const int read_status_instruction = 0x5;
1952         const int write_length = 8;     // 8 bit write lengths to eeprom
1953
1954         // enable read/write to eeprom
1955         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1956         comedi_udelay(1);
1957         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1958         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1959         comedi_udelay(1);
1960         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1961
1962         // send read status instruction
1963         labpc_serial_out(dev, read_status_instruction, write_length);
1964         // read result
1965         value = labpc_serial_in(dev);
1966
1967         // disable read/write to eeprom
1968         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1969         comedi_udelay(1);
1970         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1971
1972         return value;
1973 }
1974
1975 // writes to 8 bit calibration dacs
1976 static void write_caldac(comedi_device * dev, unsigned int channel,
1977         unsigned int value)
1978 {
1979         if (value == devpriv->caldac[channel])
1980                 return;
1981         devpriv->caldac[channel] = value;
1982
1983         // clear caldac load bit and make sure we don't write to eeprom
1984         devpriv->command5_bits &=
1985                 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1986         comedi_udelay(1);
1987         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1988
1989         // write 4 bit channel
1990         labpc_serial_out(dev, channel, 4);
1991         // write 8 bit caldac value
1992         labpc_serial_out(dev, value, 8);
1993
1994         // set and clear caldac bit to load caldac value
1995         devpriv->command5_bits |= CALDAC_LOAD_BIT;
1996         comedi_udelay(1);
1997         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1998         devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
1999         comedi_udelay(1);
2000         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2001 }
2002
2003 COMEDI_INITCLEANUP(driver_labpc);
2004
2005 EXPORT_SYMBOL_GPL(labpc_common_attach);
2006 EXPORT_SYMBOL_GPL(labpc_common_detach);
2007 EXPORT_SYMBOL_GPL(labpc_cs_boards);