3 comedi/drivers/me_daq.c
5 Hardware driver for Meilhaus data acquisition cards:
7 ME-2000i, ME-2600i, ME-3000vm1
9 Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Description: Meilhaus PCI data acquisition cards
29 Author: Michael Hillmann <hillmann@syscongroup.de>
30 Devices: [Meilhaus] ME-2600i (me_daq), ME-2000i
37 Configuration options:
39 [0] - PCI bus number (optional)
40 [1] - PCI slot number (optional)
42 If bus/slot is not specified, the first available PCI
45 The 2600 requires a firmware upload, which can be accomplished
46 using the -i or --init-data option of comedi_config.
48 found in the comedi_nonfree_firmware tarball available
49 from http://www.comedi.org
53 #include <linux/sched.h>
54 #include <linux/comedidev.h>
56 #include "comedi_pci.h"
58 //#include "me2600_fw.h"
60 #define ME_DRIVER_NAME "me_daq"
62 #define ME2000_DEVICE_ID 0x2000
63 #define ME2600_DEVICE_ID 0x2600
65 #define PLX_INTCSR 0x4C // PLX interrupt status register
66 #define XILINX_DOWNLOAD_RESET 0x42 // Xilinx registers
68 #define ME_CONTROL_1 0x0000 // - | W
69 #define INTERRUPT_ENABLE (1<<15)
70 #define COUNTER_B_IRQ (1<<12)
71 #define COUNTER_A_IRQ (1<<11)
72 #define CHANLIST_READY_IRQ (1<<10)
73 #define EXT_IRQ (1<<9)
74 #define ADFIFO_HALFFULL_IRQ (1<<8)
75 #define SCAN_COUNT_ENABLE (1<<5)
76 #define SIMULTANEOUS_ENABLE (1<<4)
77 #define TRIGGER_FALLING_EDGE (1<<3)
78 #define CONTINUOUS_MODE (1<<2)
79 #define DISABLE_ADC (0<<0)
80 #define SOFTWARE_TRIGGERED_ADC (1<<0)
81 #define SCAN_TRIGGERED_ADC (2<<0)
82 #define EXT_TRIGGERED_ADC (3<<0)
83 #define ME_ADC_START 0x0000 // R | -
84 #define ME_CONTROL_2 0x0002 // - | W
85 #define ENABLE_ADFIFO (1<<10)
86 #define ENABLE_CHANLIST (1<<9)
87 #define ENABLE_PORT_B (1<<7)
88 #define ENABLE_PORT_A (1<<6)
89 #define ENABLE_COUNTER_B (1<<4)
90 #define ENABLE_COUNTER_A (1<<3)
91 #define ENABLE_DAC (1<<1)
92 #define BUFFERED_DAC (1<<0)
93 #define ME_DAC_UPDATE 0x0002 // R | -
94 #define ME_STATUS 0x0004 // R | -
95 #define COUNTER_B_IRQ_PENDING (1<<12)
96 #define COUNTER_A_IRQ_PENDING (1<<11)
97 #define CHANLIST_READY_IRQ_PENDING (1<<10)
98 #define EXT_IRQ_PENDING (1<<9)
99 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
100 #define ADFIFO_FULL (1<<4)
101 #define ADFIFO_HALFFULL (1<<3)
102 #define ADFIFO_EMPTY (1<<2)
103 #define CHANLIST_FULL (1<<1)
104 #define FST_ACTIVE (1<<0)
105 #define ME_RESET_INTERRUPT 0x0004 // - | W
106 #define ME_DIO_PORT_A 0x0006 // R | W
107 #define ME_DIO_PORT_B 0x0008 // R | W
108 #define ME_TIMER_DATA_0 0x000A // - | W
109 #define ME_TIMER_DATA_1 0x000C // - | W
110 #define ME_TIMER_DATA_2 0x000E // - | W
111 #define ME_CHANNEL_LIST 0x0010 // - | W
112 #define ADC_UNIPOLAR (1<<6)
113 #define ADC_GAIN_0 (0<<4)
114 #define ADC_GAIN_1 (1<<4)
115 #define ADC_GAIN_2 (2<<4)
116 #define ADC_GAIN_3 (3<<4)
117 #define ME_READ_AD_FIFO 0x0010 // R | -
118 #define ME_DAC_CONTROL 0x0012 // - | W
119 #define DAC_UNIPOLAR_D (0<<4)
120 #define DAC_BIPOLAR_D (1<<4)
121 #define DAC_UNIPOLAR_C (0<<5)
122 #define DAC_BIPOLAR_C (1<<5)
123 #define DAC_UNIPOLAR_B (0<<6)
124 #define DAC_BIPOLAR_B (1<<6)
125 #define DAC_UNIPOLAR_A (0<<7)
126 #define DAC_BIPOLAR_A (1<<7)
127 #define DAC_GAIN_0_D (0<<8)
128 #define DAC_GAIN_1_D (1<<8)
129 #define DAC_GAIN_0_C (0<<9)
130 #define DAC_GAIN_1_C (1<<9)
131 #define DAC_GAIN_0_B (0<<10)
132 #define DAC_GAIN_1_B (1<<10)
133 #define DAC_GAIN_0_A (0<<11)
134 #define DAC_GAIN_1_A (1<<11)
135 #define ME_DAC_CONTROL_UPDATE 0x0012 // R | -
136 #define ME_DAC_DATA_A 0x0014 // - | W
137 #define ME_DAC_DATA_B 0x0016 // - | W
138 #define ME_DAC_DATA_C 0x0018 // - | W
139 #define ME_DAC_DATA_D 0x001A // - | W
140 #define ME_COUNTER_ENDDATA_A 0x001C // - | W
141 #define ME_COUNTER_ENDDATA_B 0x001E // - | W
142 #define ME_COUNTER_STARTDATA_A 0x0020 // - | W
143 #define ME_COUNTER_VALUE_A 0x0020 // R | -
144 #define ME_COUNTER_STARTDATA_B 0x0022 // - | W
145 #define ME_COUNTER_VALUE_B 0x0022 // R | -
148 // Function prototypes
151 static int me_attach(comedi_device * dev, comedi_devconfig * it);
152 static int me_detach(comedi_device * dev);
154 static const comedi_lrange me2000_ai_range = {
168 static const comedi_lrange me2600_ai_range = {
182 static const comedi_lrange me2600_ao_range = {
191 static DEFINE_PCI_DEVICE_TABLE(me_pci_table) = {
192 {PCI_VENDOR_ID_MEILHAUS, ME2600_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
194 {PCI_VENDOR_ID_MEILHAUS, ME2000_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
199 MODULE_DEVICE_TABLE(pci, me_pci_table);
202 // Board specification structure
206 const char *name; // driver name
208 int ao_channel_nbr; // DA config
210 int ao_resolution_mask;
211 const comedi_lrange *ao_range_list;
212 int ai_channel_nbr; // AD config
214 int ai_resolution_mask;
215 const comedi_lrange *ai_range_list;
216 int dio_channel_nbr; // DIO config
219 static const me_board_struct me_boards[] = {
221 name: ME_DRIVER_NAME,
222 device_id:ME2600_DEVICE_ID,
223 ao_channel_nbr:4,// Analog Output
225 ao_resolution_mask:0x0fff,
226 ao_range_list:&me2600_ao_range,
230 ai_resolution_mask:0x0fff,
231 ai_range_list:&me2600_ai_range,
235 name: ME_DRIVER_NAME,
236 device_id:ME2000_DEVICE_ID,
237 ao_channel_nbr:0,// Analog Output
239 ao_resolution_mask:0,
244 ai_resolution_mask:0x0fff,
245 ai_range_list:&me2000_ai_range,
250 #define me_board_nbr (sizeof(me_boards)/sizeof(me_board_struct))
252 static comedi_driver me_driver = {
253 driver_name:ME_DRIVER_NAME,
259 COMEDI_PCI_INITCLEANUP(me_driver, me_pci_table);
262 // Private data structure
266 struct pci_dev *pci_device;
267 void *plx_regbase; // PLX configuration base address
268 void *me_regbase; // Base address of the Meilhaus card
269 unsigned long plx_regbase_size; // Size of PLX configuration space
270 unsigned long me_regbase_size; // Size of Meilhaus space
272 unsigned short control_1; // Mirror of CONTROL_1 register
273 unsigned short control_2; // Mirror of CONTROL_2 register
274 unsigned short dac_control; // Mirror of the DAC_CONTROL register
275 int ao_readback[4]; // Mirror of analog output data
277 } me_private_data_struct;
279 #define dev_private ((me_private_data_struct *)dev->private)
281 // ------------------------------------------------------------------
285 // ------------------------------------------------------------------
287 static __inline__ void sleep(unsigned sec)
289 current->state = TASK_INTERRUPTIBLE;
290 schedule_timeout(sec * HZ);
293 // ------------------------------------------------------------------
295 // DIGITAL INPUT/OUTPUT SECTION
297 // ------------------------------------------------------------------
299 static int me_dio_insn_config(comedi_device * dev,
300 comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
303 int mask = 1 << CR_CHAN(insn->chanspec);
306 if (mask & 0x0000ffff) { /* Port A in use */
310 dev_private->control_2 |= ENABLE_PORT_A;
311 writew(dev_private->control_2,
312 dev_private->me_regbase + ME_CONTROL_2);
313 } else { /* Port B in use */
318 dev_private->control_2 |= ENABLE_PORT_B;
319 writew(dev_private->control_2,
320 dev_private->me_regbase + ME_CONTROL_2);
323 if (data[0]) { /* Config port as output */
325 } else { /* Config port as input */
334 // Digital instant input/outputs
337 static int me_dio_insn_bits(comedi_device * dev,
338 comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
340 unsigned int mask = data[0];
342 s->state |= (mask & data[1]);
345 if (mask & 0x0000ffff) { /* Port A */
346 writew((s->state & 0xffff),
347 dev_private->me_regbase + ME_DIO_PORT_A);
349 data[1] &= ~0x0000ffff;
350 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A);
353 if (mask & 0xffff0000) { /* Port B */
354 writew(((s->state >> 16) & 0xffff),
355 dev_private->me_regbase + ME_DIO_PORT_B);
357 data[1] &= ~0xffff0000;
358 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16;
364 // ------------------------------------------------------------------
366 // ANALOG INPUT SECTION
368 // ------------------------------------------------------------------
371 // Analog instant input
373 static int me_ai_insn_read(comedi_device * dev,
374 comedi_subdevice * subdevice, comedi_insn * insn, lsampl_t * data)
376 unsigned short value;
377 int chan = CR_CHAN((&insn->chanspec)[0]);
378 int rang = CR_RANGE((&insn->chanspec)[0]);
379 int aref = CR_AREF((&insn->chanspec)[0]);
385 /* stop any running conversion */
386 dev_private->control_1 &= 0xFFFC;
387 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
389 /* clear chanlist and ad fifo */
390 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
391 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
393 /* reset any pending interrupt */
394 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
396 /* enable the chanlist and ADC fifo */
397 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
398 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
400 /* write to channel list fifo */
401 value = chan & 0x0f; // b3:b0 are the channel number
402 value |= (rang & 0x03) << 4; // b5:b4 are the channel gain
403 value |= (rang & 0x04) << 4; // b6 channel polarity
404 value |= ((aref & AREF_DIFF) ? 0x80 : 0); // b7 single or differential
405 writew(value & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
407 /* set ADC mode to software trigger */
408 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
409 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
411 /* start conversion by reading from ADC_START */
412 readw(dev_private->me_regbase + ME_ADC_START);
414 /* wait for ADC fifo not empty flag */
415 for (i = 100000; i > 0; i--) {
416 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004)) {
421 /* get value from ADC fifo */
424 (readw(dev_private->me_regbase +
425 ME_READ_AD_FIFO) ^ 0x800) & 0x0FFF;
427 printk("comedi%d: Cannot get single value\n", dev->minor);
431 /* stop any running conversion */
432 dev_private->control_1 &= 0xFFFC;
433 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
438 // ------------------------------------------------------------------
440 // HARDWARE TRIGGERED ANALOG INPUT SECTION
442 // ------------------------------------------------------------------
445 // Cancel analog input autoscan
447 static int me_ai_cancel(comedi_device * dev, comedi_subdevice * s)
449 /* disable interrupts */
451 /* stop any running conversion */
452 dev_private->control_1 &= 0xFFFC;
453 writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
459 // Test analog input command
461 static int me_ai_do_cmd_test(comedi_device * dev,
462 comedi_subdevice * s, comedi_cmd * cmd)
468 // Analog input command
470 static int me_ai_do_cmd(comedi_device * dev, comedi_subdevice * subdevice)
475 // ------------------------------------------------------------------
477 // ANALOG OUTPUT SECTION
479 // ------------------------------------------------------------------
482 // Analog instant output
484 static int me_ao_insn_write(comedi_device * dev,
485 comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
492 dev_private->control_2 |= ENABLE_DAC;
493 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
495 /* and set DAC to "buffered" mode */
496 dev_private->control_2 |= BUFFERED_DAC;
497 writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
499 /* Set dac-control register */
500 for (i = 0; i < insn->n; i++) {
501 chan = CR_CHAN((&insn->chanspec)[i]);
502 rang = CR_RANGE((&insn->chanspec)[i]);
504 dev_private->dac_control &= ~(0x0880 >> chan); /* clear bits for this channel */
506 dev_private->dac_control |=
507 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
509 dev_private->dac_control |=
510 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
512 writew(dev_private->dac_control,
513 dev_private->me_regbase + ME_DAC_CONTROL);
515 /* Update dac-control register */
516 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
518 /* Set data register */
519 for (i = 0; i < insn->n; i++) {
520 chan = CR_CHAN((&insn->chanspec)[i]);
521 writew((data[i] & s->maxdata),
522 dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
523 dev_private->ao_readback[chan] = (data[i] & s->maxdata);
526 /* Update dac with data registers */
527 readw(dev_private->me_regbase + ME_DAC_UPDATE);
533 // Analog output readback
535 static int me_ao_insn_read(comedi_device * dev,
536 comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
540 for (i = 0; i < insn->n; i++) {
542 dev_private->ao_readback[CR_CHAN((&insn->chanspec)[i])];
548 // ------------------------------------------------------------------
550 // INITIALISATION SECTION
552 // ------------------------------------------------------------------
555 // Xilinx firmware download for card: ME-2600i
558 static int me2600_xilinx_download(comedi_device * dev, unsigned char
559 *me2600_firmware, unsigned int length)
562 unsigned int file_length;
565 /* disable irq's on PLX */
566 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
568 /* First, make a dummy read to reset xilinx */
569 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
571 /* Wait until reset is over */
574 /* Write a dummy value to Xilinx */
575 writeb(0x00, dev_private->me_regbase + 0x0);
579 * Format of the firmware
580 * Build longs from the byte-wise coded header
581 * Byte 1-3: length of the array
584 * Byte 12-15: reserved
589 (((unsigned int)me2600_firmware[0] & 0xff) << 24) +
590 (((unsigned int)me2600_firmware[1] & 0xff) << 16) +
591 (((unsigned int)me2600_firmware[2] & 0xff) << 8) +
592 ((unsigned int)me2600_firmware[3] & 0xff);
595 * Loop for writing firmware byte by byte to xilinx
596 * Firmware data start at offfset 16
598 for (i = 0; i < file_length; i++) {
599 writeb((me2600_firmware[16 + i] & 0xff),
600 dev_private->me_regbase + 0x0);
603 /* Write 5 dummy values to xilinx */
604 for (i = 0; i < 5; i++) {
605 writeb(0x00, dev_private->me_regbase + 0x0);
608 /* Test if there was an error during download -> INTB was thrown */
609 value = readl(dev_private->plx_regbase + PLX_INTCSR);
611 /* Disable interrupt */
612 writel(0x00, dev_private->plx_regbase + PLX_INTCSR);
613 printk("comedi%d: Xilinx download failed\n", dev->minor);
617 /* Wait until the Xilinx is ready for real work */
620 /* Enable PLX-Interrupts */
621 writel(0x43, dev_private->plx_regbase + PLX_INTCSR);
630 static int me_reset(comedi_device * dev)
633 writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
634 writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
635 writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
636 writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
638 /* Save values in the board context */
639 dev_private->dac_control = 0;
640 dev_private->control_1 = 0;
641 dev_private->control_2 = 0;
649 // - Register PCI device
650 // - Declare device driver capability
653 static int me_attach(comedi_device * dev, comedi_devconfig * it)
655 struct pci_dev *pci_device;
656 comedi_subdevice *subdevice;
657 me_board_struct *board;
658 resource_size_t plx_regbase_tmp;
659 unsigned long plx_regbase_size_tmp;
660 resource_size_t me_regbase_tmp;
661 unsigned long me_regbase_size_tmp;
662 resource_size_t swap_regbase_tmp;
663 unsigned long swap_regbase_size_tmp;
664 resource_size_t regbase_tmp;
665 int result, error, i;
667 // Allocate private memory
668 if (alloc_private(dev, sizeof(me_private_data_struct)) < 0) {
672 // Probe the device to determine what device in the series it is.
674 for (pci_device = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
677 pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_device)) {
678 if (pci_device->vendor == PCI_VENDOR_ID_MEILHAUS) {
679 for (i = 0; i < me_board_nbr; i++) {
680 if (me_boards[i].device_id ==
681 pci_device->device) {
682 // was a particular bus/slot requested?
683 if ((it->options[0] != 0)
684 || (it->options[1] != 0)) {
685 // are we on the wrong bus/slot?
686 if (pci_device->bus->number !=
688 || PCI_SLOT(pci_device->
695 dev->board_ptr = me_boards + i;
696 board = (me_board_struct *) dev->
698 dev_private->pci_device = pci_device;
705 printk("comedi%d: no supported board found! (req. bus/slot : %d/%d)\n",
706 dev->minor, it->options[0], it->options[1]);
711 printk("comedi%d: found %s at PCI bus %d, slot %d\n",
712 dev->minor, me_boards[i].name,
713 pci_device->bus->number, PCI_SLOT(pci_device->devfn));
715 // Enable PCI device and request PCI regions
716 if (comedi_pci_enable(pci_device, ME_DRIVER_NAME) < 0) {
717 printk("comedi%d: Failed to enable PCI device and request regions\n", dev->minor);
720 // Set data in device structure
722 dev->board_name = board->name;
724 // Read PLX register base address [PCI_BASE_ADDRESS #0].
726 plx_regbase_tmp = pci_resource_start(pci_device, 0);
727 plx_regbase_size_tmp = pci_resource_len(pci_device, 0);
728 dev_private->plx_regbase =
729 ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
730 dev_private->plx_regbase_size = plx_regbase_size_tmp;
731 if (!dev_private->plx_regbase) {
732 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
735 // Read Swap base address [PCI_BASE_ADDRESS #5].
737 swap_regbase_tmp = pci_resource_start(pci_device, 5);
738 swap_regbase_size_tmp = pci_resource_len(pci_device, 5);
740 if (!swap_regbase_tmp) {
741 printk("comedi%d: Swap not present\n", dev->minor);
744 /*----------------------------------------------------- Workaround start ---*/
745 if (plx_regbase_tmp & 0x0080) {
746 printk("comedi%d: PLX-Bug detected\n", dev->minor);
748 if (swap_regbase_tmp) {
749 regbase_tmp = plx_regbase_tmp;
750 plx_regbase_tmp = swap_regbase_tmp;
751 swap_regbase_tmp = regbase_tmp;
753 result = pci_write_config_dword(pci_device,
754 PCI_BASE_ADDRESS_0, plx_regbase_tmp);
755 if (result != PCIBIOS_SUCCESSFUL)
758 result = pci_write_config_dword(pci_device,
759 PCI_BASE_ADDRESS_5, swap_regbase_tmp);
760 if (result != PCIBIOS_SUCCESSFUL)
763 plx_regbase_tmp -= 0x80;
764 result = pci_write_config_dword(pci_device,
765 PCI_BASE_ADDRESS_0, plx_regbase_tmp);
766 if (result != PCIBIOS_SUCCESSFUL)
770 /*----------------------------------------------------- Workaround end -----*/
772 // Read Meilhaus register base address [PCI_BASE_ADDRESS #2].
774 me_regbase_tmp = pci_resource_start(pci_device, 2);
775 me_regbase_size_tmp = pci_resource_len(pci_device, 2);
776 dev_private->me_regbase_size = me_regbase_size_tmp;
777 dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
778 if (!dev_private->me_regbase) {
779 printk("comedi%d: Failed to remap I/O memory\n", dev->minor);
782 // Download firmware and reset card
783 if (board->device_id == ME2600_DEVICE_ID) {
784 unsigned char *aux_data;
787 aux_data = comedi_aux_data(it->options, 0);
788 aux_len = it->options[COMEDI_DEVCONF_AUX_DATA_LENGTH];
790 if (!aux_data || aux_len < 1) {
792 "You must provide me2600 firmware using the --init-data option of comedi_config");
795 me2600_xilinx_download(dev, aux_data, aux_len);
800 // device driver capabilities
802 if ((error = alloc_subdevices(dev, 3)) < 0)
805 subdevice = dev->subdevices + 0;
806 subdevice->type = COMEDI_SUBD_AI;
807 subdevice->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_CMD_READ;
808 subdevice->n_chan = board->ai_channel_nbr;
809 subdevice->maxdata = board->ai_resolution_mask;
810 subdevice->len_chanlist = board->ai_channel_nbr;
811 subdevice->range_table = board->ai_range_list;
812 subdevice->cancel = me_ai_cancel;
813 subdevice->insn_read = me_ai_insn_read;
814 subdevice->do_cmdtest = me_ai_do_cmd_test;
815 subdevice->do_cmd = me_ai_do_cmd;
817 subdevice = dev->subdevices + 1;
818 subdevice->type = COMEDI_SUBD_AO;
819 subdevice->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
820 subdevice->n_chan = board->ao_channel_nbr;
821 subdevice->maxdata = board->ao_resolution_mask;
822 subdevice->len_chanlist = board->ao_channel_nbr;
823 subdevice->range_table = board->ao_range_list;
824 subdevice->insn_read = me_ao_insn_read;
825 subdevice->insn_write = me_ao_insn_write;
827 subdevice = dev->subdevices + 2;
828 subdevice->type = COMEDI_SUBD_DIO;
829 subdevice->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
830 subdevice->n_chan = board->dio_channel_nbr;
831 subdevice->maxdata = 1;
832 subdevice->len_chanlist = board->dio_channel_nbr;
833 subdevice->range_table = &range_digital;
834 subdevice->insn_bits = me_dio_insn_bits;
835 subdevice->insn_config = me_dio_insn_config;
836 subdevice->io_bits = 0;
838 printk("comedi%d: " ME_DRIVER_NAME " attached.\n", dev->minor);
846 static int me_detach(comedi_device * dev)
849 if (dev_private->me_regbase) {
851 iounmap(dev_private->me_regbase);
853 if (dev_private->plx_regbase)
854 iounmap(dev_private->plx_regbase);
855 if (dev_private->pci_device) {
856 if (dev_private->plx_regbase_size) {
857 comedi_pci_disable(dev_private->pci_device);
859 pci_dev_put(dev_private->pci_device);