comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include <linux/sched.h>
  65 #include "8255.h"
  66 #include "mite.h"
  67 #include "comedi_fc.h"
  68
  69 #ifndef MDPRINTK
  70 #define MDPRINTK(format,args...)
  71 #endif
  72
  73 /* A timeout count */
  74 #define NI_TIMEOUT 1000
  75 static const unsigned old_RTSI_clock_channel = 7;
  76
  77 /* Note: this table must match the ai_gain_* definitions */
  78 static const short ni_gainlkup[][16] = {
  79         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  80                 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  81         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  82         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  83                 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  84         [ai_gain_4] = {0, 1, 4, 7},
  85         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  86                 0x003, 0x004, 0x005, 0x006},
  87         [ai_gain_622x] = {0, 1, 4, 5},
  88         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  89         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  90 };
  91
  92 static const comedi_lrange range_ni_E_ai = { 16, {
  93                         RANGE(-10, 10),
  94                         RANGE(-5, 5),
  95                         RANGE(-2.5, 2.5),
  96                         RANGE(-1, 1),
  97                         RANGE(-0.5, 0.5),
  98                         RANGE(-0.25, 0.25),
  99                         RANGE(-0.1, 0.1),
 100                         RANGE(-0.05, 0.05),
 101                         RANGE(0, 20),
 102                         RANGE(0, 10),
 103                         RANGE(0, 5),
 104                         RANGE(0, 2),
 105                         RANGE(0, 1),
 106                         RANGE(0, 0.5),
 107                         RANGE(0, 0.2),
 108                         RANGE(0, 0.1),
 109         }
 110 };
 111 static const comedi_lrange range_ni_E_ai_limited = { 8, {
 112                         RANGE(-10, 10),
 113                         RANGE(-5, 5),
 114                         RANGE(-1, 1),
 115                         RANGE(-0.1, 0.1),
 116                         RANGE(0, 10),
 117                         RANGE(0, 5),
 118                         RANGE(0, 1),
 119                         RANGE(0, 0.1),
 120         }
 121 };
 122 static const comedi_lrange range_ni_E_ai_limited14 = { 14, {
 123                         RANGE(-10, 10),
 124                         RANGE(-5, 5),
 125                         RANGE(-2, 2),
 126                         RANGE(-1, 1),
 127                         RANGE(-0.5, 0.5),
 128                         RANGE(-0.2, 0.2),
 129                         RANGE(-0.1, 0.1),
 130                         RANGE(0, 10),
 131                         RANGE(0, 5),
 132                         RANGE(0, 2),
 133                         RANGE(0, 1),
 134                         RANGE(0, 0.5),
 135                         RANGE(0, 0.2),
 136                         RANGE(0, 0.1),
 137         }
 138 };
 139 static const comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
 140                         RANGE(-10, 10),
 141                         RANGE(-5, 5),
 142                         RANGE(-0.5, 0.5),
 143                         RANGE(-0.05, 0.05),
 144         }
 145 };
 146 static const comedi_lrange range_ni_E_ai_611x = { 8, {
 147                         RANGE(-50, 50),
 148                         RANGE(-20, 20),
 149                         RANGE(-10, 10),
 150                         RANGE(-5, 5),
 151                         RANGE(-2, 2),
 152                         RANGE(-1, 1),
 153                         RANGE(-0.5, 0.5),
 154                         RANGE(-0.2, 0.2),
 155         }
 156 };
 157 static const comedi_lrange range_ni_M_ai_622x = { 4, {
 158                         RANGE(-10, 10),
 159                         RANGE(-5, 5),
 160                         RANGE(-1, 1),
 161                         RANGE(-0.2, 0.2),
 162         }
 163 };
 164 static const comedi_lrange range_ni_M_ai_628x = { 7, {
 165                         RANGE(-10, 10),
 166                         RANGE(-5, 5),
 167                         RANGE(-2, 2),
 168                         RANGE(-1, 1),
 169                         RANGE(-0.5, 0.5),
 170                         RANGE(-0.2, 0.2),
 171                         RANGE(-0.1, 0.1),
 172         }
 173 };
 174 static const comedi_lrange range_ni_S_ai_6143 = { 1, {
 175                         RANGE(-5, +5),
 176         }
 177 };
 178 static const comedi_lrange range_ni_E_ao_ext = { 4, {
 179                         RANGE(-10, 10),
 180                         RANGE(0, 10),
 181                         RANGE_ext(-1, 1),
 182                         RANGE_ext(0, 1),
 183         }
 184 };
 185
 186 static const comedi_lrange *const ni_range_lkup[] = {
 187         [ai_gain_16] = &range_ni_E_ai,
 188         [ai_gain_8] = &range_ni_E_ai_limited,
 189         [ai_gain_14] = &range_ni_E_ai_limited14,
 190         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 191         [ai_gain_611x] = &range_ni_E_ai_611x,
 192         [ai_gain_622x] = &range_ni_M_ai_622x,
 193         [ai_gain_628x] = &range_ni_M_ai_628x,
 194         [ai_gain_6143] = &range_ni_S_ai_6143
 195 };
 196
 197 static int ni_dio_insn_config(comedi_device * dev, comedi_subdevice * s,
 198         comedi_insn * insn, lsampl_t * data);
 199 static int ni_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
 200         comedi_insn * insn, lsampl_t * data);
 201 static int ni_cdio_cmdtest(comedi_device * dev, comedi_subdevice * s,
 202         comedi_cmd * cmd);
 203 static int ni_cdio_cmd(comedi_device * dev, comedi_subdevice * s);
 204 static int ni_cdio_cancel(comedi_device * dev, comedi_subdevice * s);
 205 static void handle_cdio_interrupt(comedi_device * dev);
 206 static int ni_cdo_inttrig(comedi_device * dev, comedi_subdevice * s,
 207         unsigned int trignum);
 208
 209 static int ni_serial_insn_config(comedi_device * dev, comedi_subdevice * s,
 210         comedi_insn * insn, lsampl_t * data);
 211 static int ni_serial_hw_readwrite8(comedi_device * dev, comedi_subdevice * s,
 212         unsigned char data_out, unsigned char *data_in);
 213 static int ni_serial_sw_readwrite8(comedi_device * dev, comedi_subdevice * s,
 214         unsigned char data_out, unsigned char *data_in);
 215
 216 static int ni_calib_insn_read(comedi_device * dev, comedi_subdevice * s,
 217         comedi_insn * insn, lsampl_t * data);
 218 static int ni_calib_insn_write(comedi_device * dev, comedi_subdevice * s,
 219         comedi_insn * insn, lsampl_t * data);
 220
 221 static int ni_eeprom_insn_read(comedi_device * dev, comedi_subdevice * s,
 222         comedi_insn * insn, lsampl_t * data);
 223 static int ni_m_series_eeprom_insn_read(comedi_device * dev,
 224         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data);
 225
 226 static int ni_pfi_insn_bits(comedi_device * dev, comedi_subdevice * s,
 227         comedi_insn * insn, lsampl_t * data);
 228 static int ni_pfi_insn_config(comedi_device * dev, comedi_subdevice * s,
 229         comedi_insn * insn, lsampl_t * data);
 230 static unsigned ni_old_get_pfi_routing(comedi_device * dev, unsigned chan);
 231
 232 static void ni_rtsi_init(comedi_device * dev);
 233 static int ni_rtsi_insn_bits(comedi_device * dev, comedi_subdevice * s,
 234         comedi_insn * insn, lsampl_t * data);
 235 static int ni_rtsi_insn_config(comedi_device * dev, comedi_subdevice * s,
 236         comedi_insn * insn, lsampl_t * data);
 237
 238 static void caldac_setup(comedi_device * dev, comedi_subdevice * s);
 239 static int ni_read_eeprom(comedi_device * dev, int addr);
 240
 241 #ifdef DEBUG_STATUS_A
 242 static void ni_mio_print_status_a(int status);
 243 #else
 244 #define ni_mio_print_status_a(a)
 245 #endif
 246 #ifdef DEBUG_STATUS_B
 247 static void ni_mio_print_status_b(int status);
 248 #else
 249 #define ni_mio_print_status_b(a)
 250 #endif
 251
 252 static int ni_ai_reset(comedi_device * dev, comedi_subdevice * s);
 253 #ifndef PCIDMA
 254 static void ni_handle_fifo_half_full(comedi_device * dev);
 255 static int ni_ao_fifo_half_empty(comedi_device * dev, comedi_subdevice * s);
 256 #endif
 257 static void ni_handle_fifo_dregs(comedi_device * dev);
 258 static int ni_ai_inttrig(comedi_device * dev, comedi_subdevice * s,
 259         unsigned int trignum);
 260 static void ni_load_channelgain_list(comedi_device * dev, unsigned int n_chan,
 261         unsigned int *list);
 262 static void shutdown_ai_command(comedi_device * dev);
 263
 264 static int ni_ao_inttrig(comedi_device * dev, comedi_subdevice * s,
 265         unsigned int trignum);
 266
 267 static int ni_ao_reset(comedi_device * dev, comedi_subdevice * s);
 268
 269 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 270
 271 static int ni_gpct_insn_write(comedi_device * dev, comedi_subdevice * s,
 272         comedi_insn * insn, lsampl_t * data);
 273 static int ni_gpct_insn_read(comedi_device * dev, comedi_subdevice * s,
 274         comedi_insn * insn, lsampl_t * data);
 275 static int ni_gpct_insn_config(comedi_device * dev, comedi_subdevice * s,
 276         comedi_insn * insn, lsampl_t * data);
 277 static int ni_gpct_cmd(comedi_device * dev, comedi_subdevice * s);
 278 static int ni_gpct_cmdtest(comedi_device * dev, comedi_subdevice * s,
 279         comedi_cmd * cmd);
 280 static int ni_gpct_cancel(comedi_device * dev, comedi_subdevice * s);
 281 static void handle_gpct_interrupt(comedi_device * dev,
 282         unsigned short counter_index);
 283
 284 static int init_cs5529(comedi_device * dev);
 285 static int cs5529_do_conversion(comedi_device * dev, unsigned short *data);
 286 static int cs5529_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
 287         comedi_insn * insn, lsampl_t * data);
 288 #ifdef NI_CS5529_DEBUG
 289 static unsigned int cs5529_config_read(comedi_device * dev,
 290         unsigned int reg_select_bits);
 291 #endif
 292 static void cs5529_config_write(comedi_device * dev, unsigned int value,
 293         unsigned int reg_select_bits);
 294
 295 static int ni_m_series_pwm_config(comedi_device * dev, comedi_subdevice * s,
 296         comedi_insn * insn, lsampl_t * data);
 297 static int ni_6143_pwm_config(comedi_device * dev, comedi_subdevice * s,
 298         comedi_insn * insn, lsampl_t * data);
 299
 300 static int ni_set_master_clock(comedi_device * dev, unsigned source,
 301         unsigned period_ns);
 302 static void ack_a_interrupt(comedi_device * dev, unsigned short a_status);
 303 static void ack_b_interrupt(comedi_device * dev, unsigned short b_status);
 304
 305 enum aimodes {
 306         AIMODE_NONE = 0,
 307         AIMODE_HALF_FULL = 1,
 308         AIMODE_SCAN = 2,
 309         AIMODE_SAMPLE = 3,
 310 };
 311
 312 enum ni_common_subdevices {
 313         NI_AI_SUBDEV,
 314         NI_AO_SUBDEV,
 315         NI_DIO_SUBDEV,
 316         NI_8255_DIO_SUBDEV,
 317         NI_UNUSED_SUBDEV,
 318         NI_CALIBRATION_SUBDEV,
 319         NI_EEPROM_SUBDEV,
 320         NI_PFI_DIO_SUBDEV,
 321         NI_CS5529_CALIBRATION_SUBDEV,
 322         NI_SERIAL_SUBDEV,
 323         NI_RTSI_SUBDEV,
 324         NI_GPCT0_SUBDEV,
 325         NI_GPCT1_SUBDEV,
 326         NI_FREQ_OUT_SUBDEV,
 327         NI_NUM_SUBDEVICES
 328 };
 329 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 330 {
 331         switch (counter_index) {
 332         case 0:
 333                 return NI_GPCT0_SUBDEV;
 334                 break;
 335         case 1:
 336                 return NI_GPCT1_SUBDEV;
 337                 break;
 338         default:
 339                 break;
 340         }
 341         BUG();
 342         return NI_GPCT0_SUBDEV;
 343 }
 344
 345 enum timebase_nanoseconds {
 346         TIMEBASE_1_NS = 50,
 347         TIMEBASE_2_NS = 10000
 348 };
 349
 350 #define SERIAL_DISABLED         0
 351 #define SERIAL_600NS            600
 352 #define SERIAL_1_2US            1200
 353 #define SERIAL_10US                     10000
 354
 355 static const int num_adc_stages_611x = 3;
 356
 357 static void handle_a_interrupt(comedi_device * dev, unsigned short status,
 358         unsigned ai_mite_status);
 359 static void handle_b_interrupt(comedi_device * dev, unsigned short status,
 360         unsigned ao_mite_status);
 361 static void get_last_sample_611x(comedi_device * dev);
 362 static void get_last_sample_6143(comedi_device * dev);
 363
 364 static inline void ni_set_bitfield(comedi_device * dev, int reg,
 365         unsigned bit_mask, unsigned bit_values)
 366 {
 367         unsigned long flags;
 368
 369         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 370         switch (reg) {
 371         case Interrupt_A_Enable_Register:
 372                 devpriv->int_a_enable_reg &= ~bit_mask;
 373                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 374                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 375                         Interrupt_A_Enable_Register);
 376                 break;
 377         case Interrupt_B_Enable_Register:
 378                 devpriv->int_b_enable_reg &= ~bit_mask;
 379                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 380                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 381                         Interrupt_B_Enable_Register);
 382                 break;
 383         case IO_Bidirection_Pin_Register:
 384                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 385                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 386                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 387                         IO_Bidirection_Pin_Register);
 388                 break;
 389         case AI_AO_Select:
 390                 devpriv->ai_ao_select_reg &= ~bit_mask;
 391                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 392                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 393                 break;
 394         case G0_G1_Select:
 395                 devpriv->g0_g1_select_reg &= ~bit_mask;
 396                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 397                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 398                 break;
 399         default:
 400                 rt_printk("Warning %s() called with invalid register\n",
 401                         __FUNCTION__);
 402                 rt_printk("reg is %d\n", reg);
 403                 break;
 404         }
 405         mmiowb();
 406         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 407 }
 408
 409 #ifdef PCIDMA
 410 static int ni_ai_drain_dma(comedi_device * dev);
 411
 412 /* DMA channel setup */
 413
 414 // negative channel means no channel
 415 static inline void ni_set_ai_dma_channel(comedi_device * dev, int channel)
 416 {
 417         unsigned bitfield;
 418
 419         if (channel >= 0) {
 420                 bitfield =
 421                         (ni_stc_dma_channel_select_bitfield(channel) <<
 422                         AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 423         } else {
 424                 bitfield = 0;
 425         }
 426         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 427 }
 428
 429 // negative channel means no channel
 430 static inline void ni_set_ao_dma_channel(comedi_device * dev, int channel)
 431 {
 432         unsigned bitfield;
 433
 434         if (channel >= 0) {
 435                 bitfield =
 436                         (ni_stc_dma_channel_select_bitfield(channel) <<
 437                         AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 438         } else {
 439                 bitfield = 0;
 440         }
 441         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 442 }
 443
 444 // negative mite_channel means no channel
 445 static inline void ni_set_gpct_dma_channel(comedi_device * dev,
 446         unsigned gpct_index, int mite_channel)
 447 {
 448         unsigned bitfield;
 449
 450         if (mite_channel >= 0) {
 451                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 452         } else {
 453                 bitfield = 0;
 454         }
 455         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 456                 bitfield);
 457 }
 458
 459 // negative mite_channel means no channel
 460 static inline void ni_set_cdo_dma_channel(comedi_device * dev, int mite_channel)
 461 {
 462         unsigned long flags;
 463
 464         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 465         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 466         if (mite_channel >= 0) {
 467                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 468                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 469                    Definitely works for dma channels 0 and 1. */
 470                 devpriv->cdio_dma_select_reg |=
 471                         (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 472                         CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 473         }
 474         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 475         mmiowb();
 476         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 477 }
 478
 479 static int ni_request_ai_mite_channel(comedi_device * dev)
 480 {
 481         unsigned long flags;
 482
 483         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 484         BUG_ON(devpriv->ai_mite_chan);
 485         devpriv->ai_mite_chan =
 486                 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 487         if (devpriv->ai_mite_chan == NULL) {
 488                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 489                         flags);
 490                 comedi_error(dev,
 491                         "failed to reserve mite dma channel for analog input.");
 492                 return -EBUSY;
 493         }
 494         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 495         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 496         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 497         return 0;
 498 }
 499
 500 static int ni_request_ao_mite_channel(comedi_device * dev)
 501 {
 502         unsigned long flags;
 503
 504         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 505         BUG_ON(devpriv->ao_mite_chan);
 506         devpriv->ao_mite_chan =
 507                 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 508         if (devpriv->ao_mite_chan == NULL) {
 509                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 510                         flags);
 511                 comedi_error(dev,
 512                         "failed to reserve mite dma channel for analog outut.");
 513                 return -EBUSY;
 514         }
 515         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 516         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 517         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 518         return 0;
 519 }
 520
 521 static int ni_request_gpct_mite_channel(comedi_device * dev,
 522         unsigned gpct_index, enum comedi_io_direction direction)
 523 {
 524         unsigned long flags;
 525         struct mite_channel *mite_chan;
 526
 527         BUG_ON(gpct_index >= NUM_GPCT);
 528         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 529         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 530         mite_chan =
 531                 mite_request_channel(devpriv->mite,
 532                 devpriv->gpct_mite_ring[gpct_index]);
 533         if (mite_chan == NULL) {
 534                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 535                         flags);
 536                 comedi_error(dev,
 537                         "failed to reserve mite dma channel for counter.");
 538                 return -EBUSY;
 539         }
 540         mite_chan->dir = direction;
 541         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 542                 mite_chan);
 543         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 544         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 545         return 0;
 546 }
 547
 548 #endif // PCIDMA
 549
 550 static int ni_request_cdo_mite_channel(comedi_device * dev)
 551 {
 552 #ifdef PCIDMA
 553         unsigned long flags;
 554
 555         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 556         BUG_ON(devpriv->cdo_mite_chan);
 557         devpriv->cdo_mite_chan =
 558                 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 559         if (devpriv->cdo_mite_chan == NULL) {
 560                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 561                         flags);
 562                 comedi_error(dev,
 563                         "failed to reserve mite dma channel for correlated digital outut.");
 564                 return -EBUSY;
 565         }
 566         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 567         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 568         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 569 #endif // PCIDMA
 570         return 0;
 571 }
 572
 573 static void ni_release_ai_mite_channel(comedi_device * dev)
 574 {
 575 #ifdef PCIDMA
 576         unsigned long flags;
 577
 578         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 579         if (devpriv->ai_mite_chan) {
 580                 ni_set_ai_dma_channel(dev, -1);
 581                 mite_release_channel(devpriv->ai_mite_chan);
 582                 devpriv->ai_mite_chan = NULL;
 583         }
 584         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 585 #endif // PCIDMA
 586 }
 587
 588 static void ni_release_ao_mite_channel(comedi_device * dev)
 589 {
 590 #ifdef PCIDMA
 591         unsigned long flags;
 592
 593         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 594         if (devpriv->ao_mite_chan) {
 595                 ni_set_ao_dma_channel(dev, -1);
 596                 mite_release_channel(devpriv->ao_mite_chan);
 597                 devpriv->ao_mite_chan = NULL;
 598         }
 599         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 600 #endif // PCIDMA
 601 }
 602
 603 static void ni_release_gpct_mite_channel(comedi_device * dev,
 604                 unsigned gpct_index)
 605 {
 606 #ifdef PCIDMA
 607         unsigned long flags;
 608
 609         BUG_ON(gpct_index >= NUM_GPCT);
 610         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 611         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 612                 struct mite_channel *mite_chan =
 613                         devpriv->counter_dev->counters[gpct_index].mite_chan;
 614
 615                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 616                 ni_tio_set_mite_channel(&devpriv->counter_dev->
 617                         counters[gpct_index], NULL);
 618                 mite_release_channel(mite_chan);
 619         }
 620         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 621 #endif // PCIDMA
 622 }
 623
 624 static void ni_release_cdo_mite_channel(comedi_device * dev)
 625 {
 626 #ifdef PCIDMA
 627         unsigned long flags;
 628
 629         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 630         if (devpriv->cdo_mite_chan) {
 631                 ni_set_cdo_dma_channel(dev, -1);
 632                 mite_release_channel(devpriv->cdo_mite_chan);
 633                 devpriv->cdo_mite_chan = NULL;
 634         }
 635         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 636 #endif // PCIDMA
 637 }
 638
 639 // e-series boards use the second irq signals to generate dma requests for their counters
 640 #ifdef PCIDMA
 641 static void ni_e_series_enable_second_irq(comedi_device * dev,
 642         unsigned gpct_index, short enable)
 643 {
 644         if (boardtype.reg_type & ni_reg_m_series_mask)
 645                 return;
 646         switch (gpct_index) {
 647         case 0:
 648                 if (enable) {
 649                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 650                                 Second_IRQ_A_Enable_Register);
 651                 } else {
 652                         devpriv->stc_writew(dev, 0,
 653                                 Second_IRQ_A_Enable_Register);
 654                 }
 655                 break;
 656         case 1:
 657                 if (enable) {
 658                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 659                                 Second_IRQ_B_Enable_Register);
 660                 } else {
 661                         devpriv->stc_writew(dev, 0,
 662                                 Second_IRQ_B_Enable_Register);
 663                 }
 664                 break;
 665         default:
 666                 BUG();
 667                 break;
 668         }
 669 }
 670 #endif // PCIDMA
 671
 672 static void ni_clear_ai_fifo(comedi_device * dev)
 673 {
 674         if (boardtype.reg_type == ni_reg_6143) {
 675                 // Flush the 6143 data FIFO
 676                 ni_writel(0x10, AIFIFO_Control_6143);   // Flush fifo
 677                 ni_writel(0x00, AIFIFO_Control_6143);   // Flush fifo
 678                 while (ni_readl(AIFIFO_Status_6143) & 0x10) ;   // Wait for complete
 679         } else {
 680                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 681                 if (boardtype.reg_type == ni_reg_625x) {
 682                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 683                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 684 #if 0
 685                         /* the NI example code does 3 convert pulses for 625x boards,
 686                            but that appears to be wrong in practice. */
 687                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 688                                 AI_Command_1_Register);
 689                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 690                                 AI_Command_1_Register);
 691                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 692                                 AI_Command_1_Register);
 693 #endif
 694                 }
 695         }
 696 }
 697
 698 static void win_out2(comedi_device * dev, uint32_t data, int reg)
 699 {
 700         devpriv->stc_writew(dev, data >> 16, reg);
 701         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 702 }
 703
 704 static uint32_t win_in2(comedi_device * dev, int reg)
 705 {
 706         uint32_t bits;
 707         bits = devpriv->stc_readw(dev, reg) << 16;
 708         bits |= devpriv->stc_readw(dev, reg + 1);
 709         return bits;
 710 }
 711
 712 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 713 static inline void ni_ao_win_outw(comedi_device * dev, uint16_t data, int addr)
 714 {
 715         unsigned long flags;
 716
 717         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 718         ni_writew(addr, AO_Window_Address_611x);
 719         ni_writew(data, AO_Window_Data_611x);
 720         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 721 }
 722
 723 static inline void ni_ao_win_outl(comedi_device * dev, uint32_t data, int addr)
 724 {
 725         unsigned long flags;
 726
 727         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 728         ni_writew(addr, AO_Window_Address_611x);
 729         ni_writel(data, AO_Window_Data_611x);
 730         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 731 }
 732
 733 static inline unsigned short ni_ao_win_inw(comedi_device * dev, int addr)
 734 {
 735         unsigned long flags;
 736         unsigned short data;
 737
 738         comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
 739         ni_writew(addr, AO_Window_Address_611x);
 740         data = ni_readw(AO_Window_Data_611x);
 741         comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
 742         return data;
 743 }
 744
 745 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 746 * share registers (such as Interrupt_A_Register) without interfering with
 747 * each other.
 748 *
 749 * NOTE: the switch/case statements are optimized out for a constant argument
 750 * so this is actually quite fast---  If you must wrap another function around this
 751 * make it inline to avoid a large speed penalty.
 752 *
 753 * value should only be 1 or 0.
 754 */
 755 static inline void ni_set_bits(comedi_device * dev, int reg, unsigned bits,
 756         unsigned value)
 757 {
 758         unsigned bit_values;
 759
 760         if (value)
 761                 bit_values = bits;
 762         else
 763                 bit_values = 0;
 764         ni_set_bitfield(dev, reg, bits, bit_values);
 765 }
 766
 767 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 768 {
 769         comedi_device *dev = d;
 770         unsigned short a_status;
 771         unsigned short b_status;
 772         unsigned int ai_mite_status = 0;
 773         unsigned int ao_mite_status = 0;
 774         unsigned long flags;
 775 #ifdef PCIDMA
 776         struct mite_struct *mite = devpriv->mite;
 777 #endif
 778
 779         if (dev->attached == 0)
 780                 return IRQ_NONE;
 781         smp_mb();               // make sure dev->attached is checked before handler does anything else.
 782
 783         // lock to avoid race with comedi_poll
 784         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 785         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 786         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 787 #ifdef PCIDMA
 788         if (mite) {
 789                 unsigned long flags_too;
 790
 791                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock,
 792                         flags_too);
 793                 if (devpriv->ai_mite_chan) {
 794                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 795                         if (ai_mite_status & CHSR_LINKC)
 796                                 writel(CHOR_CLRLC,
 797                                         devpriv->mite->mite_io_addr +
 798                                         MITE_CHOR(devpriv->ai_mite_chan->
 799                                                 channel));
 800                 }
 801                 if (devpriv->ao_mite_chan) {
 802                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 803                         if (ao_mite_status & CHSR_LINKC)
 804                                 writel(CHOR_CLRLC,
 805                                         mite->mite_io_addr +
 806                                         MITE_CHOR(devpriv->ao_mite_chan->
 807                                                 channel));
 808                 }
 809                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
 810                         flags_too);
 811         }
 812 #endif
 813         ack_a_interrupt(dev, a_status);
 814         ack_b_interrupt(dev, b_status);
 815         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 816                 handle_a_interrupt(dev, a_status, ai_mite_status);
 817         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 818                 handle_b_interrupt(dev, b_status, ao_mite_status);
 819         handle_gpct_interrupt(dev, 0);
 820         handle_gpct_interrupt(dev, 1);
 821         handle_cdio_interrupt(dev);
 822
 823         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 824         return IRQ_HANDLED;
 825 }
 826
 827 #ifdef PCIDMA
 828 static void ni_sync_ai_dma(comedi_device * dev)
 829 {
 830         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 831         unsigned long flags;
 832
 833         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 834         if (devpriv->ai_mite_chan)
 835                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 836         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 837 }
 838
 839 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device * dev)
 840 {
 841         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
 842         unsigned long flags;
 843
 844         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 845         if (devpriv->ao_mite_chan) {
 846                 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
 847         }
 848         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 849 }
 850
 851 static int ni_ao_wait_for_dma_load(comedi_device * dev)
 852 {
 853         static const int timeout = 10000;
 854         int i;
 855         for (i = 0; i < timeout; i++) {
 856                 unsigned short b_status;
 857
 858                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 859                 if (b_status & AO_FIFO_Half_Full_St)
 860                         break;
 861                 /* if we poll too often, the pci bus activity seems
 862                    to slow the dma transfer down */
 863                 comedi_udelay(10);
 864         }
 865         if (i == timeout) {
 866                 comedi_error(dev, "timed out waiting for dma load");
 867                 return -EPIPE;
 868         }
 869         return 0;
 870 }
 871
 872 #endif //PCIDMA
 873 static void ni_handle_eos(comedi_device * dev, comedi_subdevice * s)
 874 {
 875         if (devpriv->aimode == AIMODE_SCAN) {
 876 #ifdef PCIDMA
 877                 static const int timeout = 10;
 878                 int i;
 879
 880                 for (i = 0; i < timeout; i++) {
 881                         ni_sync_ai_dma(dev);
 882                         if ((s->async->events & COMEDI_CB_EOS))
 883                                 break;
 884                         comedi_udelay(1);
 885                 }
 886 #else
 887                 ni_handle_fifo_dregs(dev);
 888                 s->async->events |= COMEDI_CB_EOS;
 889 #endif
 890         }
 891         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 892         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
 893                 shutdown_ai_command(dev);
 894         }
 895 }
 896
 897 static void shutdown_ai_command(comedi_device * dev)
 898 {
 899         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 900
 901 #ifdef PCIDMA
 902         ni_ai_drain_dma(dev);
 903 #endif
 904         ni_handle_fifo_dregs(dev);
 905         get_last_sample_611x(dev);
 906         get_last_sample_6143(dev);
 907
 908         s->async->events |= COMEDI_CB_EOA;
 909 }
 910
 911 static void ni_event(comedi_device * dev, comedi_subdevice * s)
 912 {
 913         if (s->async->
 914                 events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
 915         {
 916                 switch (s - dev->subdevices) {
 917                 case NI_AI_SUBDEV:
 918                         ni_ai_reset(dev, s);
 919                         break;
 920                 case NI_AO_SUBDEV:
 921                         ni_ao_reset(dev, s);
 922                         break;
 923                 case NI_GPCT0_SUBDEV:
 924                 case NI_GPCT1_SUBDEV:
 925                         ni_gpct_cancel(dev, s);
 926                         break;
 927                 case NI_DIO_SUBDEV:
 928                         ni_cdio_cancel(dev, s);
 929                         break;
 930                 default:
 931                         break;
 932                 }
 933         }
 934         comedi_event(dev, s);
 935 }
 936
 937 static void handle_gpct_interrupt(comedi_device * dev,
 938         unsigned short counter_index)
 939 {
 940 #ifdef PCIDMA
 941         comedi_subdevice *s = dev->subdevices + NI_GPCT_SUBDEV(counter_index);
 942
 943         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 944                 s);
 945         if (s->async->events)
 946                 ni_event(dev, s);
 947 #endif
 948 }
 949
 950 static void ack_a_interrupt(comedi_device * dev, unsigned short a_status)
 951 {
 952         unsigned short ack = 0;
 953
 954         if (a_status & AI_SC_TC_St) {
 955                 ack |= AI_SC_TC_Interrupt_Ack;
 956         }
 957         if (a_status & AI_START1_St) {
 958                 ack |= AI_START1_Interrupt_Ack;
 959         }
 960         if (a_status & AI_START_St) {
 961                 ack |= AI_START_Interrupt_Ack;
 962         }
 963         if (a_status & AI_STOP_St) {
 964                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 965                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
 966         }
 967         if (ack)
 968                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 969 }
 970
 971 static void handle_a_interrupt(comedi_device * dev, unsigned short status,
 972         unsigned ai_mite_status)
 973 {
 974         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
 975
 976         //67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt
 977         if (s->type == COMEDI_SUBD_UNUSED)
 978                 return;
 979
 980 #ifdef DEBUG_INTERRUPT
 981         rt_printk
 982                 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
 983                 status, ai_mite_status);
 984         ni_mio_print_status_a(status);
 985 #endif
 986 #ifdef PCIDMA
 987         if (ai_mite_status & CHSR_LINKC) {
 988                 ni_sync_ai_dma(dev);
 989         }
 990
 991         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
 992                         CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
 993                         CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
 994                 rt_printk
 995                         ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
 996                         ai_mite_status);
 997                 //mite_print_chsr(ai_mite_status);
 998                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 999                 //disable_irq(dev->irq);
1000         }
1001 #endif
1002
1003         /* test for all uncommon interrupt events at the same time */
1004         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1005                         AI_SC_TC_St | AI_START1_St)) {
1006                 if (status == 0xffff) {
1007                         rt_printk
1008                                 ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1009                         /* we probably aren't even running a command now,
1010                          * so it's a good idea to be careful. */
1011                         if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1012                                 s->async->events |=
1013                                         COMEDI_CB_ERROR | COMEDI_CB_EOA;
1014                                 ni_event(dev, s);
1015                         }
1016                         return;
1017                 }
1018                 if (status & (AI_Overrun_St | AI_Overflow_St |
1019                                 AI_SC_TC_Error_St)) {
1020                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
1021                                 status);
1022                         ni_mio_print_status_a(status);
1023
1024                         shutdown_ai_command(dev);
1025
1026                         s->async->events |= COMEDI_CB_ERROR;
1027                         if (status & (AI_Overrun_St | AI_Overflow_St))
1028                                 s->async->events |= COMEDI_CB_OVERFLOW;
1029
1030                         ni_event(dev, s);
1031
1032                         return;
1033                 }
1034                 if (status & AI_SC_TC_St) {
1035 #ifdef DEBUG_INTERRUPT
1036                         rt_printk("ni_mio_common: SC_TC interrupt\n");
1037 #endif
1038                         if (!devpriv->ai_continuous) {
1039                                 shutdown_ai_command(dev);
1040                         }
1041                 }
1042         }
1043 #ifndef PCIDMA
1044         if (status & AI_FIFO_Half_Full_St) {
1045                 int i;
1046                 static const int timeout = 10;
1047                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1048                  *fail to get the fifo less than half full, so loop to be sure.*/
1049                 for (i = 0; i < timeout; ++i) {
1050                         ni_handle_fifo_half_full(dev);
1051                         if ((devpriv->stc_readw(dev,
1052                                                 AI_Status_1_Register) &
1053                                         AI_FIFO_Half_Full_St) == 0)
1054                                 break;
1055                 }
1056         }
1057 #endif // !PCIDMA
1058
1059         if ((status & AI_STOP_St)) {
1060                 ni_handle_eos(dev, s);
1061         }
1062
1063         ni_event(dev, s);
1064
1065 #ifdef DEBUG_INTERRUPT
1066         status = devpriv->stc_readw(dev, AI_Status_1_Register);
1067         if (status & Interrupt_A_St) {
1068                 rt_printk
1069                         ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1070                         status);
1071         }
1072 #endif
1073 }
1074
1075 static void ack_b_interrupt(comedi_device * dev, unsigned short b_status)
1076 {
1077         unsigned short ack = 0;
1078         if (b_status & AO_BC_TC_St) {
1079                 ack |= AO_BC_TC_Interrupt_Ack;
1080         }
1081         if (b_status & AO_Overrun_St) {
1082                 ack |= AO_Error_Interrupt_Ack;
1083         }
1084         if (b_status & AO_START_St) {
1085                 ack |= AO_START_Interrupt_Ack;
1086         }
1087         if (b_status & AO_START1_St) {
1088                 ack |= AO_START1_Interrupt_Ack;
1089         }
1090         if (b_status & AO_UC_TC_St) {
1091                 ack |= AO_UC_TC_Interrupt_Ack;
1092         }
1093         if (b_status & AO_UI2_TC_St) {
1094                 ack |= AO_UI2_TC_Interrupt_Ack;
1095         }
1096         if (b_status & AO_UPDATE_St) {
1097                 ack |= AO_UPDATE_Interrupt_Ack;
1098         }
1099         if (ack)
1100                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1101 }
1102
1103 static void handle_b_interrupt(comedi_device * dev, unsigned short b_status,
1104         unsigned ao_mite_status)
1105 {
1106         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1107         //unsigned short ack=0;
1108 #ifdef DEBUG_INTERRUPT
1109         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1110                 b_status, ao_mite_status);
1111         ni_mio_print_status_b(b_status);
1112 #endif
1113
1114 #ifdef PCIDMA
1115         /* Currently, mite.c requires us to handle LINKC */
1116         if (ao_mite_status & CHSR_LINKC) {
1117                 mite_handle_b_linkc(devpriv->mite, dev);
1118         }
1119
1120         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1121                         CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1122                         CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1123                 rt_printk
1124                         ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1125                         ao_mite_status);
1126                 //mite_print_chsr(ao_mite_status);
1127                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1128         }
1129 #endif
1130
1131         if (b_status == 0xffff)
1132                 return;
1133         if (b_status & AO_Overrun_St) {
1134                 rt_printk
1135                         ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1136                         b_status, devpriv->stc_readw(dev,
1137                                 AO_Status_2_Register));
1138                 s->async->events |= COMEDI_CB_OVERFLOW;
1139         }
1140
1141         if (b_status & AO_BC_TC_St) {
1142                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1143                 s->async->events |= COMEDI_CB_EOA;
1144         }
1145 #ifndef PCIDMA
1146         if (b_status & AO_FIFO_Request_St) {
1147                 int ret;
1148
1149                 ret = ni_ao_fifo_half_empty(dev, s);
1150                 if (!ret) {
1151                         rt_printk("ni_mio_common: AO buffer underrun\n");
1152                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1153                                 AO_FIFO_Interrupt_Enable |
1154                                 AO_Error_Interrupt_Enable, 0);
1155                         s->async->events |= COMEDI_CB_OVERFLOW;
1156                 }
1157         }
1158 #endif
1159
1160         ni_event(dev, s);
1161 }
1162
1163 #ifdef DEBUG_STATUS_A
1164 static const char *const status_a_strings[] = {
1165         "passthru0", "fifo", "G0_gate", "G0_TC",
1166         "stop", "start", "sc_tc", "start1",
1167         "start2", "sc_tc_error", "overflow", "overrun",
1168         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1169 };
1170
1171 static void ni_mio_print_status_a(int status)
1172 {
1173         int i;
1174
1175         rt_printk("A status:");
1176         for (i = 15; i >= 0; i--) {
1177                 if (status & (1 << i)) {
1178                         rt_printk(" %s", status_a_strings[i]);
1179                 }
1180         }
1181         rt_printk("\n");
1182 }
1183 #endif
1184
1185 #ifdef DEBUG_STATUS_B
1186 static const char *const status_b_strings[] = {
1187         "passthru1", "fifo", "G1_gate", "G1_TC",
1188         "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1189         "start1", "overrun", "start", "bc_tc_error",
1190         "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1191 };
1192
1193 static void ni_mio_print_status_b(int status)
1194 {
1195         int i;
1196
1197         rt_printk("B status:");
1198         for (i = 15; i >= 0; i--) {
1199                 if (status & (1 << i)) {
1200                         rt_printk(" %s", status_b_strings[i]);
1201                 }
1202         }
1203         rt_printk("\n");
1204 }
1205 #endif
1206
1207 #ifndef PCIDMA
1208
1209 static void ni_ao_fifo_load(comedi_device * dev, comedi_subdevice * s, int n)
1210 {
1211         comedi_async *async = s->async;
1212         comedi_cmd *cmd = &async->cmd;
1213         int chan;
1214         int i;
1215         sampl_t d;
1216         u32 packed_data;
1217         int range;
1218         int err = 1;
1219
1220         chan = async->cur_chan;
1221         for (i = 0; i < n; i++) {
1222                 err &= comedi_buf_get(async, &d);
1223                 if (err == 0)
1224                         break;
1225
1226                 range = CR_RANGE(cmd->chanlist[chan]);
1227
1228                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1229                         packed_data = d & 0xffff;
1230                         /* 6711 only has 16 bit wide ao fifo */
1231                         if (boardtype.reg_type != ni_reg_6711) {
1232                                 err &= comedi_buf_get(async, &d);
1233                                 if (err == 0)
1234                                         break;
1235                                 chan++;
1236                                 i++;
1237                                 packed_data |= (d << 16) & 0xffff0000;
1238                         }
1239                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1240                 } else {
1241                         ni_writew(d, DAC_FIFO_Data);
1242                 }
1243                 chan++;
1244                 chan %= cmd->chanlist_len;
1245         }
1246         async->cur_chan = chan;
1247         if (err == 0) {
1248                 async->events |= COMEDI_CB_OVERFLOW;
1249         }
1250 }
1251
1252 /*
1253  *  There's a small problem if the FIFO gets really low and we
1254  *  don't have the data to fill it.  Basically, if after we fill
1255  *  the FIFO with all the data available, the FIFO is _still_
1256  *  less than half full, we never clear the interrupt.  If the
1257  *  IRQ is in edge mode, we never get another interrupt, because
1258  *  this one wasn't cleared.  If in level mode, we get flooded
1259  *  with interrupts that we can't fulfill, because nothing ever
1260  *  gets put into the buffer.
1261  *
1262  *  This kind of situation is recoverable, but it is easier to
1263  *  just pretend we had a FIFO underrun, since there is a good
1264  *  chance it will happen anyway.  This is _not_ the case for
1265  *  RT code, as RT code might purposely be running close to the
1266  *  metal.  Needs to be fixed eventually.
1267  */
1268 static int ni_ao_fifo_half_empty(comedi_device * dev, comedi_subdevice * s)
1269 {
1270         int n;
1271
1272         n = comedi_buf_read_n_available(s->async);
1273         if (n == 0) {
1274                 s->async->events |= COMEDI_CB_OVERFLOW;
1275                 return 0;
1276         }
1277
1278         n /= sizeof(sampl_t);
1279         if (n > boardtype.ao_fifo_depth / 2)
1280                 n = boardtype.ao_fifo_depth / 2;
1281
1282         ni_ao_fifo_load(dev, s, n);
1283
1284         s->async->events |= COMEDI_CB_BLOCK;
1285
1286         return 1;
1287 }
1288
1289 static int ni_ao_prep_fifo(comedi_device * dev, comedi_subdevice * s)
1290 {
1291         int n;
1292
1293         /* reset fifo */
1294         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1295         if (boardtype.reg_type & ni_reg_6xxx_mask)
1296                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1297
1298         /* load some data */
1299         n = comedi_buf_read_n_available(s->async);
1300         if (n == 0)
1301                 return 0;
1302
1303         n /= sizeof(sampl_t);
1304         if (n > boardtype.ao_fifo_depth)
1305                 n = boardtype.ao_fifo_depth;
1306
1307         ni_ao_fifo_load(dev, s, n);
1308
1309         return n;
1310 }
1311
1312 static void ni_ai_fifo_read(comedi_device * dev, comedi_subdevice * s, int n)
1313 {
1314         comedi_async *async = s->async;
1315         int i;
1316
1317         if (boardtype.reg_type == ni_reg_611x) {
1318                 sampl_t data[2];
1319                 u32 dl;
1320
1321                 for (i = 0; i < n / 2; i++) {
1322                         dl = ni_readl(ADC_FIFO_Data_611x);
1323                         /* This may get the hi/lo data in the wrong order */
1324                         data[0] = (dl >> 16) & 0xffff;
1325                         data[1] = dl & 0xffff;
1326                         cfc_write_array_to_buffer(s, data, sizeof(data));
1327                 }
1328                 /* Check if there's a single sample stuck in the FIFO */
1329                 if (n % 2) {
1330                         dl = ni_readl(ADC_FIFO_Data_611x);
1331                         data[0] = dl & 0xffff;
1332                         cfc_write_to_buffer(s, data[0]);
1333                 }
1334         } else if (boardtype.reg_type == ni_reg_6143) {
1335                 sampl_t data[2];
1336                 u32 dl;
1337
1338                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1339                 for (i = 0; i < n / 2; i++) {
1340                         dl = ni_readl(AIFIFO_Data_6143);
1341
1342                         data[0] = (dl >> 16) & 0xffff;
1343                         data[1] = dl & 0xffff;
1344                         cfc_write_array_to_buffer(s, data, sizeof(data));
1345                 }
1346                 if (n % 2) {
1347                         /* Assume there is a single sample stuck in the FIFO */
1348                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1349                         dl = ni_readl(AIFIFO_Data_6143);
1350                         data[0] = (dl >> 16) & 0xffff;
1351                         cfc_write_to_buffer(s, data[0]);
1352                 }
1353         } else {
1354                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1355                         sizeof(devpriv->ai_fifo_buffer[0])) {
1356                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1357                         async->events |= COMEDI_CB_ERROR;
1358                         return;
1359                 }
1360                 for (i = 0; i < n; i++) {
1361                         devpriv->ai_fifo_buffer[i] =
1362                                 ni_readw(ADC_FIFO_Data_Register);
1363                 }
1364                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1365                         n * sizeof(devpriv->ai_fifo_buffer[0]));
1366         }
1367 }
1368
1369 static void ni_handle_fifo_half_full(comedi_device * dev)
1370 {
1371         int n;
1372         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1373
1374         n = boardtype.ai_fifo_depth / 2;
1375
1376         ni_ai_fifo_read(dev, s, n);
1377 }
1378 #endif
1379
1380 #ifdef PCIDMA
1381 static int ni_ai_drain_dma(comedi_device * dev)
1382 {
1383         int i;
1384         static const int timeout = 10000;
1385         unsigned long flags;
1386         int retval = 0;
1387
1388         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1389         if (devpriv->ai_mite_chan) {
1390                 for (i = 0; i < timeout; i++) {
1391                         if ((devpriv->stc_readw(dev,
1392                                                 AI_Status_1_Register) &
1393                                         AI_FIFO_Empty_St)
1394                                 && mite_bytes_in_transit(devpriv->
1395                                         ai_mite_chan) == 0)
1396                                 break;
1397                         comedi_udelay(5);
1398                 }
1399                 if (i == timeout) {
1400                         rt_printk
1401                                 ("ni_mio_common: wait for dma drain timed out\n");
1402                         rt_printk
1403                                 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1404                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
1405                                 devpriv->stc_readw(dev, AI_Status_1_Register));
1406                         retval = -1;
1407                 }
1408         }
1409         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1410
1411         ni_sync_ai_dma(dev);
1412
1413         return retval;
1414 }
1415 #endif
1416 /*
1417    Empties the AI fifo
1418 */
1419 static void ni_handle_fifo_dregs(comedi_device * dev)
1420 {
1421         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1422         sampl_t data[2];
1423         u32 dl;
1424         short fifo_empty;
1425         int i;
1426
1427         if (boardtype.reg_type == ni_reg_611x) {
1428                 while ((devpriv->stc_readw(dev,
1429                                         AI_Status_1_Register) &
1430                                 AI_FIFO_Empty_St) == 0) {
1431                         dl = ni_readl(ADC_FIFO_Data_611x);
1432
1433                         /* This may get the hi/lo data in the wrong order */
1434                         data[0] = (dl >> 16);
1435                         data[1] = (dl & 0xffff);
1436                         cfc_write_array_to_buffer(s, data, sizeof(data));
1437                 }
1438         } else if (boardtype.reg_type == ni_reg_6143) {
1439                 i = 0;
1440                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1441                         dl = ni_readl(AIFIFO_Data_6143);
1442
1443                         /* This may get the hi/lo data in the wrong order */
1444                         data[0] = (dl >> 16);
1445                         data[1] = (dl & 0xffff);
1446                         cfc_write_array_to_buffer(s, data, sizeof(data));
1447                         i += 2;
1448                 }
1449                 // Check if stranded sample is present
1450                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1451                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1452                         dl = ni_readl(AIFIFO_Data_6143);
1453                         data[0] = (dl >> 16) & 0xffff;
1454                         cfc_write_to_buffer(s, data[0]);
1455                 }
1456
1457         } else {
1458                 fifo_empty =
1459                         devpriv->stc_readw(dev,
1460                         AI_Status_1_Register) & AI_FIFO_Empty_St;
1461                 while (fifo_empty == 0) {
1462                         for (i = 0;
1463                                 i <
1464                                 sizeof(devpriv->ai_fifo_buffer) /
1465                                 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1466                                 fifo_empty =
1467                                         devpriv->stc_readw(dev,
1468                                         AI_Status_1_Register) &
1469                                         AI_FIFO_Empty_St;
1470                                 if (fifo_empty)
1471                                         break;
1472                                 devpriv->ai_fifo_buffer[i] =
1473                                         ni_readw(ADC_FIFO_Data_Register);
1474                         }
1475                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1476                                 i * sizeof(devpriv->ai_fifo_buffer[0]));
1477                 }
1478         }
1479 }
1480
1481 static void get_last_sample_611x(comedi_device * dev)
1482 {
1483         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1484         sampl_t data;
1485         u32 dl;
1486
1487         if (boardtype.reg_type != ni_reg_611x)
1488                 return;
1489
1490         /* Check if there's a single sample stuck in the FIFO */
1491         if (ni_readb(XXX_Status) & 0x80) {
1492                 dl = ni_readl(ADC_FIFO_Data_611x);
1493                 data = (dl & 0xffff);
1494                 cfc_write_to_buffer(s, data);
1495         }
1496 }
1497
1498 static void get_last_sample_6143(comedi_device * dev)
1499 {
1500         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1501         sampl_t data;
1502         u32 dl;
1503
1504         if (boardtype.reg_type != ni_reg_6143)
1505                 return;
1506
1507         /* Check if there's a single sample stuck in the FIFO */
1508         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1509                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1510                 dl = ni_readl(AIFIFO_Data_6143);
1511
1512                 /* This may get the hi/lo data in the wrong order */
1513                 data = (dl >> 16) & 0xffff;
1514                 cfc_write_to_buffer(s, data);
1515         }
1516 }
1517
1518 static void ni_ai_munge(comedi_device * dev, comedi_subdevice * s,
1519         void *data, unsigned int num_bytes, unsigned int chan_index)
1520 {
1521         comedi_async *async = s->async;
1522         unsigned int i;
1523         unsigned int length = num_bytes / bytes_per_sample(s);
1524         sampl_t *array = data;
1525         lsampl_t *larray = data;
1526         for (i = 0; i < length; i++) {
1527 #ifdef PCIDMA
1528                 if (s->subdev_flags & SDF_LSAMPL)
1529                         larray[i] = le32_to_cpu(larray[i]);
1530                 else
1531                         array[i] = le16_to_cpu(array[i]);
1532 #endif
1533                 if (s->subdev_flags & SDF_LSAMPL)
1534                         larray[i] += devpriv->ai_offset[chan_index];
1535                 else
1536                         array[i] += devpriv->ai_offset[chan_index];
1537                 chan_index++;
1538                 chan_index %= async->cmd.chanlist_len;
1539         }
1540 }
1541
1542 #ifdef PCIDMA
1543
1544 static int ni_ai_setup_MITE_dma(comedi_device * dev)
1545 {
1546         comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1547         int retval;
1548         unsigned long flags;
1549
1550         retval = ni_request_ai_mite_channel(dev);
1551         if (retval)
1552                 return retval;
1553 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1554
1555         /* write alloc the entire buffer */
1556         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1557
1558         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1559         if(devpriv->ai_mite_chan == NULL)
1560         {
1561                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1562                 return -EIO;
1563         }
1564
1565         switch (boardtype.reg_type) {
1566         case ni_reg_611x:
1567         case ni_reg_6143:
1568                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1569                 break;
1570         case ni_reg_628x:
1571                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1572                 break;
1573         default:
1574                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1575                 break;
1576         };
1577         /*start the MITE */
1578         mite_dma_arm(devpriv->ai_mite_chan);
1579         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1580
1581         return 0;
1582 }
1583
1584 static int ni_ao_setup_MITE_dma(comedi_device * dev)
1585 {
1586         comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1587         int retval;
1588         unsigned long flags;
1589
1590         retval = ni_request_ao_mite_channel(dev);
1591         if (retval)
1592                 return retval;
1593
1594         /* read alloc the entire buffer */
1595         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1596
1597         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1598         if (devpriv->ao_mite_chan) {
1599                 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1600                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1601                 } else {
1602                         /* doing 32 instead of 16 bit wide transfers from memory
1603                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1604                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1605                 }
1606                 mite_dma_arm(devpriv->ao_mite_chan);
1607         } else
1608                 retval = -EIO;
1609         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1610
1611         return retval;
1612 }
1613
1614 #endif // PCIDMA
1615
1616 /*
1617    used for both cancel ioctl and board initialization
1618
1619    this is pretty harsh for a cancel, but it works...
1620  */
1621
1622 static int ni_ai_reset(comedi_device * dev, comedi_subdevice * s)
1623 {
1624         ni_release_ai_mite_channel(dev);
1625         /* ai configuration */
1626         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1627                 Joint_Reset_Register);
1628
1629         ni_set_bits(dev, Interrupt_A_Enable_Register,
1630                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1631                 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1632                 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1633                 AI_FIFO_Interrupt_Enable, 0);
1634
1635         ni_clear_ai_fifo(dev);
1636
1637         if (boardtype.reg_type != ni_reg_6143)
1638                 ni_writeb(0, Misc_Command);
1639
1640         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1641         devpriv->stc_writew(dev,
1642                 AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */ ,
1643                 AI_Mode_1_Register);
1644         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1645         /* generate FIFO interrupts on non-empty */
1646         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1647         if (boardtype.reg_type == ni_reg_611x) {
1648                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1649                         AI_SOC_Polarity |
1650                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1651                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1652                         AI_EXTMUX_CLK_Output_Select(0) |
1653                         AI_LOCALMUX_CLK_Output_Select(2) |
1654                         AI_SC_TC_Output_Select(3) |
1655                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High),
1656                         AI_Output_Control_Register);
1657         } else if (boardtype.reg_type == ni_reg_6143) {
1658                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1659                         AI_SOC_Polarity |
1660                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1661                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1662                         AI_EXTMUX_CLK_Output_Select(0) |
1663                         AI_LOCALMUX_CLK_Output_Select(2) |
1664                         AI_SC_TC_Output_Select(3) |
1665                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),
1666                         AI_Output_Control_Register);
1667         } else {
1668                 unsigned ai_output_control_bits;
1669                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1670                         AI_SOC_Polarity |
1671                         AI_CONVERT_Pulse_Width |
1672                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1673                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1674                         AI_EXTMUX_CLK_Output_Select(0) |
1675                         AI_LOCALMUX_CLK_Output_Select(2) |
1676                         AI_SC_TC_Output_Select(3);
1677                 if (boardtype.reg_type == ni_reg_622x)
1678                         ai_output_control_bits |=
1679                                 AI_CONVERT_Output_Select
1680                                 (AI_CONVERT_Output_Enable_High);
1681                 else
1682                         ai_output_control_bits |=
1683                                 AI_CONVERT_Output_Select
1684                                 (AI_CONVERT_Output_Enable_Low);
1685                 devpriv->stc_writew(dev, ai_output_control_bits,
1686                         AI_Output_Control_Register);
1687         }
1688         /* the following registers should not be changed, because there
1689          * are no backup registers in devpriv.  If you want to change
1690          * any of these, add a backup register and other appropriate code:
1691          *      AI_Mode_1_Register
1692          *      AI_Mode_3_Register
1693          *      AI_Personal_Register
1694          *      AI_Output_Control_Register
1695          */
1696         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1697
1698         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1699
1700         return 0;
1701 }
1702
1703 static int ni_ai_poll(comedi_device * dev, comedi_subdevice * s)
1704 {
1705         unsigned long flags = 0;
1706         int count;
1707
1708         // lock to avoid race with interrupt handler
1709         if (in_interrupt() == 0)
1710                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1711 #ifndef PCIDMA
1712         ni_handle_fifo_dregs(dev);
1713 #else
1714         ni_sync_ai_dma(dev);
1715 #endif
1716         count = s->async->buf_write_count - s->async->buf_read_count;
1717         if (in_interrupt() == 0)
1718                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1719
1720         return count;
1721 }
1722
1723 static int ni_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
1724         comedi_insn * insn, lsampl_t * data)
1725 {
1726         int i, n;
1727         const unsigned int mask = (1 << boardtype.adbits) - 1;
1728         unsigned signbits;
1729         unsigned short d;
1730         unsigned long dl;
1731
1732         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1733
1734         ni_clear_ai_fifo(dev);
1735
1736         signbits = devpriv->ai_offset[0];
1737         if (boardtype.reg_type == ni_reg_611x) {
1738                 for (n = 0; n < num_adc_stages_611x; n++) {
1739                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1740                                 AI_Command_1_Register);
1741                         comedi_udelay(1);
1742                 }
1743                 for (n = 0; n < insn->n; n++) {
1744                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1745                                 AI_Command_1_Register);
1746                         /* The 611x has screwy 32-bit FIFOs. */
1747                         d = 0;
1748                         for (i = 0; i < NI_TIMEOUT; i++) {
1749                                 if (ni_readb(XXX_Status) & 0x80) {
1750                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1751                                                 & 0xffff;
1752                                         break;
1753                                 }
1754                                 if (!(devpriv->stc_readw(dev,
1755                                                         AI_Status_1_Register) &
1756                                                 AI_FIFO_Empty_St)) {
1757                                         d = ni_readl(ADC_FIFO_Data_611x) &
1758                                                 0xffff;
1759                                         break;
1760                                 }
1761                         }
1762                         if (i == NI_TIMEOUT) {
1763                                 rt_printk
1764                                         ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1765                                 return -ETIME;
1766                         }
1767                         d += signbits;
1768                         data[n] = d;
1769                 }
1770         } else if (boardtype.reg_type == ni_reg_6143) {
1771                 for (n = 0; n < insn->n; n++) {
1772                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1773                                 AI_Command_1_Register);
1774
1775                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1776                         dl = 0;
1777                         for (i = 0; i < NI_TIMEOUT; i++) {
1778                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1779                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1780                                         dl = ni_readl(AIFIFO_Data_6143);
1781                                         break;
1782                                 }
1783                         }
1784                         if (i == NI_TIMEOUT) {
1785                                 rt_printk
1786                                         ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1787                                 return -ETIME;
1788                         }
1789                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1790                 }
1791         } else {
1792                 for (n = 0; n < insn->n; n++) {
1793                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1794                                 AI_Command_1_Register);
1795                         for (i = 0; i < NI_TIMEOUT; i++) {
1796                                 if (!(devpriv->stc_readw(dev,
1797                                                         AI_Status_1_Register) &
1798                                                 AI_FIFO_Empty_St))
1799                                         break;
1800                         }
1801                         if (i == NI_TIMEOUT) {
1802                                 rt_printk
1803                                         ("ni_mio_common: timeout in ni_ai_insn_read\n");
1804                                 return -ETIME;
1805                         }
1806                         if (boardtype.reg_type & ni_reg_m_series_mask) {
1807                                 data[n] =
1808                                         ni_readl(M_Offset_AI_FIFO_Data) & mask;
1809                         } else {
1810                                 d = ni_readw(ADC_FIFO_Data_Register);
1811                                 d += signbits;  /* subtle: needs to be short addition */
1812                                 data[n] = d;
1813                         }
1814                 }
1815         }
1816         return insn->n;
1817 }
1818
1819 static void ni_prime_channelgain_list(comedi_device * dev)
1820 {
1821         int i;
1822         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1823         for (i = 0; i < NI_TIMEOUT; ++i) {
1824                 if (!(devpriv->stc_readw(dev,
1825                                         AI_Status_1_Register) &
1826                                 AI_FIFO_Empty_St)) {
1827                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1828                         return;
1829                 }
1830                 comedi_udelay(1);
1831         }
1832         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1833 }
1834
1835 static void ni_m_series_load_channelgain_list(comedi_device * dev,
1836         unsigned int n_chan, unsigned int *list)
1837 {
1838         unsigned int chan, range, aref;
1839         unsigned int i;
1840         unsigned offset;
1841         unsigned int dither;
1842         unsigned range_code;
1843
1844         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1845
1846 //      offset = 1 << (boardtype.adbits - 1);
1847         if ((list[0] & CR_ALT_SOURCE)) {
1848                 unsigned bypass_bits;
1849                 chan = CR_CHAN(list[0]);
1850                 range = CR_RANGE(list[0]);
1851                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1852                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1853                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1854                 bypass_bits |= chan;
1855                 bypass_bits |=
1856                         (devpriv->
1857                         ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1858                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1859                         MSeries_AI_Bypass_Mode_Mux_Mask |
1860                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1861                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1862                 if (dither)
1863                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1864                 // don't use 2's complement encoding
1865                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1866                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1867         } else {
1868                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1869         }
1870         offset = 0;
1871         for (i = 0; i < n_chan; i++) {
1872                 unsigned config_bits = 0;
1873                 chan = CR_CHAN(list[i]);
1874                 aref = CR_AREF(list[i]);
1875                 range = CR_RANGE(list[i]);
1876                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1877
1878                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1879                 devpriv->ai_offset[i] = offset;
1880                 switch (aref) {
1881                 case AREF_DIFF:
1882                         config_bits |=
1883                                 MSeries_AI_Config_Channel_Type_Differential_Bits;
1884                         break;
1885                 case AREF_COMMON:
1886                         config_bits |=
1887                                 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1888                         break;
1889                 case AREF_GROUND:
1890                         config_bits |=
1891                                 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1892                         break;
1893                 case AREF_OTHER:
1894                         break;
1895                 }
1896                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1897                 config_bits |=
1898                         MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1899                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1900                 if (i == n_chan - 1)
1901                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1902                 if (dither)
1903                         config_bits |= MSeries_AI_Config_Dither_Bit;
1904                 // don't use 2's complement encoding
1905                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1906                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1907         }
1908         ni_prime_channelgain_list(dev);
1909 }
1910
1911 /*
1912  * Notes on the 6110 and 6111:
1913  * These boards a slightly different than the rest of the series, since
1914  * they have multiple A/D converters.
1915  * From the driver side, the configuration memory is a
1916  * little different.
1917  * Configuration Memory Low:
1918  *   bits 15-9: same
1919  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1920  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1921  *       1001 gain=0.1 (+/- 50)
1922  *       1010 0.2
1923  *       1011 0.1
1924  *       0001 1
1925  *       0010 2
1926  *       0011 5
1927  *       0100 10
1928  *       0101 20
1929  *       0110 50
1930  * Configuration Memory High:
1931  *   bits 12-14: Channel Type
1932  *       001 for differential
1933  *       000 for calibration
1934  *   bit 11: coupling  (this is not currently handled)
1935  *       1 AC coupling
1936  *       0 DC coupling
1937  *   bits 0-2: channel
1938  *       valid channels are 0-3
1939  */
1940 static void ni_load_channelgain_list(comedi_device * dev, unsigned int n_chan,
1941         unsigned int *list)
1942 {
1943         unsigned int chan, range, aref;
1944         unsigned int i;
1945         unsigned int hi, lo;
1946         unsigned offset;
1947         unsigned int dither;
1948
1949         if (boardtype.reg_type & ni_reg_m_series_mask) {
1950                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1951                 return;
1952         }
1953         if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
1954                 && (boardtype.reg_type != ni_reg_6143)) {
1955                 if (devpriv->changain_state
1956                         && devpriv->changain_spec == list[0]) {
1957                         // ready to go.
1958                         return;
1959                 }
1960                 devpriv->changain_state = 1;
1961                 devpriv->changain_spec = list[0];
1962         } else {
1963                 devpriv->changain_state = 0;
1964         }
1965
1966         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1967
1968         // Set up Calibration mode if required
1969         if (boardtype.reg_type == ni_reg_6143) {
1970                 if ((list[0] & CR_ALT_SOURCE)
1971                         && !devpriv->ai_calib_source_enabled) {
1972                         // Strobe Relay enable bit
1973                         ni_writew(devpriv->
1974                                 ai_calib_source |
1975                                 Calibration_Channel_6143_RelayOn,
1976                                 Calibration_Channel_6143);
1977                         ni_writew(devpriv->ai_calib_source,
1978                                 Calibration_Channel_6143);
1979                         devpriv->ai_calib_source_enabled = 1;
1980                         msleep_interruptible(100);      // Allow relays to change
1981                 } else if (!(list[0] & CR_ALT_SOURCE)
1982                         && devpriv->ai_calib_source_enabled) {
1983                         // Strobe Relay disable bit
1984                         ni_writew(devpriv->
1985                                 ai_calib_source |
1986                                 Calibration_Channel_6143_RelayOff,
1987                                 Calibration_Channel_6143);
1988                         ni_writew(devpriv->ai_calib_source,
1989                                 Calibration_Channel_6143);
1990                         devpriv->ai_calib_source_enabled = 0;
1991                         msleep_interruptible(100);      // Allow relays to change
1992                 }
1993         }
1994
1995         offset = 1 << (boardtype.adbits - 1);
1996         for (i = 0; i < n_chan; i++) {
1997                 if ((boardtype.reg_type != ni_reg_6143)
1998                         && (list[i] & CR_ALT_SOURCE)) {
1999                         chan = devpriv->ai_calib_source;
2000                 } else {
2001                         chan = CR_CHAN(list[i]);
2002                 }
2003                 aref = CR_AREF(list[i]);
2004                 range = CR_RANGE(list[i]);
2005                 dither = ((list[i] & CR_ALT_FILTER) != 0);
2006
2007                 /* fix the external/internal range differences */
2008                 range = ni_gainlkup[boardtype.gainlkup][range];
2009                 if (boardtype.reg_type == ni_reg_611x)
2010                         devpriv->ai_offset[i] = offset;
2011                 else
2012                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2013
2014                 hi = 0;
2015                 if ((list[i] & CR_ALT_SOURCE)) {
2016                         if (boardtype.reg_type == ni_reg_611x)
2017                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
2018                                         Calibration_Channel_Select_611x);
2019                 } else {
2020                         if (boardtype.reg_type == ni_reg_611x)
2021                                 aref = AREF_DIFF;
2022                         else if (boardtype.reg_type == ni_reg_6143)
2023                                 aref = AREF_OTHER;
2024                         switch (aref) {
2025                         case AREF_DIFF:
2026                                 hi |= AI_DIFFERENTIAL;
2027                                 break;
2028                         case AREF_COMMON:
2029                                 hi |= AI_COMMON;
2030                                 break;
2031                         case AREF_GROUND:
2032                                 hi |= AI_GROUND;
2033                                 break;
2034                         case AREF_OTHER:
2035                                 break;
2036                         }
2037                 }
2038                 hi |= AI_CONFIG_CHANNEL(chan);
2039
2040                 ni_writew(hi, Configuration_Memory_High);
2041
2042                 if (boardtype.reg_type != ni_reg_6143) {
2043                         lo = range;
2044                         if (i == n_chan - 1)
2045                                 lo |= AI_LAST_CHANNEL;
2046                         if (dither)
2047                                 lo |= AI_DITHER;
2048
2049                         ni_writew(lo, Configuration_Memory_Low);
2050                 }
2051         }
2052
2053         /* prime the channel/gain list */
2054         if ((boardtype.reg_type != ni_reg_611x)
2055                 && (boardtype.reg_type != ni_reg_6143)) {
2056                 ni_prime_channelgain_list(dev);
2057         }
2058 }
2059
2060 static int ni_ns_to_timer(const comedi_device * dev, unsigned nanosec,
2061         int round_mode)
2062 {
2063         int divider;
2064         switch (round_mode) {
2065         case TRIG_ROUND_NEAREST:
2066         default:
2067                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2068                 break;
2069         case TRIG_ROUND_DOWN:
2070                 divider = (nanosec) / devpriv->clock_ns;
2071                 break;
2072         case TRIG_ROUND_UP:
2073                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2074                 break;
2075         }
2076         return divider - 1;
2077 }
2078
2079 static unsigned ni_timer_to_ns(const comedi_device * dev, int timer)
2080 {
2081         return devpriv->clock_ns * (timer + 1);
2082 }
2083
2084 static unsigned ni_min_ai_scan_period_ns(comedi_device * dev,
2085         unsigned num_channels)
2086 {
2087         switch (boardtype.reg_type) {
2088         case ni_reg_611x:
2089         case ni_reg_6143:
2090                 // simultaneously-sampled inputs
2091                 return boardtype.ai_speed;
2092                 break;
2093         default:
2094                 // multiplexed inputs
2095                 break;
2096         };
2097         return boardtype.ai_speed * num_channels;
2098 }
2099
2100 static int ni_ai_cmdtest(comedi_device * dev, comedi_subdevice * s,
2101         comedi_cmd * cmd)
2102 {
2103         int err = 0;
2104         int tmp;
2105         int sources;
2106
2107         /* step 1: make sure trigger sources are trivially valid */
2108
2109         if ((cmd->flags & CMDF_WRITE)) {
2110                 cmd->flags &= ~CMDF_WRITE;
2111         }
2112
2113         tmp = cmd->start_src;
2114         cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2115         if (!cmd->start_src || tmp != cmd->start_src)
2116                 err++;
2117
2118         tmp = cmd->scan_begin_src;
2119         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2120         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2121                 err++;
2122
2123         tmp = cmd->convert_src;
2124         sources = TRIG_TIMER | TRIG_EXT;
2125         if ((boardtype.reg_type == ni_reg_611x)
2126                 || (boardtype.reg_type == ni_reg_6143))
2127                 sources |= TRIG_NOW;
2128         cmd->convert_src &= sources;
2129         if (!cmd->convert_src || tmp != cmd->convert_src)
2130                 err++;
2131
2132         tmp = cmd->scan_end_src;
2133         cmd->scan_end_src &= TRIG_COUNT;
2134         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2135                 err++;
2136
2137         tmp = cmd->stop_src;
2138         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2139         if (!cmd->stop_src || tmp != cmd->stop_src)
2140                 err++;
2141
2142         if (err)
2143                 return 1;
2144
2145         /* step 2: make sure trigger sources are unique and mutually compatible */
2146
2147         /* note that mutual compatiblity is not an issue here */
2148         if (cmd->start_src != TRIG_NOW &&
2149                 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2150                 err++;
2151         if (cmd->scan_begin_src != TRIG_TIMER &&
2152                 cmd->scan_begin_src != TRIG_EXT &&
2153                 cmd->scan_begin_src != TRIG_OTHER)
2154                 err++;
2155         if (cmd->convert_src != TRIG_TIMER &&
2156                 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2157                 err++;
2158         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2159                 err++;
2160
2161         if (err)
2162                 return 2;
2163
2164         /* step 3: make sure arguments are trivially compatible */
2165
2166         if (cmd->start_src == TRIG_EXT) {
2167                 /* external trigger */
2168                 unsigned int tmp = CR_CHAN(cmd->start_arg);
2169
2170                 if (tmp > 16)
2171                         tmp = 16;
2172                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2173                 if (cmd->start_arg != tmp) {
2174                         cmd->start_arg = tmp;
2175                         err++;
2176                 }
2177         } else {
2178                 if (cmd->start_arg != 0) {
2179                         /* true for both TRIG_NOW and TRIG_INT */
2180                         cmd->start_arg = 0;
2181                         err++;
2182                 }
2183         }
2184         if (cmd->scan_begin_src == TRIG_TIMER) {
2185                 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2186                                 cmd->chanlist_len)) {
2187                         cmd->scan_begin_arg =
2188                                 ni_min_ai_scan_period_ns(dev,
2189                                 cmd->chanlist_len);
2190                         err++;
2191                 }
2192                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2193                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2194                         err++;
2195                 }
2196         } else if (cmd->scan_begin_src == TRIG_EXT) {
2197                 /* external trigger */
2198                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2199
2200                 if (tmp > 16)
2201                         tmp = 16;
2202                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2203                 if (cmd->scan_begin_arg != tmp) {
2204                         cmd->scan_begin_arg = tmp;
2205                         err++;
2206                 }
2207         } else {                /* TRIG_OTHER */
2208                 if (cmd->scan_begin_arg) {
2209                         cmd->scan_begin_arg = 0;
2210                         err++;
2211                 }
2212         }
2213         if (cmd->convert_src == TRIG_TIMER) {
2214                 if ((boardtype.reg_type == ni_reg_611x)
2215                         || (boardtype.reg_type == ni_reg_6143)) {
2216                         if (cmd->convert_arg != 0) {
2217                                 cmd->convert_arg = 0;
2218                                 err++;
2219                         }
2220                 } else {
2221                         if (cmd->convert_arg < boardtype.ai_speed) {
2222                                 cmd->convert_arg = boardtype.ai_speed;
2223                                 err++;
2224                         }
2225                         if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2226                                 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2227                                 err++;
2228                         }
2229                 }
2230         } else if (cmd->convert_src == TRIG_EXT) {
2231                 /* external trigger */
2232                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2233
2234                 if (tmp > 16)
2235                         tmp = 16;
2236                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2237                 if (cmd->convert_arg != tmp) {
2238                         cmd->convert_arg = tmp;
2239                         err++;
2240                 }
2241         } else if (cmd->convert_src == TRIG_NOW) {
2242                 if (cmd->convert_arg != 0) {
2243                         cmd->convert_arg = 0;
2244                         err++;
2245                 }
2246         }
2247
2248         if (cmd->scan_end_arg != cmd->chanlist_len) {
2249                 cmd->scan_end_arg = cmd->chanlist_len;
2250                 err++;
2251         }
2252         if (cmd->stop_src == TRIG_COUNT) {
2253                 unsigned int max_count = 0x01000000;
2254
2255                 if (boardtype.reg_type == ni_reg_611x)
2256                         max_count -= num_adc_stages_611x;
2257                 if (cmd->stop_arg > max_count) {
2258                         cmd->stop_arg = max_count;
2259                         err++;
2260                 }
2261                 if (cmd->stop_arg < 1) {
2262                         cmd->stop_arg = 1;
2263                         err++;
2264                 }
2265         } else {
2266                 /* TRIG_NONE */
2267                 if (cmd->stop_arg != 0) {
2268                         cmd->stop_arg = 0;
2269                         err++;
2270                 }
2271         }
2272
2273         if (err)
2274                 return 3;
2275
2276         /* step 4: fix up any arguments */
2277
2278         if (cmd->scan_begin_src == TRIG_TIMER) {
2279                 tmp = cmd->scan_begin_arg;
2280                 cmd->scan_begin_arg =
2281                         ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2282                                 cmd->scan_begin_arg,
2283                                 cmd->flags & TRIG_ROUND_MASK));
2284                 if (tmp != cmd->scan_begin_arg)
2285                         err++;
2286         }
2287         if (cmd->convert_src == TRIG_TIMER) {
2288                 if ((boardtype.reg_type != ni_reg_611x)
2289                         && (boardtype.reg_type != ni_reg_6143)) {
2290                         tmp = cmd->convert_arg;
2291                         cmd->convert_arg =
2292                                 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2293                                         cmd->convert_arg,
2294                                         cmd->flags & TRIG_ROUND_MASK));
2295                         if (tmp != cmd->convert_arg)
2296                                 err++;
2297                         if (cmd->scan_begin_src == TRIG_TIMER &&
2298                                 cmd->scan_begin_arg <
2299                                 cmd->convert_arg * cmd->scan_end_arg) {
2300                                 cmd->scan_begin_arg =
2301                                         cmd->convert_arg * cmd->scan_end_arg;
2302                                 err++;
2303                         }
2304                 }
2305         }
2306
2307         if (err)
2308                 return 4;
2309
2310         return 0;
2311 }
2312
2313 static int ni_ai_cmd(comedi_device * dev, comedi_subdevice * s)
2314 {
2315         const comedi_cmd *cmd = &s->async->cmd;
2316         int timer;
2317         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2318         int mode2 = 0;
2319         int start_stop_select = 0;
2320         unsigned int stop_count;
2321         int interrupt_a_enable = 0;
2322
2323         MDPRINTK("ni_ai_cmd\n");
2324         if (dev->irq == 0) {
2325                 comedi_error(dev, "cannot run command without an irq");
2326                 return -EIO;
2327         }
2328         ni_clear_ai_fifo(dev);
2329
2330         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2331
2332         /* start configuration */
2333         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2334
2335         /* disable analog triggering for now, since it
2336          * interferes with the use of pfi0 */
2337         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2338         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2339                 Analog_Trigger_Etc_Register);
2340
2341         switch (cmd->start_src) {
2342         case TRIG_INT:
2343         case TRIG_NOW:
2344                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2345                         AI_START1_Sync | AI_START1_Edge | AI_START1_Select(0),
2346                         AI_Trigger_Select_Register);
2347                 break;
2348         case TRIG_EXT:
2349                 {
2350                         int chan = CR_CHAN(cmd->start_arg);
2351                         unsigned int bits = AI_START2_Select(0) |
2352                                 AI_START1_Sync | AI_START1_Select(chan + 1);
2353
2354                         if (cmd->start_arg & CR_INVERT)
2355                                 bits |= AI_START1_Polarity;
2356                         if (cmd->start_arg & CR_EDGE)
2357                                 bits |= AI_START1_Edge;
2358                         devpriv->stc_writew(dev, bits,
2359                                 AI_Trigger_Select_Register);
2360                         break;
2361                 }
2362         }
2363
2364         mode2 &= ~AI_Pre_Trigger;
2365         mode2 &= ~AI_SC_Initial_Load_Source;
2366         mode2 &= ~AI_SC_Reload_Mode;
2367         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2368
2369         if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2370                 || (boardtype.reg_type == ni_reg_6143)) {
2371                 start_stop_select |= AI_STOP_Polarity;
2372                 start_stop_select |= AI_STOP_Select(31);        // logic low
2373                 start_stop_select |= AI_STOP_Sync;
2374         } else {
2375                 start_stop_select |= AI_STOP_Select(19);        // ai configuration memory
2376         }
2377         devpriv->stc_writew(dev, start_stop_select,
2378                 AI_START_STOP_Select_Register);
2379
2380         devpriv->ai_cmd2 = 0;
2381         switch (cmd->stop_src) {
2382         case TRIG_COUNT:
2383                 stop_count = cmd->stop_arg - 1;
2384
2385                 if (boardtype.reg_type == ni_reg_611x) {
2386                         // have to take 3 stage adc pipeline into account
2387                         stop_count += num_adc_stages_611x;
2388                 }
2389                 /* stage number of scans */
2390                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2391
2392                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2393                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2394                 /* load SC (Scan Count) */
2395                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2396
2397                 devpriv->ai_continuous = 0;
2398                 if (stop_count == 0) {
2399                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2400                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2401                         // this is required to get the last sample for chanlist_len > 1, not sure why
2402                         if (cmd->chanlist_len > 1)
2403                                 start_stop_select |=
2404                                         AI_STOP_Polarity | AI_STOP_Edge;
2405                 }
2406                 break;
2407         case TRIG_NONE:
2408                 /* stage number of scans */
2409                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2410
2411                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2412                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2413
2414                 /* load SC (Scan Count) */
2415                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2416
2417                 devpriv->ai_continuous = 1;
2418
2419                 break;
2420         }
2421
2422         switch (cmd->scan_begin_src) {
2423         case TRIG_TIMER:
2424                 /*
2425                    stop bits for non 611x boards
2426                    AI_SI_Special_Trigger_Delay=0
2427                    AI_Pre_Trigger=0
2428                    AI_START_STOP_Select_Register:
2429                    AI_START_Polarity=0 (?)      rising edge
2430                    AI_START_Edge=1              edge triggered
2431                    AI_START_Sync=1 (?)
2432                    AI_START_Select=0            SI_TC
2433                    AI_STOP_Polarity=0           rising edge
2434                    AI_STOP_Edge=0               level
2435                    AI_STOP_Sync=1
2436                    AI_STOP_Select=19            external pin (configuration mem)
2437                  */
2438                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2439                 devpriv->stc_writew(dev, start_stop_select,
2440                         AI_START_STOP_Select_Register);
2441
2442                 mode2 |= AI_SI_Reload_Mode(0);
2443                 /* AI_SI_Initial_Load_Source=A */
2444                 mode2 &= ~AI_SI_Initial_Load_Source;
2445                 //mode2 |= AI_SC_Reload_Mode;
2446                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2447
2448                 /* load SI */
2449                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2450                         TRIG_ROUND_NEAREST);
2451                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2452                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2453                 break;
2454         case TRIG_EXT:
2455                 if (cmd->scan_begin_arg & CR_EDGE)
2456                         start_stop_select |= AI_START_Edge;
2457                 /* AI_START_Polarity==1 is falling edge */
2458                 if (cmd->scan_begin_arg & CR_INVERT)
2459                         start_stop_select |= AI_START_Polarity;
2460                 if (cmd->scan_begin_src != cmd->convert_src ||
2461                         (cmd->scan_begin_arg & ~CR_EDGE) !=
2462                         (cmd->convert_arg & ~CR_EDGE))
2463                         start_stop_select |= AI_START_Sync;
2464                 start_stop_select |=
2465                         AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2466                 devpriv->stc_writew(dev, start_stop_select,
2467                         AI_START_STOP_Select_Register);
2468                 break;
2469         }
2470
2471         switch (cmd->convert_src) {
2472         case TRIG_TIMER:
2473         case TRIG_NOW:
2474                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2475                         timer = 1;
2476                 else
2477                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2478                                 TRIG_ROUND_NEAREST);
2479                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2480                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2481
2482                 /* AI_SI2_Reload_Mode = alternate */
2483                 /* AI_SI2_Initial_Load_Source = A */
2484                 mode2 &= ~AI_SI2_Initial_Load_Source;
2485                 mode2 |= AI_SI2_Reload_Mode;
2486                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2487
2488                 /* AI_SI2_Load */
2489                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2490
2491                 mode2 |= AI_SI2_Reload_Mode;    // alternate
2492                 mode2 |= AI_SI2_Initial_Load_Source;    // B
2493
2494                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2495                 break;
2496         case TRIG_EXT:
2497                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2498                 if ((cmd->convert_arg & CR_INVERT) == 0)
2499                         mode1 |= AI_CONVERT_Source_Polarity;
2500                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2501
2502                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2503                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2504
2505                 break;
2506         }
2507
2508         if (dev->irq) {
2509
2510                 /* interrupt on FIFO, errors, SC_TC */
2511                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2512                         AI_SC_TC_Interrupt_Enable;
2513
2514 #ifndef PCIDMA
2515                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2516 #endif
2517
2518                 if (cmd->flags & TRIG_WAKE_EOS
2519                         || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2520                         /* wake on end-of-scan */
2521                         devpriv->aimode = AIMODE_SCAN;
2522                 } else {
2523                         devpriv->aimode = AIMODE_HALF_FULL;
2524                 }
2525
2526                 switch (devpriv->aimode) {
2527                 case AIMODE_HALF_FULL:
2528                         /*generate FIFO interrupts and DMA requests on half-full */
2529 #ifdef PCIDMA
2530                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2531                                 AI_Mode_3_Register);
2532 #else
2533                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2534                                 AI_Mode_3_Register);
2535 #endif
2536                         break;
2537                 case AIMODE_SAMPLE:
2538                         /*generate FIFO interrupts on non-empty */
2539                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2540                                 AI_Mode_3_Register);
2541                         break;
2542                 case AIMODE_SCAN:
2543 #ifdef PCIDMA
2544                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2545                                 AI_Mode_3_Register);
2546 #else
2547                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2548                                 AI_Mode_3_Register);
2549 #endif
2550                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2551                         break;
2552                 default:
2553                         break;
2554                 }
2555
2556                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2557
2558                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2559                         interrupt_a_enable, 1);
2560
2561                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2562                         devpriv->int_a_enable_reg);
2563         } else {
2564                 /* interrupt on nothing */
2565                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2566
2567                 /* XXX start polling if necessary */
2568                 MDPRINTK("interrupting on nothing\n");
2569         }
2570
2571         /* end configuration */
2572         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2573
2574         switch (cmd->scan_begin_src) {
2575         case TRIG_TIMER:
2576                 devpriv->stc_writew(dev,
2577                         AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2578                         AI_Command_1_Register);
2579                 break;
2580         case TRIG_EXT:
2581                 /* XXX AI_SI_Arm? */
2582                 devpriv->stc_writew(dev,
2583                         AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2584                         AI_Command_1_Register);
2585                 break;
2586         }
2587
2588 #ifdef PCIDMA
2589         {
2590                 int retval = ni_ai_setup_MITE_dma(dev);
2591                 if (retval)
2592                         return retval;
2593         }
2594         //mite_dump_regs(devpriv->mite);
2595 #endif
2596
2597         switch (cmd->start_src) {
2598         case TRIG_NOW:
2599                 /* AI_START1_Pulse */
2600                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2601                         AI_Command_2_Register);
2602                 s->async->inttrig = NULL;
2603                 break;
2604         case TRIG_EXT:
2605                 s->async->inttrig = NULL;
2606                 break;
2607         case TRIG_INT:
2608                 s->async->inttrig = &ni_ai_inttrig;
2609                 break;
2610         }
2611
2612         MDPRINTK("exit ni_ai_cmd\n");
2613
2614         return 0;
2615 }
2616
2617 static int ni_ai_inttrig(comedi_device * dev, comedi_subdevice * s,
2618         unsigned int trignum)
2619 {
2620         if (trignum != 0)
2621                 return -EINVAL;
2622
2623         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2624                 AI_Command_2_Register);
2625         s->async->inttrig = NULL;
2626
2627         return 1;
2628 }
2629
2630 static int ni_ai_config_analog_trig(comedi_device * dev, comedi_subdevice * s,
2631         comedi_insn * insn, lsampl_t * data);
2632
2633 static int ni_ai_insn_config(comedi_device * dev, comedi_subdevice * s,
2634         comedi_insn * insn, lsampl_t * data)
2635 {
2636         if (insn->n < 1)
2637                 return -EINVAL;
2638
2639         switch (data[0]) {
2640         case INSN_CONFIG_ANALOG_TRIG:
2641                 return ni_ai_config_analog_trig(dev, s, insn, data);
2642         case INSN_CONFIG_ALT_SOURCE:
2643                 if (boardtype.reg_type & ni_reg_m_series_mask) {
2644                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2645                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2646                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2647                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2648                                 return -EINVAL;
2649                         }
2650                         devpriv->ai_calib_source = data[1];
2651                 } else if (boardtype.reg_type == ni_reg_6143) {
2652                         unsigned int calib_source;
2653
2654                         calib_source = data[1] & 0xf;
2655
2656                         if (calib_source > 0xF)
2657                                 return -EINVAL;
2658
2659                         devpriv->ai_calib_source = calib_source;
2660                         ni_writew(calib_source, Calibration_Channel_6143);
2661                 } else {
2662                         unsigned int calib_source;
2663                         unsigned int calib_source_adjust;
2664
2665                         calib_source = data[1] & 0xf;
2666                         calib_source_adjust = (data[1] >> 4) & 0xff;
2667
2668                         if (calib_source >= 8)
2669                                 return -EINVAL;
2670                         devpriv->ai_calib_source = calib_source;
2671                         if (boardtype.reg_type == ni_reg_611x) {
2672                                 ni_writeb(calib_source_adjust,
2673                                         Cal_Gain_Select_611x);
2674                         }
2675                 }
2676                 return 2;
2677         default:
2678                 break;
2679         }
2680
2681         return -EINVAL;
2682 }
2683
2684 static int ni_ai_config_analog_trig(comedi_device * dev, comedi_subdevice * s,
2685         comedi_insn * insn, lsampl_t * data)
2686 {
2687         unsigned int a, b, modebits;
2688         int err = 0;
2689
2690         /* data[1] is flags
2691          * data[2] is analog line
2692          * data[3] is set level
2693          * data[4] is reset level */
2694         if (!boardtype.has_analog_trig)
2695                 return -EINVAL;
2696         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2697                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2698                 err++;
2699         }
2700         if (data[2] >= boardtype.n_adchan) {
2701                 data[2] = boardtype.n_adchan - 1;
2702                 err++;
2703         }
2704         if (data[3] > 255) {    /* a */
2705                 data[3] = 255;
2706                 err++;
2707         }
2708         if (data[4] > 255) {    /* b */
2709                 data[4] = 255;
2710                 err++;
2711         }
2712         /*
2713          * 00 ignore
2714          * 01 set
2715          * 10 reset
2716          *
2717          * modes:
2718          *   1 level:                    +b-   +a-
2719          *     high mode                00 00 01 10
2720          *     low mode                 00 00 10 01
2721          *   2 level: (a<b)
2722          *     hysteresis low mode      10 00 00 01
2723          *     hysteresis high mode     01 00 00 10
2724          *     middle mode              10 01 01 10
2725          */
2726
2727         a = data[3];
2728         b = data[4];
2729         modebits = data[1] & 0xff;
2730         if (modebits & 0xf0) {
2731                 /* two level mode */
2732                 if (b < a) {
2733                         /* swap order */
2734                         a = data[4];
2735                         b = data[3];
2736                         modebits =
2737                                 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >>
2738                                 4);
2739                 }
2740                 devpriv->atrig_low = a;
2741                 devpriv->atrig_high = b;
2742                 switch (modebits) {
2743                 case 0x81:      /* low hysteresis mode */
2744                         devpriv->atrig_mode = 6;
2745                         break;
2746                 case 0x42:      /* high hysteresis mode */
2747                         devpriv->atrig_mode = 3;
2748                         break;
2749                 case 0x96:      /* middle window mode */
2750                         devpriv->atrig_mode = 2;
2751                         break;
2752                 default:
2753                         data[1] &= ~0xff;
2754                         err++;
2755                 }
2756         } else {
2757                 /* one level mode */
2758                 if (b != 0) {
2759                         data[4] = 0;
2760                         err++;
2761                 }
2762                 switch (modebits) {
2763                 case 0x06:      /* high window mode */
2764                         devpriv->atrig_high = a;
2765                         devpriv->atrig_mode = 0;
2766                         break;
2767                 case 0x09:      /* low window mode */
2768                         devpriv->atrig_low = a;
2769                         devpriv->atrig_mode = 1;
2770                         break;
2771                 default:
2772                         data[1] &= ~0xff;
2773                         err++;
2774                 }
2775         }
2776         if (err)
2777                 return -EAGAIN;
2778         return 5;
2779 }
2780
2781 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2782 static void ni_ao_munge(comedi_device * dev, comedi_subdevice * s,
2783         void *data, unsigned int num_bytes, unsigned int chan_index)
2784 {
2785         comedi_async *async = s->async;
2786         unsigned int range;
2787         unsigned int i;
2788         unsigned int offset;
2789         unsigned int length = num_bytes / sizeof(sampl_t);
2790         sampl_t *array = data;
2791
2792         offset = 1 << (boardtype.aobits - 1);
2793         for (i = 0; i < length; i++) {
2794                 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2795                 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2796                         array[i] -= offset;
2797 #ifdef PCIDMA
2798                 array[i] = cpu_to_le16(array[i]);
2799 #endif
2800                 chan_index++;
2801                 chan_index %= async->cmd.chanlist_len;
2802         }
2803 }
2804
2805 static int ni_m_series_ao_config_chanlist(comedi_device * dev,
2806         comedi_subdevice * s, unsigned int chanspec[], unsigned int n_chans,
2807         int timed)
2808 {
2809         unsigned int range;
2810         unsigned int chan;
2811         unsigned int conf;
2812         int i;
2813         int invert = 0;
2814
2815         if(timed) {
2816                 for (i = 0; i < boardtype.n_aochan; ++i) {
2817                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2818                         ni_writeb(devpriv->ao_conf[i], M_Offset_AO_Config_Bank(i));
2819                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2820                 }
2821         }
2822         for (i = 0; i < n_chans; i++) {
2823                 const comedi_krange *krange;
2824                 chan = CR_CHAN(chanspec[i]);
2825                 range = CR_RANGE(chanspec[i]);
2826                 krange = s->range_table->range + range;
2827                 invert = 0;
2828                 conf = 0;
2829                 switch (krange->max - krange->min) {
2830                 case 20000000:
2831                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2832                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2833                         break;
2834                 case 10000000:
2835                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2836                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2837                         break;
2838                 case 4000000:
2839                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2840                         ni_writeb(MSeries_Attenuate_x5_Bit,
2841                                 M_Offset_AO_Reference_Attenuation(chan));
2842                         break;
2843                 case 2000000:
2844                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2845                         ni_writeb(MSeries_Attenuate_x5_Bit,
2846                                 M_Offset_AO_Reference_Attenuation(chan));
2847                         break;
2848                 default:
2849                         rt_printk("%s: bug! unhandled ao reference voltage\n",
2850                                 __FUNCTION__);
2851                         break;
2852                 }
2853                 switch (krange->max + krange->min) {
2854                 case 0:
2855                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2856                         break;
2857                 case 10000000:
2858                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2859                         break;
2860                 default:
2861                         rt_printk("%s: bug! unhandled ao offset voltage\n",
2862                                 __FUNCTION__);
2863                         break;
2864                 }
2865                 if (timed)
2866                         conf |= MSeries_AO_Update_Timed_Bit;
2867                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2868                 devpriv->ao_conf[chan] = conf;
2869                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2870         }
2871         return invert;
2872 }
2873
2874 static int ni_old_ao_config_chanlist(comedi_device * dev, comedi_subdevice * s,
2875         unsigned int chanspec[], unsigned int n_chans)
2876 {
2877         unsigned int range;
2878         unsigned int chan;
2879         unsigned int conf;
2880         int i;
2881         int invert = 0;
2882
2883         for (i = 0; i < n_chans; i++) {
2884                 chan = CR_CHAN(chanspec[i]);
2885                 range = CR_RANGE(chanspec[i]);
2886                 conf = AO_Channel(chan);
2887
2888                 if (boardtype.ao_unipolar) {
2889                         if ((range & 1) == 0) {
2890                                 conf |= AO_Bipolar;
2891                                 invert = (1 << (boardtype.aobits - 1));
2892                         } else {
2893                                 invert = 0;
2894                         }
2895                         if (range & 2)
2896                                 conf |= AO_Ext_Ref;
2897                 } else {
2898                         conf |= AO_Bipolar;
2899                         invert = (1 << (boardtype.aobits - 1));
2900                 }
2901
2902                 /* not all boards can deglitch, but this shouldn't hurt */
2903                 if (chanspec[i] & CR_DEGLITCH)
2904                         conf |= AO_Deglitch;
2905
2906                 /* analog reference */
2907                 /* AREF_OTHER connects AO ground to AI ground, i think */
2908                 conf |= (CR_AREF(chanspec[i]) ==
2909                         AREF_OTHER) ? AO_Ground_Ref : 0;
2910
2911                 ni_writew(conf, AO_Configuration);
2912                 devpriv->ao_conf[chan] = conf;
2913         }
2914         return invert;
2915 }
2916
2917 static int ni_ao_config_chanlist(comedi_device * dev, comedi_subdevice * s,
2918         unsigned int chanspec[], unsigned int n_chans, int timed)
2919 {
2920         if (boardtype.reg_type & ni_reg_m_series_mask)
2921                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2922                         timed);
2923         else
2924                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2925 }
2926 static int ni_ao_insn_read(comedi_device * dev, comedi_subdevice * s,
2927         comedi_insn * insn, lsampl_t * data)
2928 {
2929         if (insn->n == 0)
2930                 return 0;
2931
2932         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2933
2934         return 1;
2935 }
2936
2937 static int ni_ao_insn_write(comedi_device * dev, comedi_subdevice * s,
2938         comedi_insn * insn, lsampl_t * data)
2939 {
2940         unsigned int chan = CR_CHAN(insn->chanspec);
2941         unsigned int invert;
2942
2943         if (insn->n == 0)
2944                 return 0;
2945
2946         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2947
2948         devpriv->ao[chan] = data[0];
2949
2950         if (boardtype.reg_type & ni_reg_m_series_mask) {
2951                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2952         } else
2953                 ni_writew(data[0] ^ invert,
2954                         (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2955
2956         return 1;
2957 }
2958
2959 static int ni_ao_insn_write_671x(comedi_device * dev, comedi_subdevice * s,
2960         comedi_insn * insn, lsampl_t * data)
2961 {
2962         unsigned int chan = CR_CHAN(insn->chanspec);
2963         unsigned int invert;
2964
2965         if (insn->n == 0)
2966                 return 0;
2967
2968         ao_win_out(1 << chan, AO_Immediate_671x);
2969         invert = 1 << (boardtype.aobits - 1);
2970
2971         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2972
2973         devpriv->ao[chan] = data[0];
2974         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2975
2976         return 1;
2977 }
2978
2979 static int ni_ao_insn_config(comedi_device * dev, comedi_subdevice * s,
2980         comedi_insn * insn, lsampl_t * data)
2981 {
2982         switch (data[0]) {
2983         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2984                 switch(data[1])
2985                 {
2986                 case COMEDI_OUTPUT:
2987                         data[2] = 1 + boardtype.ao_fifo_depth * sizeof(sampl_t);
2988                         if(devpriv->mite) data[2] += devpriv->mite->fifo_size;
2989                         break;
2990                 case COMEDI_INPUT:
2991                         data[2] = 0;
2992                         break;
2993                 default:
2994                         return -EINVAL;
2995                         break;
2996                 }
2997                 return 0;
2998         default:
2999                 break;
3000         }
3001
3002         return -EINVAL;
3003 }
3004
3005 static int ni_ao_inttrig(comedi_device * dev, comedi_subdevice * s,
3006         unsigned int trignum)
3007 {
3008         int ret;
3009         int interrupt_b_bits;
3010         int i;
3011         static const int timeout = 1000;
3012
3013         if (trignum != 0)
3014                 return -EINVAL;
3015
3016         /* Null trig at beginning prevent ao start trigger from executing more than
3017            once per command (and doing things like trying to allocate the ao dma channel
3018            multiple times) */
3019         s->async->inttrig = NULL;
3020
3021         ni_set_bits(dev, Interrupt_B_Enable_Register,
3022                 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3023         interrupt_b_bits = AO_Error_Interrupt_Enable;
3024 #ifdef PCIDMA
3025         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3026         if (boardtype.reg_type & ni_reg_6xxx_mask)
3027                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3028         ret = ni_ao_setup_MITE_dma(dev);
3029         if (ret)
3030                 return ret;
3031         ret = ni_ao_wait_for_dma_load(dev);
3032         if (ret < 0)
3033                 return ret;
3034 #else
3035         ret = ni_ao_prep_fifo(dev, s);
3036         if (ret == 0)
3037                 return -EPIPE;
3038
3039         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3040 #endif
3041
3042         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3043                 AO_Mode_3_Register);
3044         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3045         /* wait for DACs to be loaded */
3046         for (i = 0; i < timeout; i++) {
3047                 comedi_udelay(1);
3048                 if ((devpriv->stc_readw(dev,
3049                                         Joint_Status_2_Register) &
3050                                 AO_TMRDACWRs_In_Progress_St) == 0)
3051                         break;
3052         }
3053         if (i == timeout) {
3054                 comedi_error(dev,
3055                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3056                 return -EIO;
3057         }
3058         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
3059         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3060                 Interrupt_B_Ack_Register);
3061
3062         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3063
3064         devpriv->stc_writew(dev,
3065                 devpriv->
3066                 ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3067                 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3068                 AO_Command_1_Register);
3069
3070         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3071                 AO_Command_2_Register);
3072
3073         return 0;
3074 }
3075
3076 static int ni_ao_cmd(comedi_device * dev, comedi_subdevice * s)
3077 {
3078         const comedi_cmd *cmd = &s->async->cmd;
3079         int bits;
3080         int i;
3081         unsigned trigvar;
3082
3083         if (dev->irq == 0) {
3084                 comedi_error(dev, "cannot run command without an irq");
3085                 return -EIO;
3086         }
3087
3088         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3089
3090         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3091
3092         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3093                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3094
3095                 bits = 0;
3096                 for (i = 0; i < cmd->chanlist_len; i++) {
3097                         int chan;
3098
3099                         chan = CR_CHAN(cmd->chanlist[i]);
3100                         bits |= 1 << chan;
3101                         ao_win_out(chan, AO_Waveform_Generation_611x);
3102                 }
3103                 ao_win_out(bits, AO_Timed_611x);
3104         }
3105
3106         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3107
3108         if (cmd->stop_src == TRIG_NONE) {
3109                 devpriv->ao_mode1 |= AO_Continuous;
3110                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3111         } else {
3112                 devpriv->ao_mode1 &= ~AO_Continuous;
3113                 devpriv->ao_mode1 |= AO_Trigger_Once;
3114         }
3115         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3116         switch (cmd->start_src) {
3117         case TRIG_INT:
3118         case TRIG_NOW:
3119                 devpriv->ao_trigger_select &=
3120                         ~(AO_START1_Polarity | AO_START1_Select(-1));
3121                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3122                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3123                         AO_Trigger_Select_Register);
3124                 break;
3125         case TRIG_EXT:
3126                 devpriv->ao_trigger_select = AO_START1_Select(CR_CHAN(cmd->start_arg)+1);
3127                 if (cmd->start_arg & CR_INVERT)
3128                         devpriv->ao_trigger_select |= AO_START1_Polarity;  // 0=active high, 1=active low. see daq-stc 3-24 (p186)
3129                 if (cmd->start_arg & CR_EDGE)
3130                         devpriv->ao_trigger_select |= AO_START1_Edge;      // 0=edge detection disabled, 1=enabled
3131                 devpriv->stc_writew(dev, devpriv->ao_trigger_select, AO_Trigger_Select_Register);
3132                 break;
3133         default:
3134                 BUG();
3135                 break;
3136         }
3137         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3138         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3139
3140         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3141         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3142         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3143         if (cmd->stop_src == TRIG_NONE) {
3144                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3145         } else {
3146                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3147         }
3148         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3149         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3150         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3151         switch (cmd->stop_src) {
3152         case TRIG_COUNT:
3153                 if(boardtype.reg_type & ni_reg_m_series_mask)
3154                 {
3155                         // this is how the NI example code does it for m-series boards, verified correct with 6259
3156                         devpriv->stc_writel(dev, cmd->stop_arg - 1, AO_UC_Load_A_Register);
3157                         devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3158                 }else
3159                 {
3160                         devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3161                         devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3162                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3163                                 AO_UC_Load_A_Register);
3164                 }
3165                 break;
3166         case TRIG_NONE:
3167                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3168                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3169                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3170                 break;
3171         default:
3172                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3173                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3174                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3175         }
3176
3177         devpriv->ao_mode1 &=
3178                 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3179                 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3180         switch (cmd->scan_begin_src) {
3181         case TRIG_TIMER:
3182                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3183                 trigvar =
3184                         ni_ns_to_timer(dev, cmd->scan_begin_arg,
3185                         TRIG_ROUND_NEAREST);
3186                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3187                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3188                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3189                 break;
3190         case TRIG_EXT:
3191                 devpriv->ao_mode1 |=
3192                         AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3193                 if (cmd->scan_begin_arg & CR_INVERT)
3194                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3195                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3196                 break;
3197         default:
3198                 BUG();
3199                 break;
3200         }
3201         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3202         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3203         devpriv->ao_mode2 &=
3204                 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3205         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3206
3207         if (cmd->scan_end_arg > 1) {
3208                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3209                 devpriv->stc_writew(dev,
3210                         AO_Number_Of_Channels(cmd->scan_end_arg -
3211                                 1) |
3212                         AO_UPDATE_Output_Select
3213                         (AO_Update_Output_High_Z),
3214                         AO_Output_Control_Register);
3215         } else {
3216                 unsigned bits;
3217                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3218                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3219                 if (boardtype.reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3220                         bits |= AO_Number_Of_Channels(0);
3221                 } else {
3222                         bits |= AO_Number_Of_Channels(CR_CHAN(cmd->
3223                                         chanlist[0]));
3224                 }
3225                 devpriv->stc_writew(dev, bits,
3226                         AO_Output_Control_Register);
3227         }
3228         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3229
3230         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3231                 AO_Command_1_Register);
3232
3233         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3234         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3235
3236         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3237 #ifdef PCIDMA
3238         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3239 #else
3240         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3241 #endif
3242         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3243         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3244
3245         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3246                 AO_TMRDACWR_Pulse_Width;
3247         if (boardtype.ao_fifo_depth)
3248                 bits |= AO_FIFO_Enable;
3249         else
3250                 bits |= AO_DMA_PIO_Control;
3251 #if 0
3252         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3253            verified with bus analyzer. */
3254         if (boardtype.reg_type & ni_reg_m_series_mask)
3255                 bits |= AO_Number_Of_DAC_Packages;
3256 #endif
3257         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3258         // enable sending of ao dma requests
3259         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3260
3261         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3262
3263         if (cmd->stop_src == TRIG_COUNT) {
3264                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3265                         Interrupt_B_Ack_Register);
3266                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3267                         AO_BC_TC_Interrupt_Enable, 1);
3268         }
3269
3270         s->async->inttrig = &ni_ao_inttrig;
3271
3272         return 0;
3273 }
3274
3275 static int ni_ao_cmdtest(comedi_device * dev, comedi_subdevice * s,
3276         comedi_cmd * cmd)
3277 {
3278         int err = 0;
3279         int tmp;
3280
3281         /* step 1: make sure trigger sources are trivially valid */
3282
3283         if ((cmd->flags & CMDF_WRITE) == 0) {
3284                 cmd->flags |= CMDF_WRITE;
3285         }
3286
3287         tmp = cmd->start_src;
3288         cmd->start_src &= TRIG_INT | TRIG_EXT;
3289         if (!cmd->start_src || tmp != cmd->start_src)
3290                 err++;
3291
3292         tmp = cmd->scan_begin_src;
3293         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3294         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3295                 err++;
3296
3297         tmp = cmd->convert_src;
3298         cmd->convert_src &= TRIG_NOW;
3299         if (!cmd->convert_src || tmp != cmd->convert_src)
3300                 err++;
3301
3302         tmp = cmd->scan_end_src;
3303         cmd->scan_end_src &= TRIG_COUNT;
3304         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3305                 err++;
3306
3307         tmp = cmd->stop_src;
3308         cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3309         if (!cmd->stop_src || tmp != cmd->stop_src)
3310                 err++;
3311
3312         if (err)
3313                 return 1;
3314
3315         /* step 2: make sure trigger sources are unique and mutually compatible */
3316
3317         if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3318                 err++;
3319
3320         if (err)
3321                 return 2;
3322
3323         /* step 3: make sure arguments are trivially compatible */
3324
3325         if (cmd->start_src == TRIG_EXT) {
3326                 /* external trigger */
3327                 unsigned int tmp = CR_CHAN(cmd->start_arg);
3328
3329                 if (tmp > 18)
3330                         tmp = 18;
3331                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3332                 if (cmd->start_arg != tmp) {
3333                         cmd->start_arg = tmp;
3334                         err++;
3335                 }
3336         } else {
3337                 if (cmd->start_arg != 0) {
3338                         /* true for both TRIG_NOW and TRIG_INT */
3339                         cmd->start_arg = 0;
3340                         err++;
3341                 }
3342         }
3343         if (cmd->scan_begin_src == TRIG_TIMER) {
3344                 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3345                         cmd->scan_begin_arg = boardtype.ao_speed;
3346                         err++;
3347                 }
3348                 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {       /* XXX check */
3349                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3350                         err++;
3351                 }
3352         }
3353         if (cmd->convert_arg != 0) {
3354                 cmd->convert_arg = 0;
3355                 err++;
3356         }
3357         if (cmd->scan_end_arg != cmd->chanlist_len) {
3358                 cmd->scan_end_arg = cmd->chanlist_len;
3359                 err++;
3360         }
3361         if (cmd->stop_src == TRIG_COUNT) {      /* XXX check */
3362                 if (cmd->stop_arg > 0x00ffffff) {
3363                         cmd->stop_arg = 0x00ffffff;
3364                         err++;
3365                 }
3366         } else {
3367                 /* TRIG_NONE */
3368                 if (cmd->stop_arg != 0) {
3369                         cmd->stop_arg = 0;
3370                         err++;
3371                 }
3372         }
3373
3374         if (err)
3375                 return 3;
3376
3377         /* step 4: fix up any arguments */
3378         if (cmd->scan_begin_src == TRIG_TIMER) {
3379                 tmp = cmd->scan_begin_arg;
3380                 cmd->scan_begin_arg =
3381                         ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3382                                 cmd->scan_begin_arg,
3383                                 cmd->flags & TRIG_ROUND_MASK));
3384                 if (tmp != cmd->scan_begin_arg)
3385                         err++;
3386         }
3387         if (err)
3388                 return 4;
3389
3390         /* step 5: fix up chanlist */
3391
3392         if (err)
3393                 return 5;
3394
3395         return 0;
3396 }
3397
3398 static int ni_ao_reset(comedi_device * dev, comedi_subdevice * s)
3399 {
3400         //devpriv->ao0p=0x0000;
3401         //ni_writew(devpriv->ao0p,AO_Configuration);
3402
3403         //devpriv->ao1p=AO_Channel(1);
3404         //ni_writew(devpriv->ao1p,AO_Configuration);
3405
3406         ni_release_ao_mite_channel(dev);
3407
3408         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3409         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3410         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3411         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3412         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3413         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3414                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3415         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3416         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3417         devpriv->ao_cmd1 = 0;
3418         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3419         devpriv->ao_cmd2 = 0;
3420         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3421         devpriv->ao_mode1 = 0;
3422         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3423         devpriv->ao_mode2 = 0;
3424         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3425         if (boardtype.reg_type & ni_reg_m_series_mask)
3426                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3427         else
3428                 devpriv->ao_mode3 = 0;
3429         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3430         devpriv->ao_trigger_select = 0;
3431         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3432                 AO_Trigger_Select_Register);
3433         if (boardtype.reg_type & ni_reg_6xxx_mask) {
3434                 unsigned immediate_bits = 0;
3435                 unsigned i;
3436                 for(i = 0; i < s->n_chan; ++i)
3437                 {
3438                         immediate_bits |= 1 << i;
3439                 }
3440                 ao_win_out(immediate_bits, AO_Immediate_671x);
3441                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3442         }
3443         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3444
3445         return 0;
3446 }
3447
3448 // digital io
3449
3450 static int ni_dio_insn_config(comedi_device * dev, comedi_subdevice * s,
3451         comedi_insn * insn, lsampl_t * data)
3452 {
3453 #ifdef DEBUG_DIO
3454         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
3455                 CR_CHAN(insn->chanspec), data[0]);
3456 #endif
3457         switch (data[0]) {
3458         case INSN_CONFIG_DIO_OUTPUT:
3459                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3460                 break;
3461         case INSN_CONFIG_DIO_INPUT:
3462                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3463                 break;
3464         case INSN_CONFIG_DIO_QUERY:
3465                 data[1] =
3466                         (s->io_bits & (1 << CR_CHAN(insn->
3467                                         chanspec))) ? COMEDI_OUTPUT :
3468                         COMEDI_INPUT;
3469                 return insn->n;
3470                 break;
3471         default:
3472                 return -EINVAL;
3473         }
3474
3475         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3476         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3477         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3478
3479         return 1;
3480 }
3481
3482 static int ni_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
3483         comedi_insn * insn, lsampl_t * data)
3484 {
3485 #ifdef DEBUG_DIO
3486         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3487 #endif
3488         if (insn->n != 2)
3489                 return -EINVAL;
3490         if (data[0]) {
3491                 /* Perform check to make sure we're not using the
3492                    serial part of the dio */
3493                 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3494                         && devpriv->serial_interval_ns)
3495                         return -EBUSY;
3496
3497                 s->state &= ~data[0];
3498                 s->state |= (data[0] & data[1]);
3499                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3500                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3501                 devpriv->stc_writew(dev, devpriv->dio_output,
3502                         DIO_Output_Register);
3503         }
3504         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3505
3506         return 2;
3507 }
3508
3509 static int ni_m_series_dio_insn_config(comedi_device * dev,
3510         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
3511 {
3512 #ifdef DEBUG_DIO
3513         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3514                 CR_CHAN(insn->chanspec), data[0]);
3515 #endif
3516         switch (data[0]) {
3517         case INSN_CONFIG_DIO_OUTPUT:
3518                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3519                 break;
3520         case INSN_CONFIG_DIO_INPUT:
3521                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3522                 break;
3523         case INSN_CONFIG_DIO_QUERY:
3524                 data[1] =
3525                         (s->io_bits & (1 << CR_CHAN(insn->
3526                                         chanspec))) ? COMEDI_OUTPUT :
3527                         COMEDI_INPUT;
3528                 return insn->n;
3529                 break;
3530         default:
3531                 return -EINVAL;
3532         }
3533
3534         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3535
3536         return 1;
3537 }
3538
3539 static int ni_m_series_dio_insn_bits(comedi_device * dev, comedi_subdevice * s,
3540         comedi_insn * insn, lsampl_t * data)
3541 {
3542 #ifdef DEBUG_DIO
3543         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3544                 data[1]);
3545 #endif
3546         if (insn->n != 2)
3547                 return -EINVAL;
3548         if (data[0]) {
3549                 s->state &= ~data[0];
3550                 s->state |= (data[0] & data[1]);
3551                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3552         }
3553         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3554
3555         return 2;
3556 }
3557
3558 static int ni_cdio_cmdtest(comedi_device * dev, comedi_subdevice * s,
3559         comedi_cmd * cmd)
3560 {
3561         int err = 0;
3562         int tmp;
3563         int sources;
3564         unsigned i;
3565
3566         /* step 1: make sure trigger sources are trivially valid */
3567
3568         tmp = cmd->start_src;
3569         sources = TRIG_INT;
3570         cmd->start_src &= sources;
3571         if (!cmd->start_src || tmp != cmd->start_src)
3572                 err++;
3573
3574         tmp = cmd->scan_begin_src;
3575         cmd->scan_begin_src &= TRIG_EXT;
3576         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3577                 err++;
3578
3579         tmp = cmd->convert_src;
3580         cmd->convert_src &= TRIG_NOW;
3581         if (!cmd->convert_src || tmp != cmd->convert_src)
3582                 err++;
3583
3584         tmp = cmd->scan_end_src;
3585         cmd->scan_end_src &= TRIG_COUNT;
3586         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3587                 err++;
3588
3589         tmp = cmd->stop_src;
3590         cmd->stop_src &= TRIG_NONE;
3591         if (!cmd->stop_src || tmp != cmd->stop_src)
3592                 err++;
3593
3594         if (err)
3595                 return 1;
3596
3597         /* step 2: make sure trigger sources are unique... */
3598
3599         if (cmd->start_src != TRIG_INT)
3600                 err++;
3601         if (cmd->scan_begin_src != TRIG_EXT)
3602                 err++;
3603         if (cmd->convert_src != TRIG_NOW)
3604                 err++;
3605         if (cmd->stop_src != TRIG_NONE)
3606                 err++;
3607         /* ... and mutually compatible */
3608
3609         if (err)
3610                 return 2;
3611
3612         /* step 3: make sure arguments are trivially compatible */
3613         if (cmd->start_src == TRIG_INT) {
3614                 if (cmd->start_arg != 0) {
3615                         cmd->start_arg = 0;
3616                         err++;
3617                 }
3618         }
3619         if (cmd->scan_begin_src == TRIG_EXT) {
3620                 tmp = cmd->scan_begin_arg;
3621                 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3622                         CR_INVERT);
3623                 if (tmp != cmd->scan_begin_arg) {
3624                         err++;
3625                 }
3626         }
3627         if (cmd->convert_src == TRIG_NOW) {
3628                 if (cmd->convert_arg) {
3629                         cmd->convert_arg = 0;
3630                         err++;
3631                 }
3632         }
3633
3634         if (cmd->scan_end_arg != cmd->chanlist_len) {
3635                 cmd->scan_end_arg = cmd->chanlist_len;
3636                 err++;
3637         }
3638
3639         if (cmd->stop_src == TRIG_NONE) {
3640                 if (cmd->stop_arg != 0) {
3641                         cmd->stop_arg = 0;
3642                         err++;
3643                 }
3644         }
3645
3646         if (err)
3647                 return 3;
3648
3649         /* step 4: fix up any arguments */
3650
3651         if (err)
3652                 return 4;
3653
3654         /* step 5: check chanlist */
3655
3656         for (i = 0; i < cmd->chanlist_len; ++i) {
3657                 if (cmd->chanlist[i] != i)
3658                         err = 1;
3659         }
3660
3661         if (err)
3662                 return 5;
3663
3664         return 0;
3665 }
3666
3667 static int ni_cdio_cmd(comedi_device * dev, comedi_subdevice * s)
3668 {
3669         const comedi_cmd *cmd = &s->async->cmd;
3670         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3671         int retval;
3672
3673         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3674         switch (cmd->scan_begin_src) {
3675         case TRIG_EXT:
3676                 cdo_mode_bits |=
3677                         CR_CHAN(cmd->
3678                         scan_begin_arg) & CDO_Sample_Source_Select_Mask;
3679                 break;
3680         default:
3681                 BUG();
3682                 break;
3683         }
3684         if (cmd->scan_begin_arg & CR_INVERT)
3685                 cdo_mode_bits |= CDO_Polarity_Bit;
3686         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3687         if (s->io_bits) {
3688                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3689                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3690                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3691         } else {
3692                 comedi_error(dev,
3693                         "attempted to run digital output command with no lines configured as outputs");
3694                 return -EIO;
3695         }
3696         retval = ni_request_cdo_mite_channel(dev);
3697         if (retval < 0) {
3698                 return retval;
3699         }
3700         s->async->inttrig = &ni_cdo_inttrig;
3701         return 0;
3702 }
3703
3704 static int ni_cdo_inttrig(comedi_device * dev, comedi_subdevice * s,
3705         unsigned int trignum)
3706 {
3707 #ifdef PCIDMA
3708         unsigned long flags;
3709 #endif
3710         int retval = 0;
3711         unsigned i;
3712         const unsigned timeout = 1000;
3713
3714         s->async->inttrig = NULL;
3715
3716         /* read alloc the entire buffer */
3717         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3718
3719 #ifdef PCIDMA
3720         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3721         if (devpriv->cdo_mite_chan) {
3722                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3723                 mite_dma_arm(devpriv->cdo_mite_chan);
3724         } else {
3725                 comedi_error(dev, "BUG: no cdo mite channel?");
3726                 retval = -EIO;
3727         }
3728         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3729         if (retval < 0)
3730                 return retval;
3731 #endif
3732 // XXX not sure what interrupt C group does
3733 //      ni_writeb(Interrupt_Group_C_Enable_Bit, M_Offset_Interrupt_C_Enable);
3734         //wait for dma to fill output fifo
3735         for (i = 0; i < timeout; ++i) {
3736                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3737                         break;
3738                 comedi_udelay(10);
3739         }
3740         if (i == timeout) {
3741                 comedi_error(dev, "dma failed to fill cdo fifo!");
3742                 ni_cdio_cancel(dev, s);
3743                 return -EIO;
3744         }
3745         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3746                 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, M_Offset_CDIO_Command);
3747         return retval;
3748 }
3749
3750 static int ni_cdio_cancel(comedi_device * dev, comedi_subdevice * s)
3751 {
3752         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3753                 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3754                 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3755                 M_Offset_CDIO_Command);
3756 // XXX not sure what interrupt C group does
3757 //      ni_writeb(0, M_Offset_Interrupt_C_Enable);
3758         ni_writel(0, M_Offset_CDO_Mask_Enable);
3759         ni_release_cdo_mite_channel(dev);
3760         return 0;
3761 }
3762
3763 static void handle_cdio_interrupt(comedi_device * dev)
3764 {
3765         unsigned cdio_status;
3766         comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3767 #ifdef PCIDMA
3768         unsigned long flags;
3769 #endif
3770
3771         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3772                 return;
3773         }
3774 #ifdef PCIDMA
3775         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3776         if (devpriv->cdo_mite_chan) {
3777                 unsigned cdo_mite_status =
3778                         mite_get_status(devpriv->cdo_mite_chan);
3779                 if (cdo_mite_status & CHSR_LINKC) {
3780                         writel(CHOR_CLRLC,
3781                                 devpriv->mite->mite_io_addr +
3782                                 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3783                 }
3784                 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3785         }
3786         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3787 #endif
3788
3789         cdio_status = ni_readl(M_Offset_CDIO_Status);
3790         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3791 //              rt_printk("cdio error: statux=0x%x\n", cdio_status);
3792                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      // XXX just guessing this is needed and does something useful
3793                 s->async->events |= COMEDI_CB_OVERFLOW;
3794         }
3795         if (cdio_status & CDO_FIFO_Empty_Bit) {
3796 //              rt_printk("cdio fifo empty\n");
3797                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3798                         M_Offset_CDIO_Command);
3799 //              s->async->events |= COMEDI_CB_EOA;
3800         }
3801         ni_event(dev, s);
3802 }
3803
3804 static int ni_serial_insn_config(comedi_device * dev, comedi_subdevice * s,
3805         comedi_insn * insn, lsampl_t * data)
3806 {
3807         int err = insn->n;
3808         unsigned char byte_out, byte_in = 0;
3809
3810         if (insn->n != 2)
3811                 return -EINVAL;
3812
3813         switch (data[0]) {
3814         case INSN_CONFIG_SERIAL_CLOCK:
3815
3816 #ifdef DEBUG_DIO
3817                 rt_printk("SPI serial clock Config cd\n", data[1]);
3818 #endif
3819                 devpriv->serial_hw_mode = 1;
3820                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3821
3822                 if (data[1] == SERIAL_DISABLED) {
3823                         devpriv->serial_hw_mode = 0;
3824                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3825                                 DIO_Software_Serial_Control);
3826                         data[1] = SERIAL_DISABLED;
3827                         devpriv->serial_interval_ns = data[1];
3828                 } else if (data[1] <= SERIAL_600NS) {
3829                         /* Warning: this clock speed is too fast to reliably
3830                            control SCXI. */
3831                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3832                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3833                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3834                         data[1] = SERIAL_600NS;
3835                         devpriv->serial_interval_ns = data[1];
3836                 } else if (data[1] <= SERIAL_1_2US) {
3837                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3838                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3839                                 DIO_Serial_Out_Divide_By_2;
3840                         data[1] = SERIAL_1_2US;
3841                         devpriv->serial_interval_ns = data[1];
3842                 } else if (data[1] <= SERIAL_10US) {
3843                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3844                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3845                                 DIO_Serial_Out_Divide_By_2;
3846                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3847                            600ns/1.2us. If you turn divide_by_2 off with the
3848                            slow clock, you will still get 10us, except then
3849                            all your delays are wrong. */
3850                         data[1] = SERIAL_10US;
3851                         devpriv->serial_interval_ns = data[1];
3852                 } else {
3853                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3854                                 DIO_Software_Serial_Control);
3855                         devpriv->serial_hw_mode = 0;
3856                         data[1] = (data[1] / 1000) * 1000;
3857                         devpriv->serial_interval_ns = data[1];
3858                 }
3859
3860                 devpriv->stc_writew(dev, devpriv->dio_control,
3861                         DIO_Control_Register);
3862                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3863                         Clock_and_FOUT_Register);
3864                 return 1;
3865
3866                 break;
3867
3868         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3869
3870                 if (devpriv->serial_interval_ns == 0) {
3871                         return -EINVAL;
3872                 }
3873
3874                 byte_out = data[1] & 0xFF;
3875
3876                 if (devpriv->serial_hw_mode) {
3877                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3878                                 &byte_in);
3879                 } else if (devpriv->serial_interval_ns > 0) {
3880                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3881                                 &byte_in);
3882                 } else {
3883                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3884                         return -EINVAL;
3885                 }
3886                 if (err < 0)
3887                         return err;
3888                 data[1] = byte_in & 0xFF;
3889                 return insn->n;
3890
3891                 break;
3892         default:
3893                 return -EINVAL;
3894         }
3895
3896 }
3897
3898 static int ni_serial_hw_readwrite8(comedi_device * dev, comedi_subdevice * s,
3899         unsigned char data_out, unsigned char *data_in)
3900 {
3901         unsigned int status1;
3902         int err = 0, count = 20;
3903
3904 #ifdef DEBUG_DIO
3905         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3906 #endif
3907
3908         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3909         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3910         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3911
3912         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3913         if (status1 & DIO_Serial_IO_In_Progress_St) {
3914                 err = -EBUSY;
3915                 goto Error;
3916         }
3917
3918         devpriv->dio_control |= DIO_HW_Serial_Start;
3919         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3920         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3921
3922         /* Wait until STC says we're done, but don't loop infinitely. */
3923         while ((status1 =
3924                         devpriv->stc_readw(dev,
3925                                 Joint_Status_1_Register)) &
3926                 DIO_Serial_IO_In_Progress_St) {
3927                 /* Delay one bit per loop */
3928                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3929                 if (--count < 0) {
3930                         rt_printk
3931                                 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3932                         err = -ETIME;
3933                         goto Error;
3934                 }
3935         }
3936
3937         /* Delay for last bit. This delay is absolutely necessary, because
3938            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3939         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3940
3941         if (data_in != NULL) {
3942                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3943 #ifdef DEBUG_DIO
3944                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3945 #endif
3946         }
3947
3948       Error:
3949         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3950
3951         return err;
3952 }
3953
3954 static int ni_serial_sw_readwrite8(comedi_device * dev, comedi_subdevice * s,
3955         unsigned char data_out, unsigned char *data_in)
3956 {
3957         unsigned char mask, input = 0;
3958
3959 #ifdef DEBUG_DIO
3960         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3961 #endif
3962
3963         /* Wait for one bit before transfer */
3964         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3965
3966         for (mask = 0x80; mask; mask >>= 1) {
3967                 /* Output current bit; note that we cannot touch s->state
3968                    because it is a per-subdevice field, and serial is
3969                    a separate subdevice from DIO. */
3970                 devpriv->dio_output &= ~DIO_SDOUT;
3971                 if (data_out & mask) {
3972                         devpriv->dio_output |= DIO_SDOUT;
3973                 }
3974                 devpriv->stc_writew(dev, devpriv->dio_output,
3975                         DIO_Output_Register);
3976
3977                 /* Assert SDCLK (active low, inverted), wait for half of
3978                    the delay, deassert SDCLK, and wait for the other half. */
3979                 devpriv->dio_control |= DIO_Software_Serial_Control;
3980                 devpriv->stc_writew(dev, devpriv->dio_control,
3981                         DIO_Control_Register);
3982
3983                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3984
3985                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3986                 devpriv->stc_writew(dev, devpriv->dio_control,
3987                         DIO_Control_Register);
3988
3989                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3990
3991                 /* Input current bit */
3992                 if (devpriv->stc_readw(dev,
3993                                 DIO_Parallel_Input_Register) & DIO_SDIN) {
3994 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3995                         input |= mask;
3996                 }
3997         }
3998 #ifdef DEBUG_DIO
3999         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4000 #endif
4001         if (data_in)
4002                 *data_in = input;
4003
4004         return 0;
4005 }
4006
4007 static void mio_common_detach(comedi_device * dev)
4008 {
4009         if (dev->private) {
4010                 if (devpriv->counter_dev) {
4011                         ni_gpct_device_destroy(devpriv->counter_dev);
4012                 }
4013         }
4014         if (dev->subdevices && boardtype.has_8255)
4015                 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
4016 }
4017
4018 static void init_ao_67xx(comedi_device * dev, comedi_subdevice * s)
4019 {
4020         int i;
4021
4022         for (i = 0; i < s->n_chan; i++)
4023         {
4024                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4025                         AO_Configuration_2_67xx);
4026         }
4027         ao_win_out(0x0, AO_Later_Single_Point_Updates);
4028 }
4029
4030 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4031 {
4032         unsigned stc_register;
4033         switch (reg) {
4034         case NITIO_G0_Autoincrement_Reg:
4035                 stc_register = G_Autoincrement_Register(0);
4036                 break;
4037         case NITIO_G1_Autoincrement_Reg:
4038                 stc_register = G_Autoincrement_Register(1);
4039                 break;
4040         case NITIO_G0_Command_Reg:
4041                 stc_register = G_Command_Register(0);
4042                 break;
4043         case NITIO_G1_Command_Reg:
4044                 stc_register = G_Command_Register(1);
4045                 break;
4046         case NITIO_G0_HW_Save_Reg:
4047                 stc_register = G_HW_Save_Register(0);
4048                 break;
4049         case NITIO_G1_HW_Save_Reg:
4050                 stc_register = G_HW_Save_Register(1);
4051                 break;
4052         case NITIO_G0_SW_Save_Reg:
4053                 stc_register = G_Save_Register(0);
4054                 break;
4055         case NITIO_G1_SW_Save_Reg:
4056                 stc_register = G_Save_Register(1);
4057                 break;
4058         case NITIO_G0_Mode_Reg:
4059                 stc_register = G_Mode_Register(0);
4060                 break;
4061         case NITIO_G1_Mode_Reg:
4062                 stc_register = G_Mode_Register(1);
4063                 break;
4064         case NITIO_G0_LoadA_Reg:
4065                 stc_register = G_Load_A_Register(0);
4066                 break;
4067         case NITIO_G1_LoadA_Reg:
4068                 stc_register = G_Load_A_Register(1);
4069                 break;
4070         case NITIO_G0_LoadB_Reg:
4071                 stc_register = G_Load_B_Register(0);
4072                 break;
4073         case NITIO_G1_LoadB_Reg:
4074                 stc_register = G_Load_B_Register(1);
4075                 break;
4076         case NITIO_G0_Input_Select_Reg:
4077                 stc_register = G_Input_Select_Register(0);
4078                 break;
4079         case NITIO_G1_Input_Select_Reg:
4080                 stc_register = G_Input_Select_Register(1);
4081                 break;
4082         case NITIO_G01_Status_Reg:
4083                 stc_register = G_Status_Register;
4084                 break;
4085         case NITIO_G01_Joint_Reset_Reg:
4086                 stc_register = Joint_Reset_Register;
4087                 break;
4088         case NITIO_G01_Joint_Status1_Reg:
4089                 stc_register = Joint_Status_1_Register;
4090                 break;
4091         case NITIO_G01_Joint_Status2_Reg:
4092                 stc_register = Joint_Status_2_Register;
4093                 break;
4094         case NITIO_G0_Interrupt_Acknowledge_Reg:
4095                 stc_register = Interrupt_A_Ack_Register;
4096                 break;
4097         case NITIO_G1_Interrupt_Acknowledge_Reg:
4098                 stc_register = Interrupt_B_Ack_Register;
4099                 break;
4100         case NITIO_G0_Status_Reg:
4101                 stc_register = AI_Status_1_Register;
4102                 break;
4103         case NITIO_G1_Status_Reg:
4104                 stc_register = AO_Status_1_Register;
4105                 break;
4106         case NITIO_G0_Interrupt_Enable_Reg:
4107                 stc_register = Interrupt_A_Enable_Register;
4108                 break;
4109         case NITIO_G1_Interrupt_Enable_Reg:
4110                 stc_register = Interrupt_B_Enable_Register;
4111                 break;
4112         default:
4113                 rt_printk("%s: unhandled register 0x%x in switch.\n",
4114                         __FUNCTION__, reg);
4115                 BUG();
4116                 return 0;
4117                 break;
4118         }
4119         return stc_register;
4120 }
4121
4122 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4123         enum ni_gpct_register reg)
4124 {
4125         comedi_device *dev = counter->counter_dev->dev;
4126         unsigned stc_register;
4127         /* bits in the join reset register which are relevant to counters */
4128         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4129         static const unsigned gpct_interrupt_a_enable_mask =
4130                 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4131         static const unsigned gpct_interrupt_b_enable_mask =
4132                 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4133
4134         switch (reg) {
4135                 /* m-series-only registers */
4136         case NITIO_G0_Counting_Mode_Reg:
4137                 ni_writew(bits, M_Offset_G0_Counting_Mode);
4138                 break;
4139         case NITIO_G1_Counting_Mode_Reg:
4140                 ni_writew(bits, M_Offset_G1_Counting_Mode);
4141                 break;
4142         case NITIO_G0_Second_Gate_Reg:
4143                 ni_writew(bits, M_Offset_G0_Second_Gate);
4144                 break;
4145         case NITIO_G1_Second_Gate_Reg:
4146                 ni_writew(bits, M_Offset_G1_Second_Gate);
4147                 break;
4148         case NITIO_G0_DMA_Config_Reg:
4149                 ni_writew(bits, M_Offset_G0_DMA_Config);
4150                 break;
4151         case NITIO_G1_DMA_Config_Reg:
4152                 ni_writew(bits, M_Offset_G1_DMA_Config);
4153                 break;
4154         case NITIO_G0_ABZ_Reg:
4155                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4156                 break;
4157         case NITIO_G1_ABZ_Reg:
4158                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4159                 break;
4160
4161                 /* 32 bit registers */
4162         case NITIO_G0_LoadA_Reg:
4163         case NITIO_G1_LoadA_Reg:
4164         case NITIO_G0_LoadB_Reg:
4165         case NITIO_G1_LoadB_Reg:
4166                 stc_register = ni_gpct_to_stc_register(reg);
4167                 devpriv->stc_writel(dev, bits, stc_register);
4168                 break;
4169
4170                 /* 16 bit registers */
4171         case NITIO_G0_Interrupt_Enable_Reg:
4172                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4173                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4174                         gpct_interrupt_a_enable_mask, bits);
4175                 break;
4176         case NITIO_G1_Interrupt_Enable_Reg:
4177                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4178                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4179                         gpct_interrupt_b_enable_mask, bits);
4180                 break;
4181         case NITIO_G01_Joint_Reset_Reg:
4182                 BUG_ON(bits & ~gpct_joint_reset_mask);
4183                 /* fall-through */
4184         default:
4185                 stc_register = ni_gpct_to_stc_register(reg);
4186                 devpriv->stc_writew(dev, bits, stc_register);
4187         }
4188 }
4189
4190 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4191         enum ni_gpct_register reg)
4192 {
4193         comedi_device *dev = counter->counter_dev->dev;
4194         unsigned stc_register;
4195         switch (reg) {
4196                 /* m-series only registers */
4197         case NITIO_G0_DMA_Status_Reg:
4198                 return ni_readw(M_Offset_G0_DMA_Status);
4199                 break;
4200         case NITIO_G1_DMA_Status_Reg:
4201                 return ni_readw(M_Offset_G1_DMA_Status);
4202                 break;
4203
4204                 /* 32 bit registers */
4205         case NITIO_G0_HW_Save_Reg:
4206         case NITIO_G1_HW_Save_Reg:
4207         case NITIO_G0_SW_Save_Reg:
4208         case NITIO_G1_SW_Save_Reg:
4209                 stc_register = ni_gpct_to_stc_register(reg);
4210                 return devpriv->stc_readl(dev, stc_register);
4211                 break;
4212
4213                 /* 16 bit registers */
4214         default:
4215                 stc_register = ni_gpct_to_stc_register(reg);
4216                 return devpriv->stc_readw(dev, stc_register);
4217                 break;
4218         }
4219         return 0;
4220 }
4221
4222 static int ni_freq_out_insn_read(comedi_device * dev,
4223         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4224 {
4225         if (insn->n == 0)
4226                 return 0;
4227
4228         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4229         return 1;
4230 }
4231
4232 static int ni_freq_out_insn_write(comedi_device * dev,
4233         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4234 {
4235         if (insn->n == 0)
4236                 return 0;
4237
4238         devpriv->clock_and_fout &= ~FOUT_Enable;
4239         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4240                 Clock_and_FOUT_Register);
4241         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4242         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4243         devpriv->clock_and_fout |= FOUT_Enable;
4244         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4245                 Clock_and_FOUT_Register);
4246         return insn->n;
4247 }
4248
4249 static int ni_set_freq_out_clock(comedi_device * dev, lsampl_t clock_source)
4250 {
4251         switch (clock_source) {
4252         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4253                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4254                 break;
4255         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4256                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4257                 break;
4258         default:
4259                 return -EINVAL;
4260         }
4261         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4262                 Clock_and_FOUT_Register);
4263         return 3;
4264 }
4265
4266 static void ni_get_freq_out_clock(comedi_device * dev, lsampl_t * clock_source,
4267         lsampl_t * clock_period_ns)
4268 {
4269         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4270                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4271                 *clock_period_ns = TIMEBASE_2_NS;
4272         } else {
4273                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4274                 *clock_period_ns = TIMEBASE_1_NS * 2;
4275         }
4276 }
4277
4278 static int ni_freq_out_insn_config(comedi_device * dev, comedi_subdevice * s,
4279         comedi_insn * insn, lsampl_t * data)
4280 {
4281         switch (data[0]) {
4282         case INSN_CONFIG_SET_CLOCK_SRC:
4283                 return ni_set_freq_out_clock(dev, data[1]);
4284                 break;
4285         case INSN_CONFIG_GET_CLOCK_SRC:
4286                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4287                 return 3;
4288         default:
4289                 break;
4290         }
4291         return -EINVAL;
4292 }
4293
4294 static int ni_alloc_private(comedi_device * dev)
4295 {
4296         int ret;
4297
4298         ret = alloc_private(dev, sizeof(ni_private));
4299         if (ret < 0)
4300                 return ret;
4301
4302         spin_lock_init(&devpriv->window_lock);
4303         spin_lock_init(&devpriv->soft_reg_copy_lock);
4304         spin_lock_init(&devpriv->mite_channel_lock);
4305
4306         return 0;
4307 };
4308
4309 static int ni_E_init(comedi_device * dev, comedi_devconfig * it)
4310 {
4311         comedi_subdevice *s;
4312         unsigned j;
4313         enum ni_gpct_variant counter_variant;
4314
4315         if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4316                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4317                 return -EINVAL;
4318         }
4319
4320         if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4321                 return -ENOMEM;
4322
4323         /* analog input subdevice */
4324
4325         s = dev->subdevices + NI_AI_SUBDEV;
4326         dev->read_subdev = s;
4327         if (boardtype.n_adchan) {
4328                 s->type = COMEDI_SUBD_AI;
4329                 s->subdev_flags =
4330                         SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4331                 if (boardtype.reg_type != ni_reg_611x)
4332                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4333                 if (boardtype.adbits > 16)
4334                         s->subdev_flags |= SDF_LSAMPL;
4335                 if (boardtype.reg_type & ni_reg_m_series_mask)
4336                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4337                 s->n_chan = boardtype.n_adchan;
4338                 s->len_chanlist = 512;
4339                 s->maxdata = (1 << boardtype.adbits) - 1;
4340                 s->range_table = ni_range_lkup[boardtype.gainlkup];
4341                 s->insn_read = &ni_ai_insn_read;
4342                 s->insn_config = &ni_ai_insn_config;
4343                 s->do_cmdtest = &ni_ai_cmdtest;
4344                 s->do_cmd = &ni_ai_cmd;
4345                 s->cancel = &ni_ai_reset;
4346                 s->poll = &ni_ai_poll;
4347                 s->munge = &ni_ai_munge;
4348 #ifdef PCIDMA
4349                 s->async_dma_dir = DMA_FROM_DEVICE;
4350 #endif
4351         } else {
4352                 s->type = COMEDI_SUBD_UNUSED;
4353         }
4354
4355         /* analog output subdevice */
4356
4357         s = dev->subdevices + NI_AO_SUBDEV;
4358         if (boardtype.n_aochan) {
4359                 s->type = COMEDI_SUBD_AO;
4360                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4361                 if (boardtype.reg_type & ni_reg_m_series_mask)
4362                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4363                 s->n_chan = boardtype.n_aochan;
4364                 s->maxdata = (1 << boardtype.aobits) - 1;
4365                 s->range_table = boardtype.ao_range_table;
4366                 s->insn_read = &ni_ao_insn_read;
4367                 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4368                         s->insn_write = &ni_ao_insn_write_671x;
4369                 } else {
4370                         s->insn_write = &ni_ao_insn_write;
4371                 }
4372                 s->insn_config = &ni_ao_insn_config;
4373 #ifdef PCIDMA
4374                 if (boardtype.n_aochan) {
4375                         s->async_dma_dir = DMA_TO_DEVICE;
4376 #else
4377                 if (boardtype.ao_fifo_depth) {
4378 #endif
4379                         dev->write_subdev = s;
4380                         s->subdev_flags |= SDF_CMD_WRITE;
4381                         s->do_cmd = &ni_ao_cmd;
4382                         s->do_cmdtest = &ni_ao_cmdtest;
4383                         s->len_chanlist = boardtype.n_aochan;
4384                         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4385                                 s->munge = ni_ao_munge;
4386                 }
4387                 s->cancel = &ni_ao_reset;
4388         } else {
4389                 s->type = COMEDI_SUBD_UNUSED;
4390         }
4391         if ((boardtype.reg_type & ni_reg_67xx_mask))
4392                 init_ao_67xx(dev, s);
4393
4394         /* digital i/o subdevice */
4395
4396         s = dev->subdevices + NI_DIO_SUBDEV;
4397         s->type = COMEDI_SUBD_DIO;
4398         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4399         s->maxdata = 1;
4400         s->io_bits = 0;         /* all bits input */
4401         s->range_table = &range_digital;
4402         s->n_chan = boardtype.num_p0_dio_channels;
4403         if (boardtype.reg_type & ni_reg_m_series_mask) {
4404                 s->subdev_flags |=
4405                         SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4406                 s->insn_bits = &ni_m_series_dio_insn_bits;
4407                 s->insn_config = &ni_m_series_dio_insn_config;
4408                 s->do_cmd = &ni_cdio_cmd;
4409                 s->do_cmdtest = &ni_cdio_cmdtest;
4410                 s->cancel = &ni_cdio_cancel;
4411                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4412                 s->len_chanlist = s->n_chan;
4413
4414                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4415                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4416         } else {
4417                 s->insn_bits = &ni_dio_insn_bits;
4418                 s->insn_config = &ni_dio_insn_config;
4419                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4420                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4421         }
4422
4423         /* 8255 device */
4424         s = dev->subdevices + NI_8255_DIO_SUBDEV;
4425         if (boardtype.has_8255) {
4426                 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4427         } else {
4428                 s->type = COMEDI_SUBD_UNUSED;
4429         }
4430
4431         /* formerly general purpose counter/timer device, but no longer used */
4432         s = dev->subdevices + NI_UNUSED_SUBDEV;
4433         s->type = COMEDI_SUBD_UNUSED;
4434
4435         /* calibration subdevice -- ai and ao */
4436         s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4437         s->type = COMEDI_SUBD_CALIB;
4438         if (boardtype.reg_type & ni_reg_m_series_mask) {
4439                 // internal PWM analog output used for AI nonlinearity calibration
4440                 s->subdev_flags = SDF_INTERNAL;
4441                 s->insn_config = &ni_m_series_pwm_config;
4442                 s->n_chan = 1;
4443                 s->maxdata = 0;
4444                 ni_writel(0x0, M_Offset_Cal_PWM);
4445         } else if (boardtype.reg_type == ni_reg_6143) {
4446                 // internal PWM analog output used for AI nonlinearity calibration
4447                 s->subdev_flags = SDF_INTERNAL;
4448                 s->insn_config = &ni_6143_pwm_config;
4449                 s->n_chan = 1;
4450                 s->maxdata = 0;
4451         } else {
4452                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4453                 s->insn_read = &ni_calib_insn_read;
4454                 s->insn_write = &ni_calib_insn_write;
4455                 caldac_setup(dev, s);
4456         }
4457
4458         /* EEPROM */
4459         s = dev->subdevices + NI_EEPROM_SUBDEV;
4460         s->type = COMEDI_SUBD_MEMORY;
4461         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4462         s->maxdata = 0xff;
4463         if (boardtype.reg_type & ni_reg_m_series_mask) {
4464                 s->n_chan = M_SERIES_EEPROM_SIZE;
4465                 s->insn_read = &ni_m_series_eeprom_insn_read;
4466         } else {
4467                 s->n_chan = 512;
4468                 s->insn_read = &ni_eeprom_insn_read;
4469         }
4470
4471         /* PFI */
4472         s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4473         s->type = COMEDI_SUBD_DIO;
4474         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4475         if (boardtype.reg_type & ni_reg_m_series_mask) {
4476                 unsigned i;
4477                 s->n_chan = 16;
4478                 ni_writew(s->state, M_Offset_PFI_DO);
4479                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4480                         ni_writew(devpriv->pfi_output_select_reg[i],
4481                                 M_Offset_PFI_Output_Select(i + 1));
4482                 }
4483         } else {
4484                 s->n_chan = 10;
4485         }
4486         s->maxdata = 1;
4487         if (boardtype.reg_type & ni_reg_m_series_mask) {
4488                 s->insn_bits = &ni_pfi_insn_bits;
4489         }
4490         s->insn_config = &ni_pfi_insn_config;
4491         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4492
4493         /* cs5529 calibration adc */
4494         s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4495         if (boardtype.reg_type & ni_reg_67xx_mask) {
4496                 s->type = COMEDI_SUBD_AI;
4497                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4498                 // one channel for each analog output channel
4499                 s->n_chan = boardtype.n_aochan;
4500                 s->maxdata = (1 << 16) - 1;
4501                 s->range_table = &range_unknown;        /* XXX */
4502                 s->insn_read = cs5529_ai_insn_read;
4503                 s->insn_config = NULL;
4504                 init_cs5529(dev);
4505         } else {
4506                 s->type = COMEDI_SUBD_UNUSED;
4507         }
4508
4509         /* Serial */
4510         s = dev->subdevices + NI_SERIAL_SUBDEV;
4511         s->type = COMEDI_SUBD_SERIAL;
4512         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4513         s->n_chan = 1;
4514         s->maxdata = 0xff;
4515         s->insn_config = ni_serial_insn_config;
4516         devpriv->serial_interval_ns = 0;
4517         devpriv->serial_hw_mode = 0;
4518
4519         /* RTSI */
4520         s = dev->subdevices + NI_RTSI_SUBDEV;
4521         s->type = COMEDI_SUBD_DIO;
4522         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4523         s->n_chan = 8;
4524         s->maxdata = 1;
4525         s->insn_bits = ni_rtsi_insn_bits;
4526         s->insn_config = ni_rtsi_insn_config;
4527         ni_rtsi_init(dev);
4528
4529         if (boardtype.reg_type & ni_reg_m_series_mask) {
4530                 counter_variant = ni_gpct_variant_m_series;
4531         } else {
4532                 counter_variant = ni_gpct_variant_e_series;
4533         }
4534         devpriv->counter_dev = ni_gpct_device_construct(dev,
4535                 &ni_gpct_write_register, &ni_gpct_read_register,
4536                 counter_variant, NUM_GPCT);
4537         /* General purpose counters */
4538         for (j = 0; j < NUM_GPCT; ++j) {
4539                 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4540                 s->type = COMEDI_SUBD_COUNTER;
4541                 s->subdev_flags =
4542                         SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4543                         /* | SDF_CMD_WRITE */ ;
4544                 s->n_chan = 3;
4545                 if (boardtype.reg_type & ni_reg_m_series_mask)
4546                         s->maxdata = 0xffffffff;
4547                 else
4548                         s->maxdata = 0xffffff;
4549                 s->insn_read = &ni_gpct_insn_read;
4550                 s->insn_write = &ni_gpct_insn_write;
4551                 s->insn_config = &ni_gpct_insn_config;
4552                 s->do_cmd = &ni_gpct_cmd;
4553                 s->len_chanlist = 1;
4554                 s->do_cmdtest = &ni_gpct_cmdtest;
4555                 s->cancel = &ni_gpct_cancel;
4556                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4557                 s->private = &devpriv->counter_dev->counters[j];
4558
4559                 devpriv->counter_dev->counters[j].chip_index = 0;
4560                 devpriv->counter_dev->counters[j].counter_index = j;
4561                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4562         }
4563
4564         /* Frequency output */
4565         s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4566         s->type = COMEDI_SUBD_COUNTER;
4567         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4568         s->n_chan = 1;
4569         s->maxdata = 0xf;
4570         s->insn_read = &ni_freq_out_insn_read;
4571         s->insn_write = &ni_freq_out_insn_write;
4572         s->insn_config = &ni_freq_out_insn_config;
4573
4574         /* ai configuration */
4575         ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV);
4576         if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4577                 // BEAM is this needed for PCI-6143 ??
4578                 devpriv->clock_and_fout =
4579                         Slow_Internal_Time_Divide_By_2 |
4580                         Slow_Internal_Timebase |
4581                         Clock_To_Board_Divide_By_2 |
4582                         Clock_To_Board |
4583                         AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4584         } else {
4585                 devpriv->clock_and_fout =
4586                         Slow_Internal_Time_Divide_By_2 |
4587                         Slow_Internal_Timebase |
4588                         Clock_To_Board_Divide_By_2 | Clock_To_Board;
4589         }
4590         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4591                 Clock_and_FOUT_Register);
4592
4593         /* analog output configuration */
4594         ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV);
4595
4596         if (dev->irq) {
4597                 devpriv->stc_writew(dev,
4598                         (IRQ_POLARITY ? Interrupt_Output_Polarity : 0) |
4599                         (Interrupt_Output_On_3_Pins & 0) | Interrupt_A_Enable |
4600                         Interrupt_B_Enable |
4601                         Interrupt_A_Output_Select(interrupt_pin(dev->
4602                                         irq)) |
4603                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
4604                         Interrupt_Control_Register);
4605         }
4606
4607         /* DMA setup */
4608         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4609         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4610
4611         if (boardtype.reg_type & ni_reg_6xxx_mask) {
4612                 ni_writeb(0, Magic_611x);
4613         } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4614                 int channel;
4615                 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4616                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4617                         ni_writeb(0x0,
4618                                 M_Offset_AO_Reference_Attenuation(channel));
4619                 }
4620                 ni_writeb(0x0, M_Offset_AO_Calibration);
4621         }
4622
4623         printk("\n");
4624         return 0;
4625 }
4626
4627 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4628 {
4629         comedi_device *dev = (comedi_device *) arg;
4630
4631         if (dir) {
4632                 ni_writeb(data, Port_A + 2 * port);
4633                 return 0;
4634         } else {
4635                 return ni_readb(Port_A + 2 * port);
4636         }
4637 }
4638
4639 /*
4640         presents the EEPROM as a subdevice
4641 */
4642
4643 static int ni_eeprom_insn_read(comedi_device * dev, comedi_subdevice * s,
4644         comedi_insn * insn, lsampl_t * data)
4645 {
4646         if (insn->n == 0)
4647                 return 0;
4648
4649         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4650
4651         return 1;
4652 }
4653
4654 /*
4655         reads bytes out of eeprom
4656 */
4657
4658 static int ni_read_eeprom(comedi_device * dev, int addr)
4659 {
4660         int bit;
4661         int bitstring;
4662
4663         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4664         ni_writeb(0x04, Serial_Command);
4665         for (bit = 0x8000; bit; bit >>= 1) {
4666                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4667                         Serial_Command);
4668                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4669                         Serial_Command);
4670         }
4671         bitstring = 0;
4672         for (bit = 0x80; bit; bit >>= 1) {
4673                 ni_writeb(0x04, Serial_Command);
4674                 ni_writeb(0x05, Serial_Command);
4675                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4676         }
4677         ni_writeb(0x00, Serial_Command);
4678
4679         return bitstring;
4680 }
4681
4682 static int ni_m_series_eeprom_insn_read(comedi_device * dev,
4683         comedi_subdevice * s, comedi_insn * insn, lsampl_t * data)
4684 {
4685         if (insn->n == 0)
4686                 return 0;
4687
4688         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4689
4690         return 1;
4691 }
4692
4693 static int ni_get_pwm_config(comedi_device * dev, lsampl_t * data)
4694 {
4695         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4696         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4697         return 3;
4698 }
4699
4700 static int ni_m_series_pwm_config(comedi_device * dev, comedi_subdevice * s,
4701         comedi_insn * insn, lsampl_t * data)
4702 {
4703         unsigned up_count, down_count;
4704         switch (data[0]) {
4705         case INSN_CONFIG_PWM_OUTPUT:
4706                 switch (data[1]) {
4707                 case TRIG_ROUND_NEAREST:
4708                         up_count =
4709                                 (data[2] +
4710                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4711                         break;
4712                 case TRIG_ROUND_DOWN:
4713                         up_count = data[2] / devpriv->clock_ns;
4714                         break;
4715                 case TRIG_ROUND_UP:
4716                         up_count =
4717                                 (data[2] + devpriv->clock_ns -
4718                                 1) / devpriv->clock_ns;
4719                         break;
4720                 default:
4721                         return -EINVAL;
4722                         break;
4723                 }
4724                 switch (data[3]) {
4725                 case TRIG_ROUND_NEAREST:
4726                         down_count =
4727                                 (data[4] +
4728                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4729                         break;
4730                 case TRIG_ROUND_DOWN:
4731                         down_count = data[4] / devpriv->clock_ns;
4732                         break;
4733                 case TRIG_ROUND_UP:
4734                         down_count =
4735                                 (data[4] + devpriv->clock_ns -
4736                                 1) / devpriv->clock_ns;
4737                         break;
4738                 default:
4739                         return -EINVAL;
4740                         break;
4741                 }
4742                 if (up_count * devpriv->clock_ns != data[2] ||
4743                         down_count * devpriv->clock_ns != data[4]) {
4744                         data[2] = up_count * devpriv->clock_ns;
4745                         data[4] = down_count * devpriv->clock_ns;
4746                         return -EAGAIN;
4747                 }
4748                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4749                         MSeries_Cal_PWM_Low_Time_Bits(down_count),
4750                         M_Offset_Cal_PWM);
4751                 devpriv->pwm_up_count = up_count;
4752                 devpriv->pwm_down_count = down_count;
4753                 return 5;
4754                 break;
4755         case INSN_CONFIG_GET_PWM_OUTPUT:
4756                 return ni_get_pwm_config(dev, data);
4757                 break;
4758         default:
4759                 return -EINVAL;
4760                 break;
4761         }
4762         return 0;
4763 }
4764
4765 static int ni_6143_pwm_config(comedi_device * dev, comedi_subdevice * s,
4766         comedi_insn * insn, lsampl_t * data)
4767 {
4768         unsigned up_count, down_count;
4769         switch (data[0]) {
4770         case INSN_CONFIG_PWM_OUTPUT:
4771                 switch (data[1]) {
4772                 case TRIG_ROUND_NEAREST:
4773                         up_count =
4774                                 (data[2] +
4775                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4776                         break;
4777                 case TRIG_ROUND_DOWN:
4778                         up_count = data[2] / devpriv->clock_ns;
4779                         break;
4780                 case TRIG_ROUND_UP:
4781                         up_count =
4782                                 (data[2] + devpriv->clock_ns -
4783                                 1) / devpriv->clock_ns;
4784                         break;
4785                 default:
4786                         return -EINVAL;
4787                         break;
4788                 }
4789                 switch (data[3]) {
4790                 case TRIG_ROUND_NEAREST:
4791                         down_count =
4792                                 (data[4] +
4793                                 devpriv->clock_ns / 2) / devpriv->clock_ns;
4794                         break;
4795                 case TRIG_ROUND_DOWN:
4796                         down_count = data[4] / devpriv->clock_ns;
4797                         break;
4798                 case TRIG_ROUND_UP:
4799                         down_count =
4800                                 (data[4] + devpriv->clock_ns -
4801                                 1) / devpriv->clock_ns;
4802                         break;
4803                 default:
4804                         return -EINVAL;
4805                         break;
4806                 }
4807                 if (up_count * devpriv->clock_ns != data[2] ||
4808                         down_count * devpriv->clock_ns != data[4]) {
4809                         data[2] = up_count * devpriv->clock_ns;
4810                         data[4] = down_count * devpriv->clock_ns;
4811                         return -EAGAIN;
4812                 }
4813                 ni_writel(up_count, Calibration_HighTime_6143);
4814                 devpriv->pwm_up_count = up_count;
4815                 ni_writel(down_count, Calibration_LowTime_6143);
4816                 devpriv->pwm_down_count = down_count;
4817                 return 5;
4818                 break;
4819         case INSN_CONFIG_GET_PWM_OUTPUT:
4820                 return ni_get_pwm_config(dev, data);
4821         default:
4822                 return -EINVAL;
4823                 break;
4824         }
4825         return 0;
4826 }
4827
4828 static void ni_write_caldac(comedi_device * dev, int addr, int val);
4829 /*
4830         calibration subdevice
4831 */
4832 static int ni_calib_insn_write(comedi_device * dev, comedi_subdevice * s,
4833         comedi_insn * insn, lsampl_t * data)
4834 {
4835         if (insn->n == 0)
4836                 return 0;
4837
4838         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4839
4840         return 1;
4841 }
4842
4843 static int ni_calib_insn_read(comedi_device * dev, comedi_subdevice * s,
4844         comedi_insn * insn, lsampl_t * data)
4845 {
4846         if (insn->n == 0)
4847                 return 0;
4848
4849         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4850
4851         return 1;
4852 }
4853
4854 static int pack_mb88341(int addr, int val, int *bitstring);
4855 static int pack_dac8800(int addr, int val, int *bitstring);
4856 static int pack_dac8043(int addr, int val, int *bitstring);
4857 static int pack_ad8522(int addr, int val, int *bitstring);
4858 static int pack_ad8804(int addr, int val, int *bitstring);
4859 static int pack_ad8842(int addr, int val, int *bitstring);
4860
4861 struct caldac_struct {
4862         int n_chans;
4863         int n_bits;
4864         int (*packbits) (int, int, int *);
4865 };
4866
4867 static struct caldac_struct caldacs[] = {
4868         [mb88341] = {12, 8, pack_mb88341},
4869         [dac8800] = {8, 8, pack_dac8800},
4870         [dac8043] = {1, 12, pack_dac8043},
4871         [ad8522] = {2, 12, pack_ad8522},
4872         [ad8804] = {12, 8, pack_ad8804},
4873         [ad8842] = {8, 8, pack_ad8842},
4874         [ad8804_debug] = {16, 8, pack_ad8804},
4875 };
4876
4877 static void caldac_setup(comedi_device * dev, comedi_subdevice * s)
4878 {
4879         int i, j;
4880         int n_dacs;
4881         int n_chans = 0;
4882         int n_bits;
4883         int diffbits = 0;
4884         int type;
4885         int chan;
4886
4887         type = boardtype.caldac[0];
4888         if (type == caldac_none)
4889                 return;
4890         n_bits = caldacs[type].n_bits;
4891         for (i = 0; i < 3; i++) {
4892                 type = boardtype.caldac[i];
4893                 if (type == caldac_none)
4894                         break;
4895                 if (caldacs[type].n_bits != n_bits)
4896                         diffbits = 1;
4897                 n_chans += caldacs[type].n_chans;
4898         }
4899         n_dacs = i;
4900         s->n_chan = n_chans;
4901
4902         if (diffbits) {
4903                 unsigned int *maxdata_list;
4904
4905                 if (n_chans > MAX_N_CALDACS) {
4906                         printk("BUG! MAX_N_CALDACS too small\n");
4907                 }
4908                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4909                 chan = 0;
4910                 for (i = 0; i < n_dacs; i++) {
4911                         type = boardtype.caldac[i];
4912                         for (j = 0; j < caldacs[type].n_chans; j++) {
4913                                 maxdata_list[chan] =
4914                                         (1 << caldacs[type].n_bits) - 1;
4915                                 chan++;
4916                         }
4917                 }
4918
4919                 for (chan = 0; chan < s->n_chan; chan++)
4920                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4921         } else {
4922                 type = boardtype.caldac[0];
4923                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4924
4925                 for (chan = 0; chan < s->n_chan; chan++)
4926                         ni_write_caldac(dev, i, s->maxdata / 2);
4927         }
4928 }
4929
4930 static void ni_write_caldac(comedi_device * dev, int addr, int val)
4931 {
4932         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4933         int i;
4934         int type;
4935
4936         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4937         if (devpriv->caldacs[addr] == val)
4938                 return;
4939         devpriv->caldacs[addr] = val;
4940
4941         for (i = 0; i < 3; i++) {
4942                 type = boardtype.caldac[i];
4943                 if (type == caldac_none)
4944                         break;
4945                 if (addr < caldacs[type].n_chans) {
4946                         bits = caldacs[type].packbits(addr, val, &bitstring);
4947                         loadbit = SerDacLd(i);
4948                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4949                         break;
4950                 }
4951                 addr -= caldacs[type].n_chans;
4952         }
4953
4954         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4955                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4956                 comedi_udelay(1);
4957                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4958                 comedi_udelay(1);
4959         }
4960         ni_writeb(loadbit, Serial_Command);
4961         comedi_udelay(1);
4962         ni_writeb(0, Serial_Command);
4963 }
4964
4965 static int pack_mb88341(int addr, int val, int *bitstring)
4966 {
4967         /*
4968            Fujitsu MB 88341
4969            Note that address bits are reversed.  Thanks to
4970            Ingo Keen for noticing this.
4971
4972            Note also that the 88341 expects address values from
4973            1-12, whereas we use channel numbers 0-11.  The NI
4974            docs use 1-12, also, so be careful here.
4975          */
4976         addr++;
4977         *bitstring = ((addr & 0x1) << 11) |
4978                 ((addr & 0x2) << 9) |
4979                 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4980         return 12;
4981 }
4982
4983 static int pack_dac8800(int addr, int val, int *bitstring)
4984 {
4985         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4986         return 11;
4987 }
4988
4989 static int pack_dac8043(int addr, int val, int *bitstring)
4990 {
4991         *bitstring = val & 0xfff;
4992         return 12;
4993 }
4994
4995 static int pack_ad8522(int addr, int val, int *bitstring)
4996 {
4997         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4998         return 16;
4999 }
5000
5001 static int pack_ad8804(int addr, int val, int *bitstring)
5002 {
5003         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5004         return 12;
5005 }
5006
5007 static int pack_ad8842(int addr, int val, int *bitstring)
5008 {
5009         *bitstring = ((addr + 1) << 8) | (val & 0xff);
5010         return 12;
5011 }
5012
5013 #if 0
5014 /*
5015  *      Read the GPCTs current value.
5016  */
5017 static int GPCT_G_Watch(comedi_device * dev, int chan)
5018 {
5019         unsigned int hi1, hi2, lo;
5020
5021         devpriv->gpct_command[chan] &= ~G_Save_Trace;
5022         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5023                 G_Command_Register(chan));
5024
5025         devpriv->gpct_command[chan] |= G_Save_Trace;
5026         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5027                 G_Command_Register(chan));
5028
5029         /* This procedure is used because the two registers cannot
5030          * be read atomically. */
5031         do {
5032                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5033                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5034                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5035         } while (hi1 != hi2);
5036
5037         return (hi1 << 16) | lo;
5038 }
5039
5040 static void GPCT_Reset(comedi_device * dev, int chan)
5041 {
5042         int temp_ack_reg = 0;
5043
5044         //printk("GPCT_Reset...");
5045         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5046
5047         switch (chan) {
5048         case 0:
5049                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5050                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5051                         G0_TC_Interrupt_Enable, 0);
5052                 ni_set_bits(dev, Interrupt_A_Enable_Register,
5053                         G0_Gate_Interrupt_Enable, 0);
5054                 temp_ack_reg |= G0_Gate_Error_Confirm;
5055                 temp_ack_reg |= G0_TC_Error_Confirm;
5056                 temp_ack_reg |= G0_TC_Interrupt_Ack;
5057                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5058                 devpriv->stc_writew(dev, temp_ack_reg,
5059                         Interrupt_A_Ack_Register);
5060
5061                 //problem...this interferes with the other ctr...
5062                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5063                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5064                         Analog_Trigger_Etc_Register);
5065                 break;
5066         case 1:
5067                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5068                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5069                         G1_TC_Interrupt_Enable, 0);
5070                 ni_set_bits(dev, Interrupt_B_Enable_Register,
5071                         G0_Gate_Interrupt_Enable, 0);
5072                 temp_ack_reg |= G1_Gate_Error_Confirm;
5073                 temp_ack_reg |= G1_TC_Error_Confirm;
5074                 temp_ack_reg |= G1_TC_Interrupt_Ack;
5075                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5076                 devpriv->stc_writew(dev, temp_ack_reg,
5077                         Interrupt_B_Ack_Register);
5078
5079                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5080                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5081                         Analog_Trigger_Etc_Register);
5082                 break;
5083         };
5084
5085         devpriv->gpct_mode[chan] = 0;
5086         devpriv->gpct_input_select[chan] = 0;
5087         devpriv->gpct_command[chan] = 0;
5088
5089         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5090
5091         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5092                 G_Mode_Register(chan));
5093         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5094                 G_Input_Select_Register(chan));
5095         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5096
5097         //printk("exit GPCT_Reset\n");
5098 }
5099
5100 #endif
5101
5102 static int ni_gpct_insn_config(comedi_device * dev, comedi_subdevice * s,
5103         comedi_insn * insn, lsampl_t * data)
5104 {
5105         struct ni_gpct *counter = s->private;
5106         return ni_tio_insn_config(counter, insn, data);
5107 }
5108
5109 static int ni_gpct_insn_read(comedi_device * dev, comedi_subdevice * s,
5110         comedi_insn * insn, lsampl_t * data)
5111 {
5112         struct ni_gpct *counter = s->private;
5113         return ni_tio_rinsn(counter, insn, data);
5114 }
5115
5116 static int ni_gpct_insn_write(comedi_device * dev, comedi_subdevice * s,
5117         comedi_insn * insn, lsampl_t * data)
5118 {
5119         struct ni_gpct *counter = s->private;
5120         return ni_tio_winsn(counter, insn, data);
5121 }
5122
5123 static int ni_gpct_cmd(comedi_device * dev, comedi_subdevice * s)
5124 {
5125         int retval;
5126 #ifdef PCIDMA
5127         struct ni_gpct *counter = s->private;
5128 //      const comedi_cmd *cmd = &s->async->cmd;
5129
5130         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5131                 COMEDI_INPUT);
5132         if (retval) {
5133                 comedi_error(dev,
5134                         "no dma channel available for use by counter");
5135                 return retval;
5136         }
5137         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5138         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5139         retval = ni_tio_cmd(counter, s->async);
5140 #else
5141         retval = -ENOTSUPP;
5142 #endif
5143         return retval;
5144 }
5145
5146 static int ni_gpct_cmdtest(comedi_device * dev, comedi_subdevice * s,
5147         comedi_cmd * cmd)
5148 {
5149 #ifdef PCIDMA
5150         struct ni_gpct *counter = s->private;
5151
5152         return ni_tio_cmdtest(counter, cmd);
5153 #else
5154         return -ENOTSUPP;
5155 #endif
5156 }
5157
5158 static int ni_gpct_cancel(comedi_device * dev, comedi_subdevice * s)
5159 {
5160 #ifdef PCIDMA
5161         struct ni_gpct *counter = s->private;
5162         int retval;
5163
5164         retval = ni_tio_cancel(counter);
5165         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5166         ni_release_gpct_mite_channel(dev, counter->counter_index);
5167         return retval;
5168 #else
5169         return 0;
5170 #endif
5171 }
5172
5173 /*
5174  *
5175  *  Programmable Function Inputs
5176  *
5177  */
5178
5179 static int ni_m_series_set_pfi_routing(comedi_device * dev, unsigned chan,
5180         unsigned source)
5181 {
5182         unsigned pfi_reg_index;
5183         unsigned array_offset;
5184         if ((source & 0x1f) != source)
5185                 return -EINVAL;
5186         pfi_reg_index = 1 + chan / 3;
5187         array_offset = pfi_reg_index - 1;
5188         devpriv->pfi_output_select_reg[array_offset] &=
5189                 ~MSeries_PFI_Output_Select_Mask(chan);
5190         devpriv->pfi_output_select_reg[array_offset] |=
5191                 MSeries_PFI_Output_Select_Bits(chan, source);
5192         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5193                 M_Offset_PFI_Output_Select(pfi_reg_index));
5194         return 2;
5195 }
5196
5197 static int ni_old_set_pfi_routing(comedi_device * dev, unsigned chan,
5198         unsigned source)
5199 {
5200         // pre-m-series boards have fixed signals on pfi pins
5201         if (source != ni_old_get_pfi_routing(dev, chan))
5202                 return -EINVAL;
5203         return 2;
5204 }
5205
5206 static int ni_set_pfi_routing(comedi_device * dev, unsigned chan,
5207         unsigned source)
5208 {
5209         if (boardtype.reg_type & ni_reg_m_series_mask)
5210                 return ni_m_series_set_pfi_routing(dev, chan, source);
5211         else
5212                 return ni_old_set_pfi_routing(dev, chan, source);
5213 }
5214
5215 static unsigned ni_m_series_get_pfi_routing(comedi_device * dev, unsigned chan)
5216 {
5217         const unsigned array_offset = chan / 3;
5218         return MSeries_PFI_Output_Select_Source(chan,
5219                 devpriv->pfi_output_select_reg[array_offset]);
5220 }
5221
5222 static unsigned ni_old_get_pfi_routing(comedi_device * dev, unsigned chan)
5223 {
5224         // pre-m-series boards have fixed signals on pfi pins
5225         switch (chan) {
5226         case 0:
5227                 return NI_PFI_OUTPUT_AI_START1;
5228                 break;
5229         case 1:
5230                 return NI_PFI_OUTPUT_AI_START2;
5231                 break;
5232         case 2:
5233                 return NI_PFI_OUTPUT_AI_CONVERT;
5234                 break;
5235         case 3:
5236                 return NI_PFI_OUTPUT_G_SRC1;
5237                 break;
5238         case 4:
5239                 return NI_PFI_OUTPUT_G_GATE1;
5240                 break;
5241         case 5:
5242                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5243                 break;
5244         case 6:
5245                 return NI_PFI_OUTPUT_AO_START1;
5246                 break;
5247         case 7:
5248                 return NI_PFI_OUTPUT_AI_START_PULSE;
5249                 break;
5250         case 8:
5251                 return NI_PFI_OUTPUT_G_SRC0;
5252                 break;
5253         case 9:
5254                 return NI_PFI_OUTPUT_G_GATE0;
5255                 break;
5256         default:
5257                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
5258                 break;
5259         }
5260         return 0;
5261 }
5262
5263 static unsigned ni_get_pfi_routing(comedi_device * dev, unsigned chan)
5264 {
5265         if (boardtype.reg_type & ni_reg_m_series_mask)
5266                 return ni_m_series_get_pfi_routing(dev, chan);
5267         else
5268                 return ni_old_get_pfi_routing(dev, chan);
5269 }
5270
5271 static int ni_config_filter(comedi_device * dev, unsigned pfi_channel,
5272         enum ni_pfi_filter_select filter)
5273 {
5274         unsigned bits;
5275         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5276                 return -ENOTSUPP;
5277         }
5278         bits = ni_readl(M_Offset_PFI_Filter);
5279         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5280         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5281         ni_writel(bits, M_Offset_PFI_Filter);
5282         return 0;
5283 }
5284
5285 static int ni_pfi_insn_bits(comedi_device * dev, comedi_subdevice * s,
5286         comedi_insn * insn, lsampl_t * data)
5287 {
5288         if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5289                 return -ENOTSUPP;
5290         }
5291         if (data[0]) {
5292                 s->state &= ~data[0];
5293                 s->state |= (data[0] & data[1]);
5294                 ni_writew(s->state, M_Offset_PFI_DO);
5295         }
5296         data[1] = ni_readw(M_Offset_PFI_DI);
5297         return 2;
5298 }
5299
5300 static int ni_pfi_insn_config(comedi_device * dev, comedi_subdevice * s,
5301         comedi_insn * insn, lsampl_t * data)
5302 {
5303         unsigned int chan;
5304
5305         if (insn->n < 1)
5306                 return -EINVAL;
5307
5308         chan = CR_CHAN(insn->chanspec);
5309
5310         switch (data[0]) {
5311         case COMEDI_OUTPUT:
5312                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5313                 break;
5314         case COMEDI_INPUT:
5315                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5316                 break;
5317         case INSN_CONFIG_DIO_QUERY:
5318                 data[1] =
5319                         (devpriv->
5320                         io_bidirection_pin_reg & (1 << chan)) ? COMEDI_OUTPUT :
5321                         COMEDI_INPUT;
5322                 return 0;
5323                 break;
5324         case INSN_CONFIG_SET_ROUTING:
5325                 return ni_set_pfi_routing(dev, chan, data[1]);
5326                 break;
5327         case INSN_CONFIG_GET_ROUTING:
5328                 data[1] = ni_get_pfi_routing(dev, chan);
5329                 break;
5330         case INSN_CONFIG_FILTER:
5331                 return ni_config_filter(dev, chan, data[1]);
5332                 break;
5333         default:
5334                 return -EINVAL;
5335         }
5336         return 0;
5337 }
5338
5339 /*
5340  *
5341  *  NI RTSI Bus Functions
5342  *
5343  */
5344 static void ni_rtsi_init(comedi_device * dev)
5345 {
5346         // Initialises the RTSI bus signal switch to a default state
5347
5348         // Set clock mode to internal
5349         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5350         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5351                 rt_printk("ni_set_master_clock failed, bug?");
5352         }
5353         // default internal lines routing to RTSI bus lines
5354         devpriv->rtsi_trig_a_output_reg =
5355                 RTSI_Trig_Output_Bits(0,
5356                 NI_RTSI_OUTPUT_ADR_START1) | RTSI_Trig_Output_Bits(1,
5357                 NI_RTSI_OUTPUT_ADR_START2) | RTSI_Trig_Output_Bits(2,
5358                 NI_RTSI_OUTPUT_SCLKG) | RTSI_Trig_Output_Bits(3,
5359                 NI_RTSI_OUTPUT_DACUPDN);
5360         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5361                 RTSI_Trig_A_Output_Register);
5362         devpriv->rtsi_trig_b_output_reg =
5363                 RTSI_Trig_Output_Bits(4,
5364                 NI_RTSI_OUTPUT_DA_START1) | RTSI_Trig_Output_Bits(5,
5365                 NI_RTSI_OUTPUT_G_SRC0) | RTSI_Trig_Output_Bits(6,
5366                 NI_RTSI_OUTPUT_G_GATE0);
5367         if (boardtype.reg_type & ni_reg_m_series_mask)
5368                 devpriv->rtsi_trig_b_output_reg |=
5369                         RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5370         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5371                 RTSI_Trig_B_Output_Register);
5372
5373         // Sets the source and direction of the 4 on board lines
5374 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5375 }
5376
5377 static int ni_rtsi_insn_bits(comedi_device * dev, comedi_subdevice * s,
5378         comedi_insn * insn, lsampl_t * data)
5379 {
5380         if (insn->n != 2)
5381                 return -EINVAL;
5382
5383         data[1] = 0;
5384
5385         return 2;
5386 }
5387
5388 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5389  * given an arbitrary frequency input clock */
5390 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5391         unsigned *freq_divider, unsigned *freq_multiplier,
5392         unsigned *actual_period_ns)
5393 {
5394         unsigned div;
5395         unsigned best_div = 1;
5396         static const unsigned max_div = 0x10;
5397         unsigned mult;
5398         unsigned best_mult = 1;
5399         static const unsigned max_mult = 0x100;
5400         static const unsigned pico_per_nano = 1000;
5401
5402         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5403         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5404          * 20 MHz for most timing clocks */
5405         static const unsigned target_picosec = 12500;
5406         static const unsigned fudge_factor_80_to_20Mhz = 4;
5407         int best_period_picosec = 0;
5408         for (div = 1; div <= max_div; ++div) {
5409                 for (mult = 1; mult <= max_mult; ++mult) {
5410                         unsigned new_period_ps =
5411                                 (reference_picosec * div) / mult;
5412                         if (abs(new_period_ps - target_picosec) <
5413                                 abs(best_period_picosec - target_picosec)) {
5414                                 best_period_picosec = new_period_ps;
5415                                 best_div = div;
5416                                 best_mult = mult;
5417                         }
5418                 }
5419         }
5420         if (best_period_picosec == 0) {
5421                 rt_printk("%s: bug, failed to find pll parameters\n",
5422                         __FUNCTION__);
5423                 return -EIO;
5424         }
5425         *freq_divider = best_div;
5426         *freq_multiplier = best_mult;
5427         *actual_period_ns =
5428                 (best_period_picosec * fudge_factor_80_to_20Mhz +
5429                 (pico_per_nano / 2)) / pico_per_nano;
5430         return 0;
5431 }
5432
5433 static inline unsigned num_configurable_rtsi_channels(comedi_device * dev)
5434 {
5435         if (boardtype.reg_type & ni_reg_m_series_mask)
5436                 return 8;
5437         else
5438                 return 7;
5439 }
5440
5441 static int ni_mseries_set_pll_master_clock(comedi_device * dev, unsigned source,
5442         unsigned period_ns)
5443 {
5444         static const unsigned min_period_ns = 50;
5445         static const unsigned max_period_ns = 1000;
5446         static const unsigned timeout = 1000;
5447         unsigned pll_control_bits;
5448         unsigned freq_divider;
5449         unsigned freq_multiplier;
5450         unsigned i;
5451         int retval;
5452         if (source == NI_MIO_PLL_PXI10_CLOCK)
5453                 period_ns = 100;
5454         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
5455         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5456                 rt_printk
5457                         ("%s: you must specify an input clock frequency between %i and %i nanosec "
5458                         "for the phased-lock loop.\n", __FUNCTION__,
5459                         min_period_ns, max_period_ns);
5460                 return -EINVAL;
5461         }
5462         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5463         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5464                 RTSI_Trig_Direction_Register);
5465         pll_control_bits =
5466                 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5467         devpriv->clock_and_fout2 |=
5468                 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5469         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5470         switch (source) {
5471         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5472                 devpriv->clock_and_fout2 |=
5473                         MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5474                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5475                         &freq_multiplier, &devpriv->clock_ns);
5476                 if (retval < 0)
5477                         return retval;
5478                 break;
5479         case NI_MIO_PLL_PXI10_CLOCK:
5480                 /* pxi clock is 10MHz */
5481                 devpriv->clock_and_fout2 |=
5482                         MSeries_PLL_In_Source_Select_PXI_Clock10;
5483                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5484                         &freq_multiplier, &devpriv->clock_ns);
5485                 if (retval < 0)
5486                         return retval;
5487                 break;
5488         default:
5489                 {
5490                         unsigned rtsi_channel;
5491                         static const unsigned max_rtsi_channel = 7;
5492                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5493                                 ++rtsi_channel) {
5494                                 if (source ==
5495                                         NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5496                                         devpriv->clock_and_fout2 |=
5497                                                 MSeries_PLL_In_Source_Select_RTSI_Bits
5498                                                 (rtsi_channel);
5499                                         break;
5500                                 }
5501                         }
5502                         if (rtsi_channel > max_rtsi_channel)
5503                                 return -EINVAL;
5504                         retval = ni_mseries_get_pll_parameters(period_ns,
5505                                 &freq_divider, &freq_multiplier,
5506                                 &devpriv->clock_ns);
5507                         if (retval < 0)
5508                                 return retval;
5509                 }
5510                 break;
5511         }
5512         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5513         pll_control_bits |=
5514                 MSeries_PLL_Divisor_Bits(freq_divider) |
5515                 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5516 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
5517 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
5518         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5519         devpriv->clock_source = source;
5520         /* it seems to typically take a few hundred microseconds for PLL to lock */
5521         for (i = 0; i < timeout; ++i) {
5522                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5523                         break;
5524                 }
5525                 udelay(1);
5526         }
5527         if (i == timeout) {
5528                 rt_printk
5529                         ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5530                         __FUNCTION__, source, period_ns);
5531                 return -ETIMEDOUT;
5532         }
5533         return 3;
5534 }
5535
5536 static int ni_set_master_clock(comedi_device * dev, unsigned source,
5537         unsigned period_ns)
5538 {
5539         if (source == NI_MIO_INTERNAL_CLOCK) {
5540                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5541                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5542                         RTSI_Trig_Direction_Register);
5543                 devpriv->clock_ns = TIMEBASE_1_NS;
5544                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5545                         devpriv->clock_and_fout2 &=
5546                                 ~(MSeries_Timebase1_Select_Bit |
5547                                 MSeries_Timebase3_Select_Bit);
5548                         ni_writew(devpriv->clock_and_fout2,
5549                                 M_Offset_Clock_and_Fout2);
5550                         ni_writew(0, M_Offset_PLL_Control);
5551                 }
5552                 devpriv->clock_source = source;
5553         } else {
5554                 if (boardtype.reg_type & ni_reg_m_series_mask) {
5555                         return ni_mseries_set_pll_master_clock(dev, source,
5556                                 period_ns);
5557                 } else {
5558                         if (source == NI_MIO_RTSI_CLOCK) {
5559                                 devpriv->rtsi_trig_direction_reg |=
5560                                         Use_RTSI_Clock_Bit;
5561                                 devpriv->stc_writew(dev,
5562                                         devpriv->rtsi_trig_direction_reg,
5563                                         RTSI_Trig_Direction_Register);
5564                                 if (period_ns == 0) {
5565                                         rt_printk
5566                                                 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5567                                                 __FUNCTION__);
5568                                         return -EINVAL;
5569                                 } else {
5570                                         devpriv->clock_ns = period_ns;
5571                                 }
5572                                 devpriv->clock_source = source;
5573                         } else
5574                                 return -EINVAL;
5575                 }
5576         }
5577         return 3;
5578 }
5579
5580 static int ni_valid_rtsi_output_source(comedi_device * dev, unsigned chan,
5581         unsigned source)
5582 {
5583         if (chan >= num_configurable_rtsi_channels(dev)) {
5584                 if (chan == old_RTSI_clock_channel) {
5585                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5586                                 return 1;
5587                         else {
5588                                 rt_printk
5589                                         ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5590                                         __FUNCTION__, chan,
5591                                         old_RTSI_clock_channel);
5592                                 return 0;
5593                         }
5594                 }
5595                 return 0;
5596         }
5597         switch (source) {
5598         case NI_RTSI_OUTPUT_ADR_START1:
5599         case NI_RTSI_OUTPUT_ADR_START2:
5600         case NI_RTSI_OUTPUT_SCLKG:
5601         case NI_RTSI_OUTPUT_DACUPDN:
5602         case NI_RTSI_OUTPUT_DA_START1:
5603         case NI_RTSI_OUTPUT_G_SRC0:
5604         case NI_RTSI_OUTPUT_G_GATE0:
5605         case NI_RTSI_OUTPUT_RGOUT0:
5606         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5607                 return 1;
5608                 break;
5609         case NI_RTSI_OUTPUT_RTSI_OSC:
5610                 if (boardtype.reg_type & ni_reg_m_series_mask)
5611                         return 1;
5612                 else
5613                         return 0;
5614                 break;
5615         default:
5616                 return 0;
5617                 break;
5618         }
5619 }
5620
5621 static int ni_set_rtsi_routing(comedi_device * dev, unsigned chan,
5622         unsigned source)
5623 {
5624         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5625                 return -EINVAL;
5626         if (chan < 4) {
5627                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5628                 devpriv->rtsi_trig_a_output_reg |=
5629                         RTSI_Trig_Output_Bits(chan, source);
5630                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5631                         RTSI_Trig_A_Output_Register);
5632         } else if (chan < 8) {
5633                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5634                 devpriv->rtsi_trig_b_output_reg |=
5635                         RTSI_Trig_Output_Bits(chan, source);
5636                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5637                         RTSI_Trig_B_Output_Register);
5638         }
5639         return 2;
5640 }
5641
5642 static unsigned ni_get_rtsi_routing(comedi_device * dev, unsigned chan)
5643 {
5644         if (chan < 4) {
5645                 return RTSI_Trig_Output_Source(chan,
5646                         devpriv->rtsi_trig_a_output_reg);
5647         } else if (chan < num_configurable_rtsi_channels(dev)) {
5648                 return RTSI_Trig_Output_Source(chan,
5649                         devpriv->rtsi_trig_b_output_reg);
5650         } else {
5651                 if (chan == old_RTSI_clock_channel)
5652                         return NI_RTSI_OUTPUT_RTSI_OSC;
5653                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
5654                 return 0;
5655         }
5656 }
5657
5658 static int ni_rtsi_insn_config(comedi_device * dev, comedi_subdevice * s,
5659         comedi_insn * insn, lsampl_t * data)
5660 {
5661         unsigned int chan = CR_CHAN(insn->chanspec);
5662         switch (data[0]) {
5663         case INSN_CONFIG_DIO_OUTPUT:
5664                 if (chan < num_configurable_rtsi_channels(dev)) {
5665                         devpriv->rtsi_trig_direction_reg |=
5666                                 RTSI_Output_Bit(chan,
5667                                 (boardtype.reg_type & ni_reg_m_series_mask) !=
5668                                 0);
5669                 } else if (chan == old_RTSI_clock_channel) {
5670                         devpriv->rtsi_trig_direction_reg |=
5671                                 Drive_RTSI_Clock_Bit;
5672                 }
5673                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5674                         RTSI_Trig_Direction_Register);
5675                 break;
5676         case INSN_CONFIG_DIO_INPUT:
5677                 if (chan < num_configurable_rtsi_channels(dev)) {
5678                         devpriv->rtsi_trig_direction_reg &=
5679                                 ~RTSI_Output_Bit(chan,
5680                                 (boardtype.reg_type & ni_reg_m_series_mask) !=
5681                                 0);
5682                 } else if (chan == old_RTSI_clock_channel) {
5683                         devpriv->rtsi_trig_direction_reg &=
5684                                 ~Drive_RTSI_Clock_Bit;
5685                 }
5686                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5687                         RTSI_Trig_Direction_Register);
5688                 break;
5689         case INSN_CONFIG_DIO_QUERY:
5690                 if (chan < num_configurable_rtsi_channels(dev)) {
5691                         data[1] =
5692                                 (devpriv->
5693                                 rtsi_trig_direction_reg & RTSI_Output_Bit(chan,
5694                                         (boardtype.
5695                                                 reg_type & ni_reg_m_series_mask)
5696                                         !=
5697                                         0)) ? INSN_CONFIG_DIO_OUTPUT :
5698                                 INSN_CONFIG_DIO_INPUT;
5699                 } else if (chan == old_RTSI_clock_channel) {
5700                         data[1] =
5701                                 (devpriv->
5702                                 rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit)
5703                                 ? INSN_CONFIG_DIO_OUTPUT :
5704                                 INSN_CONFIG_DIO_INPUT;
5705                 }
5706                 return 2;
5707                 break;
5708         case INSN_CONFIG_SET_CLOCK_SRC:
5709                 return ni_set_master_clock(dev, data[1], data[2]);
5710                 break;
5711         case INSN_CONFIG_GET_CLOCK_SRC:
5712                 data[1] = devpriv->clock_source;
5713                 data[2] = devpriv->clock_ns;
5714                 return 3;
5715                 break;
5716         case INSN_CONFIG_SET_ROUTING:
5717                 return ni_set_rtsi_routing(dev, chan, data[1]);
5718                 break;
5719         case INSN_CONFIG_GET_ROUTING:
5720                 data[1] = ni_get_rtsi_routing(dev, chan);
5721                 return 2;
5722                 break;
5723         default:
5724                 return -EINVAL;
5725                 break;
5726         }
5727         return 1;
5728 }
5729
5730 static int cs5529_wait_for_idle(comedi_device * dev)
5731 {
5732         unsigned short status;
5733         const int timeout = HZ;
5734         int i;
5735
5736         for (i = 0; i < timeout; i++) {
5737                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5738                 if ((status & CSS_ADC_BUSY) == 0) {
5739                         break;
5740                 }
5741                 set_current_state(TASK_INTERRUPTIBLE);
5742                 if (schedule_timeout(1)) {
5743                         return -EIO;
5744                 }
5745         }
5746 //printk("looped %i times waiting for idle\n", i);
5747         if (i == timeout) {
5748                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
5749                 return -ETIME;
5750         }
5751         return 0;
5752 }
5753
5754 static void cs5529_command(comedi_device * dev, unsigned short value)
5755 {
5756         static const int timeout = 100;
5757         int i;
5758
5759         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5760         /* give time for command to start being serially clocked into cs5529.
5761          * this insures that the CSS_ADC_BUSY bit will get properly
5762          * set before we exit this function.
5763          */
5764         for (i = 0; i < timeout; i++) {
5765                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5766                         break;
5767                 comedi_udelay(1);
5768         }
5769 //printk("looped %i times writing command to cs5529\n", i);
5770         if (i == timeout) {
5771                 comedi_error(dev, "possible problem - never saw adc go busy?");
5772         }
5773 }
5774
5775 /* write to cs5529 register */
5776 static void cs5529_config_write(comedi_device * dev, unsigned int value,
5777         unsigned int reg_select_bits)
5778 {
5779         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5780                 CAL_ADC_Config_Data_High_Word_67xx);
5781         ni_ao_win_outw(dev, (value & 0xffff),
5782                 CAL_ADC_Config_Data_Low_Word_67xx);
5783         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5784         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5785         if (cs5529_wait_for_idle(dev))
5786                 comedi_error(dev, "time or signal in cs5529_config_write()");
5787 }
5788
5789 #ifdef NI_CS5529_DEBUG
5790 /* read from cs5529 register */
5791 static unsigned int cs5529_config_read(comedi_device * dev,
5792         unsigned int reg_select_bits)
5793 {
5794         unsigned int value;
5795
5796         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5797         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5798         if (cs5529_wait_for_idle(dev))
5799                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5800         value = (ni_ao_win_inw(dev,
5801                         CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
5802         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5803         return value;
5804 }
5805 #endif
5806
5807 static int cs5529_do_conversion(comedi_device * dev, unsigned short *data)
5808 {
5809         int retval;
5810         unsigned short status;
5811
5812         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5813         retval = cs5529_wait_for_idle(dev);
5814         if (retval) {
5815                 comedi_error(dev,
5816                         "timeout or signal in cs5529_do_conversion()");
5817                 return -ETIME;
5818         }
5819         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5820         if (status & CSS_OSC_DETECT) {
5821                 rt_printk
5822                         ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5823                 return -EIO;
5824         }
5825         if (status & CSS_OVERRANGE) {
5826                 rt_printk
5827                         ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5828         }
5829         if (data) {
5830                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5831                 /* cs5529 returns 16 bit signed data in bipolar mode */
5832                 *data ^= (1 << 15);
5833         }
5834         return 0;
5835 }
5836
5837 static int cs5529_ai_insn_read(comedi_device * dev, comedi_subdevice * s,
5838         comedi_insn * insn, lsampl_t * data)
5839 {
5840         int n, retval;
5841         unsigned short sample;
5842         unsigned int channel_select;
5843         const unsigned int INTERNAL_REF = 0x1000;
5844
5845         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5846          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5847          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5848         if (insn->chanspec & CR_ALT_SOURCE)
5849                 channel_select = INTERNAL_REF;
5850         else
5851                 channel_select = CR_CHAN(insn->chanspec);
5852         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5853
5854         for (n = 0; n < insn->n; n++) {
5855                 retval = cs5529_do_conversion(dev, &sample);
5856                 if (retval < 0)
5857                         return retval;
5858                 data[n] = sample;
5859         }
5860         return insn->n;
5861 }
5862
5863 static int init_cs5529(comedi_device * dev)
5864 {
5865         unsigned int config_bits =
5866                 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5867
5868 #if 1
5869         /* do self-calibration */
5870         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5871                 CSCMD_CONFIG_REGISTER);
5872         /* need to force a conversion for calibration to run */
5873         cs5529_do_conversion(dev, NULL);
5874 #else
5875         /* force gain calibration to 1 */
5876         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5877         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5878                 CSCMD_CONFIG_REGISTER);
5879         if (cs5529_wait_for_idle(dev))
5880                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5881 #endif
5882 #ifdef NI_CS5529_DEBUG
5883         rt_printk("config: 0x%x\n", cs5529_config_read(dev,
5884                 CSCMD_CONFIG_REGISTER));
5885         rt_printk("gain: 0x%x\n", cs5529_config_read(dev,
5886                 CSCMD_GAIN_REGISTER));
5887         rt_printk("offset: 0x%x\n", cs5529_config_read(dev,
5888                 CSCMD_OFFSET_REGISTER));
5889 #endif
5890         return 0;
5891 }