amplc_dio200: Allow extra clock and gate sources for PCIe boards.

One of the enhancements of the new PCIe boards is the addition of extra
clock and gate sources.  Allow clock and gate sources up to 31 for these
boards (compared to 7 for the old boards) although most of those are
reserved for future use.

Add constants to comedi.h for the new clock and gate sources.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>

diff --git a/comedi/drivers/amplc_dio200.c b/comedi/drivers/amplc_dio200.c
index 5e8a394fbdb915d075ef139affe0699b8db9f8bf..04716c51a0310ebe5c0b90759f54fa4d1eafadd8 100644 (file)
--- a/comedi/drivers/amplc_dio200.c
+++ b/comedi/drivers/amplc_dio200.c
@@ -280,15 +280,17 @@ order they appear in the channel list.
  *
  * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
  * 'chan' is the channel: 0, 1 or 2.
- * 'source' is the signal source: 0 to 7.
+ * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
  */
-#define CLK_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | (source))
-#define GAT_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | (source))
+#define CLK_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | \
+               (((source) & 030) << 3) | ((source) & 007))
+#define GAT_SCE(which, chan, source) (((which) << 5) | ((chan) << 3) | \
+               (((source) & 030) << 3) | ((source) & 007))
 
 /*
  * Periods of the internal clock sources in nanoseconds.
  */
-static const unsigned clock_period[8] = {
+static const unsigned clock_period[32] = {
        0,                      /* dedicated clock input/output pin */
        100,                    /* 10 MHz */
        1000,                   /* 1 MHz */
@@ -296,7 +298,12 @@ static const unsigned clock_period[8] = {
        100000,                 /* 10 kHz */
        1000000,                /* 1 kHz */
        0,                      /* OUT N-1 */
-       0                       /* group clock input pin */
+       0,                      /* group clock input pin */
+       0,                      /* HIGH (VCC) (enhanced) */
+       0,                      /* LOW (GND) (enhanced) */
+       0,                      /* pattern present (enhanced) */
+       50,                     /* 20 MHz (enhanced) */
+       /* remaining clock sources reserved (enhanced) */
 };
 
 /*
@@ -1337,7 +1344,7 @@ dio200_subdev_8254_set_gate_src(comedi_device * dev, comedi_subdevice *s,
                return -1;
        if (counter_number > 2)
                return -1;
-       if (gate_src > 7)
+       if (gate_src > (thislayout->has_enhancements ? 31 : 7))
                return -1;
 
        subpriv->gate_src[counter_number] = gate_src;
@@ -1378,7 +1385,7 @@ dio200_subdev_8254_set_clock_src(comedi_device * dev, comedi_subdevice *s,
                return -1;
        if (counter_number > 2)
                return -1;
-       if (clock_src > 7)
+       if (clock_src > (thislayout->has_enhancements ? 31 : 7))
                return -1;
 
        subpriv->clock_src[counter_number] = clock_src;

diff --git a/include/linux/comedi.h b/include/linux/comedi.h
index 320dfc499fc463c6368492cbad9b843d0ae2481d..c0bf757e04e96eb8b1ca34cb14e43f1996f8324a 100644 (file)
--- a/include/linux/comedi.h
+++ b/include/linux/comedi.h
@@ -852,7 +852,12 @@ CR_INVERT to change polarity. */
                                           subdevice, preceding counter
                                           subdevice is the last counter
                                           subdevice) */
-               AMPLC_DIO_CLK_EXT       /* per chip external input pin */
+               AMPLC_DIO_CLK_EXT,      /* per chip external input pin */
+               /* the following are "enhanced" clock sources for PCIe models */
+               AMPLC_DIO_CLK_VCC,      /* clock input HIGH */
+               AMPLC_DIO_CLK_GND,      /* clock input set LOW */
+               AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */
+               AMPLC_DIO_CLK_20MHZ     /* 20 MHz internal clock */
        };
 
 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
@@ -871,7 +876,17 @@ CR_INVERT to change polarity. */
                AMPLC_DIO_GAT_RESERVED4,
                AMPLC_DIO_GAT_RESERVED5,
                AMPLC_DIO_GAT_RESERVED6,
-               AMPLC_DIO_GAT_RESERVED7
+               AMPLC_DIO_GAT_RESERVED7,
+               /* the following are "enhanced" gate sources for PCIe models */
+               AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */
+               AMPLC_DIO_GAT_OUTNM2,   /* non-negated output of counter
+                                          channel minus 2 */
+               AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */
+               AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */
+               AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */
+               AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */
+               AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */
+               AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */
        };
 
 #ifdef __cplusplus