#ifndef _COMEDI_NI_STC_H
#define _COMEDI_NI_STC_H
+#include "ni_tio.h"
+
#define _bit15 0x8000
#define _bit14 0x4000
#define _bit13 0x2000
#define _bit1 0x0002
#define _bit0 0x0001
+#define NUM_PFI_OUTPUT_SELECT_REGS 6
+
/* Registers in the National Instruments DAQ-STC chip */
#define Interrupt_A_Ack_Register 2
#define Interrupt_B_Ack_Register 3
enum Interrupt_B_Ack_Bits
{
+ G1_Gate_Error_Confirm = _bit1,
+ G1_TC_Error_Confirm = _bit2,
+ AO_BC_TC_Trigger_Error_Confirm = _bit3,
+ AO_BC_TC_Error_Confirm = _bit4,
+ AO_UI2_TC_Error_Confrim = _bit5,
+ AO_UI2_TC_Interrupt_Ack = _bit6,
+ AO_UC_TC_Interrupt_Ack = _bit7,
AO_BC_TC_Interrupt_Ack = _bit8,
+ AO_START1_Interrupt_Ack = _bit9,
+ AO_UPDATE_Interrupt_Ack = _bit10,
+ AO_START_Interrupt_Ack = _bit11,
+ AO_STOP_Interrupt_Ack = _bit12,
AO_Error_Interrupt_Ack = _bit13,
+ G1_TC_Interrupt_Ack = _bit14,
+ G1_Gate_Interrupt_Ack = _bit15
};
#define AO_Status_1_Register 3
#define FOUT_Divider(x) (((x) & 0xf) << 0)
#define IO_Bidirection_Pin_Register 57
+#define RTSI_Trig_Direction_Register 58
+enum RTSI_Trig_Direction_Bits
+{
+ Drive_RTSI_Clock_Bit = 0x1,
+ Use_RTSI_Clock_Bit = 0x2,
+};
+static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries)
+{
+ unsigned max_channel;
+ unsigned base_bit_shift;
+ if(is_mseries)
+ {
+ base_bit_shift = 8;
+ max_channel = 7;
+ }else
+ {
+ base_bit_shift = 9;
+ max_channel = 6;
+ }
+ if(channel > max_channel)
+ {
+ rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, channel);
+ return 0;
+ }
+ return 1 << (base_bit_shift + channel);
+}
#define Interrupt_Control_Register 59
#define Interrupt_B_Enable _bit15
#define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
#define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
#define AI_SC_TC_Output_Select(x) ((x)<<2)
-#define AI_CONVERT_Output_Select(x) (((x) & 0x3) << 0)
+enum ai_convert_output_selection
+{
+ AI_CONVERT_Output_High_Z = 0,
+ AI_CONVERT_Output_Ground = 1,
+ AI_CONVERT_Output_Enable_Low = 2,
+ AI_CONVERT_Output_Enable_High = 3
+};
+static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection selection)
+{
+ return selection & 0x3;
+}
#define AI_START_STOP_Select_Register 62
#define AI_START_Polarity _bit15
#define AO_START1_Interrupt_Enable _bit1
#define AO_BC_TC_Interrupt_Enable _bit0
+#define Second_IRQ_A_Enable_Register 74
+enum Second_IRQ_A_Enable_Bits
+{
+ AI_SC_TC_Second_Irq_Enable = _bit0,
+ AI_START1_Second_Irq_Enable = _bit1,
+ AI_START2_Second_Irq_Enable = _bit2,
+ AI_START_Second_Irq_Enable = _bit3,
+ AI_STOP_Second_Irq_Enable = _bit4,
+ AI_Error_Second_Irq_Enable = _bit5,
+ G0_TC_Second_Irq_Enable = _bit6,
+ AI_FIFO_Second_Irq_Enable = _bit7,
+ G0_Gate_Second_Irq_Enable = _bit8,
+ Pass_Thru_0_Second_Irq_Enable = _bit9
+};
+
#define Second_IRQ_B_Enable_Register 76
+enum Second_IRQ_B_Enable_Bits
+{
+ AO_BC_TC_Second_Irq_Enable = _bit0,
+ AO_START1_Second_Irq_Enable = _bit1,
+ AO_UPDATE_Second_Irq_Enable = _bit2,
+ AO_START_Second_Irq_Enable = _bit3,
+ AO_STOP_Second_Irq_Enable = _bit4,
+ AO_Error_Second_Irq_Enable = _bit5,
+ AO_UC_TC_Second_Irq_Enable = _bit6,
+ AO_UI2_TC_Second_Irq_Enable = _bit7,
+ AO_FIFO_Second_Irq_Enable = _bit8,
+ G1_TC_Second_Irq_Enable = _bit9,
+ G1_Gate_Second_Irq_Enable = _bit10,
+ Pass_Thru_1_Second_Irq_Enable = _bit11
+};
+
#define AI_Personal_Register 77
#define AI_SHIFTIN_Pulse_Width _bit15
#define AI_EOC_Polarity _bit14
AO_Interval_Buffer_Mode = 1 << 3,
AO_BC_Source_Select = 1 << 4,
AO_UPDATE_Pulse_Width = 1 << 5,
+ AO_UPDATE_Pulse_Timebase = 1 << 6,
+ AO_UPDATE_Original_Pulse = 1 << 7,
AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
AO_FIFO_Enable = 1 << 10,
+ AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */
AO_TMRDACWR_Pulse_Width = 1 << 12,
+ AO_Fast_CPU = 1 << 13, /* M Series: reserved */
AO_Number_Of_DAC_Packages = 1 << 14, // 1 for "single" mode, 0 for "dual"
+ AO_Multiple_DACS_Per_Package = 1 << 15 // m-series only
+};
+#define RTSI_Trig_A_Output_Register 79
+#define RTSI_Trig_B_Output_Register 80
+enum RTSI_Trig_B_Output_Bits
+{
+ RTSI_Sub_Selection_1_Bit = 0x8000 // not for m-series
+};
+static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel, unsigned source)
+{
+ return (source & 0xf) << ((rtsi_channel % 4) * 4);
+};
+static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel)
+{
+ return 0xf << ((rtsi_channel % 4) * 4);
+};
+// inverse to RTSI_Trig_Output_Bits()
+static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel, unsigned bits)
+{
+ return (bits >> ((rtsi_channel % 4) * 4)) & 0xf;
};
+
+#define RTSI_Board_Register 81
#define Write_Strobe_0_Register 82
#define Write_Strobe_1_Register 83
#define Write_Strobe_2_Register 84
#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
#define AO_External_Gate_Polarity _bit3
#define AO_UPDATE2_Output_Toggle _bit2
-#define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
+enum ao_update_output_selection
+{
+ AO_Update_Output_High_Z = 0,
+ AO_Update_Output_Ground = 1,
+ AO_Update_Output_Enable_Low = 2,
+ AO_Update_Output_Enable_High = 3
+};
+static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection selection)
+{
+ return selection & 0x3;
+}
#define AI_Mode_3_Register 87
#define AI_Trigger_Length _bit15
#define G_Bank_Switch_Mode _bit11
#define G_Load _bit2 /* strobe */
-
/* input select register */
#define G_Gate_Select(a) (((a)&0x1f)<<7)
#define G_Source_Select(a) (((a)&0x1f)<<2)
#define G_OR_Gate _bit13
#define G_Gate_Select_Load_Source _bit12
-
/* mode register */
#define G_Loading_On_TC _bit12
#define G_Output_Mode(a) (((a)&0x03)<<8)
#define G0_Save_St _bit0
/* general purpose counter timer */
-#define G0_TC_Interrupt_Enable _bit6
-#define G1_TC_Interrupt_Enable _bit9
-#define G0_Gate_Interrupt_Enable _bit8
-#define G1_Gate_Interrupt_Enable _bit10
-#define G0_Synchronized_Gate _bit8
-#define G1_Synchronized_Gate _bit8
-#define G0_Gate_Error_Confirm _bit5
-#define G1_Gate_Error_Confirm _bit1
-#define G0_TC_Error_Confirm _bit6
-#define G1_TC_Error_Confirm _bit2
-#define G0_TC_Interrupt_Ack _bit14
-#define G1_TC_Interrupt_Ack _bit14
-#define G0_Gate_Interrupt_Ack _bit15
-#define G1_Gate_Interrupt_Ack _bit15
-#define G_Autoincrement(a) ((a)<<0)
#define G_Autoincrement(a) ((a)<<0)
-#define G0_Arm _bit0
-#define G1_Arm _bit0
/*Analog_Trigger_Etc_Register*/
#define Analog_Trigger_Mode(x) ((x) & 0x7)
#define Channel_B_Mode 0x05
#define Channel_C_Mode 0x07
#define AI_AO_Select 0x09
+enum AI_AO_Select_Bits
+{
+ AI_DMA_Select_Shift = 0,
+ AI_DMA_Select_Mask = 0xf,
+ AO_DMA_Select_Shift = 4,
+ AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
+};
#define G0_G1_Select 0x0b
+static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
+{
+ if(channel < 4) return 1 << channel;
+ if(channel == 4) return 0x3;
+ if(channel == 5) return 0x5;
+ BUG();
+ return 0;
+}
+static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, unsigned mite_channel)
+{
+ BUG_ON(gpct_index > 1);
+ return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * gpct_index);
+}
+static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
+{
+ BUG_ON(gpct_index > 1);
+ return 0xf << (4 * gpct_index);
+}
+
/* 16 bit registers */
#define AO_Window_Address_611x 0x18
#define AO_Window_Data_611x 0x1e
+/* 6143 registers */
+#define Magic_6143 0x19 /* w8 */
+#define G0G1_DMA_Select_6143 0x0B /* w8 */
+#define PipelineDelay_6143 0x1f /* w8 */
+#define EOC_Set_6143 0x1D /* w8 */
+#define AIDMA_Select_6143 0x09 /* w8 */
+#define AIFIFO_Data_6143 0x8C /* w32 */
+#define AIFIFO_Flag_6143 0x84 /* w32 */
+#define AIFIFO_Control_6143 0x88 /* w32 */
+#define AIFIFO_Status_6143 0x88 /* w32 */
+#define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
+#define AIFIFO_Words_Available_6143 0x94 /* w32 */
+
+#define Calibration_Channel_6143 0x42 /* w16 */
+#define Calibration_LowTime_6143 0x20 /* w16 */
+#define Calibration_HighTime_6143 0x22 /* w16 */
+#define Relay_Counter_Load_Val__6143 0x4C /* w32 */
+#define Signature_6143 0x50 /* w32 */
+#define Release_Date_6143 0x54 /* w32 */
+#define Release_Oldest_Date_6143 0x58 /* w32 */
+
+#define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
+#define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
+#define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
+#define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
+#define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
+#define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
+#define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
+#define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
+
/* 671x, 611x registers */
/* 671xi, 611x windowed ao registers */
but I thought I'd put it here anyway.
*/
-/* our default usage of mite channels */
-enum mite_dma_channel{
- AI_DMA_CHAN = 0,
- AO_DMA_CHAN = 1,
- GPC0_DMA_CHAN = 2,
- GPC1_DMA_CHAN = 3,
-};
-
-enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, ai_gain_628x };
+enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, ai_gain_628x, ai_gain_6143};
enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
ad8804, ad8842, ad8804_debug };
enum ni_reg_type {
ni_reg_6713 = 0x4,
ni_reg_67xx_mask = 0x6,
ni_reg_6xxx_mask = 0x7,
- ni_reg_m_series = 0x8
+ ni_reg_622x = 0x8,
+ ni_reg_625x = 0x10,
+ ni_reg_628x = 0x18,
+ ni_reg_m_series_mask = 0x18,
+ ni_reg_6143 = 0x20
};
static comedi_lrange range_ni_E_ao_ext;
{
M_Offset_CDIO_DMA_Select = 0x7, // write
M_Offset_SCXI_Status = 0x7, // read
- M_Offset_AI_AO_Select = 0x9, // write
+ M_Offset_AI_AO_Select = 0x9, // write, same offset as e-series
M_Offset_SCXI_Serial_Data_In = 0x9, // read
- M_Offset_G0_G1_Select = 0xb,
+ M_Offset_G0_G1_Select = 0xb, // write, same offset as e-series
M_Offset_Misc_Command = 0xf,
M_Offset_SCXI_Serial_Data_Out = 0x11,
M_Offset_SCXI_Control = 0x13,
M_Offset_Interrupt_B_Enable = 0x196,
M_Offset_AI_Personal = 0x19a,
M_Offset_AO_Personal = 0x19c,
+ M_Offset_RTSI_Trig_A_Output = 0x19e,
M_Offset_RTSI_Trig_B_Output = 0x1a0,
- M_Offset_RTSI_Shared_MUX = 0x1a2,
+ M_Offset_RTSI_Shared_MUX = 0x1a2,
M_Offset_AO_Output_Control = 0x1ac,
M_Offset_AI_Mode_3 = 0x1ae,
M_Offset_Configuration_Memory_Clear = 0x1a4,
M_Offset_G1_DMA_Status = 0x1ba, // read
M_Offset_G0_MSeries_ABZ = 0x1c0,
M_Offset_G1_MSeries_ABZ = 0x1c2,
- M_Offset_Clock_And_Fout2 = 0x1c4,
+ M_Offset_Clock_and_Fout2 = 0x1c4,
M_Offset_PLL_Control = 0x1c6,
M_Offset_PLL_Status = 0x1c8,
M_Offset_PFI_Output_Select_1 = 0x1d0,
}
return offset[channel];
};
+static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
+{
+ if(n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS)
+ {
+ rt_printk("%s: invalid pfi output select register=%i\n", __FUNCTION__, n);
+ return M_Offset_PFI_Output_Select_1;
+ }
+ return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
+}
+
+enum MSeries_AI_Config_FIFO_Data_Bits
+{
+ MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
+ MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
+ MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
+ MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
+ MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
+ MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
+ MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
+ MSeries_AI_Config_Polarity_Bit = 0x1000, // 0 for 2's complement encoding
+ MSeries_AI_Config_Dither_Bit = 0x2000,
+ MSeries_AI_Config_Last_Channel_Bit = 0x4000,
+};
+static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel)
+{
+ return channel & 0xf;
+}
+static inline unsigned MSeries_AI_Config_Bank_Bits(unsigned channel)
+{
+ return channel & 0x30;
+}
+static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range)
+{
+ return (range & 0x7) << 9;
+}
+
+enum MSeries_Clock_and_Fout2_Bits
+{
+ MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
+ MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
+ MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
+ MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
+ MSeries_PLL_In_Source_Select_Mask = 0x1f,
+ MSeries_Timebase1_Select_Bit = 0x20, // use PLL for timebase 1
+ MSeries_Timebase3_Select_Bit = 0x40, // use PLL for timebase 3
+ /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears
+ to have no effect, at least on pxi-6281, which always uses
+ 20MHz rtsi clock frequency */
+ MSeries_RTSI_10MHz_Bit = 0x80
+};
+static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned RTSI_channel)
+{
+ if(RTSI_channel > 7)
+ {
+ rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, RTSI_channel);
+ return 0;
+ }
+ if(RTSI_channel == 7) return MSeries_PLL_In_Source_Select_RTSI7_Bits;
+ else return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
+}
+
+enum MSeries_PLL_Control_Bits
+{
+ MSeries_PLL_Enable_Bit = 0x1000,
+ MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
+ MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
+ MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
+ MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000,
+};
+static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)
+{
+ static const unsigned max_divisor = 0x10;
+ if(divisor < 1 || divisor > max_divisor)
+ {
+ rt_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, divisor);
+ return 0;
+ }
+ return (divisor & 0xf) << 8;
+}
+static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)
+{
+ static const unsigned max_multiplier = 0x100;
+ if(multiplier < 1 || multiplier > max_multiplier)
+ {
+ rt_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, multiplier);
+ return 0;
+ }
+ return multiplier & 0xff;
+}
+
+enum MSeries_PLL_Status
+{
+ MSeries_PLL_Locked_Bit = 0x1
+};
enum MSeries_AI_Config_FIFO_Bypass_Bits
{
MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
MSeries_AI_Bypass_Dither_Bit = 0x200000,
- MSeries_AI_Bypass_Polarity_Bit = 0x400000,
+ MSeries_AI_Bypass_Polarity_Bit = 0x400000, // 0 for 2's complement encoding
MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
};
static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int calibration_source)
return count & 0xffff;
}
+static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel)
+{
+ return 0x1f << (channel % 3) * 5;
+};
+static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel, unsigned source)
+{
+ return (source & 0x1f) << ((channel % 3) * 5);
+};
+// inverse to MSeries_PFI_Output_Select_Bits
+static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel, unsigned bits)
+{
+ return (bits >> ((channel % 3) * 5)) & 0x1f;
+};
+
+enum MSeries_Gi_DMA_Config_Bits
+{
+ Gi_DMA_BankSW_Error_Bit = 0x10,
+ Gi_DMA_Reset_Bit = 0x8,
+ Gi_DMA_Int_Enable_Bit = 0x4,
+ Gi_DMA_Write_Bit = 0x2,
+ Gi_DMA_Enable_Bit = 0x1,
+};
+
+static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
+{
+ return 0x3 << (channel * 2);
+}
+static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel, unsigned filter)
+{
+ return (filter << (channel * 2)) & MSeries_PFI_Filter_Select_Mask(channel);
+}
+
#define M_SERIES_EEPROM_SIZE 1024
typedef struct ni_board_struct{
int n_aochan;
int aobits;
-
int ao_fifo_depth;
comedi_lrange *ao_range_table;
-
- int reg_type;
+ unsigned ao_speed;
+ unsigned num_p0_dio_channels;
+
+ int reg_type;
unsigned int ao_unipolar : 1;
unsigned int has_8255 : 1;
unsigned int has_analog_trig : 1;
#define boardtype (*(ni_board *)dev->board_ptr)
#define MAX_N_AO_CHAN 8
+#define NUM_GPCT 2
#define NI_PRIVATE_COMMON \
uint16_t (*stc_readw)(comedi_device *dev, int register); \
+ uint32_t (*stc_readl)(comedi_device *dev, int register); \
void (*stc_writew)(comedi_device *dev, uint16_t value, int register); \
void (*stc_writel)(comedi_device *dev, uint32_t value, int register); \
\
int blocksize; \
int n_left; \
unsigned int ai_calib_source; \
+ unsigned int ai_calib_source_enabled; \
spinlock_t window_lock; \
+ spinlock_t soft_reg_copy_lock; \
+ spinlock_t mite_channel_lock; \
\
int changain_state; \
unsigned int changain_spec; \
unsigned short ao[MAX_N_AO_CHAN]; \
unsigned short caldacs[MAX_N_CALDACS]; \
\
- volatile unsigned short ai_cmd2; \
+ unsigned short ai_cmd2; \
\
unsigned short ao_conf[MAX_N_AO_CHAN]; \
unsigned short ao_mode1; \
unsigned short ao_cmd3; \
unsigned short ao_trigger_select; \
\
- unsigned short gpct_mode[2]; \
- unsigned short gpct_command[2]; \
- unsigned short gpct_input_select[2]; \
- int gpct_cur_operation[2]; \
+ struct ni_gpct_device *counter_dev; \
unsigned short an_trig_etc_reg; \
\
unsigned ai_offset[512]; \
unsigned long serial_interval_ns; \
unsigned char serial_hw_mode; \
unsigned short clock_and_fout; \
+ unsigned short clock_and_fout2; \
\
- volatile unsigned short int_a_enable_reg; \
- volatile unsigned short int_b_enable_reg; \
+ unsigned short int_a_enable_reg; \
+ unsigned short int_b_enable_reg; \
unsigned short io_bidirection_pin_reg; \
- \
+ unsigned short rtsi_trig_direction_reg; \
+ unsigned short rtsi_trig_a_output_reg; \
+ unsigned short rtsi_trig_b_output_reg; \
+ unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
+ unsigned short ai_ao_select_reg; \
+ unsigned short g0_g1_select_reg; \
+ \
+ unsigned clock_ns; \
+ unsigned clock_source; \
+ \
unsigned short atrig_mode; \
unsigned short atrig_high; \
unsigned short atrig_low; \
- \
+ \
+ unsigned short pwm_up_count; \
+ unsigned short pwm_down_count; \
+ \
sampl_t ai_fifo_buffer[0x2000]; \
- uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE];
-
+ uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
+ \
+ struct mite_struct *mite; \
+ struct mite_channel *ai_mite_chan; \
+ struct mite_channel *ao_mite_chan;\
+ struct mite_dma_descriptor_ring *ai_mite_ring; \
+ struct mite_dma_descriptor_ring *ao_mite_ring; \
+ struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
+
+
#endif /* _COMEDI_NI_STC_H */
projects / comedi.git / blobdiff