#define Interrupt_B_Ack_Register 3
enum Interrupt_B_Ack_Bits
{
+ G1_Gate_Error_Confirm = _bit1,
+ G1_TC_Error_Confirm = _bit2,
+ AO_BC_TC_Trigger_Error_Confirm = _bit3,
+ AO_BC_TC_Error_Confirm = _bit4,
+ AO_UI2_TC_Error_Confrim = _bit5,
+ AO_UI2_TC_Interrupt_Ack = _bit6,
+ AO_UC_TC_Interrupt_Ack = _bit7,
AO_BC_TC_Interrupt_Ack = _bit8,
+ AO_START1_Interrupt_Ack = _bit9,
+ AO_UPDATE_Interrupt_Ack = _bit10,
+ AO_START_Interrupt_Ack = _bit11,
+ AO_STOP_Interrupt_Ack = _bit12,
AO_Error_Interrupt_Ack = _bit13,
+ G1_TC_Interrupt_Ack = _bit14,
+ G1_Gate_Interrupt_Ack = _bit15
};
#define AO_Status_1_Register 3
#define AO_START1_Interrupt_Enable _bit1
#define AO_BC_TC_Interrupt_Enable _bit0
+#define Second_IRQ_A_Enable_Register 74
+enum Second_IRQ_A_Enable_Bits
+{
+ AI_SC_TC_Second_Irq_Enable = _bit0,
+ AI_START1_Second_Irq_Enable = _bit1,
+ AI_START2_Second_Irq_Enable = _bit2,
+ AI_START_Second_Irq_Enable = _bit3,
+ AI_STOP_Second_Irq_Enable = _bit4,
+ AI_Error_Second_Irq_Enable = _bit5,
+ G0_TC_Second_Irq_Enable = _bit6,
+ AI_FIFO_Second_Irq_Enable = _bit7,
+ G0_Gate_Second_Irq_Enable = _bit8,
+ Pass_Thru_0_Second_Irq_Enable = _bit9
+};
+
#define Second_IRQ_B_Enable_Register 76
+enum Second_IRQ_B_Enable_Bits
+{
+ AO_BC_TC_Second_Irq_Enable = _bit0,
+ AO_START1_Second_Irq_Enable = _bit1,
+ AO_UPDATE_Second_Irq_Enable = _bit2,
+ AO_START_Second_Irq_Enable = _bit3,
+ AO_STOP_Second_Irq_Enable = _bit4,
+ AO_Error_Second_Irq_Enable = _bit5,
+ AO_UC_TC_Second_Irq_Enable = _bit6,
+ AO_UI2_TC_Second_Irq_Enable = _bit7,
+ AO_FIFO_Second_Irq_Enable = _bit8,
+ G1_TC_Second_Irq_Enable = _bit9,
+ G1_Gate_Second_Irq_Enable = _bit10,
+ Pass_Thru_1_Second_Irq_Enable = _bit11
+};
+
#define AI_Personal_Register 77
#define AI_SHIFTIN_Pulse_Width _bit15
#define AI_EOC_Polarity _bit14
#define G_Bank_Switch_Mode _bit11
#define G_Load _bit2 /* strobe */
-
/* input select register */
#define G_Gate_Select(a) (((a)&0x1f)<<7)
#define G_Source_Select(a) (((a)&0x1f)<<2)
#define G_OR_Gate _bit13
#define G_Gate_Select_Load_Source _bit12
-
/* mode register */
#define G_Loading_On_TC _bit12
#define G_Output_Mode(a) (((a)&0x03)<<8)
#define G0_Save_St _bit0
/* general purpose counter timer */
-#define G0_TC_Interrupt_Enable _bit6
-#define G1_TC_Interrupt_Enable _bit9
-#define G0_Gate_Interrupt_Enable _bit8
-#define G1_Gate_Interrupt_Enable _bit10
-#define G0_Synchronized_Gate _bit8
-#define G1_Synchronized_Gate _bit8
-#define G0_Gate_Error_Confirm _bit5
-#define G1_Gate_Error_Confirm _bit1
-#define G0_TC_Error_Confirm _bit6
-#define G1_TC_Error_Confirm _bit2
-#define G0_TC_Interrupt_Ack _bit14
-#define G1_TC_Interrupt_Ack _bit14
-#define G0_Gate_Interrupt_Ack _bit15
-#define G1_Gate_Interrupt_Ack _bit15
-#define G_Autoincrement(a) ((a)<<0)
#define G_Autoincrement(a) ((a)<<0)
-#define G0_Arm _bit0
-#define G1_Arm _bit0
/*Analog_Trigger_Etc_Register*/
#define Analog_Trigger_Mode(x) ((x) & 0x7)
BUG();
return 0;
}
+static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, unsigned mite_channel)
+{
+ BUG_ON(gpct_index > 1);
+ return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * gpct_index);
+}
+static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
+{
+ BUG_ON(gpct_index > 1);
+ return 0xf << (4 * gpct_index);
+}
+
/* 16 bit registers */
{
M_Offset_CDIO_DMA_Select = 0x7, // write
M_Offset_SCXI_Status = 0x7, // read
- M_Offset_AI_AO_Select = 0x9, // write
+ M_Offset_AI_AO_Select = 0x9, // write, same offset as e-series
M_Offset_SCXI_Serial_Data_In = 0x9, // read
- M_Offset_G0_G1_Select = 0xb,
+ M_Offset_G0_G1_Select = 0xb, // write, same offset as e-series
M_Offset_Misc_Command = 0xf,
M_Offset_SCXI_Serial_Data_Out = 0x11,
M_Offset_SCXI_Control = 0x13,
return (bits >> ((channel % 3) * 5)) & 0x1f;
};
+enum MSeries_Gi_DMA_Config_Bits
+{
+ Gi_DMA_BankSW_Error_Bit = 0x10,
+ Gi_DMA_Reset_Bit = 0x8,
+ Gi_DMA_Int_Enable_Bit = 0x4,
+ Gi_DMA_Write_Bit = 0x2,
+ Gi_DMA_Enable_Bit = 0x1,
+};
+
+static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
+{
+ return 0x3 << (channel * 2);
+}
+static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel, unsigned filter)
+{
+ return (filter << (channel * 2)) & MSeries_PFI_Filter_Select_Mask(channel);
+}
+
#define M_SERIES_EEPROM_SIZE 1024
typedef struct ni_board_struct{
int n_aochan;
int aobits;
-
int ao_fifo_depth;
comedi_lrange *ao_range_table;
+ unsigned ao_speed;
- int reg_type;
+ unsigned num_p0_dio_channels;
+ int reg_type;
unsigned int ao_unipolar : 1;
unsigned int has_8255 : 1;
unsigned int has_analog_trig : 1;
unsigned short ao_cmd3; \
unsigned short ao_trigger_select; \
\
- struct ni_gpct counters[NUM_GPCT]; \
+ struct ni_gpct_device *counter_dev; \
unsigned short an_trig_etc_reg; \
\
unsigned ai_offset[512]; \
unsigned short pwm_down_count; \
\
sampl_t ai_fifo_buffer[0x2000]; \
- uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE];
+ uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
+ \
+ struct mite_struct *mite; \
+ struct mite_channel *ai_mite_chan; \
+ struct mite_channel *ao_mite_chan;\
+ struct mite_dma_descriptor_ring *ai_mite_ring; \
+ struct mite_dma_descriptor_ring *ao_mite_ring; \
+ struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
+
#endif /* _COMEDI_NI_STC_H */
projects / comedi.git / blobdiff