3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
49 /* Registers in the National Instruments DAQ-STC chip */
51 #define Interrupt_A_Ack_Register 2
52 #define G0_Gate_Interrupt_Ack _bit15
53 #define G0_TC_Interrupt_Ack _bit14
54 #define AI_Error_Interrupt_Ack _bit13
55 #define AI_STOP_Interrupt_Ack _bit12
56 #define AI_START_Interrupt_Ack _bit11
57 #define AI_START2_Interrupt_Ack _bit10
58 #define AI_START1_Interrupt_Ack _bit9
59 #define AI_SC_TC_Interrupt_Ack _bit8
60 #define AI_SC_TC_Error_Confirm _bit7
61 #define G0_TC_Error_Confirm _bit6
62 #define G0_Gate_Error_Confirm _bit5
64 #define AI_Status_1_Register 2
65 #define Interrupt_A_St 0x8000
66 #define AI_FIFO_Full_St 0x4000
67 #define AI_FIFO_Half_Full_St 0x2000
68 #define AI_FIFO_Empty_St 0x1000
69 #define AI_Overrun_St 0x0800
70 #define AI_Overflow_St 0x0400
71 #define AI_SC_TC_Error_St 0x0200
72 #define AI_START2_St 0x0100
73 #define AI_START1_St 0x0080
74 #define AI_SC_TC_St 0x0040
75 #define AI_START_St 0x0020
76 #define AI_STOP_St 0x0010
77 #define G0_TC_St 0x0008
78 #define G0_Gate_Interrupt_St 0x0004
79 #define AI_FIFO_Request_St 0x0002
80 #define Pass_Thru_0_Interrupt_St 0x0001
82 #define AI_Status_2_Register 5
84 #define Interrupt_B_Ack_Register 3
85 enum Interrupt_B_Ack_Bits
87 AO_BC_TC_Interrupt_Ack = _bit8,
88 AO_Error_Interrupt_Ack = _bit13,
91 #define AO_Status_1_Register 3
92 #define Interrupt_B_St _bit15
93 #define AO_FIFO_Full_St _bit14
94 #define AO_FIFO_Half_Full_St _bit13
95 #define AO_FIFO_Empty_St _bit12
96 #define AO_BC_TC_Error_St _bit11
97 #define AO_START_St _bit10
98 #define AO_Overrun_St _bit9
99 #define AO_START1_St _bit8
100 #define AO_BC_TC_St _bit7
101 #define AO_UC_TC_St _bit6
102 #define AO_UPDATE_St _bit5
103 #define AO_UI2_TC_St _bit4
104 #define G1_TC_St _bit3
105 #define G1_Gate_Interrupt_St _bit2
106 #define AO_FIFO_Request_St _bit1
107 #define Pass_Thru_1_Interrupt_St _bit0
110 #define AI_Command_2_Register 4
111 #define AI_End_On_SC_TC _bit15
112 #define AI_End_On_End_Of_Scan _bit14
113 #define AI_START1_Disable _bit11
114 #define AI_SC_Save_Trace _bit10
115 #define AI_SI_Switch_Load_On_SC_TC _bit9
116 #define AI_SI_Switch_Load_On_STOP _bit8
117 #define AI_SI_Switch_Load_On_TC _bit7
118 #define AI_SC_Switch_Load_On_TC _bit4
119 #define AI_STOP_Pulse _bit3
120 #define AI_START_Pulse _bit2
121 #define AI_START2_Pulse _bit1
122 #define AI_START1_Pulse _bit0
124 #define AO_Command_2_Register 5
125 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
126 #define AO_Start_Stop_Gate_Enable _bit13
127 #define AO_UC_Save_Trace _bit12
128 #define AO_BC_Gate_Enable _bit11
129 #define AO_BC_Save_Trace _bit10
130 #define AO_UI_Switch_Load_On_BC_TC _bit9
131 #define AO_UI_Switch_Load_On_Stop _bit8
132 #define AO_UI_Switch_Load_On_TC _bit7
133 #define AO_UC_Switch_Load_On_BC_TC _bit6
134 #define AO_UC_Switch_Load_On_TC _bit5
135 #define AO_BC_Switch_Load_On_TC _bit4
136 #define AO_Mute_B _bit3
137 #define AO_Mute_A _bit2
138 #define AO_UPDATE2_Pulse _bit1
139 #define AO_START1_Pulse _bit0
141 #define AO_Status_2_Register 6
143 #define DIO_Parallel_Input_Register 7
145 #define AI_Command_1_Register 8
146 #define AI_Analog_Trigger_Reset _bit14
147 #define AI_Disarm _bit13
148 #define AI_SI2_Arm _bit12
149 #define AI_SI2_Load _bit11
150 #define AI_SI_Arm _bit10
151 #define AI_SI_Load _bit9
152 #define AI_DIV_Arm _bit8
153 #define AI_DIV_Load _bit7
154 #define AI_SC_Arm _bit6
155 #define AI_SC_Load _bit5
156 #define AI_SCAN_IN_PROG_Pulse _bit4
157 #define AI_EXTMUX_CLK_Pulse _bit3
158 #define AI_LOCALMUX_CLK_Pulse _bit2
159 #define AI_SC_TC_Pulse _bit1
160 #define AI_CONVERT_Pulse _bit0
162 #define AO_Command_1_Register 9
163 #define AO_Analog_Trigger_Reset _bit15
164 #define AO_START_Pulse _bit14
165 #define AO_Disarm _bit13
166 #define AO_UI2_Arm_Disarm _bit12
167 #define AO_UI2_Load _bit11
168 #define AO_UI_Arm _bit10
169 #define AO_UI_Load _bit9
170 #define AO_UC_Arm _bit8
171 #define AO_UC_Load _bit7
172 #define AO_BC_Arm _bit6
173 #define AO_BC_Load _bit5
174 #define AO_DAC1_Update_Mode _bit4
175 #define AO_LDAC1_Source_Select _bit3
176 #define AO_DAC0_Update_Mode _bit2
177 #define AO_LDAC0_Source_Select _bit1
178 #define AO_UPDATE_Pulse _bit0
181 #define DIO_Output_Register 10
182 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
183 #define DIO_Parallel_Data_Mask 0xff
184 #define DIO_SDOUT _bit0
185 #define DIO_SDIN _bit4
186 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
187 #define DIO_Serial_Data_Mask 0xff00
189 #define DIO_Control_Register 11
190 #define DIO_Software_Serial_Control _bit11
191 #define DIO_HW_Serial_Timebase _bit10
192 #define DIO_HW_Serial_Enable _bit9
193 #define DIO_HW_Serial_Start _bit8
194 #define DIO_Pins_Dir(a) ((a)&0xff)
195 #define DIO_Pins_Dir_Mask 0xff
197 #define AI_Mode_1_Register 12
198 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
199 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
200 #define AI_CONVERT_Source_Polarity _bit5
201 #define AI_SI_Source_Polarity _bit4
202 #define AI_Start_Stop _bit3
203 #define AI_Mode_1_Reserved _bit2
204 #define AI_Continuous _bit1
205 #define AI_Trigger_Once _bit0
207 #define AI_Mode_2_Register 13
208 #define AI_SC_Gate_Enable _bit15
209 #define AI_Start_Stop_Gate_Enable _bit14
210 #define AI_Pre_Trigger _bit13
211 #define AI_External_MUX_Present _bit12
212 #define AI_SI2_Initial_Load_Source _bit9
213 #define AI_SI2_Reload_Mode _bit8
214 #define AI_SI_Initial_Load_Source _bit7
215 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
216 #define AI_SI_Write_Switch _bit3
217 #define AI_SC_Initial_Load_Source _bit2
218 #define AI_SC_Reload_Mode _bit1
219 #define AI_SC_Write_Switch _bit0
221 #define AI_SI_Load_A_Registers 14
222 #define AI_SI_Load_B_Registers 16
223 #define AI_SC_Load_A_Registers 18
224 #define AI_SC_Load_B_Registers 20
225 #define AI_SI_Save_Registers 64
226 #define AI_SC_Save_Registers 66
228 #define AI_SI2_Load_A_Register 23
229 #define AI_SI2_Load_B_Register 25
231 #define Joint_Status_1_Register 27
232 #define DIO_Serial_IO_In_Progress_St _bit12
234 #define DIO_Serial_Input_Register 28
235 #define Joint_Status_2_Register 29
236 enum Joint_Status_2_Bits
238 AO_TMRDACWRs_In_Progress_St = 0x20,
241 #define AO_Mode_1_Register 38
242 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
243 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
244 #define AO_Multiple_Channels _bit5
245 #define AO_UPDATE_Source_Polarity _bit4
246 #define AO_UI_Source_Polarity _bit3
247 #define AO_UC_Switch_Load_Every_TC _bit2
248 #define AO_Continuous _bit1
249 #define AO_Trigger_Once _bit0
251 #define AO_Mode_2_Register 39
252 #define AO_FIFO_Mode_Mask ( 0x3 << 14 )
253 enum AO_FIFO_Mode_Bits
255 AO_FIFO_Mode_HF_to_F = (3<<14),
256 AO_FIFO_Mode_F = (2<<14),
257 AO_FIFO_Mode_HF = (1<<14),
258 AO_FIFO_Mode_E = (0<<14),
260 #define AO_FIFO_Retransmit_Enable _bit13
261 #define AO_START1_Disable _bit12
262 #define AO_UC_Initial_Load_Source _bit11
263 #define AO_UC_Write_Switch _bit10
264 #define AO_UI2_Initial_Load_Source _bit9
265 #define AO_UI2_Reload_Mode _bit8
266 #define AO_UI_Initial_Load_Source _bit7
267 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
268 #define AO_UI_Write_Switch _bit3
269 #define AO_BC_Initial_Load_Source _bit2
270 #define AO_BC_Reload_Mode _bit1
271 #define AO_BC_Write_Switch _bit0
273 #define AO_UI_Load_A_Register 40
274 #define AO_UI_Load_A_Register_High 40
275 #define AO_UI_Load_A_Register_Low 41
276 #define AO_UI_Load_B_Register 42
277 #define AO_UI_Save_Registers 16
278 #define AO_BC_Load_A_Register 44
279 #define AO_BC_Load_A_Register_High 44
280 #define AO_BC_Load_A_Register_Low 45
281 #define AO_BC_Load_B_Register 46
282 #define AO_BC_Load_B_Register_High 46
283 #define AO_BC_Load_B_Register_Low 47
284 #define AO_BC_Save_Registers 18
285 #define AO_UC_Load_A_Register 48
286 #define AO_UC_Load_A_Register_High 48
287 #define AO_UC_Load_A_Register_Low 49
288 #define AO_UC_Load_B_Register 50
289 #define AO_UC_Save_Registers 20
291 #define Clock_and_FOUT_Register 56
292 #define FOUT_Enable _bit15
293 #define FOUT_Timebase_Select _bit14
294 #define DIO_Serial_Out_Divide_By_2 _bit13
295 #define Slow_Internal_Time_Divide_By_2 _bit12
296 #define Slow_Internal_Timebase _bit11
297 #define G_Source_Divide_By_2 _bit10
298 #define Clock_To_Board_Divide_By_2 _bit9
299 #define Clock_To_Board _bit8
300 #define AI_Output_Divide_By_2 _bit7
301 #define AI_Source_Divide_By_2 _bit6
302 #define AO_Output_Divide_By_2 _bit5
303 #define AO_Source_Divide_By_2 _bit4
304 #define FOUT_Divider(x) (((x) & 0xf) << 0)
306 #define IO_Bidirection_Pin_Register 57
308 #define Interrupt_Control_Register 59
309 #define Interrupt_B_Enable _bit15
310 #define Interrupt_B_Output_Select(x) ((x)<<12)
311 #define Interrupt_A_Enable _bit11
312 #define Interrupt_A_Output_Select(x) ((x)<<8)
313 #define Pass_Thru_0_Interrupt_Polarity _bit3
314 #define Pass_Thru_1_Interrupt_Polarity _bit2
315 #define Interrupt_Output_On_3_Pins _bit1
316 #define Interrupt_Output_Polarity _bit0
318 #define AI_Output_Control_Register 60
319 #define AI_START_Output_Select _bit10
320 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
321 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
322 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
323 #define AI_SC_TC_Output_Select(x) ((x)<<2)
324 #define AI_CONVERT_Output_Select(x) (((x) & 0x3) << 0)
326 #define AI_START_STOP_Select_Register 62
327 #define AI_START_Polarity _bit15
328 #define AI_STOP_Polarity _bit14
329 #define AI_STOP_Sync _bit13
330 #define AI_STOP_Edge _bit12
331 #define AI_STOP_Select(a) (((a) & 0x1f)<<7)
332 #define AI_START_Sync _bit6
333 #define AI_START_Edge _bit5
334 #define AI_START_Select(a) ((a) & 0x1f)
336 #define AI_Trigger_Select_Register 63
337 #define AI_START1_Polarity _bit15
338 #define AI_START2_Polarity _bit14
339 #define AI_START2_Sync _bit13
340 #define AI_START2_Edge _bit12
341 #define AI_START2_Select(a) (((a) & 0x1f) << 7)
342 #define AI_START1_Sync _bit6
343 #define AI_START1_Edge _bit5
344 #define AI_START1_Select(a) ((a) & 0x1f)
346 #define AI_DIV_Load_A_Register 64
348 #define AO_Start_Select_Register 66
349 #define AO_UI2_Software_Gate _bit15
350 #define AO_UI2_External_Gate_Polarity _bit14
351 #define AO_START_Polarity _bit13
352 #define AO_AOFREQ_Enable _bit12
353 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
354 #define AO_START_Sync _bit6
355 #define AO_START_Edge _bit5
356 #define AO_START_Select(a) ((a) & 0x1f)
358 #define AO_Trigger_Select_Register 67
359 #define AO_UI2_External_Gate_Enable _bit15
360 #define AO_Delayed_START1 _bit14
361 #define AO_START1_Polarity _bit13
362 #define AO_UI2_Source_Polarity _bit12
363 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
364 #define AO_START1_Sync _bit6
365 #define AO_START1_Edge _bit5
366 #define AO_START1_Select(x) (((x)&0x1f)<<0)
368 #define AO_Mode_3_Register 70
369 #define AO_UI2_Switch_Load_Next_TC _bit13
370 #define AO_UC_Switch_Load_Every_BC_TC _bit12
371 #define AO_Trigger_Length _bit11
372 #define AO_Stop_On_Overrun_Error _bit5
373 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
374 #define AO_Stop_On_BC_TC_Error _bit3
375 #define AO_Not_An_UPDATE _bit2
376 #define AO_Software_Gate _bit1
377 #define AO_Last_Gate_Disable _bit0 /* M Series only */
379 #define Joint_Reset_Register 72
380 #define Software_Reset _bit11
381 #define AO_Configuration_End _bit9
382 #define AI_Configuration_End _bit8
383 #define AO_Configuration_Start _bit5
384 #define AI_Configuration_Start _bit4
385 #define G1_Reset _bit3
386 #define G0_Reset _bit2
387 #define AO_Reset _bit1
388 #define AI_Reset _bit0
390 #define Interrupt_A_Enable_Register 73
391 #define Pass_Thru_0_Interrupt_Enable _bit9
392 #define G0_Gate_Interrupt_Enable _bit8
393 #define AI_FIFO_Interrupt_Enable _bit7
394 #define G0_TC_Interrupt_Enable _bit6
395 #define AI_Error_Interrupt_Enable _bit5
396 #define AI_STOP_Interrupt_Enable _bit4
397 #define AI_START_Interrupt_Enable _bit3
398 #define AI_START2_Interrupt_Enable _bit2
399 #define AI_START1_Interrupt_Enable _bit1
400 #define AI_SC_TC_Interrupt_Enable _bit0
402 #define Interrupt_B_Enable_Register 75
403 #define Pass_Thru_1_Interrupt_Enable _bit11
404 #define G1_Gate_Interrupt_Enable _bit10
405 #define G1_TC_Interrupt_Enable _bit9
406 #define AO_FIFO_Interrupt_Enable _bit8
407 #define AO_UI2_TC_Interrupt_Enable _bit7
408 #define AO_UC_TC_Interrupt_Enable _bit6
409 #define AO_Error_Interrupt_Enable _bit5
410 #define AO_STOP_Interrupt_Enable _bit4
411 #define AO_START_Interrupt_Enable _bit3
412 #define AO_UPDATE_Interrupt_Enable _bit2
413 #define AO_START1_Interrupt_Enable _bit1
414 #define AO_BC_TC_Interrupt_Enable _bit0
416 #define Second_IRQ_B_Enable_Register 76
417 #define AI_Personal_Register 77
418 #define AI_SHIFTIN_Pulse_Width _bit15
419 #define AI_EOC_Polarity _bit14
420 #define AI_SOC_Polarity _bit13
421 #define AI_SHIFTIN_Polarity _bit12
422 #define AI_CONVERT_Pulse_Timebase _bit11
423 #define AI_CONVERT_Pulse_Width _bit10
424 #define AI_CONVERT_Original_Pulse _bit9
425 #define AI_FIFO_Flags_Polarity _bit8
426 #define AI_Overrun_Mode _bit7
427 #define AI_EXTMUX_CLK_Pulse_Width _bit6
428 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
429 #define AI_AIFREQ_Polarity _bit4
431 #define AO_Personal_Register 78
432 enum AO_Personal_Bits
434 AO_Interval_Buffer_Mode = 1 << 3,
435 AO_BC_Source_Select = 1 << 4,
436 AO_UPDATE_Pulse_Width = 1 << 5,
437 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
438 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
439 AO_FIFO_Enable = 1 << 10,
440 AO_TMRDACWR_Pulse_Width = 1 << 12,
442 #define Write_Strobe_0_Register 82
443 #define Write_Strobe_1_Register 83
444 #define Write_Strobe_2_Register 84
445 #define Write_Strobe_3_Register 85
447 #define AO_Output_Control_Register 86
448 #define AO_External_Gate_Enable _bit15
449 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
450 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
451 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
452 #define AO_External_Gate_Polarity _bit3
453 #define AO_UPDATE2_Output_Toggle _bit2
454 #define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
456 #define AI_Mode_3_Register 87
457 #define AI_Trigger_Length _bit15
458 #define AI_Delay_START _bit14
459 #define AI_Software_Gate _bit13
460 #define AI_SI_Special_Trigger_Delay _bit12
461 #define AI_SI2_Source_Select _bit11
462 #define AI_Delayed_START2 _bit10
463 #define AI_Delayed_START1 _bit9
464 #define AI_External_Gate_Mode _bit8
465 #define AI_FIFO_Mode_HF_to_E (3<<6)
466 #define AI_FIFO_Mode_F (2<<6)
467 #define AI_FIFO_Mode_HF (1<<6)
468 #define AI_FIFO_Mode_NE (0<<6)
469 #define AI_External_Gate_Polarity _bit5
470 #define AI_External_Gate_Select(a) ((a) & 0x1f)
472 #define G_Autoincrement_Register(a) (68+(a))
473 #define G_Command_Register(a) (6+(a))
474 #define G_HW_Save_Register(a) (8+(a)*2)
475 #define G_HW_Save_Register_High(a) (8+(a)*2)
476 #define G_HW_Save_Register_Low(a) (9+(a)*2)
477 #define G_Input_Select_Register(a) (36+(a))
478 #define G_Load_A_Register(a) (28+(a)*4)
479 #define G_Load_A_Register_High(a) (28+(a)*4)
480 #define G_Load_A_Register_Low(a) (29+(a)*4)
481 #define G_Load_B_Register(a) (30+(a)*4)
482 #define G_Load_B_Register_High(a) (30+(a)*4)
483 #define G_Load_B_Register_Low(a) (31+(a)*4)
484 #define G_Mode_Register(a) (26+(a))
485 #define G_Save_Register(a) (12+(a)*2)
486 #define G_Save_Register_High(a) (12+(a)*2)
487 #define G_Save_Register_Low(a) (13+(a)*2)
488 #define G_Status_Register 4
489 #define Analog_Trigger_Etc_Register 61
491 /* command register */
492 #define G_Disarm_Copy _bit15 /* strobe */
493 #define G_Save_Trace_Copy _bit14
494 #define G_Arm_Copy _bit13 /* strobe */
495 #define G_Bank_Switch_Start _bit10 /* strobe */
496 #define G_Little_Big_Endian _bit9
497 #define G_Synchronized_Gate _bit8
498 #define G_Write_Switch _bit7
499 #define G_Up_Down(a) (((a)&0x03)<<5)
500 #define G_Disarm _bit4 /* strobe */
501 #define G_Analog_Trigger_Reset _bit3 /* strobe */
502 #define G_Save_Trace _bit1
503 #define G_Arm _bit0 /* strobe */
505 /*channel agnostic names for the command register #defines */
506 #define G_Bank_Switch_Enable _bit12
507 #define G_Bank_Switch_Mode _bit11
508 #define G_Load _bit2 /* strobe */
511 /* input select register */
512 #define G_Gate_Select(a) (((a)&0x1f)<<7)
513 #define G_Source_Select(a) (((a)&0x1f)<<2)
514 #define G_Write_Acknowledges_Irq _bit1
515 #define G_Read_Acknowledges_Irq _bit0
517 /* same input select register, but with channel agnostic names */
518 #define G_Source_Polarity _bit15
519 #define G_Output_Polarity _bit14
520 #define G_OR_Gate _bit13
521 #define G_Gate_Select_Load_Source _bit12
525 #define G_Loading_On_TC _bit12
526 #define G_Output_Mode(a) (((a)&0x03)<<8)
527 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
528 #define G_Gating_Mode(a) (((a)&0x03)<<0)
530 /* same input mode register, but with channel agnostic names */
531 #define G_Load_Source_Select _bit7
532 #define G_Reload_Source_Switching _bit15
533 #define G_Loading_On_Gate _bit14
534 #define G_Gate_Polarity _bit13
536 #define G_Counting_Once(a) (((a)&0x03)<<10)
537 #define G_Stop_Mode(a) (((a)&0x03)<<5)
538 #define G_Gate_On_Both_Edges _bit2
540 /* G_Status_Register */
541 #define G1_Gate_Error_St _bit15
542 #define G0_Gate_Error_St _bit14
543 #define G1_TC_Error_St _bit13
544 #define G0_TC_Error_St _bit12
545 #define G1_No_Load_Between_Gates_St _bit11
546 #define G0_No_Load_Between_Gates_St _bit10
547 #define G1_Armed_St _bit9
548 #define G0_Armed_St _bit8
549 #define G1_Stale_Data_St _bit7
550 #define G0_Stale_Data_St _bit6
551 #define G1_Next_Load_Source_St _bit5
552 #define G0_Next_Load_Source_St _bit4
553 #define G1_Counting_St _bit3
554 #define G0_Counting_St _bit2
555 #define G1_Save_St _bit1
556 #define G0_Save_St _bit0
558 /* general purpose counter timer */
559 #define G0_TC_Interrupt_Enable _bit6
560 #define G1_TC_Interrupt_Enable _bit9
561 #define G0_Gate_Interrupt_Enable _bit8
562 #define G1_Gate_Interrupt_Enable _bit10
563 #define G0_Synchronized_Gate _bit8
564 #define G1_Synchronized_Gate _bit8
565 #define G0_Gate_Error_Confirm _bit5
566 #define G1_Gate_Error_Confirm _bit1
567 #define G0_TC_Error_Confirm _bit6
568 #define G1_TC_Error_Confirm _bit2
569 #define G0_TC_Interrupt_Ack _bit14
570 #define G1_TC_Interrupt_Ack _bit14
571 #define G0_Gate_Interrupt_Ack _bit15
572 #define G1_Gate_Interrupt_Ack _bit15
573 #define G_Autoincrement(a) ((a)<<0)
574 #define G_Autoincrement(a) ((a)<<0)
578 /*Analog_Trigger_Etc_Register*/
579 #define Analog_Trigger_Mode(x) ((x) & 0x7)
580 #define Analog_Trigger_Enable _bit3
581 #define Analog_Trigger_Drive _bit4
582 #define GPFO_1_Output_Select _bit7
583 #define GPFO_0_Output_Select(a) ((a)<<11)
584 #define GPFO_0_Output_Enable _bit14
585 #define GPFO_1_Output_Enable _bit15
587 /* Additional windowed registers unique to E series */
589 /* 16 bit registers shadowed from DAQ-STC */
590 #define Window_Address 0x00
591 #define Window_Data 0x02
593 #define Configuration_Memory_Clear 82
594 #define ADC_FIFO_Clear 83
595 #define DAC_FIFO_Clear 84
597 /* i/o port offsets */
599 /* 8 bit registers */
600 #define XXX_Status 0x01
604 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
606 #define Serial_Command 0x0d
607 #define Misc_Command 0x0f
611 #define Configuration 0x1f
613 #define Channel_A_Mode 0x03
614 #define Channel_B_Mode 0x05
615 #define Channel_C_Mode 0x07
616 #define AI_AO_Select 0x09
617 #define G0_G1_Select 0x0b
619 /* 16 bit registers */
621 #define Configuration_Memory_Low 0x10
622 enum Configuration_Memory_Low_Bits
625 AI_LAST_CHANNEL = 0x8000,
627 #define Configuration_Memory_High 0x12
628 enum Configuration_Memory_High_Bits
630 AI_AC_COUPLE = 0x800,
631 AI_DIFFERENTIAL = 0x1000,
635 static inline unsigned int AI_CONFIG_CHANNEL( unsigned int channel )
637 return ( channel & 0x3f );
640 #define ADC_FIFO_Data_Register 0x1c
642 #define AO_Configuration 0x16
643 #define AO_Bipolar _bit0
644 #define AO_Deglitch _bit1
645 #define AO_Ext_Ref _bit2
646 #define AO_Ground_Ref _bit3
647 #define AO_Channel(x) ((x) << 8)
649 #define DAC_FIFO_Data 0x1e
650 #define DAC0_Direct_Data 0x18
651 #define DAC1_Direct_Data 0x1a
654 /* 611x registers (these boards differ from the e-series) */
656 #define Magic_611x 0x19 /* w8 (new) */
657 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
658 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
659 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
660 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
661 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
663 #define AO_Window_Address_611x 0x18
664 #define AO_Window_Data_611x 0x1e
666 /* 671x, 611x registers */
668 /* 671xi, 611x windowed ao registers */
669 enum windowed_regs_67xx_61xx
671 AO_Immediate_671x = 0x11, /* W 16 */
672 AO_Timed_611x = 0x10, /* W 16 */
673 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
674 AO_Later_Single_Point_Updates = 0x14, /* W 16 */
675 AO_Waveform_Generation_611x = 0x15, /* W 16 */
676 AO_Misc_611x = 0x16, /* W 16 */
677 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
678 AO_Configuration_2_67xx = 0x18, /* W 16 */
679 CAL_ADC_Command_67xx = 0x19, /* W 8 */
680 CAL_ADC_Status_67xx = 0x1a, /* R 8 */
681 CAL_ADC_Data_67xx = 0x1b, /* R 16 */
682 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
683 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
685 static inline unsigned int DACx_Direct_Data_671x(int channel)
689 enum AO_Misc_611x_Bits
693 enum cs5529_configuration_bits
695 CSCFG_CAL_CONTROL_MASK = 0x7,
696 CSCFG_SELF_CAL_OFFSET = 0x1,
697 CSCFG_SELF_CAL_GAIN = 0x2,
698 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
699 CSCFG_SYSTEM_CAL_OFFSET = 0x5,
700 CSCFG_SYSTEM_CAL_GAIN = 0x6,
702 CSCFG_POWER_SAVE_SELECT = 1 << 4,
703 CSCFG_PORT_MODE = 1 << 5,
704 CSCFG_RESET_VALID = 1 << 6,
705 CSCFG_RESET = 1 << 7,
706 CSCFG_UNIPOLAR = 1 << 12,
707 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
708 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
709 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
710 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
711 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
712 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
713 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
714 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
715 CSCFG_WORD_RATE_MASK = 0x7 << 13,
716 CSCFG_LOW_POWER = 1 << 16,
718 static inline unsigned int CS5529_CONFIG_DOUT(int output)
720 return 1 << (18 + output);
722 static inline unsigned int CS5529_CONFIG_AOUT(int output)
724 return 1 << (22 + output);
726 enum cs5529_command_bits
728 CSCMD_POWER_SAVE = 0x1,
729 CSCMD_REGISTER_SELECT_MASK = 0xe,
730 CSCMD_OFFSET_REGISTER = 0x0,
731 CSCMD_GAIN_REGISTER = 0x2,
732 CSCMD_CONFIG_REGISTER = 0x4,
734 CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
735 CSCMD_SINGLE_CONVERSION = 0x40,
736 CSCMD_COMMAND = 0x80,
738 enum cs5529_status_bits
741 CSS_OSC_DETECT = 0x2, /* indicates adc error */
744 #define SerDacLd(x) (0x08<<(x))
747 This is stuff unique to the NI E series drivers,
748 but I thought I'd put it here anyway.
751 /* our default usage of mite channels */
752 enum mite_dma_channel{
759 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x };
760 enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
761 ad8804, ad8842, ad8804_debug };
767 ni_reg_67xx_mask = 0x6,
768 ni_reg_6xxx_mask = 0x7,
769 ni_reg_m_series = 0x8
772 enum m_series_register_offsets
774 M_Offset_CDIO_DMA_Select = 0x7, // write
775 M_Offset_SCXI_Status = 0x7, // read
776 M_Offset_AI_AO_Select = 0x9, // write
777 M_Offset_SCXI_Serial_Data_In = 0x9, // read
778 M_Offset_G0_G1_Select = 0xb,
779 M_Offset_Misc_Command = 0xf,
780 M_Offset_SCXI_Serial_Data_Out = 0x11,
781 M_Offset_SCXI_Control = 0x13,
782 M_Offset_SCXI_Output_Enable = 0x15,
783 M_Offset_AI_FIFO_Data = 0x1c,
784 M_Offset_Static_Digital_Output = 0x24, // write
785 M_Offset_Static_Digital_Input = 0x24, // read
786 M_Offset_DIO_Direction = 0x28,
787 M_Offset_Cal_PWM = 0x40,
788 M_Offset_AI_Config_FIFO_Data = 0x5e,
789 M_Offset_Interrupt_C_Enable = 0x88, // write
790 M_Offset_Interrupt_C_Status = 0x88, // read
791 M_Offset_Analog_Trigger_Control = 0x8c,
792 M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
793 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, // write
794 M_Offset_AO_Serial_Interrupt_Status = 0xa1, // read
795 M_Offset_AO_Calibration = 0xa3,
796 M_Offset_AO_FIFO_Data = 0xa4,
797 M_Offset_PFI_Filter = 0xb0,
798 M_Offset_RTSI_Filter = 0xb4,
799 M_Offset_SCXI_Legacy_Compatibility = 0xbc,
800 M_Offset_Interrupt_A_Ack = 0x104, // write
801 M_Offset_AI_Status_1 = 0x104, // read
802 M_Offset_Interrupt_B_Ack = 0x106, // write
803 M_Offset_AO_Status_1 = 0x106, // read
804 M_Offset_AI_Command_2 = 0x108,
805 M_Offset_AO_Command_2 = 0x10a,
806 M_Offset_AO_Status_2 = 0x10c,
807 M_Offset_AI_Command_1 = 0x110,
808 M_Offset_AO_Command_1 = 0x112,
809 M_Offset_AI_Mode_1 = 0x118,
810 M_Offset_AI_Mode_2 = 0x11a,
811 M_Offset_AI_SI_Load_A = 0x11c,
812 M_Offset_AI_SI_Load_B = 0x120, // write
813 M_Offset_AO_UI_Save = 0x120, // read
814 M_Offset_AI_SC_Load_A = 0x124, // write
815 M_Offset_AO_BC_Save = 0x124, // read
816 M_Offset_AI_SC_Load_B = 0x128, // write
817 M_Offset_AO_UC_Save = 0x128, //read
818 M_Offset_AI_SI2_Load_A = 0x12c,
819 M_Offset_AI_SI2_Load_B = 0x130,
820 M_Offset_Joint_Status_1 = 0x136,
821 M_Offset_Joint_Status_2 = 0x13a,
822 M_Offset_AO_Mode_1 = 0x14c,
823 M_Offset_AO_Mode_2 = 0x14e,
824 M_Offset_AO_UI_Load_A = 0x150,
825 M_Offset_AO_UI_Load_B = 0x154,
826 M_Offset_AO_BC_Load_A = 0x158,
827 M_Offset_AO_BC_Load_B = 0x15c,
828 M_Offset_AO_UC_Load_A = 0x160,
829 M_Offset_AO_UC_Load_B = 0x164,
830 M_Offset_Clock_and_FOUT = 0x170,
831 M_Offset_IO_Bidirection_Pin = 0x172,
832 M_Offset_RTSI_Trig_Direction = 0x174,
833 M_Offset_Interrupt_Control = 0x176,
834 M_Offset_AI_Output_Control = 0x178,
835 M_Offset_Analog_Trigger_Etc = 0x17a,
836 M_Offset_AI_START_STOP_Select = 0x17c,
837 M_Offset_AI_Trigger_Select = 0x17e,
838 M_Offset_AI_SI_Save = 0x180, // read
839 M_Offset_AI_DIV_Load_A = 0x180, // write
840 M_Offset_AI_SC_Save = 0x184, // read
841 M_Offset_AO_Start_Select = 0x184, // write
842 M_Offset_AO_Trigger_Select = 0x186,
843 M_Offset_AO_Mode_3 = 0x18c,
844 M_Offset_Joint_Reset = 0x190,
845 M_Offset_Interrupt_A_Enable = 0x192,
846 M_Offset_Interrupt_B_Enable = 0x196,
847 M_Offset_AI_Personal = 0x19a,
848 M_Offset_AO_Personal = 0x19c,
849 M_Offset_RTSI_Trig_B_Output = 0x1a0,
850 M_Offset_RTSI_Shared_MUX = 0x1a2,
851 M_Offset_AO_Output_Control = 0x1ac,
852 M_Offset_AI_Mode_3 = 0x1ae,
853 M_Offset_Configuration_Memory_Clear = 0x1a4,
854 M_Offset_AI_FIFO_Clear = 0x1a6,
855 M_Offset_AO_FIFO_Clear = 0x1a8,
856 M_Offset_G0_DMA_Config = 0x1b8, // write
857 M_Offset_G0_DMA_Status = 0x1b8, // read
858 M_Offset_G1_DMA_Config = 0x1ba, // write
859 M_Offset_G1_DMA_Status = 0x1ba, // read
860 M_Offset_Clock_And_Fout2 = 0x1c4,
861 M_Offset_PLL_Control = 0x1c6,
862 M_Offset_PLL_Status = 0x1c8,
863 M_Offset_PFI_Output_Select_1 = 0x1d0,
864 M_Offset_PFI_Output_Select_2 = 0x1d2,
865 M_Offset_PFI_Output_Select_3 = 0x1d4,
866 M_Offset_PFI_Output_Select_4 = 0x1d6,
867 M_Offset_PFI_Output_Select_5 = 0x1d8,
868 M_Offset_PFI_Output_Select_6 = 0x1da,
869 M_Offset_PFI_DI = 0x1dc,
870 M_Offset_PFI_DO = 0x1de,
871 M_Offset_AI_Config_FIFO_Bypass = 0x218,
872 M_Offset_SCXI_DIO_Enable = 0x21c,
873 M_Offset_CDI_FIFO_Data = 0x220, // read
874 M_Offset_CDO_FIFO_Data = 0x220, // write
875 M_Offset_CDIO_Status = 0x224, // read
876 M_Offset_CDIO_Command = 0x224, // write
877 M_Offset_CDI_Mode = 0x228,
878 M_Offset_CDO_Mode = 0x22c,
879 M_Offset_CDI_Mask_Enable = 0x230,
880 M_Offset_CDO_Mask_Enable = 0x234,
883 typedef struct ni_board_struct{
892 unsigned int alwaysdither : 1;
904 unsigned int ao_unipolar : 1;
905 unsigned int has_8255 : 1;
906 unsigned int has_analog_trig : 1;
908 enum caldac_enum caldac[3];
911 static ni_board ni_boards[];
912 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
914 #define boardtype (*(ni_board *)dev->board_ptr)
916 #define NI_PRIVATE_COMMON \
917 unsigned short dio_output; \
918 unsigned short dio_control; \
928 unsigned int ai_calib_source; \
929 spinlock_t window_lock; \
931 int changain_state; \
932 unsigned int changain_spec; \
934 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
935 unsigned short ao[2]; \
936 unsigned short caldacs[MAX_N_CALDACS]; \
938 volatile unsigned short ai_cmd2; \
940 unsigned short ao_conf[2]; \
941 unsigned short ao_mode1; \
942 unsigned short ao_mode2; \
943 unsigned short ao_mode3; \
944 unsigned short ao_cmd1; \
945 unsigned short ao_cmd2; \
946 unsigned short ao_cmd3; \
947 unsigned short ao_trigger_select; \
949 unsigned short gpct_mode[2]; \
950 unsigned short gpct_command[2]; \
951 unsigned short gpct_input_select[2]; \
952 int gpct_cur_operation[2]; \
953 unsigned short an_trig_etc_reg; \
955 unsigned short ai_offset[512]; \
957 unsigned long serial_interval_ns; \
958 unsigned char serial_hw_mode; \
959 unsigned short clock_and_fout; \
961 volatile unsigned short int_a_enable_reg; \
962 volatile unsigned short int_b_enable_reg; \
963 unsigned short io_bidirection_pin_reg; \
965 unsigned short atrig_mode; \
966 unsigned short atrig_high; \
967 unsigned short atrig_low; \
969 sampl_t ai_fifo_buffer[0x2000]; \
971 #endif /* _COMEDI_NI_STC_H */