3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
49 /* Registers in the National Instruments DAQ-STC chip */
51 #define Interrupt_A_Ack_Register 2
52 #define G0_Gate_Interrupt_Ack _bit15
53 #define G0_TC_Interrupt_Ack _bit14
54 #define AI_Error_Interrupt_Ack _bit13
55 #define AI_STOP_Interrupt_Ack _bit12
56 #define AI_START_Interrupt_Ack _bit11
57 #define AI_START2_Interrupt_Ack _bit10
58 #define AI_START1_Interrupt_Ack _bit9
59 #define AI_SC_TC_Interrupt_Ack _bit8
60 #define AI_SC_TC_Error_Confirm _bit7
61 #define G0_TC_Error_Confirm _bit6
62 #define G0_Gate_Error_Confirm _bit5
64 #define AI_Status_1_Register 2
65 #define Interrupt_A_St 0x8000
66 #define AI_FIFO_Full_St 0x4000
67 #define AI_FIFO_Half_Full_St 0x2000
68 #define AI_FIFO_Empty_St 0x1000
69 #define AI_Overrun_St 0x0800
70 #define AI_Overflow_St 0x0400
71 #define AI_SC_TC_Error_St 0x0200
72 #define AI_START2_St 0x0100
73 #define AI_START1_St 0x0080
74 #define AI_SC_TC_St 0x0040
75 #define AI_START_St 0x0020
76 #define AI_STOP_St 0x0010
77 #define G0_TC_St 0x0008
78 #define G0_Gate_Interrupt_St 0x0004
79 #define AI_FIFO_Request_St 0x0002
80 #define Pass_Thru_0_Interrupt_St 0x0001
82 #define AI_Status_2_Register 5
84 #define Interrupt_B_Ack_Register 3
85 enum Interrupt_B_Ack_Bits
87 AO_BC_TC_Interrupt_Ack = _bit8,
88 AO_Error_Interrupt_Ack = _bit13,
91 #define AO_Status_1_Register 3
92 #define Interrupt_B_St _bit15
93 #define AO_FIFO_Full_St _bit14
94 #define AO_FIFO_Half_Full_St _bit13
95 #define AO_FIFO_Empty_St _bit12
96 #define AO_BC_TC_Error_St _bit11
97 #define AO_START_St _bit10
98 #define AO_Overrun_St _bit9
99 #define AO_START1_St _bit8
100 #define AO_BC_TC_St _bit7
101 #define AO_UC_TC_St _bit6
102 #define AO_UPDATE_St _bit5
103 #define AO_UI2_TC_St _bit4
104 #define G1_TC_St _bit3
105 #define G1_Gate_Interrupt_St _bit2
106 #define AO_FIFO_Request_St _bit1
107 #define Pass_Thru_1_Interrupt_St _bit0
110 #define AI_Command_2_Register 4
111 #define AI_End_On_SC_TC _bit15
112 #define AI_End_On_End_Of_Scan _bit14
113 #define AI_START1_Disable _bit11
114 #define AI_SC_Save_Trace _bit10
115 #define AI_SI_Switch_Load_On_SC_TC _bit9
116 #define AI_SI_Switch_Load_On_STOP _bit8
117 #define AI_SI_Switch_Load_On_TC _bit7
118 #define AI_SC_Switch_Load_On_TC _bit4
119 #define AI_STOP_Pulse _bit3
120 #define AI_START_Pulse _bit2
121 #define AI_START2_Pulse _bit1
122 #define AI_START1_Pulse _bit0
124 #define AO_Command_2_Register 5
125 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
126 #define AO_Start_Stop_Gate_Enable _bit13
127 #define AO_UC_Save_Trace _bit12
128 #define AO_BC_Gate_Enable _bit11
129 #define AO_BC_Save_Trace _bit10
130 #define AO_UI_Switch_Load_On_BC_TC _bit9
131 #define AO_UI_Switch_Load_On_Stop _bit8
132 #define AO_UI_Switch_Load_On_TC _bit7
133 #define AO_UC_Switch_Load_On_BC_TC _bit6
134 #define AO_UC_Switch_Load_On_TC _bit5
135 #define AO_BC_Switch_Load_On_TC _bit4
136 #define AO_Mute_B _bit3
137 #define AO_Mute_A _bit2
138 #define AO_UPDATE2_Pulse _bit1
139 #define AO_START1_Pulse _bit0
141 #define AO_Status_2_Register 6
143 #define DIO_Parallel_Input_Register 7
145 #define AI_Command_1_Register 8
146 #define AI_Analog_Trigger_Reset _bit14
147 #define AI_Disarm _bit13
148 #define AI_SI2_Arm _bit12
149 #define AI_SI2_Load _bit11
150 #define AI_SI_Arm _bit10
151 #define AI_SI_Load _bit9
152 #define AI_DIV_Arm _bit8
153 #define AI_DIV_Load _bit7
154 #define AI_SC_Arm _bit6
155 #define AI_SC_Load _bit5
156 #define AI_SCAN_IN_PROG_Pulse _bit4
157 #define AI_EXTMUX_CLK_Pulse _bit3
158 #define AI_LOCALMUX_CLK_Pulse _bit2
159 #define AI_SC_TC_Pulse _bit1
160 #define AI_CONVERT_Pulse _bit0
162 #define AO_Command_1_Register 9
163 #define AO_Analog_Trigger_Reset _bit15
164 #define AO_START_Pulse _bit14
165 #define AO_Disarm _bit13
166 #define AO_UI2_Arm_Disarm _bit12
167 #define AO_UI2_Load _bit11
168 #define AO_UI_Arm _bit10
169 #define AO_UI_Load _bit9
170 #define AO_UC_Arm _bit8
171 #define AO_UC_Load _bit7
172 #define AO_BC_Arm _bit6
173 #define AO_BC_Load _bit5
174 #define AO_DAC1_Update_Mode _bit4
175 #define AO_LDAC1_Source_Select _bit3
176 #define AO_DAC0_Update_Mode _bit2
177 #define AO_LDAC0_Source_Select _bit1
178 #define AO_UPDATE_Pulse _bit0
181 #define DIO_Output_Register 10
182 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
183 #define DIO_Parallel_Data_Mask 0xff
184 #define DIO_SDOUT _bit0
185 #define DIO_SDIN _bit4
186 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
187 #define DIO_Serial_Data_Mask 0xff00
189 #define DIO_Control_Register 11
190 #define DIO_Software_Serial_Control _bit11
191 #define DIO_HW_Serial_Timebase _bit10
192 #define DIO_HW_Serial_Enable _bit9
193 #define DIO_HW_Serial_Start _bit8
194 #define DIO_Pins_Dir(a) ((a)&0xff)
195 #define DIO_Pins_Dir_Mask 0xff
197 #define AI_Mode_1_Register 12
198 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
199 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
200 #define AI_CONVERT_Source_Polarity _bit5
201 #define AI_SI_Source_Polarity _bit4
202 #define AI_Start_Stop _bit3
203 #define AI_Mode_1_Reserved _bit2
204 #define AI_Continuous _bit1
205 #define AI_Trigger_Once _bit0
207 #define AI_Mode_2_Register 13
208 #define AI_SC_Gate_Enable _bit15
209 #define AI_Start_Stop_Gate_Enable _bit14
210 #define AI_Pre_Trigger _bit13
211 #define AI_External_MUX_Present _bit12
212 #define AI_SI2_Initial_Load_Source _bit9
213 #define AI_SI2_Reload_Mode _bit8
214 #define AI_SI_Initial_Load_Source _bit7
215 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
216 #define AI_SI_Write_Switch _bit3
217 #define AI_SC_Initial_Load_Source _bit2
218 #define AI_SC_Reload_Mode _bit1
219 #define AI_SC_Write_Switch _bit0
221 #define AI_SI_Load_A_Registers 14
222 #define AI_SI_Load_B_Registers 16
223 #define AI_SC_Load_A_Registers 18
224 #define AI_SC_Load_B_Registers 20
225 #define AI_SI_Save_Registers 64
226 #define AI_SC_Save_Registers 66
228 #define AI_SI2_Load_A_Register 23
229 #define AI_SI2_Load_B_Register 25
231 #define Joint_Status_1_Register 27
232 #define DIO_Serial_IO_In_Progress_St _bit12
234 #define DIO_Serial_Input_Register 28
235 #define Joint_Status_2_Register 29
236 enum Joint_Status_2_Bits
238 AO_TMRDACWRs_In_Progress_St = 0x20,
241 #define AO_Mode_1_Register 38
242 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
243 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
244 #define AO_Multiple_Channels _bit5
245 #define AO_UPDATE_Source_Polarity _bit4
246 #define AO_UI_Source_Polarity _bit3
247 #define AO_UC_Switch_Load_Every_TC _bit2
248 #define AO_Continuous _bit1
249 #define AO_Trigger_Once _bit0
251 #define AO_Mode_2_Register 39
252 #define AO_FIFO_Mode_Mask ( 0x3 << 14 )
253 enum AO_FIFO_Mode_Bits
255 AO_FIFO_Mode_HF_to_F = (3<<14),
256 AO_FIFO_Mode_F = (2<<14),
257 AO_FIFO_Mode_HF = (1<<14),
258 AO_FIFO_Mode_E = (0<<14),
260 #define AO_FIFO_Retransmit_Enable _bit13
261 #define AO_START1_Disable _bit12
262 #define AO_UC_Initial_Load_Source _bit11
263 #define AO_UC_Write_Switch _bit10
264 #define AO_UI2_Initial_Load_Source _bit9
265 #define AO_UI2_Reload_Mode _bit8
266 #define AO_UI_Initial_Load_Source _bit7
267 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
268 #define AO_UI_Write_Switch _bit3
269 #define AO_BC_Initial_Load_Source _bit2
270 #define AO_BC_Reload_Mode _bit1
271 #define AO_BC_Write_Switch _bit0
273 #define AO_UI_Load_A_Register 40
274 #define AO_UI_Load_A_Register_High 40
275 #define AO_UI_Load_A_Register_Low 41
276 #define AO_UI_Load_B_Register 42
277 #define AO_UI_Save_Registers 16
278 #define AO_BC_Load_A_Register 44
279 #define AO_BC_Load_A_Register_High 44
280 #define AO_BC_Load_A_Register_Low 45
281 #define AO_BC_Load_B_Register 46
282 #define AO_BC_Load_B_Register_High 46
283 #define AO_BC_Load_B_Register_Low 47
284 #define AO_BC_Save_Registers 18
285 #define AO_UC_Load_A_Register 48
286 #define AO_UC_Load_A_Register_High 48
287 #define AO_UC_Load_A_Register_Low 49
288 #define AO_UC_Load_B_Register 50
289 #define AO_UC_Save_Registers 20
291 #define Clock_and_FOUT_Register 56
292 #define FOUT_Enable _bit15
293 #define FOUT_Timebase_Select _bit14
294 #define DIO_Serial_Out_Divide_By_2 _bit13
295 #define Slow_Internal_Time_Divide_By_2 _bit12
296 #define Slow_Internal_Timebase _bit11
297 #define G_Source_Divide_By_2 _bit10
298 #define Clock_To_Board_Divide_By_2 _bit9
299 #define Clock_To_Board _bit8
300 #define AI_Output_Divide_By_2 _bit7
301 #define AI_Source_Divide_By_2 _bit6
302 #define AO_Output_Divide_By_2 _bit5
303 #define AO_Source_Divide_By_2 _bit4
304 #define FOUT_Divider(x) (((x) & 0xf) << 0)
306 #define IO_Bidirection_Pin_Register 57
307 #define RTSI_Trig_Direction_Register 58
309 #define Interrupt_Control_Register 59
310 #define Interrupt_B_Enable _bit15
311 #define Interrupt_B_Output_Select(x) ((x)<<12)
312 #define Interrupt_A_Enable _bit11
313 #define Interrupt_A_Output_Select(x) ((x)<<8)
314 #define Pass_Thru_0_Interrupt_Polarity _bit3
315 #define Pass_Thru_1_Interrupt_Polarity _bit2
316 #define Interrupt_Output_On_3_Pins _bit1
317 #define Interrupt_Output_Polarity _bit0
319 #define AI_Output_Control_Register 60
320 #define AI_START_Output_Select _bit10
321 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
322 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
323 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
324 #define AI_SC_TC_Output_Select(x) ((x)<<2)
325 #define AI_CONVERT_Output_Select(x) (((x) & 0x3) << 0)
327 #define AI_START_STOP_Select_Register 62
328 #define AI_START_Polarity _bit15
329 #define AI_STOP_Polarity _bit14
330 #define AI_STOP_Sync _bit13
331 #define AI_STOP_Edge _bit12
332 #define AI_STOP_Select(a) (((a) & 0x1f)<<7)
333 #define AI_START_Sync _bit6
334 #define AI_START_Edge _bit5
335 #define AI_START_Select(a) ((a) & 0x1f)
337 #define AI_Trigger_Select_Register 63
338 #define AI_START1_Polarity _bit15
339 #define AI_START2_Polarity _bit14
340 #define AI_START2_Sync _bit13
341 #define AI_START2_Edge _bit12
342 #define AI_START2_Select(a) (((a) & 0x1f) << 7)
343 #define AI_START1_Sync _bit6
344 #define AI_START1_Edge _bit5
345 #define AI_START1_Select(a) ((a) & 0x1f)
347 #define AI_DIV_Load_A_Register 64
349 #define AO_Start_Select_Register 66
350 #define AO_UI2_Software_Gate _bit15
351 #define AO_UI2_External_Gate_Polarity _bit14
352 #define AO_START_Polarity _bit13
353 #define AO_AOFREQ_Enable _bit12
354 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
355 #define AO_START_Sync _bit6
356 #define AO_START_Edge _bit5
357 #define AO_START_Select(a) ((a) & 0x1f)
359 #define AO_Trigger_Select_Register 67
360 #define AO_UI2_External_Gate_Enable _bit15
361 #define AO_Delayed_START1 _bit14
362 #define AO_START1_Polarity _bit13
363 #define AO_UI2_Source_Polarity _bit12
364 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
365 #define AO_START1_Sync _bit6
366 #define AO_START1_Edge _bit5
367 #define AO_START1_Select(x) (((x)&0x1f)<<0)
369 #define AO_Mode_3_Register 70
370 #define AO_UI2_Switch_Load_Next_TC _bit13
371 #define AO_UC_Switch_Load_Every_BC_TC _bit12
372 #define AO_Trigger_Length _bit11
373 #define AO_Stop_On_Overrun_Error _bit5
374 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
375 #define AO_Stop_On_BC_TC_Error _bit3
376 #define AO_Not_An_UPDATE _bit2
377 #define AO_Software_Gate _bit1
378 #define AO_Last_Gate_Disable _bit0 /* M Series only */
380 #define Joint_Reset_Register 72
381 #define Software_Reset _bit11
382 #define AO_Configuration_End _bit9
383 #define AI_Configuration_End _bit8
384 #define AO_Configuration_Start _bit5
385 #define AI_Configuration_Start _bit4
386 #define G1_Reset _bit3
387 #define G0_Reset _bit2
388 #define AO_Reset _bit1
389 #define AI_Reset _bit0
391 #define Interrupt_A_Enable_Register 73
392 #define Pass_Thru_0_Interrupt_Enable _bit9
393 #define G0_Gate_Interrupt_Enable _bit8
394 #define AI_FIFO_Interrupt_Enable _bit7
395 #define G0_TC_Interrupt_Enable _bit6
396 #define AI_Error_Interrupt_Enable _bit5
397 #define AI_STOP_Interrupt_Enable _bit4
398 #define AI_START_Interrupt_Enable _bit3
399 #define AI_START2_Interrupt_Enable _bit2
400 #define AI_START1_Interrupt_Enable _bit1
401 #define AI_SC_TC_Interrupt_Enable _bit0
403 #define Interrupt_B_Enable_Register 75
404 #define Pass_Thru_1_Interrupt_Enable _bit11
405 #define G1_Gate_Interrupt_Enable _bit10
406 #define G1_TC_Interrupt_Enable _bit9
407 #define AO_FIFO_Interrupt_Enable _bit8
408 #define AO_UI2_TC_Interrupt_Enable _bit7
409 #define AO_UC_TC_Interrupt_Enable _bit6
410 #define AO_Error_Interrupt_Enable _bit5
411 #define AO_STOP_Interrupt_Enable _bit4
412 #define AO_START_Interrupt_Enable _bit3
413 #define AO_UPDATE_Interrupt_Enable _bit2
414 #define AO_START1_Interrupt_Enable _bit1
415 #define AO_BC_TC_Interrupt_Enable _bit0
417 #define Second_IRQ_B_Enable_Register 76
418 #define AI_Personal_Register 77
419 #define AI_SHIFTIN_Pulse_Width _bit15
420 #define AI_EOC_Polarity _bit14
421 #define AI_SOC_Polarity _bit13
422 #define AI_SHIFTIN_Polarity _bit12
423 #define AI_CONVERT_Pulse_Timebase _bit11
424 #define AI_CONVERT_Pulse_Width _bit10
425 #define AI_CONVERT_Original_Pulse _bit9
426 #define AI_FIFO_Flags_Polarity _bit8
427 #define AI_Overrun_Mode _bit7
428 #define AI_EXTMUX_CLK_Pulse_Width _bit6
429 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
430 #define AI_AIFREQ_Polarity _bit4
432 #define AO_Personal_Register 78
433 enum AO_Personal_Bits
435 AO_Interval_Buffer_Mode = 1 << 3,
436 AO_BC_Source_Select = 1 << 4,
437 AO_UPDATE_Pulse_Width = 1 << 5,
438 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
439 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
440 AO_FIFO_Enable = 1 << 10,
441 AO_TMRDACWR_Pulse_Width = 1 << 12,
442 AO_Number_Of_DAC_Packages = 1 << 14, // 1 for "single" mode, 0 for "dual"
444 #define RTSI_Trig_A_Output_Register 79
445 #define RTSI_Trig_B_Output_Register 80
446 #define RTSI_Board_Register 81
447 #define Write_Strobe_0_Register 82
448 #define Write_Strobe_1_Register 83
449 #define Write_Strobe_2_Register 84
450 #define Write_Strobe_3_Register 85
452 #define AO_Output_Control_Register 86
453 #define AO_External_Gate_Enable _bit15
454 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
455 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
456 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
457 #define AO_External_Gate_Polarity _bit3
458 #define AO_UPDATE2_Output_Toggle _bit2
459 #define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
461 #define AI_Mode_3_Register 87
462 #define AI_Trigger_Length _bit15
463 #define AI_Delay_START _bit14
464 #define AI_Software_Gate _bit13
465 #define AI_SI_Special_Trigger_Delay _bit12
466 #define AI_SI2_Source_Select _bit11
467 #define AI_Delayed_START2 _bit10
468 #define AI_Delayed_START1 _bit9
469 #define AI_External_Gate_Mode _bit8
470 #define AI_FIFO_Mode_HF_to_E (3<<6)
471 #define AI_FIFO_Mode_F (2<<6)
472 #define AI_FIFO_Mode_HF (1<<6)
473 #define AI_FIFO_Mode_NE (0<<6)
474 #define AI_External_Gate_Polarity _bit5
475 #define AI_External_Gate_Select(a) ((a) & 0x1f)
477 #define G_Autoincrement_Register(a) (68+(a))
478 #define G_Command_Register(a) (6+(a))
479 #define G_HW_Save_Register(a) (8+(a)*2)
480 #define G_HW_Save_Register_High(a) (8+(a)*2)
481 #define G_HW_Save_Register_Low(a) (9+(a)*2)
482 #define G_Input_Select_Register(a) (36+(a))
483 #define G_Load_A_Register(a) (28+(a)*4)
484 #define G_Load_A_Register_High(a) (28+(a)*4)
485 #define G_Load_A_Register_Low(a) (29+(a)*4)
486 #define G_Load_B_Register(a) (30+(a)*4)
487 #define G_Load_B_Register_High(a) (30+(a)*4)
488 #define G_Load_B_Register_Low(a) (31+(a)*4)
489 #define G_Mode_Register(a) (26+(a))
490 #define G_Save_Register(a) (12+(a)*2)
491 #define G_Save_Register_High(a) (12+(a)*2)
492 #define G_Save_Register_Low(a) (13+(a)*2)
493 #define G_Status_Register 4
494 #define Analog_Trigger_Etc_Register 61
496 /* command register */
497 #define G_Disarm_Copy _bit15 /* strobe */
498 #define G_Save_Trace_Copy _bit14
499 #define G_Arm_Copy _bit13 /* strobe */
500 #define G_Bank_Switch_Start _bit10 /* strobe */
501 #define G_Little_Big_Endian _bit9
502 #define G_Synchronized_Gate _bit8
503 #define G_Write_Switch _bit7
504 #define G_Up_Down(a) (((a)&0x03)<<5)
505 #define G_Disarm _bit4 /* strobe */
506 #define G_Analog_Trigger_Reset _bit3 /* strobe */
507 #define G_Save_Trace _bit1
508 #define G_Arm _bit0 /* strobe */
510 /*channel agnostic names for the command register #defines */
511 #define G_Bank_Switch_Enable _bit12
512 #define G_Bank_Switch_Mode _bit11
513 #define G_Load _bit2 /* strobe */
516 /* input select register */
517 #define G_Gate_Select(a) (((a)&0x1f)<<7)
518 #define G_Source_Select(a) (((a)&0x1f)<<2)
519 #define G_Write_Acknowledges_Irq _bit1
520 #define G_Read_Acknowledges_Irq _bit0
522 /* same input select register, but with channel agnostic names */
523 #define G_Source_Polarity _bit15
524 #define G_Output_Polarity _bit14
525 #define G_OR_Gate _bit13
526 #define G_Gate_Select_Load_Source _bit12
530 #define G_Loading_On_TC _bit12
531 #define G_Output_Mode(a) (((a)&0x03)<<8)
532 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
533 #define G_Gating_Mode(a) (((a)&0x03)<<0)
535 /* same input mode register, but with channel agnostic names */
536 #define G_Load_Source_Select _bit7
537 #define G_Reload_Source_Switching _bit15
538 #define G_Loading_On_Gate _bit14
539 #define G_Gate_Polarity _bit13
541 #define G_Counting_Once(a) (((a)&0x03)<<10)
542 #define G_Stop_Mode(a) (((a)&0x03)<<5)
543 #define G_Gate_On_Both_Edges _bit2
545 /* G_Status_Register */
546 #define G1_Gate_Error_St _bit15
547 #define G0_Gate_Error_St _bit14
548 #define G1_TC_Error_St _bit13
549 #define G0_TC_Error_St _bit12
550 #define G1_No_Load_Between_Gates_St _bit11
551 #define G0_No_Load_Between_Gates_St _bit10
552 #define G1_Armed_St _bit9
553 #define G0_Armed_St _bit8
554 #define G1_Stale_Data_St _bit7
555 #define G0_Stale_Data_St _bit6
556 #define G1_Next_Load_Source_St _bit5
557 #define G0_Next_Load_Source_St _bit4
558 #define G1_Counting_St _bit3
559 #define G0_Counting_St _bit2
560 #define G1_Save_St _bit1
561 #define G0_Save_St _bit0
563 /* general purpose counter timer */
564 #define G0_TC_Interrupt_Enable _bit6
565 #define G1_TC_Interrupt_Enable _bit9
566 #define G0_Gate_Interrupt_Enable _bit8
567 #define G1_Gate_Interrupt_Enable _bit10
568 #define G0_Synchronized_Gate _bit8
569 #define G1_Synchronized_Gate _bit8
570 #define G0_Gate_Error_Confirm _bit5
571 #define G1_Gate_Error_Confirm _bit1
572 #define G0_TC_Error_Confirm _bit6
573 #define G1_TC_Error_Confirm _bit2
574 #define G0_TC_Interrupt_Ack _bit14
575 #define G1_TC_Interrupt_Ack _bit14
576 #define G0_Gate_Interrupt_Ack _bit15
577 #define G1_Gate_Interrupt_Ack _bit15
578 #define G_Autoincrement(a) ((a)<<0)
579 #define G_Autoincrement(a) ((a)<<0)
583 /*Analog_Trigger_Etc_Register*/
584 #define Analog_Trigger_Mode(x) ((x) & 0x7)
585 #define Analog_Trigger_Enable _bit3
586 #define Analog_Trigger_Drive _bit4
587 #define GPFO_1_Output_Select _bit7
588 #define GPFO_0_Output_Select(a) ((a)<<11)
589 #define GPFO_0_Output_Enable _bit14
590 #define GPFO_1_Output_Enable _bit15
592 /* Additional windowed registers unique to E series */
594 /* 16 bit registers shadowed from DAQ-STC */
595 #define Window_Address 0x00
596 #define Window_Data 0x02
598 #define Configuration_Memory_Clear 82
599 #define ADC_FIFO_Clear 83
600 #define DAC_FIFO_Clear 84
602 /* i/o port offsets */
604 /* 8 bit registers */
605 #define XXX_Status 0x01
609 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
611 #define Serial_Command 0x0d
612 #define Misc_Command 0x0f
616 #define Configuration 0x1f
618 #define Channel_A_Mode 0x03
619 #define Channel_B_Mode 0x05
620 #define Channel_C_Mode 0x07
621 #define AI_AO_Select 0x09
622 #define G0_G1_Select 0x0b
624 /* 16 bit registers */
626 #define Configuration_Memory_Low 0x10
627 enum Configuration_Memory_Low_Bits
630 AI_LAST_CHANNEL = 0x8000,
632 #define Configuration_Memory_High 0x12
633 enum Configuration_Memory_High_Bits
635 AI_AC_COUPLE = 0x800,
636 AI_DIFFERENTIAL = 0x1000,
640 static inline unsigned int AI_CONFIG_CHANNEL( unsigned int channel )
642 return ( channel & 0x3f );
645 #define ADC_FIFO_Data_Register 0x1c
647 #define AO_Configuration 0x16
648 #define AO_Bipolar _bit0
649 #define AO_Deglitch _bit1
650 #define AO_Ext_Ref _bit2
651 #define AO_Ground_Ref _bit3
652 #define AO_Channel(x) ((x) << 8)
654 #define DAC_FIFO_Data 0x1e
655 #define DAC0_Direct_Data 0x18
656 #define DAC1_Direct_Data 0x1a
659 /* 611x registers (these boards differ from the e-series) */
661 #define Magic_611x 0x19 /* w8 (new) */
662 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
663 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
664 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
665 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
666 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
668 #define AO_Window_Address_611x 0x18
669 #define AO_Window_Data_611x 0x1e
672 #define Magic_6143 0x19 /* w8 */
673 #define G0G1_DMA_Select_6143 0x0B /* w8 */
674 #define PipelineDelay_6143 0x1f /* w8 */
675 #define EOC_Set_6143 0x1D /* w8 */
676 #define AIDMA_Select_6143 0x09 /* w8 */
677 #define AIFIFO_Data_6143 0x8C /* w32 */
678 #define AIFIFO_Flag_6143 0x84 /* w32 */
679 #define AIFIFO_Control_6143 0x88 /* w32 */
680 #define AIFIFO_Status_6143 0x88 /* w32 */
681 #define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
682 #define AIFIFO_Words_Available_6143 0x94 /* w32 */
684 #define Calibration_Channel_6143 0x42 /* w16 */
685 #define Calibration_LowTime_6143 0x20 /* w16 */
686 #define Calibration_HighTime_6143 0x22 /* w16 */
687 #define Relay_Counter_Load_Val__6143 0x4C /* w32 */
688 #define Signature_6143 0x50 /* w32 */
689 #define Release_Date_6143 0x54 /* w32 */
690 #define Release_Oldest_Date_6143 0x58 /* w32 */
692 #define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
693 #define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
694 #define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
695 #define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
696 #define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
697 #define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
698 #define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
699 #define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
701 /* 671x, 611x registers */
703 /* 671xi, 611x windowed ao registers */
704 enum windowed_regs_67xx_61xx
706 AO_Immediate_671x = 0x11, /* W 16 */
707 AO_Timed_611x = 0x10, /* W 16 */
708 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
709 AO_Later_Single_Point_Updates = 0x14, /* W 16 */
710 AO_Waveform_Generation_611x = 0x15, /* W 16 */
711 AO_Misc_611x = 0x16, /* W 16 */
712 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
713 AO_Configuration_2_67xx = 0x18, /* W 16 */
714 CAL_ADC_Command_67xx = 0x19, /* W 8 */
715 CAL_ADC_Status_67xx = 0x1a, /* R 8 */
716 CAL_ADC_Data_67xx = 0x1b, /* R 16 */
717 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
718 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
720 static inline unsigned int DACx_Direct_Data_671x(int channel)
724 enum AO_Misc_611x_Bits
728 enum cs5529_configuration_bits
730 CSCFG_CAL_CONTROL_MASK = 0x7,
731 CSCFG_SELF_CAL_OFFSET = 0x1,
732 CSCFG_SELF_CAL_GAIN = 0x2,
733 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
734 CSCFG_SYSTEM_CAL_OFFSET = 0x5,
735 CSCFG_SYSTEM_CAL_GAIN = 0x6,
737 CSCFG_POWER_SAVE_SELECT = 1 << 4,
738 CSCFG_PORT_MODE = 1 << 5,
739 CSCFG_RESET_VALID = 1 << 6,
740 CSCFG_RESET = 1 << 7,
741 CSCFG_UNIPOLAR = 1 << 12,
742 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
743 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
744 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
745 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
746 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
747 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
748 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
749 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
750 CSCFG_WORD_RATE_MASK = 0x7 << 13,
751 CSCFG_LOW_POWER = 1 << 16,
753 static inline unsigned int CS5529_CONFIG_DOUT(int output)
755 return 1 << (18 + output);
757 static inline unsigned int CS5529_CONFIG_AOUT(int output)
759 return 1 << (22 + output);
761 enum cs5529_command_bits
763 CSCMD_POWER_SAVE = 0x1,
764 CSCMD_REGISTER_SELECT_MASK = 0xe,
765 CSCMD_OFFSET_REGISTER = 0x0,
766 CSCMD_GAIN_REGISTER = 0x2,
767 CSCMD_CONFIG_REGISTER = 0x4,
769 CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
770 CSCMD_SINGLE_CONVERSION = 0x40,
771 CSCMD_COMMAND = 0x80,
773 enum cs5529_status_bits
776 CSS_OSC_DETECT = 0x2, /* indicates adc error */
779 #define SerDacLd(x) (0x08<<(x))
782 This is stuff unique to the NI E series drivers,
783 but I thought I'd put it here anyway.
786 /* our default usage of mite channels */
787 enum mite_dma_channel{
794 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, ai_gain_628x, ai_gain_6143};
795 enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
796 ad8804, ad8842, ad8804_debug };
802 ni_reg_67xx_mask = 0x6,
803 ni_reg_6xxx_mask = 0x7,
804 ni_reg_m_series = 0x8,
808 static comedi_lrange range_ni_E_ao_ext;
810 enum m_series_register_offsets
812 M_Offset_CDIO_DMA_Select = 0x7, // write
813 M_Offset_SCXI_Status = 0x7, // read
814 M_Offset_AI_AO_Select = 0x9, // write
815 M_Offset_SCXI_Serial_Data_In = 0x9, // read
816 M_Offset_G0_G1_Select = 0xb,
817 M_Offset_Misc_Command = 0xf,
818 M_Offset_SCXI_Serial_Data_Out = 0x11,
819 M_Offset_SCXI_Control = 0x13,
820 M_Offset_SCXI_Output_Enable = 0x15,
821 M_Offset_AI_FIFO_Data = 0x1c,
822 M_Offset_Static_Digital_Output = 0x24, // write
823 M_Offset_Static_Digital_Input = 0x24, // read
824 M_Offset_DIO_Direction = 0x28,
825 M_Offset_Cal_PWM = 0x40,
826 M_Offset_AI_Config_FIFO_Data = 0x5e,
827 M_Offset_Interrupt_C_Enable = 0x88, // write
828 M_Offset_Interrupt_C_Status = 0x88, // read
829 M_Offset_Analog_Trigger_Control = 0x8c,
830 M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
831 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, // write
832 M_Offset_AO_Serial_Interrupt_Status = 0xa1, // read
833 M_Offset_AO_Calibration = 0xa3,
834 M_Offset_AO_FIFO_Data = 0xa4,
835 M_Offset_PFI_Filter = 0xb0,
836 M_Offset_RTSI_Filter = 0xb4,
837 M_Offset_SCXI_Legacy_Compatibility = 0xbc,
838 M_Offset_Interrupt_A_Ack = 0x104, // write
839 M_Offset_AI_Status_1 = 0x104, // read
840 M_Offset_Interrupt_B_Ack = 0x106, // write
841 M_Offset_AO_Status_1 = 0x106, // read
842 M_Offset_AI_Command_2 = 0x108, // write
843 M_Offset_G01_Status = 0x108, // read
844 M_Offset_AO_Command_2 = 0x10a,
845 M_Offset_AO_Status_2 = 0x10c, // read
846 M_Offset_G0_Command = 0x10c, // write
847 M_Offset_G1_Command = 0x10e, // write
848 M_Offset_G0_HW_Save = 0x110,
849 M_Offset_G0_HW_Save_High = 0x110,
850 M_Offset_AI_Command_1 = 0x110,
851 M_Offset_G0_HW_Save_Low = 0x112,
852 M_Offset_AO_Command_1 = 0x112,
853 M_Offset_G1_HW_Save = 0x114,
854 M_Offset_G1_HW_Save_High = 0x114,
855 M_Offset_G1_HW_Save_Low = 0x116,
856 M_Offset_AI_Mode_1 = 0x118,
857 M_Offset_G0_Save = 0x118,
858 M_Offset_G0_Save_High = 0x118,
859 M_Offset_AI_Mode_2 = 0x11a,
860 M_Offset_G0_Save_Low = 0x11a,
861 M_Offset_AI_SI_Load_A = 0x11c,
862 M_Offset_G1_Save = 0x11c,
863 M_Offset_G1_Save_High = 0x11c,
864 M_Offset_G1_Save_Low = 0x11e,
865 M_Offset_AI_SI_Load_B = 0x120, // write
866 M_Offset_AO_UI_Save = 0x120, // read
867 M_Offset_AI_SC_Load_A = 0x124, // write
868 M_Offset_AO_BC_Save = 0x124, // read
869 M_Offset_AI_SC_Load_B = 0x128, // write
870 M_Offset_AO_UC_Save = 0x128, //read
871 M_Offset_AI_SI2_Load_A = 0x12c,
872 M_Offset_AI_SI2_Load_B = 0x130,
873 M_Offset_G0_Mode = 0x134,
874 M_Offset_G1_Mode = 0x136, // write
875 M_Offset_Joint_Status_1 = 0x136, // read
876 M_Offset_G0_Load_A = 0x138,
877 M_Offset_Joint_Status_2 = 0x13a,
878 M_Offset_G0_Load_B = 0x13c,
879 M_Offset_G1_Load_A = 0x140,
880 M_Offset_G1_Load_B = 0x144,
881 M_Offset_G0_Input_Select = 0x148,
882 M_Offset_G1_Input_Select = 0x14a,
883 M_Offset_AO_Mode_1 = 0x14c,
884 M_Offset_AO_Mode_2 = 0x14e,
885 M_Offset_AO_UI_Load_A = 0x150,
886 M_Offset_AO_UI_Load_B = 0x154,
887 M_Offset_AO_BC_Load_A = 0x158,
888 M_Offset_AO_BC_Load_B = 0x15c,
889 M_Offset_AO_UC_Load_A = 0x160,
890 M_Offset_AO_UC_Load_B = 0x164,
891 M_Offset_Clock_and_FOUT = 0x170,
892 M_Offset_IO_Bidirection_Pin = 0x172,
893 M_Offset_RTSI_Trig_Direction = 0x174,
894 M_Offset_Interrupt_Control = 0x176,
895 M_Offset_AI_Output_Control = 0x178,
896 M_Offset_Analog_Trigger_Etc = 0x17a,
897 M_Offset_AI_START_STOP_Select = 0x17c,
898 M_Offset_AI_Trigger_Select = 0x17e,
899 M_Offset_AI_SI_Save = 0x180, // read
900 M_Offset_AI_DIV_Load_A = 0x180, // write
901 M_Offset_AI_SC_Save = 0x184, // read
902 M_Offset_AO_Start_Select = 0x184, // write
903 M_Offset_AO_Trigger_Select = 0x186,
904 M_Offset_AO_Mode_3 = 0x18c,
905 M_Offset_G0_Autoincrement = 0x188,
906 M_Offset_G1_Autoincrement = 0x18a,
907 M_Offset_Joint_Reset = 0x190,
908 M_Offset_Interrupt_A_Enable = 0x192,
909 M_Offset_Interrupt_B_Enable = 0x196,
910 M_Offset_AI_Personal = 0x19a,
911 M_Offset_AO_Personal = 0x19c,
912 M_Offset_RTSI_Trig_B_Output = 0x1a0,
913 M_Offset_RTSI_Shared_MUX = 0x1a2,
914 M_Offset_AO_Output_Control = 0x1ac,
915 M_Offset_AI_Mode_3 = 0x1ae,
916 M_Offset_Configuration_Memory_Clear = 0x1a4,
917 M_Offset_AI_FIFO_Clear = 0x1a6,
918 M_Offset_AO_FIFO_Clear = 0x1a8,
919 M_Offset_G0_Counting_Mode = 0x1b0,
920 M_Offset_G1_Counting_Mode = 0x1b2,
921 M_Offset_G0_Second_Gate = 0x1b4,
922 M_Offset_G1_Second_Gate = 0x1b6,
923 M_Offset_G0_DMA_Config = 0x1b8, // write
924 M_Offset_G0_DMA_Status = 0x1b8, // read
925 M_Offset_G1_DMA_Config = 0x1ba, // write
926 M_Offset_G1_DMA_Status = 0x1ba, // read
927 M_Offset_G0_MSeries_ABZ = 0x1c0,
928 M_Offset_G1_MSeries_ABZ = 0x1c2,
929 M_Offset_Clock_and_Fout2 = 0x1c4,
930 M_Offset_PLL_Control = 0x1c6,
931 M_Offset_PLL_Status = 0x1c8,
932 M_Offset_PFI_Output_Select_1 = 0x1d0,
933 M_Offset_PFI_Output_Select_2 = 0x1d2,
934 M_Offset_PFI_Output_Select_3 = 0x1d4,
935 M_Offset_PFI_Output_Select_4 = 0x1d6,
936 M_Offset_PFI_Output_Select_5 = 0x1d8,
937 M_Offset_PFI_Output_Select_6 = 0x1da,
938 M_Offset_PFI_DI = 0x1dc,
939 M_Offset_PFI_DO = 0x1de,
940 M_Offset_AI_Config_FIFO_Bypass = 0x218,
941 M_Offset_SCXI_DIO_Enable = 0x21c,
942 M_Offset_CDI_FIFO_Data = 0x220, // read
943 M_Offset_CDO_FIFO_Data = 0x220, // write
944 M_Offset_CDIO_Status = 0x224, // read
945 M_Offset_CDIO_Command = 0x224, // write
946 M_Offset_CDI_Mode = 0x228,
947 M_Offset_CDO_Mode = 0x22c,
948 M_Offset_CDI_Mask_Enable = 0x230,
949 M_Offset_CDO_Mask_Enable = 0x234,
951 static inline int M_Offset_AO_Waveform_Order(int channel)
953 return 0xc2 + 0x4 * channel;
955 static inline int M_Offset_AO_Config_Bank(int channel)
957 return 0xc3 + 0x4 * channel;
959 static inline int M_Offset_DAC_Direct_Data(int channel)
961 return 0xc0 + 0x4 * channel;
963 static inline int M_Offset_Gen_PWM(int channel)
965 return 0x44 + 0x2 * channel;
967 static inline int M_Offset_Static_AI_Control(int i)
976 if(((unsigned)i) >= sizeof(offset) / sizeof(offset[0]))
978 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, i);
983 static inline int M_Offset_AO_Reference_Attenuation(int channel)
992 if(((unsigned)channel) >= sizeof(offset) / sizeof(offset[0]))
994 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, channel);
997 return offset[channel];
1000 enum MSeries_AI_Config_FIFO_Data_Bits
1002 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
1003 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
1004 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
1005 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
1006 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
1007 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
1008 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
1009 MSeries_AI_Config_Polarity_Bit = 0x1000, // 0 for 2's complement encoding
1010 MSeries_AI_Config_Dither_Bit = 0x2000,
1011 MSeries_AI_Config_Last_Channel_Bit = 0x4000,
1013 static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel)
1015 return channel & 0xf;
1017 static inline unsigned MSeries_AI_Config_Bank_Bits(unsigned channel)
1019 return channel & 0x30;
1021 static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range)
1023 return (range & 0x7) << 9;
1026 enum MSeries_Clock_and_Fout2_Bits
1028 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
1029 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
1030 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
1031 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
1032 MSeries_Timebase1_Select_Bit = 0x20, // use PLL for timebase 1
1033 MSeries_Timebase3_Select_Bit = 0x40, // use PLL for timebase 3
1034 MSeries_RTSI_10MHz_Bit = 0x80 // use 10MHz instead of 20MHz for RTSI clock frequency
1036 static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned RTSI_channel)
1038 if(RTSI_channel > 7)
1040 rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, RTSI_channel);
1043 if(RTSI_channel == 7) return MSeries_PLL_In_Source_Select_RTSI7_Bits;
1044 else return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
1047 enum MSeries_PLL_Control_Bits
1049 MSeries_PLL_Enable_Bit = 0x1000,
1050 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
1051 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
1052 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
1053 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x7000,
1055 static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)
1057 static const unsigned max_divisor = 0x10;
1058 if(divisor < 1 || divisor > max_divisor)
1060 rt_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, divisor);
1063 return divisor << 8;
1065 static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)
1067 static const unsigned max_multiplier = 0x100;
1068 if(multiplier < 1 || multiplier > max_multiplier)
1070 rt_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, multiplier);
1076 enum MSeries_PLL_Status
1078 MSeries_PLL_Locked_Bit = 0x1
1081 enum MSeries_AI_Config_FIFO_Bypass_Bits
1083 MSeries_AI_Bypass_Channel_Mask = 0x7,
1084 MSeries_AI_Bypass_Bank_Mask = 0x78,
1085 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,
1086 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,
1087 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,
1088 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
1089 MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
1090 MSeries_AI_Bypass_Dither_Bit = 0x200000,
1091 MSeries_AI_Bypass_Polarity_Bit = 0x400000, // 0 for 2's complement encoding
1092 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
1094 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int calibration_source)
1096 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1098 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int calibration_source)
1100 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1102 static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain)
1104 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask;
1107 enum MSeries_AO_Config_Bank_Bits
1109 MSeries_AO_DAC_Offset_Select_Mask = 0x7,
1110 MSeries_AO_DAC_Offset_0V_Bits = 0x0,
1111 MSeries_AO_DAC_Offset_5V_Bits = 0x1,
1112 MSeries_AO_DAC_Reference_Mask = 0x38,
1113 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
1114 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
1115 MSeries_AO_Update_Timed_Bit = 0x40,
1116 MSeries_AO_Bipolar_Bit = 0x80 // turns on 2's complement encoding
1119 enum MSeries_AO_Reference_Attenuation_Bits
1121 MSeries_Attenuate_x5_Bit = 0x1
1124 static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count)
1126 return (count << 16) & 0xffff0000;
1129 static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count)
1131 return count & 0xffff;
1135 #define M_SERIES_EEPROM_SIZE 1024
1137 typedef struct ni_board_struct{
1146 unsigned int alwaysdither : 1;
1154 comedi_lrange *ao_range_table;
1158 unsigned int ao_unipolar : 1;
1159 unsigned int has_8255 : 1;
1160 unsigned int has_analog_trig : 1;
1162 enum caldac_enum caldac[3];
1165 static ni_board ni_boards[];
1166 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
1168 #define boardtype (*(ni_board *)dev->board_ptr)
1170 #define MAX_N_AO_CHAN 8
1172 #define NI_PRIVATE_COMMON \
1173 uint16_t (*stc_readw)(comedi_device *dev, int register); \
1174 void (*stc_writew)(comedi_device *dev, uint16_t value, int register); \
1175 void (*stc_writel)(comedi_device *dev, uint32_t value, int register); \
1177 unsigned short dio_output; \
1178 unsigned short dio_control; \
1185 int ai_continuous; \
1188 unsigned int ai_calib_source; \
1189 unsigned int ai_calib_source_enabled; \
1190 spinlock_t window_lock; \
1192 int changain_state; \
1193 unsigned int changain_spec; \
1195 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
1196 unsigned short ao[MAX_N_AO_CHAN]; \
1197 unsigned short caldacs[MAX_N_CALDACS]; \
1199 volatile unsigned short ai_cmd2; \
1201 unsigned short ao_conf[MAX_N_AO_CHAN]; \
1202 unsigned short ao_mode1; \
1203 unsigned short ao_mode2; \
1204 unsigned short ao_mode3; \
1205 unsigned short ao_cmd1; \
1206 unsigned short ao_cmd2; \
1207 unsigned short ao_cmd3; \
1208 unsigned short ao_trigger_select; \
1210 unsigned short gpct_mode[2]; \
1211 unsigned short gpct_command[2]; \
1212 unsigned short gpct_input_select[2]; \
1213 int gpct_cur_operation[2]; \
1214 unsigned short an_trig_etc_reg; \
1216 unsigned ai_offset[512]; \
1218 unsigned long serial_interval_ns; \
1219 unsigned char serial_hw_mode; \
1220 unsigned short clock_and_fout; \
1222 volatile unsigned short int_a_enable_reg; \
1223 volatile unsigned short int_b_enable_reg; \
1224 unsigned short io_bidirection_pin_reg; \
1225 unsigned short rtsi_trig_direction_reg; \
1227 unsigned short atrig_mode; \
1228 unsigned short atrig_high; \
1229 unsigned short atrig_low; \
1231 unsigned short pwm_up_count; \
1232 unsigned short pwm_down_count; \
1234 sampl_t ai_fifo_buffer[0x2000]; \
1235 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE];
1237 #endif /* _COMEDI_NI_STC_H */