3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@stm.lbl.gov>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
49 /* Registers in the National Instruments DAQ-STC chip */
51 #define Interrupt_A_Ack_Register 2
52 #define G0_Gate_Interrupt_Ack _bit15
53 #define G0_TC_Interrupt_Ack _bit14
54 #define AI_Error_Interrupt_Ack _bit13
55 #define AI_STOP_Interrupt_Ack _bit12
56 #define AI_START_Interrupt_Ack _bit11
57 #define AI_START2_Interrupt_Ack _bit10
58 #define AI_START1_Interrupt_Ack _bit9
59 #define AI_SC_TC_Interrupt_Ack _bit8
60 #define AI_SC_TC_Error_Confirm _bit7
61 #define G0_TC_Error_Confirm _bit6
62 #define G0_Gate_Error_Confirm _bit5
64 #define AI_Status_1_Register 2
65 #define Interrupt_A_St 0x8000
66 #define AI_FIFO_Full_St 0x4000
67 #define AI_FIFO_Half_Full_St 0x2000
68 #define AI_FIFO_Empty_St 0x1000
69 #define AI_Overrun_St 0x0800
70 #define AI_Overflow_St 0x0400
71 #define AI_SC_TC_Error_St 0x0200
72 #define AI_START2_St 0x0100
73 #define AI_START1_St 0x0080
74 #define AI_SC_TC_St 0x0040
75 #define AI_START_St 0x0020
76 #define AI_STOP_St 0x0010
77 #define G0_TC_St 0x0008
78 #define G0_Gate_Interrupt_St 0x0004
79 #define AI_FIFO_Request_St 0x0002
80 #define Pass_Thru_0_Interrupt_St 0x0001
82 #define Interrupt_B_Ack_Register 3
83 #define AO_Status_1_Register 3
84 #define Interrupt_B_St _bit15
85 #define AO_FIFO_Full_St _bit14
86 #define AO_FIFO_Half_Full_St _bit13
87 #define AO_FIFO_Empty_St _bit12
88 #define AO_BC_TC_Error_St _bit11
89 #define AO_START_St _bit10
90 #define AO_Overrun_St _bit9
91 #define AO_START1_St _bit8
92 #define AO_BC_TC_St _bit7
93 #define AO_UC_TC_St _bit6
94 #define AO_UPDATE_St _bit5
95 #define AO_UI2_TC_St _bit4
96 #define G1_TC_St _bit3
97 #define G1_Gate_Interrupt_St _bit2
98 #define AO_FIFO_Request_St _bit1
99 #define Pass_Thru_1_Interrupt_St _bit0
102 #define AI_Command_2_Register 4
103 #define AI_End_On_SC_TC _bit15
104 #define AI_End_On_End_Of_Scan _bit14
105 #define AI_START1_Disable _bit11
106 #define AI_SC_Save_Trace _bit10
107 #define AI_SI_Switch_Load_On_SC_TC _bit9
108 #define AI_SI_Switch_Load_On_STOP _bit8
109 #define AI_SI_Switch_Load_On_TC _bit7
110 #define AI_SC_Switch_Load_On_TC _bit4
111 #define AI_STOP_Pulse _bit3
112 #define AI_START_Pulse _bit2
113 #define AI_START2_Pulse _bit1
114 #define AI_START1_Pulse _bit0
116 #define AO_Command_2_Register 5
117 #define AO_End_On_BC_TC(x) ((x)<<14)
118 #define AO_Start_Stop_Gate_Enable _bit13
119 #define AO_UC_Save_Trace _bit12
120 #define AO_BC_Gate_Enable _bit11
121 #define AO_BC_Save_Trace _bit10
122 #define AO_UI_Switch_Load_On_BC_TC _bit9
123 #define AO_UI_Switch_Load_On_Stop _bit8
124 #define AO_UI_Switch_Load_On_TC _bit7
125 #define AO_UC_Switch_Load_On_BC_TC _bit6
126 #define AO_UC_Switch_Load_On_TC _bit5
127 #define AO_BC_Switch_Load_On_TC _bit4
128 #define AO_Mute_B _bit3
129 #define AO_Mute_A _bit2
130 #define AO_UPDATE2_Pulse _bit1
131 #define AO_START1_Pulse _bit0
133 #define DIO_Input_Register 7
135 #define AI_Command_1_Register 8
136 #define AI_Analog_Trigger_Reset _bit14
137 #define AI_Disarm _bit13
138 #define AI_SI2_Arm _bit12
139 #define AI_SI2_Load _bit11
140 #define AI_SI_Arm _bit10
141 #define AI_SI_Load _bit9
142 #define AI_DIV_Arm _bit8
143 #define AI_DIV_Load _bit7
144 #define AI_SC_Arm _bit6
145 #define AI_SC_Load _bit5
146 #define AI_SCAN_IN_PROG_Pulse _bit4
147 #define AI_EXTMUX_CLK_Pulse _bit3
148 #define AI_LOCALMUX_CLK_Pulse _bit2
149 #define AI_SC_TC_Pulse _bit1
150 #define AI_CONVERT_Pulse _bit0
152 #define AO_Command_1_Register 9
153 #define AO_Analog_Trigger_Reset _bit15
154 #define AO_START_Pulse _bit14
155 #define AO_Disarm _bit13
156 #define AO_UI2_Arm_Disarm _bit12
157 #define AO_UI2_Load _bit11
158 #define AO_UI_Arm _bit10
159 #define AO_UI_Load _bit9
160 #define AO_UC_Arm _bit8
161 #define AO_UC_Load _bit7
162 #define AO_BC_Arm _bit6
163 #define AO_BC_Load _bit5
164 #define AO_DAC1_Update_Mode _bit4
165 #define AO_LDAC1_Source_Select _bit3
166 #define AO_DAC0_Update_Mode _bit2
167 #define AO_LDAC0_Source_Select _bit1
168 #define AO_UPDATE_Pulse _bit0
171 #define DIO_Output_Register 10
172 #define DIO_Control_Register 11
174 #define AI_Mode_1_Register 12
175 #define AI_CONVERT_Source_Select(a) ((a)<<11)
176 #define AI_SI_Source_select(a) ((a)<<6)
177 #define AI_CONVERT_Source_Polarity _bit5
178 #define AI_Start_Stop _bit3
179 #define AI_Mode_1_Reserved _bit2
180 #define AI_Continuous _bit1
181 #define AI_Trigger_Once _bit0
183 #define AI_Mode_2_Register 13
184 #define AI_SC_Gate_Enable _bit15
185 #define AI_Start_Stop_Gate_Enable _bit14
186 #define AI_Pre_Trigger _bit13
187 #define AI_External_MUX_Present _bit12
188 #define AI_SI2_Initial_Load_Source _bit9
189 #define AI_SI2_Reload_Mode _bit8
190 #define AI_SI_Initial_Load_Source _bit7
191 #define AI_SI_Reload_Mode(a) ((a)<<4)
192 #define AI_SI_Write_Switch _bit3
193 #define AI_SC_Initial_Load_Source _bit2
194 #define AI_SC_Reload_Mode _bit1
195 #define AI_SC_Write_Switch _bit0
197 #define AI_SI_Load_A_Registers 14
198 #define AI_SI_Load_B_Registers 16
199 #define AI_SC_Load_A_Registers 18
200 #define AI_SC_Load_B_Registers 20
201 #define AI_SI2_Load_A_Register 23
202 #define AI_SI2_Load_B_Register 25
204 #define AO_Mode_1_Register 39
205 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
206 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
207 #define AO_Multiple_Channels _bit5
208 #define AO_UPDATE_Source_Polarity _bit4
209 #define AO_UI_Source_Polarity _bit3
210 #define AO_UC_Switch_Load_Every_TC _bit2
211 #define AO_Continuous _bit1
212 #define AO_Trigger_Once _bit0
214 #define AO_Mode_2_Register 39
215 #define AO_FIFO_Mode(x) ((x)<<14)
216 #define AO_FIFO_Retransmit_Enable _bit13
217 #define AO_START1_Disable _bit12
218 #define AO_UC_Initial_Load_Source _bit11
219 #define AO_UC_Write_Switch _bit10
220 #define AO_UI2_Initial_Load_Source _bit9
221 #define AO_UI2_Reload_Mode _bit8
222 #define AO_UI_Initial_Load_Source _bit7
223 #define AO_UI_Reload_Mode(x) ((x)<<4)
224 #define AO_UI_Write_Switch _bit3
225 #define AO_BC_Initial_Load_Source _bit2
226 #define AO_BC_Reload_Mode _bit1
227 #define AO_BC_Write_Switch _bit0
229 #define AO_UI_Load_A_Register_High 40
230 #define AO_UI_Load_A_Register_Low 41
231 #define AO_BC_Load_A_Register_High 44
232 #define AO_BC_Load_A_Register_Low 45
233 #define AO_BC_Load_B_Register_High 46
234 #define AO_BC_Load_B_Register_Low 47
235 #define AO_UC_Load_A_Register_High 48
236 #define AO_UC_Load_A_Register_Low 49
238 #define Clock_and_FOUT_Register 56
239 #define Interrupt_Control_Register 59
240 #define AI_Output_Control_Register 60
242 #define AI_START_STOP_Select_Register 62
243 #define AI_START_Polarity _bit15
244 #define AI_STOP_Polarity _bit14
245 #define AI_STOP_Sync _bit13
246 #define AI_STOP_Edge _bit12
247 #define AI_STOP_Select(a) ((a)<<7)
248 #define AI_START_Sync _bit6
249 #define AI_START_Edge _bit5
250 #define AI_START_Select(a) (a)
252 #define AI_Trigger_Select_Register 63
253 #define AI_START1_Polarity _bit15
254 #define AI_START2_Polarity _bit14
255 #define AI_START2_Sync _bit13
256 #define AI_START2_Edge _bit12
257 #define AI_START2_Select(a) ((a)<<7)
258 #define AI_START1_Sync _bit6
259 #define AI_START1_Edge _bit5
260 #define AI_START1_Select(a) (a)
262 #define AO_Start_Select_Register 66
263 #define AO_UI2_Software_Gate _bit15
264 #define AO_UI2_External_Gate_Polarity _bit14
265 #define AO_START_Polarity _bit13
266 #define AO_AOFREQ_Enable _bit12
267 #define AO_UI2_External_Gate_Select(a) ((a)<<7)
268 #define AO_START_Sync _bit6
269 #define AO_START_Edge _bit5
270 #define AO_START_Select(a) (a)
272 #define AO_Trigger_Select_Register 67
273 #define AO_UI2_External_Gate_Enable _bit15
274 #define AO_Delayed_START1 _bit14
275 #define AO_START1_Polarity _bit13
276 #define AO_UI2_Source_Polarity _bit12
277 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
278 #define AO_START1_Sync _bit6
279 #define AO_START1_Edge _bit5
280 #define AO_START1_Select(x) (((x)&0x1f)<<0)
282 #define AO_Mode_3_Register 70
283 #define AO_UI2_Switch_Load_Next_TC _bit13
284 #define AO_UC_Switch_Load_Every_BC_TC _bit12
285 #define AO_Trigger_Length _bit11
286 #define AO_Stop_On_Overrun_Error _bit5
287 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
288 #define AO_Stop_On_BC_TC_Error _bit3
289 #define AO_Not_An_UPDATE _bit2
290 #define AO_Software_Gate _bit1
292 #define Joint_Reset_Register 72
293 #define AO_Configuration_End _bit9
294 #define AI_Configuration_End _bit8
295 #define AO_Configuration_Start _bit5
296 #define AI_Configuration_Start _bit4
297 #define AO_Reset _bit1
298 #define AI_Reset _bit0
300 #define Interrupt_A_Enable_Register 73
301 #define Pass_Thru_0_Interrupt_Enable _bit9
302 #define G0_Gate_Interrupt_Enable _bit8
303 #define AI_FIFO_Interrupt_Enable _bit7
304 #define G0_TC_Interrupt_Enable _bit6
305 #define AI_Error_Interrupt_Enable _bit5
306 #define AI_STOP_Interrupt_Enable _bit4
307 #define AI_START_Interrupt_Enable _bit3
308 #define AI_START2_Interrupt_Enable _bit2
309 #define AI_START1_Interrupt_Enable _bit1
310 #define AI_SC_TC_Interrupt_Enable _bit0
312 #define Interrupt_B_Enable_Register 75
313 #define Pass_Thru_1_Interrupt_Enable _bit11
314 #define G1_Gate_Interrupt_Enable _bit10
315 #define G1_TC_Interrupt_Enable _bit9
316 #define AO_FIFO_Interrupt_Enable _bit8
317 #define AO_UI2_TC_Interrupt_Enable _bit7
318 #define AO_UC_TC_Interrupt_Enable _bit6
319 #define AO_Error_Interrupt_Enable _bit5
320 #define AO_STOP_Interrupt_Enable _bit4
321 #define AO_START_Interrupt_Enable _bit3
322 #define AO_UPDATE_Interrupt_Enable _bit2
323 #define AO_START1_Interrupt_Enable _bit1
324 #define AO_BC_TC_Interrupt_Enable _bit0
326 #define Second_IRQ_B_Enable_Register 76
327 #define AI_Personal_Register 77
328 #define AO_Personal_Register 78
329 #define Write_Strobe_0_Register 82
330 #define Write_Strobe_1_Register 83
331 #define Write_Strobe_2_Register 84
332 #define Write_Strobe_3_Register 85
334 #define AO_Output_Control_Register 86
335 #define AO_External_Gate_Enable _bit15
336 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
337 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
338 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
339 #define AO_External_Gate_Polarity _bit3
340 #define AO_UPDATE2_Output_Toggle _bit2
341 #define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
343 #define AI_Mode_3_Register 87
344 #define AI_Trigger_Length _bit15
345 #define AI_Delay_START _bit14
346 #define AI_Software_Gate _bit13
347 #define AI_SI_Special_Trigger_Delay _bit12
348 #define AI_SI2_Source_Select _bit11
349 #define AI_Delayed_START2 _bit10
350 #define AI_Delayed_START1 _bit9
351 #define AI_External_Gate_Mode _bit8
352 #define AI_FIFO_Mode_HF_to_E (3<<6)
353 #define AI_FIFO_Mode_F (2<<6)
354 #define AI_FIFO_Mode_HF (1<<6)
355 #define AI_FIFO_Mode_NE (0<<6)
356 #define AI_External_Gate_Polarity _bit5
357 #define AI_External_Gate_Select(a) (a)
360 /* 16 bit registers shadowed from DAQ-STC */
361 #define Window_Address 0x00
362 #define Window_Data 0x02
363 #define Interrupt_A_Ack 0x04
364 #define AI_Status_1 0x04
365 #define Interrupt_B_Ack 0x06
366 #define AO_Status_1 0x06
367 #define AI_Command_2 0x08
368 #define G_Status 0x08
369 #define AO_Command_2 0x0a
370 #define AI_Status_2 0x0a
371 #define G0_Command 0x0c
372 #define AO_Status_2 0x0c
373 #define G1_Command 0x0e
374 #define DIO_Parallel_Input 0x0e
376 #define G_Autoincrement_Register(a) (68+(a))
377 #define G_Command_Register(a) (6+(a))
378 #define G_HW_Save_Register_High(a) (8+(a)*2)
379 #define G_HW_Save_Register_Low(a) (9+(a)*2)
380 #define G_Input_Select_Register(a) (36+(a))
381 #define G_Load_A_Register_High(a) (28+(a)*4)
382 #define G_Load_A_Register_Low(a) (29+(a)*4)
383 #define G_Load_B_Register_High(a) (30+(a)*4)
384 #define G_Load_B_Register_Low(a) (31+(a)*4)
385 #define G_Mode_Register(a) (26+(a))
386 #define G_Save_Register_High(a) (12+(a)*2)
387 #define G_Save_Register_Low(a) (13+(a)*2)
388 #define G_Status_Register 4
390 /* command register */
391 #define G_Disarm_Copy _bit15 /* strobe */
392 #define G_Save_Trace_Copy _bit14
393 #define G_Arm_Copy _bit13 /* strobe */
394 #define G0_Bank_Switch_Enable _bit12
395 #define G1_Bank_Switch_Enable _bit12
396 #define G0_Bank_Switch_Mode _bit11
397 #define G1_Bank_Switch_Mode _bit11
398 #define G_Bank_Switch_Start _bit10 /* strobe */
399 #define G_Little_Big_Endian _bit9
400 #define G_Synchronized_Gate _bit8
401 #define G_Write_Switch _bit7
402 #define G_Up_Down(a) (((a)&0x03)<<5)
403 #define G_Disarm _bit4 /* strobe */
404 #define G_Analog_Trigger_Reset _bit3 /* strobe */
405 #define G0_Load _bit2 /* strobe */
406 #define G1_Load _bit2 /* strobe */
407 #define G_Save_Trace _bit1
408 #define G_Arm _bit0 /* strobe */
410 /* input select register */
411 #define G0_Source_Polarity _bit15
412 #define G1_Source_Polarity _bit15
413 #define G0_Output_Polarity _bit14
414 #define G1_Output_Polarity _bit14
415 #define G0_OR_Gate _bit13
416 #define G1_OR_Gate _bit13
417 #define G0_Gate_Select_Load_Source _bit12
418 #define G1_Gate_Select_Load_Source _bit12
419 #define G_Gate_Select(a) (((a)&0x1f)<<7)
420 #define G_Source_Select(a) (((a)&0x1f)<<2)
421 #define G_Write_Acknowledges_Irq _bit1
422 #define G_Read_Acknowledges_Irq _bit0
425 #define G0_Load_Source_Select _bit7
426 #define G1_Load_Source_Select _bit7
428 #define G0_Reload_Source_Switching _bit15
429 #define G1_Reload_Source_Switching _bit15
430 #define G0_Loading_On_Gate _bit14
431 #define G1_Loading_On_Gate _bit14
432 #define G0_Gate_Polarity _bit13
433 #define G1_Gate_Polarity _bit13
434 #define G_Loading_On_TC _bit12
435 #define G0_Counting_Once(a) (((a)&0x03)<<10)
436 #define G1_Counting_Once(a) (((a)&0x03)<<10)
437 #define G_Output_Mode(a) (((a)&0x03)<<8)
438 #define G0_Stop_Mode(a) (((a)&0x03)<<5)
439 #define G1_Stop_Mode(a) (((a)&0x03)<<5)
440 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
441 #define G0_Gate_On_Both_Edges _bit1
442 #define G1_Gate_On_Both_Edges _bit1
443 #define G_Gating_Mode(a) (((a)&0x03)<<0)
446 /* general purpose counter timer */
447 #define G0_Reset _bit2
448 #define G1_Reset _bit3
449 #define G0_TC_Interrupt_Enable _bit6
450 #define G1_TC_Interrupt_Enable _bit9
451 #define G0_Gate_Interrupt_Enable _bit8
452 #define G1_Gate_Interrupt_Enable _bit10
453 #define G0_Synchronized_Gate _bit8
454 #define G1_Synchronized_Gate _bit8
455 #define G0_Gate_Error_Confirm _bit5
456 #define G1_Gate_Error_Confirm _bit1
457 #define G0_TC_Error_Confirm _bit6
458 #define G1_TC_Error_Confirm _bit2
459 #define G0_TC_Interrupt_Ack _bit14
460 #define G1_TC_Interrupt_Ack _bit14
461 #define G0_Gate_Interrupt_Ack _bit15
462 #define G1_Gate_Interrupt_Ack _bit15
463 #define G_Autoincrement(a) ((a)<<0)
464 #define G_Autoincrement(a) ((a)<<0)
468 /* Additional windowed registers unique to E series */
470 #define Configuration_Memory_Clear 82
471 #define ADC_FIFO_Clear 83
472 #define DAC_FIFO_Clear 84
475 /* i/o port offsets */
477 /* 8 bit registers */
478 #define XXX_Status 0x01
479 #define Serial_Command 0x0d
480 #define Misc_Command 0x0f
484 #define Configuration 0x1f
486 #define Channel_A_Mode 0x03
487 #define Channel_B_Mode 0x05
488 #define Channel_C_Mode 0x07
489 #define AI_AO_Select 0x09
490 #define G0_G1_Select 0x0b
492 /* 16 bit registers */
493 #define Configuration_Memory_Low 0x10
494 #define Configuration_Memory_High 0x12
495 #define ADC_FIFO_Data_Register 0x1c
496 #define AO_Configuration 0x16
497 #define DAC_FIFO_Data 0x1e
498 #define DAC0_Direct_Data 0x18
499 #define DAC1_Direct_Data 0x1a
502 #define SerDacLd(x) (0x08<<(x))
505 This is stuff unique to the NI E series drivers,
506 but I thought I'd put it here anyway.
509 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_8_602x };
510 extern struct caldac_struct caldac_mb88341,
515 typedef struct ni_board_struct{
539 struct caldac_struct **caldac;
542 static ni_board ni_boards[];
543 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
545 #define boardtype ni_boards[dev->board]
549 #endif /* _COMEDI_NI_STC_H */