comedi/drivers/ni_stc.h

   1 /*
   2     module/ni_stc.h
   3     Register descriptions for NI DAQ-STC chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1998-9 David A. Schleef <ds@stm.lbl.gov>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         References:
  26             DAQ-STC Technical Reference Manual
  27 */
  28
  29 #ifndef _COMEDI_NI_STC_H
  30 #define _COMEDI_NI_STC_H
  31
  32 #define _bit15          0x8000
  33 #define _bit14          0x4000
  34 #define _bit13          0x2000
  35 #define _bit12          0x1000
  36 #define _bit11          0x0800
  37 #define _bit10          0x0400
  38 #define _bit9           0x0200
  39 #define _bit8           0x0100
  40 #define _bit7           0x0080
  41 #define _bit6           0x0040
  42 #define _bit5           0x0020
  43 #define _bit4           0x0010
  44 #define _bit3           0x0008
  45 #define _bit2           0x0004
  46 #define _bit1           0x0002
  47 #define _bit0           0x0001
  48
  49 /* Registers in the National Instruments DAQ-STC chip */
  50
  51 #define Interrupt_A_Ack_Register        2
  52 #define G0_Gate_Interrupt_Ack                   _bit15
  53 #define G0_TC_Interrupt_Ack                     _bit14
  54 #define AI_Error_Interrupt_Ack                  _bit13
  55 #define AI_STOP_Interrupt_Ack                   _bit12
  56 #define AI_START_Interrupt_Ack                  _bit11
  57 #define AI_START2_Interrupt_Ack                 _bit10
  58 #define AI_START1_Interrupt_Ack                 _bit9
  59 #define AI_SC_TC_Interrupt_Ack                  _bit8
  60 #define AI_SC_TC_Error_Confirm                  _bit7
  61 #define G0_TC_Error_Confirm                     _bit6
  62 #define G0_Gate_Error_Confirm                   _bit5
  63
  64 #define AI_Status_1_Register            2
  65 #define Interrupt_A_St                          0x8000
  66 #define AI_FIFO_Full_St                         0x4000
  67 #define AI_FIFO_Half_Full_St                    0x2000
  68 #define AI_FIFO_Empty_St                        0x1000
  69 #define AI_Overrun_St                           0x0800
  70 #define AI_Overflow_St                          0x0400
  71 #define AI_SC_TC_Error_St                       0x0200
  72 #define AI_START2_St                            0x0100
  73 #define AI_START1_St                            0x0080
  74 #define AI_SC_TC_St                             0x0040
  75 #define AI_START_St                             0x0020
  76 #define AI_STOP_St                              0x0010
  77 #define G0_TC_St                                0x0008
  78 #define G0_Gate_Interrupt_St                    0x0004
  79 #define AI_FIFO_Request_St                      0x0002
  80 #define Pass_Thru_0_Interrupt_St                0x0001
  81
  82 #define AI_Status_2_Register            5
  83
  84 #define Interrupt_B_Ack_Register        3
  85 #define AO_Status_1_Register            3
  86 #define Interrupt_B_St                          _bit15
  87 #define AO_FIFO_Full_St                         _bit14
  88 #define AO_FIFO_Half_Full_St                    _bit13
  89 #define AO_FIFO_Empty_St                        _bit12
  90 #define AO_BC_TC_Error_St                       _bit11
  91 #define AO_START_St                             _bit10
  92 #define AO_Overrun_St                           _bit9
  93 #define AO_START1_St                            _bit8
  94 #define AO_BC_TC_St                             _bit7
  95 #define AO_UC_TC_St                             _bit6
  96 #define AO_UPDATE_St                            _bit5
  97 #define AO_UI2_TC_St                            _bit4
  98 #define G1_TC_St                                _bit3
  99 #define G1_Gate_Interrupt_St                    _bit2
 100 #define AO_FIFO_Request_St                      _bit1
 101 #define Pass_Thru_1_Interrupt_St                _bit0
 102
 103
 104 #define AI_Command_2_Register           4
 105 #define AI_End_On_SC_TC                         _bit15
 106 #define AI_End_On_End_Of_Scan                   _bit14
 107 #define AI_START1_Disable                       _bit11
 108 #define AI_SC_Save_Trace                        _bit10
 109 #define AI_SI_Switch_Load_On_SC_TC              _bit9
 110 #define AI_SI_Switch_Load_On_STOP               _bit8
 111 #define AI_SI_Switch_Load_On_TC                 _bit7
 112 #define AI_SC_Switch_Load_On_TC                 _bit4
 113 #define AI_STOP_Pulse                           _bit3
 114 #define AI_START_Pulse                          _bit2
 115 #define AI_START2_Pulse                         _bit1
 116 #define AI_START1_Pulse                         _bit0
 117
 118 #define AO_Command_2_Register           5
 119 #define AO_End_On_BC_TC(x)                      ((x)<<14)
 120 #define AO_Start_Stop_Gate_Enable               _bit13
 121 #define AO_UC_Save_Trace                        _bit12
 122 #define AO_BC_Gate_Enable                       _bit11
 123 #define AO_BC_Save_Trace                        _bit10
 124 #define AO_UI_Switch_Load_On_BC_TC              _bit9
 125 #define AO_UI_Switch_Load_On_Stop               _bit8
 126 #define AO_UI_Switch_Load_On_TC                 _bit7
 127 #define AO_UC_Switch_Load_On_BC_TC              _bit6
 128 #define AO_UC_Switch_Load_On_TC                 _bit5
 129 #define AO_BC_Switch_Load_On_TC                 _bit4
 130 #define AO_Mute_B                               _bit3
 131 #define AO_Mute_A                               _bit2
 132 #define AO_UPDATE2_Pulse                        _bit1
 133 #define AO_START1_Pulse                         _bit0
 134
 135 #define DIO_Input_Register              7
 136 #define DIO_SDIN                                _bit4
 137
 138 #define AI_Command_1_Register           8
 139 #define AI_Analog_Trigger_Reset                 _bit14
 140 #define AI_Disarm                               _bit13
 141 #define AI_SI2_Arm                              _bit12
 142 #define AI_SI2_Load                             _bit11
 143 #define AI_SI_Arm                               _bit10
 144 #define AI_SI_Load                              _bit9
 145 #define AI_DIV_Arm                              _bit8
 146 #define AI_DIV_Load                             _bit7
 147 #define AI_SC_Arm                               _bit6
 148 #define AI_SC_Load                              _bit5
 149 #define AI_SCAN_IN_PROG_Pulse                   _bit4
 150 #define AI_EXTMUX_CLK_Pulse                     _bit3
 151 #define AI_LOCALMUX_CLK_Pulse                   _bit2
 152 #define AI_SC_TC_Pulse                          _bit1
 153 #define AI_CONVERT_Pulse                        _bit0
 154
 155 #define AO_Command_1_Register           9
 156 #define AO_Analog_Trigger_Reset                 _bit15
 157 #define AO_START_Pulse                          _bit14
 158 #define AO_Disarm                               _bit13
 159 #define AO_UI2_Arm_Disarm                       _bit12
 160 #define AO_UI2_Load                             _bit11
 161 #define AO_UI_Arm                               _bit10
 162 #define AO_UI_Load                              _bit9
 163 #define AO_UC_Arm                               _bit8
 164 #define AO_UC_Load                              _bit7
 165 #define AO_BC_Arm                               _bit6
 166 #define AO_BC_Load                              _bit5
 167 #define AO_DAC1_Update_Mode                     _bit4
 168 #define AO_LDAC1_Source_Select                  _bit3
 169 #define AO_DAC0_Update_Mode                     _bit2
 170 #define AO_LDAC0_Source_Select                  _bit1
 171 #define AO_UPDATE_Pulse                         _bit0
 172
 173
 174 #define DIO_Output_Register             10
 175 #define DIO_Parallel_Data_Out(a)                ((a)&0xff)
 176 #define DIO_Parallel_Data_Mask                  0xff
 177 #define DIO_SDOUT                               _bit0
 178 #define DIO_Serial_Data_Out(a)                  (((a)&0xff)<<8)
 179 #define DIO_Serial_Data_Mask                    0xff00
 180
 181 #define DIO_Control_Register            11
 182 #define DIO_Software_Serial_Control             _bit11
 183 #define DIO_HW_Serial_Timebase                  _bit10
 184 #define DIO_HW_Serial_Enable                    _bit9
 185 #define DIO_HW_Serial_Start                     _bit8
 186 #define DIO_Pins_Dir(a)                         ((a)&0xff)
 187 #define DIO_Pins_Dir_Mask                       0xff
 188
 189 #define AI_Mode_1_Register              12
 190 #define AI_CONVERT_Source_Select(a)             ((a)<<11)
 191 #define AI_SI_Source_select(a)                  ((a)<<6)
 192 #define AI_CONVERT_Source_Polarity              _bit5
 193 #define AI_Start_Stop                           _bit3
 194 #define AI_Mode_1_Reserved                      _bit2
 195 #define AI_Continuous                           _bit1
 196 #define AI_Trigger_Once                         _bit0
 197
 198 #define AI_Mode_2_Register              13
 199 #define AI_SC_Gate_Enable                       _bit15
 200 #define AI_Start_Stop_Gate_Enable               _bit14
 201 #define AI_Pre_Trigger                          _bit13
 202 #define AI_External_MUX_Present                 _bit12
 203 #define AI_SI2_Initial_Load_Source              _bit9
 204 #define AI_SI2_Reload_Mode                      _bit8
 205 #define AI_SI_Initial_Load_Source               _bit7
 206 #define AI_SI_Reload_Mode(a)                    ((a)<<4)
 207 #define AI_SI_Write_Switch                      _bit3
 208 #define AI_SC_Initial_Load_Source               _bit2
 209 #define AI_SC_Reload_Mode                       _bit1
 210 #define AI_SC_Write_Switch                      _bit0
 211
 212 #define AI_SI_Load_A_Registers          14
 213 #define AI_SI_Load_B_Registers          16
 214 #define AI_SC_Load_A_Registers          18
 215 #define AI_SC_Load_B_Registers          20
 216 #define AI_SI2_Load_A_Register          23
 217 #define AI_SI2_Load_B_Register          25
 218
 219 #define Joint_Status_1_Register         27
 220 #define DIO_Serial_IO_In_Progress_St            _bit12
 221
 222 #define DIO_Serial_Input_Register       28
 223 #define Joint_Status_2_Register         29
 224
 225 #define AO_Mode_1_Register              39
 226 #define AO_UPDATE_Source_Select(x)              (((x)&0x1f)<<11)
 227 #define AO_UI_Source_Select(x)                  (((x)&0x1f)<<6)
 228 #define AO_Multiple_Channels                    _bit5
 229 #define AO_UPDATE_Source_Polarity               _bit4
 230 #define AO_UI_Source_Polarity                   _bit3
 231 #define AO_UC_Switch_Load_Every_TC              _bit2
 232 #define AO_Continuous                           _bit1
 233 #define AO_Trigger_Once                         _bit0
 234
 235 #define AO_Mode_2_Register              39
 236 #define AO_FIFO_Mode(x)                         ((x)<<14)
 237 #define AO_FIFO_Retransmit_Enable               _bit13
 238 #define AO_START1_Disable                       _bit12
 239 #define AO_UC_Initial_Load_Source               _bit11
 240 #define AO_UC_Write_Switch                      _bit10
 241 #define AO_UI2_Initial_Load_Source              _bit9
 242 #define AO_UI2_Reload_Mode                      _bit8
 243 #define AO_UI_Initial_Load_Source               _bit7
 244 #define AO_UI_Reload_Mode(x)                    ((x)<<4)
 245 #define AO_UI_Write_Switch                      _bit3
 246 #define AO_BC_Initial_Load_Source               _bit2
 247 #define AO_BC_Reload_Mode                       _bit1
 248 #define AO_BC_Write_Switch                      _bit0
 249
 250 #define AO_UI_Load_A_Register_High      40
 251 #define AO_UI_Load_A_Register_Low       41
 252 #define AO_BC_Load_A_Register_High      44
 253 #define AO_BC_Load_A_Register_Low       45
 254 #define AO_BC_Load_B_Register_High      46
 255 #define AO_BC_Load_B_Register_Low       47
 256 #define AO_UC_Load_A_Register_High      48
 257 #define AO_UC_Load_A_Register_Low       49
 258
 259 #define Clock_and_FOUT_Register         56
 260 #define DIO_Serial_Out_Divide_By_2              _bit13
 261 #define Slow_Internal_Timebase                  _bit11
 262
 263 #define IO_Bidirection_Pin_Register     57
 264
 265 #define Interrupt_Control_Register      59
 266 #define AI_Output_Control_Register      60
 267
 268 #define AI_START_STOP_Select_Register   62
 269 #define AI_START_Polarity                       _bit15
 270 #define AI_STOP_Polarity                        _bit14
 271 #define AI_STOP_Sync                            _bit13
 272 #define AI_STOP_Edge                            _bit12
 273 #define AI_STOP_Select(a)                       ((a)<<7)
 274 #define AI_START_Sync                           _bit6
 275 #define AI_START_Edge                           _bit5
 276 #define AI_START_Select(a)                      (a)
 277
 278 #define AI_Trigger_Select_Register      63
 279 #define AI_START1_Polarity                      _bit15
 280 #define AI_START2_Polarity                      _bit14
 281 #define AI_START2_Sync                          _bit13
 282 #define AI_START2_Edge                          _bit12
 283 #define AI_START2_Select(a)                     ((a)<<7)
 284 #define AI_START1_Sync                          _bit6
 285 #define AI_START1_Edge                          _bit5
 286 #define AI_START1_Select(a)                     (a)
 287
 288 #define AO_Start_Select_Register        66
 289 #define AO_UI2_Software_Gate                    _bit15
 290 #define AO_UI2_External_Gate_Polarity           _bit14
 291 #define AO_START_Polarity                       _bit13
 292 #define AO_AOFREQ_Enable                        _bit12
 293 #define AO_UI2_External_Gate_Select(a)          ((a)<<7)
 294 #define AO_START_Sync                           _bit6
 295 #define AO_START_Edge                           _bit5
 296 #define AO_START_Select(a)                      (a)
 297
 298 #define AO_Trigger_Select_Register      67
 299 #define AO_UI2_External_Gate_Enable             _bit15
 300 #define AO_Delayed_START1                       _bit14
 301 #define AO_START1_Polarity                      _bit13
 302 #define AO_UI2_Source_Polarity                  _bit12
 303 #define AO_UI2_Source_Select(x)                 (((x)&0x1f)<<7)
 304 #define AO_START1_Sync                          _bit6
 305 #define AO_START1_Edge                          _bit5
 306 #define AO_START1_Select(x)                     (((x)&0x1f)<<0)
 307
 308 #define AO_Mode_3_Register              70
 309 #define AO_UI2_Switch_Load_Next_TC              _bit13
 310 #define AO_UC_Switch_Load_Every_BC_TC           _bit12
 311 #define AO_Trigger_Length                       _bit11
 312 #define AO_Stop_On_Overrun_Error                _bit5
 313 #define AO_Stop_On_BC_TC_Trigger_Error          _bit4
 314 #define AO_Stop_On_BC_TC_Error                  _bit3
 315 #define AO_Not_An_UPDATE                        _bit2
 316 #define AO_Software_Gate                        _bit1
 317
 318 #define Joint_Reset_Register            72
 319 #define AO_Configuration_End                    _bit9
 320 #define AI_Configuration_End                    _bit8
 321 #define AO_Configuration_Start                  _bit5
 322 #define AI_Configuration_Start                  _bit4
 323 #define AO_Reset                                _bit1
 324 #define AI_Reset                                _bit0
 325
 326 #define Interrupt_A_Enable_Register     73
 327 #define Pass_Thru_0_Interrupt_Enable            _bit9
 328 #define G0_Gate_Interrupt_Enable                _bit8
 329 #define AI_FIFO_Interrupt_Enable                _bit7
 330 #define G0_TC_Interrupt_Enable                  _bit6
 331 #define AI_Error_Interrupt_Enable               _bit5
 332 #define AI_STOP_Interrupt_Enable                _bit4
 333 #define AI_START_Interrupt_Enable               _bit3
 334 #define AI_START2_Interrupt_Enable              _bit2
 335 #define AI_START1_Interrupt_Enable              _bit1
 336 #define AI_SC_TC_Interrupt_Enable               _bit0
 337
 338 #define Interrupt_B_Enable_Register     75
 339 #define Pass_Thru_1_Interrupt_Enable            _bit11
 340 #define G1_Gate_Interrupt_Enable                _bit10
 341 #define G1_TC_Interrupt_Enable                  _bit9
 342 #define AO_FIFO_Interrupt_Enable                _bit8
 343 #define AO_UI2_TC_Interrupt_Enable              _bit7
 344 #define AO_UC_TC_Interrupt_Enable               _bit6
 345 #define AO_Error_Interrupt_Enable               _bit5
 346 #define AO_STOP_Interrupt_Enable                _bit4
 347 #define AO_START_Interrupt_Enable               _bit3
 348 #define AO_UPDATE_Interrupt_Enable              _bit2
 349 #define AO_START1_Interrupt_Enable              _bit1
 350 #define AO_BC_TC_Interrupt_Enable               _bit0
 351
 352 #define Second_IRQ_B_Enable_Register    76
 353 #define AI_Personal_Register            77
 354 #define AO_Personal_Register            78
 355 #define Write_Strobe_0_Register         82
 356 #define Write_Strobe_1_Register         83
 357 #define Write_Strobe_2_Register         84
 358 #define Write_Strobe_3_Register         85
 359
 360 #define AO_Output_Control_Register      86
 361 #define AO_External_Gate_Enable                 _bit15
 362 #define AO_External_Gate_Select(x)              (((x)&0x1f)<<10)
 363 #define AO_Number_Of_Channels(x)                (((x)&0xf)<<6)
 364 #define AO_UPDATE2_Output_Select(x)             (((x)&0x3)<<4)
 365 #define AO_External_Gate_Polarity               _bit3
 366 #define AO_UPDATE2_Output_Toggle                _bit2
 367 #define AO_UPDATE_Output_Select(x)              (((x)&0x3)<<0)
 368
 369 #define AI_Mode_3_Register              87
 370 #define AI_Trigger_Length                       _bit15
 371 #define AI_Delay_START                          _bit14
 372 #define AI_Software_Gate                        _bit13
 373 #define AI_SI_Special_Trigger_Delay             _bit12
 374 #define AI_SI2_Source_Select                    _bit11
 375 #define AI_Delayed_START2                       _bit10
 376 #define AI_Delayed_START1                       _bit9
 377 #define AI_External_Gate_Mode                   _bit8
 378 #define AI_FIFO_Mode_HF_to_E                    (3<<6)
 379 #define AI_FIFO_Mode_F                          (2<<6)
 380 #define AI_FIFO_Mode_HF                         (1<<6)
 381 #define AI_FIFO_Mode_NE                         (0<<6)
 382 #define AI_External_Gate_Polarity               _bit5
 383 #define AI_External_Gate_Select(a)              (a)
 384
 385
 386 /* 16 bit registers shadowed from DAQ-STC */
 387 #define Window_Address                  0x00
 388 #define Window_Data                     0x02
 389 #define Interrupt_A_Ack                 0x04
 390 #define AI_Status_1                     0x04
 391 #define Interrupt_B_Ack                 0x06
 392 #define AO_Status_1                     0x06
 393 #define AI_Command_2                    0x08
 394 #define G_Status                        0x08
 395 #define AO_Command_2                    0x0a
 396 #define AI_Status_2                     0x0a
 397 #define G0_Command                      0x0c
 398 #define AO_Status_2                     0x0c
 399 #define G1_Command                      0x0e
 400 #define DIO_Parallel_Input              0x0e
 401
 402 #define G_Autoincrement_Register(a)     (68+(a))
 403 #define G_Command_Register(a)           (6+(a))
 404 #define G_HW_Save_Register_High(a)      (8+(a)*2)
 405 #define G_HW_Save_Register_Low(a)       (9+(a)*2)
 406 #define G_Input_Select_Register(a)      (36+(a))
 407 #define G_Load_A_Register_High(a)       (28+(a)*4)
 408 #define G_Load_A_Register_Low(a)        (29+(a)*4)
 409 #define G_Load_B_Register_High(a)       (30+(a)*4)
 410 #define G_Load_B_Register_Low(a)        (31+(a)*4)
 411 #define G_Mode_Register(a)              (26+(a))
 412 #define G_Save_Register_High(a)         (12+(a)*2)
 413 #define G_Save_Register_Low(a)          (13+(a)*2)
 414 #define G_Status_Register               4
 415 #define Analog_Trigger_Etc_Register     61
 416
 417 /* command register */
 418 #define G_Disarm_Copy                   _bit15          /* strobe */
 419 #define G_Save_Trace_Copy               _bit14
 420 #define G_Arm_Copy                      _bit13          /* strobe */
 421 #define G_Bank_Switch_Start             _bit10          /* strobe */
 422 #define G_Little_Big_Endian             _bit9
 423 #define G_Synchronized_Gate             _bit8
 424 #define G_Write_Switch                  _bit7
 425 #define G_Up_Down(a)                    (((a)&0x03)<<5)
 426 #define G_Disarm                        _bit4           /* strobe */
 427 #define G_Analog_Trigger_Reset          _bit3           /* strobe */
 428 #define G_Save_Trace                    _bit1
 429 #define G_Arm                           _bit0           /* strobe */
 430
 431 /*channel agnostic names for the command register #defines */
 432 #define G_Bank_Switch_Enable            _bit12
 433 #define G_Bank_Switch_Mode              _bit11
 434 #define G_Load                          _bit2           /* strobe */
 435
 436
 437 /* input select register */
 438 #define G_Gate_Select(a)                (((a)&0x1f)<<7)
 439 #define G_Source_Select(a)              (((a)&0x1f)<<2)
 440 #define G_Write_Acknowledges_Irq        _bit1
 441 #define G_Read_Acknowledges_Irq         _bit0
 442
 443 /* same input select register, but with channel agnostic names */
 444 #define G_Source_Polarity               _bit15
 445 #define G_Output_Polarity               _bit14
 446 #define G_OR_Gate                       _bit13
 447 #define G_Gate_Select_Load_Source       _bit12
 448
 449
 450 /* mode register */
 451 #define G_Loading_On_TC                 _bit12
 452 #define G_Output_Mode(a)                (((a)&0x03)<<8)
 453 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
 454 #define G_Gating_Mode(a)                (((a)&0x03)<<0)
 455
 456 /* same input mode register, but with channel agnostic names */
 457 #define G_Load_Source_Select            _bit7
 458 #define G_Reload_Source_Switching       _bit15
 459 #define G_Loading_On_Gate               _bit14
 460 #define G_Gate_Polarity                 _bit13
 461
 462 #define G_Counting_Once(a)              (((a)&0x03)<<10)
 463 #define G_Stop_Mode(a)                  (((a)&0x03)<<5)
 464 #define G_Gate_On_Both_Edges            _bit2
 465
 466 /* G_Status_Register */
 467 #define G1_Gate_Error_St                _bit15
 468 #define G0_Gate_Error_St                _bit14
 469 #define G1_TC_Error_St                  _bit13
 470 #define G0_TC_Error_St                  _bit12
 471 #define G1_No_Load_Between_Gates_St     _bit11
 472 #define G0_No_Load_Between_Gates_St     _bit10
 473 #define G1_Armed_St                     _bit9
 474 #define G0_Armed_St                     _bit8
 475 #define G1_Stale_Data_St                _bit7
 476 #define G0_Stale_Data_St                _bit6
 477 #define G1_Next_Load_Source_St          _bit5
 478 #define G0_Next_Load_Source_St          _bit4
 479 #define G1_Counting_St                  _bit3
 480 #define G0_Counting_St                  _bit2
 481 #define G1_Save_St                      _bit1
 482 #define G0_Save_St                      _bit0
 483
 484 /* general purpose counter timer */
 485 #define G0_Reset                        _bit2
 486 #define G1_Reset                        _bit3
 487 #define G0_TC_Interrupt_Enable          _bit6
 488 #define G1_TC_Interrupt_Enable          _bit9
 489 #define G0_Gate_Interrupt_Enable        _bit8
 490 #define G1_Gate_Interrupt_Enable        _bit10
 491 #define G0_Synchronized_Gate            _bit8
 492 #define G1_Synchronized_Gate            _bit8
 493 #define G0_Gate_Error_Confirm           _bit5
 494 #define G1_Gate_Error_Confirm           _bit1
 495 #define G0_TC_Error_Confirm             _bit6
 496 #define G1_TC_Error_Confirm             _bit2
 497 #define G0_TC_Interrupt_Ack             _bit14
 498 #define G1_TC_Interrupt_Ack             _bit14
 499 #define G0_Gate_Interrupt_Ack           _bit15
 500 #define G1_Gate_Interrupt_Ack           _bit15
 501 #define G_Autoincrement(a)              ((a)<<0)
 502 #define G_Autoincrement(a)              ((a)<<0)
 503 #define G0_Arm                          _bit0
 504 #define G1_Arm                          _bit0
 505
 506 /*Analog_Trigger_Etc_Register*/
 507 /*This is mainly a counter/timer register */
 508 #define GPFO_1_Output_Enable            _bit15
 509 #define GPFO_0_Output_Enable            _bit14
 510 #define GPFO_0_Output_Select(a)         ((a)<<11)
 511 #define GPFO_1_Output_Select            _bit7
 512
 513 /* Additional windowed registers unique to E series */
 514
 515 #define Configuration_Memory_Clear      82
 516 #define ADC_FIFO_Clear                  83
 517 #define DAC_FIFO_Clear                  84
 518
 519
 520 /* i/o port offsets */
 521
 522 /* 8 bit registers */
 523 #define XXX_Status                      0x01
 524 #define Serial_Command                  0x0d
 525 #define Misc_Command                    0x0f
 526 #define Port_A                          0x19
 527 #define Port_B                          0x1b
 528 #define Port_C                          0x1d
 529 #define Configuration                   0x1f
 530 #define Strobes                         0x01
 531 #define Channel_A_Mode                  0x03
 532 #define Channel_B_Mode                  0x05
 533 #define Channel_C_Mode                  0x07
 534 #define AI_AO_Select                    0x09
 535 #define G0_G1_Select                    0x0b
 536
 537 /* 16 bit registers */
 538 #define Configuration_Memory_Low        0x10
 539 #define Configuration_Memory_High       0x12
 540 #define ADC_FIFO_Data_Register          0x1c
 541 #define AO_Configuration                0x16
 542 #define DAC_FIFO_Data                   0x1e
 543 #define DAC0_Direct_Data                0x18
 544 #define DAC1_Direct_Data                0x1a
 545
 546
 547 #define SerDacLd(x)                     (0x08<<(x))
 548
 549 /*
 550         This is stuff unique to the NI E series drivers,
 551         but I thought I'd put it here anyway.
 552 */
 553
 554 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4 };
 555 extern struct caldac_struct caldac_mb88341,
 556         caldac_dac8800,
 557         caldac_dac8043,
 558         caldac_ad8522;
 559
 560 typedef struct ni_board_struct{
 561         int device_id;
 562         char *name;
 563
 564         int n_adchan;
 565         int adbits;
 566
 567         int ai_fifo_depth;
 568         int alwaysdither;
 569         int gainlkup;
 570         int ai_speed;
 571
 572         int n_aochan;
 573         int aobits;
 574
 575         int ao_fifo_depth;
 576         int aorangelkup;
 577
 578         int ao_unipolar;
 579
 580         int has_8255;
 581
 582         struct caldac_struct **caldac;
 583 }ni_board;
 584
 585 static ni_board ni_boards[];
 586 #define n_ni_boards  (sizeof(ni_boards)/sizeof(ni_board))
 587
 588 #define boardtype (*(ni_board *)dev->board_ptr)
 589
 590 #define NI_PRIVATE_COMMON                                       \
 591         unsigned short dio_output;                              \
 592         unsigned short dio_control;                             \
 593         int ao0p,ao1p;                                          \
 594         int lastchan;                                           \
 595         int last_do;                                            \
 596         int rt_irq;                                             \
 597         int irqmask;                                            \
 598         int aimode;                                             \
 599         int ai_continuous;                                      \
 600         int blocksize;                                          \
 601         int n_left;                                             \
 602                                                                 \
 603         int changain_state;                                     \
 604         unsigned int changain_spec;                             \
 605                                                                 \
 606         unsigned int caldac_maxdata_list[MAX_N_CALDACS];        \
 607         unsigned short ao[2];                                   \
 608         unsigned short caldacs[12];                             \
 609                                                                 \
 610         unsigned short ao_mode1;                                \
 611         unsigned short ao_mode2;                                \
 612         unsigned short ao_mode3;                                \
 613         unsigned short ao_cmd1;                                 \
 614         unsigned short ao_cmd2;                                 \
 615         unsigned short ao_cmd3;                                 \
 616         unsigned short ao_trigger_select;                       \
 617                                                                 \
 618         unsigned short gpct_mode[2];                            \
 619         unsigned short gpct_command[2];                         \
 620         unsigned short gpct_input_select[2];                    \
 621         int gpct_cur_operation[2];                              \
 622         unsigned short an_trig_etc_reg;                         \
 623                                                                 \
 624         unsigned short ai_xorlist[512];                         \
 625                                                                 \
 626         unsigned long serial_interval_ns;                       \
 627         unsigned char serial_hw_mode;                           \
 628         unsigned short clock_and_fout;                          \
 629                                                                 \
 630         unsigned short int_a_enable_reg;                        \
 631         unsigned short int_b_enable_reg;                        \
 632         unsigned short io_bidirection_pin_reg;                  \
 633
 634 #endif /* _COMEDI_NI_STC_H */
 635