3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@stm.lbl.gov>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
49 /* Registers in the National Instruments DAQ-STC chip */
51 #define Interrupt_A_Ack_Register 2
52 #define G0_Gate_Interrupt_Ack _bit15
53 #define G0_TC_Interrupt_Ack _bit14
54 #define AI_Error_Interrupt_Ack _bit13
55 #define AI_STOP_Interrupt_Ack _bit12
56 #define AI_START_Interrupt_Ack _bit11
57 #define AI_START2_Interrupt_Ack _bit10
58 #define AI_START1_Interrupt_Ack _bit9
59 #define AI_SC_TC_Interrupt_Ack _bit8
60 #define AI_SC_TC_Error_Confirm _bit7
61 #define G0_TC_Error_Confirm _bit6
62 #define G0_Gate_Error_Confirm _bit5
64 #define AI_Status_1_Register 2
65 #define Interrupt_A_St 0x8000
66 #define AI_FIFO_Full_St 0x4000
67 #define AI_FIFO_Half_Full_St 0x2000
68 #define AI_FIFO_Empty_St 0x1000
69 #define AI_Overrun_St 0x0800
70 #define AI_Overflow_St 0x0400
71 #define AI_SC_TC_Error_St 0x0200
72 #define AI_START2_St 0x0100
73 #define AI_START1_St 0x0080
74 #define AI_SC_TC_St 0x0040
75 #define AI_START_St 0x0020
76 #define AI_STOP_St 0x0010
77 #define G0_TC_St 0x0008
78 #define G0_Gate_Interrupt_St 0x0004
79 #define AI_FIFO_Request_St 0x0002
80 #define Pass_Thru_0_Interrupt_St 0x0001
82 #define AI_Status_2_Register 5
84 #define Interrupt_B_Ack_Register 3
85 #define AO_Status_1_Register 3
86 #define Interrupt_B_St _bit15
87 #define AO_FIFO_Full_St _bit14
88 #define AO_FIFO_Half_Full_St _bit13
89 #define AO_FIFO_Empty_St _bit12
90 #define AO_BC_TC_Error_St _bit11
91 #define AO_START_St _bit10
92 #define AO_Overrun_St _bit9
93 #define AO_START1_St _bit8
94 #define AO_BC_TC_St _bit7
95 #define AO_UC_TC_St _bit6
96 #define AO_UPDATE_St _bit5
97 #define AO_UI2_TC_St _bit4
98 #define G1_TC_St _bit3
99 #define G1_Gate_Interrupt_St _bit2
100 #define AO_FIFO_Request_St _bit1
101 #define Pass_Thru_1_Interrupt_St _bit0
104 #define AI_Command_2_Register 4
105 #define AI_End_On_SC_TC _bit15
106 #define AI_End_On_End_Of_Scan _bit14
107 #define AI_START1_Disable _bit11
108 #define AI_SC_Save_Trace _bit10
109 #define AI_SI_Switch_Load_On_SC_TC _bit9
110 #define AI_SI_Switch_Load_On_STOP _bit8
111 #define AI_SI_Switch_Load_On_TC _bit7
112 #define AI_SC_Switch_Load_On_TC _bit4
113 #define AI_STOP_Pulse _bit3
114 #define AI_START_Pulse _bit2
115 #define AI_START2_Pulse _bit1
116 #define AI_START1_Pulse _bit0
118 #define AO_Command_2_Register 5
119 #define AO_End_On_BC_TC(x) ((x)<<14)
120 #define AO_Start_Stop_Gate_Enable _bit13
121 #define AO_UC_Save_Trace _bit12
122 #define AO_BC_Gate_Enable _bit11
123 #define AO_BC_Save_Trace _bit10
124 #define AO_UI_Switch_Load_On_BC_TC _bit9
125 #define AO_UI_Switch_Load_On_Stop _bit8
126 #define AO_UI_Switch_Load_On_TC _bit7
127 #define AO_UC_Switch_Load_On_BC_TC _bit6
128 #define AO_UC_Switch_Load_On_TC _bit5
129 #define AO_BC_Switch_Load_On_TC _bit4
130 #define AO_Mute_B _bit3
131 #define AO_Mute_A _bit2
132 #define AO_UPDATE2_Pulse _bit1
133 #define AO_START1_Pulse _bit0
135 #define AO_Status_2_Register 6
137 #define DIO_Parallel_Input_Register 7
138 #define DIO_SDIN _bit4
140 #define AI_Command_1_Register 8
141 #define AI_Analog_Trigger_Reset _bit14
142 #define AI_Disarm _bit13
143 #define AI_SI2_Arm _bit12
144 #define AI_SI2_Load _bit11
145 #define AI_SI_Arm _bit10
146 #define AI_SI_Load _bit9
147 #define AI_DIV_Arm _bit8
148 #define AI_DIV_Load _bit7
149 #define AI_SC_Arm _bit6
150 #define AI_SC_Load _bit5
151 #define AI_SCAN_IN_PROG_Pulse _bit4
152 #define AI_EXTMUX_CLK_Pulse _bit3
153 #define AI_LOCALMUX_CLK_Pulse _bit2
154 #define AI_SC_TC_Pulse _bit1
155 #define AI_CONVERT_Pulse _bit0
157 #define AO_Command_1_Register 9
158 #define AO_Analog_Trigger_Reset _bit15
159 #define AO_START_Pulse _bit14
160 #define AO_Disarm _bit13
161 #define AO_UI2_Arm_Disarm _bit12
162 #define AO_UI2_Load _bit11
163 #define AO_UI_Arm _bit10
164 #define AO_UI_Load _bit9
165 #define AO_UC_Arm _bit8
166 #define AO_UC_Load _bit7
167 #define AO_BC_Arm _bit6
168 #define AO_BC_Load _bit5
169 #define AO_DAC1_Update_Mode _bit4
170 #define AO_LDAC1_Source_Select _bit3
171 #define AO_DAC0_Update_Mode _bit2
172 #define AO_LDAC0_Source_Select _bit1
173 #define AO_UPDATE_Pulse _bit0
176 #define DIO_Output_Register 10
177 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
178 #define DIO_Parallel_Data_Mask 0xff
179 #define DIO_SDOUT _bit0
180 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
181 #define DIO_Serial_Data_Mask 0xff00
183 #define DIO_Control_Register 11
184 #define DIO_Software_Serial_Control _bit11
185 #define DIO_HW_Serial_Timebase _bit10
186 #define DIO_HW_Serial_Enable _bit9
187 #define DIO_HW_Serial_Start _bit8
188 #define DIO_Pins_Dir(a) ((a)&0xff)
189 #define DIO_Pins_Dir_Mask 0xff
191 #define AI_Mode_1_Register 12
192 #define AI_CONVERT_Source_Select(a) ((a)<<11)
193 #define AI_SI_Source_select(a) ((a)<<6)
194 #define AI_CONVERT_Source_Polarity _bit5
195 #define AI_Start_Stop _bit3
196 #define AI_Mode_1_Reserved _bit2
197 #define AI_Continuous _bit1
198 #define AI_Trigger_Once _bit0
200 #define AI_Mode_2_Register 13
201 #define AI_SC_Gate_Enable _bit15
202 #define AI_Start_Stop_Gate_Enable _bit14
203 #define AI_Pre_Trigger _bit13
204 #define AI_External_MUX_Present _bit12
205 #define AI_SI2_Initial_Load_Source _bit9
206 #define AI_SI2_Reload_Mode _bit8
207 #define AI_SI_Initial_Load_Source _bit7
208 #define AI_SI_Reload_Mode(a) ((a)<<4)
209 #define AI_SI_Write_Switch _bit3
210 #define AI_SC_Initial_Load_Source _bit2
211 #define AI_SC_Reload_Mode _bit1
212 #define AI_SC_Write_Switch _bit0
214 #define AI_SI_Load_A_Registers 14
215 #define AI_SI_Load_B_Registers 16
216 #define AI_SC_Load_A_Registers 18
217 #define AI_SC_Load_B_Registers 20
218 #define AI_SI2_Load_A_Register 23
219 #define AI_SI2_Load_B_Register 25
221 #define Joint_Status_1_Register 27
222 #define DIO_Serial_IO_In_Progress_St _bit12
224 #define DIO_Serial_Input_Register 28
225 #define Joint_Status_2_Register 29
227 #define AO_Mode_1_Register 38
228 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
229 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
230 #define AO_Multiple_Channels _bit5
231 #define AO_UPDATE_Source_Polarity _bit4
232 #define AO_UI_Source_Polarity _bit3
233 #define AO_UC_Switch_Load_Every_TC _bit2
234 #define AO_Continuous _bit1
235 #define AO_Trigger_Once _bit0
237 #define AO_Mode_2_Register 39
238 #define AO_FIFO_Mode(x) ((x)<<14)
239 #define AO_FIFO_Retransmit_Enable _bit13
240 #define AO_START1_Disable _bit12
241 #define AO_UC_Initial_Load_Source _bit11
242 #define AO_UC_Write_Switch _bit10
243 #define AO_UI2_Initial_Load_Source _bit9
244 #define AO_UI2_Reload_Mode _bit8
245 #define AO_UI_Initial_Load_Source _bit7
246 #define AO_UI_Reload_Mode(x) ((x)<<4)
247 #define AO_UI_Write_Switch _bit3
248 #define AO_BC_Initial_Load_Source _bit2
249 #define AO_BC_Reload_Mode _bit1
250 #define AO_BC_Write_Switch _bit0
252 #define AO_UI_Load_A_Register 40
253 #define AO_UI_Load_A_Register_High 40
254 #define AO_UI_Load_A_Register_Low 41
255 #define AO_BC_Load_A_Register 44
256 #define AO_BC_Load_A_Register_High 44
257 #define AO_BC_Load_A_Register_Low 45
258 #define AO_BC_Load_B_Register 46
259 #define AO_BC_Load_B_Register_High 46
260 #define AO_BC_Load_B_Register_Low 47
261 #define AO_UC_Load_A_Register 48
262 #define AO_UC_Load_A_Register_High 48
263 #define AO_UC_Load_A_Register_Low 49
265 #define Clock_and_FOUT_Register 56
266 #define DIO_Serial_Out_Divide_By_2 _bit13
267 #define Slow_Internal_Timebase _bit11
269 #define IO_Bidirection_Pin_Register 57
271 #define Interrupt_Control_Register 59
272 #define AI_Output_Control_Register 60
274 #define AI_START_STOP_Select_Register 62
275 #define AI_START_Polarity _bit15
276 #define AI_STOP_Polarity _bit14
277 #define AI_STOP_Sync _bit13
278 #define AI_STOP_Edge _bit12
279 #define AI_STOP_Select(a) ((a)<<7)
280 #define AI_START_Sync _bit6
281 #define AI_START_Edge _bit5
282 #define AI_START_Select(a) (a)
284 #define AI_Trigger_Select_Register 63
285 #define AI_START1_Polarity _bit15
286 #define AI_START2_Polarity _bit14
287 #define AI_START2_Sync _bit13
288 #define AI_START2_Edge _bit12
289 #define AI_START2_Select(a) ((a)<<7)
290 #define AI_START1_Sync _bit6
291 #define AI_START1_Edge _bit5
292 #define AI_START1_Select(a) (a)
294 #define AO_Start_Select_Register 66
295 #define AO_UI2_Software_Gate _bit15
296 #define AO_UI2_External_Gate_Polarity _bit14
297 #define AO_START_Polarity _bit13
298 #define AO_AOFREQ_Enable _bit12
299 #define AO_UI2_External_Gate_Select(a) ((a)<<7)
300 #define AO_START_Sync _bit6
301 #define AO_START_Edge _bit5
302 #define AO_START_Select(a) (a)
304 #define AO_Trigger_Select_Register 67
305 #define AO_UI2_External_Gate_Enable _bit15
306 #define AO_Delayed_START1 _bit14
307 #define AO_START1_Polarity _bit13
308 #define AO_UI2_Source_Polarity _bit12
309 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
310 #define AO_START1_Sync _bit6
311 #define AO_START1_Edge _bit5
312 #define AO_START1_Select(x) (((x)&0x1f)<<0)
314 #define AO_Mode_3_Register 70
315 #define AO_UI2_Switch_Load_Next_TC _bit13
316 #define AO_UC_Switch_Load_Every_BC_TC _bit12
317 #define AO_Trigger_Length _bit11
318 #define AO_Stop_On_Overrun_Error _bit5
319 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
320 #define AO_Stop_On_BC_TC_Error _bit3
321 #define AO_Not_An_UPDATE _bit2
322 #define AO_Software_Gate _bit1
324 #define Joint_Reset_Register 72
325 #define AO_Configuration_End _bit9
326 #define AI_Configuration_End _bit8
327 #define AO_Configuration_Start _bit5
328 #define AI_Configuration_Start _bit4
329 #define AO_Reset _bit1
330 #define AI_Reset _bit0
332 #define Interrupt_A_Enable_Register 73
333 #define Pass_Thru_0_Interrupt_Enable _bit9
334 #define G0_Gate_Interrupt_Enable _bit8
335 #define AI_FIFO_Interrupt_Enable _bit7
336 #define G0_TC_Interrupt_Enable _bit6
337 #define AI_Error_Interrupt_Enable _bit5
338 #define AI_STOP_Interrupt_Enable _bit4
339 #define AI_START_Interrupt_Enable _bit3
340 #define AI_START2_Interrupt_Enable _bit2
341 #define AI_START1_Interrupt_Enable _bit1
342 #define AI_SC_TC_Interrupt_Enable _bit0
344 #define Interrupt_B_Enable_Register 75
345 #define Pass_Thru_1_Interrupt_Enable _bit11
346 #define G1_Gate_Interrupt_Enable _bit10
347 #define G1_TC_Interrupt_Enable _bit9
348 #define AO_FIFO_Interrupt_Enable _bit8
349 #define AO_UI2_TC_Interrupt_Enable _bit7
350 #define AO_UC_TC_Interrupt_Enable _bit6
351 #define AO_Error_Interrupt_Enable _bit5
352 #define AO_STOP_Interrupt_Enable _bit4
353 #define AO_START_Interrupt_Enable _bit3
354 #define AO_UPDATE_Interrupt_Enable _bit2
355 #define AO_START1_Interrupt_Enable _bit1
356 #define AO_BC_TC_Interrupt_Enable _bit0
358 #define Second_IRQ_B_Enable_Register 76
359 #define AI_Personal_Register 77
360 #define AO_Personal_Register 78
361 #define Write_Strobe_0_Register 82
362 #define Write_Strobe_1_Register 83
363 #define Write_Strobe_2_Register 84
364 #define Write_Strobe_3_Register 85
366 #define AO_Output_Control_Register 86
367 #define AO_External_Gate_Enable _bit15
368 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
369 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
370 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
371 #define AO_External_Gate_Polarity _bit3
372 #define AO_UPDATE2_Output_Toggle _bit2
373 #define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
375 #define AI_Mode_3_Register 87
376 #define AI_Trigger_Length _bit15
377 #define AI_Delay_START _bit14
378 #define AI_Software_Gate _bit13
379 #define AI_SI_Special_Trigger_Delay _bit12
380 #define AI_SI2_Source_Select _bit11
381 #define AI_Delayed_START2 _bit10
382 #define AI_Delayed_START1 _bit9
383 #define AI_External_Gate_Mode _bit8
384 #define AI_FIFO_Mode_HF_to_E (3<<6)
385 #define AI_FIFO_Mode_F (2<<6)
386 #define AI_FIFO_Mode_HF (1<<6)
387 #define AI_FIFO_Mode_NE (0<<6)
388 #define AI_External_Gate_Polarity _bit5
389 #define AI_External_Gate_Select(a) (a)
391 #define G_Autoincrement_Register(a) (68+(a))
392 #define G_Command_Register(a) (6+(a))
393 #define G_HW_Save_Register(a) (8+(a)*2)
394 #define G_HW_Save_Register_High(a) (8+(a)*2)
395 #define G_HW_Save_Register_Low(a) (9+(a)*2)
396 #define G_Input_Select_Register(a) (36+(a))
397 #define G_Load_A_Register(a) (28+(a)*4)
398 #define G_Load_A_Register_High(a) (28+(a)*4)
399 #define G_Load_A_Register_Low(a) (29+(a)*4)
400 #define G_Load_B_Register(a) (30+(a)*4)
401 #define G_Load_B_Register_High(a) (30+(a)*4)
402 #define G_Load_B_Register_Low(a) (31+(a)*4)
403 #define G_Mode_Register(a) (26+(a))
404 #define G_Save_Register(a) (12+(a)*2)
405 #define G_Save_Register_High(a) (12+(a)*2)
406 #define G_Save_Register_Low(a) (13+(a)*2)
407 #define G_Status_Register 4
408 #define Analog_Trigger_Etc_Register 61
410 /* command register */
411 #define G_Disarm_Copy _bit15 /* strobe */
412 #define G_Save_Trace_Copy _bit14
413 #define G_Arm_Copy _bit13 /* strobe */
414 #define G_Bank_Switch_Start _bit10 /* strobe */
415 #define G_Little_Big_Endian _bit9
416 #define G_Synchronized_Gate _bit8
417 #define G_Write_Switch _bit7
418 #define G_Up_Down(a) (((a)&0x03)<<5)
419 #define G_Disarm _bit4 /* strobe */
420 #define G_Analog_Trigger_Reset _bit3 /* strobe */
421 #define G_Save_Trace _bit1
422 #define G_Arm _bit0 /* strobe */
424 /*channel agnostic names for the command register #defines */
425 #define G_Bank_Switch_Enable _bit12
426 #define G_Bank_Switch_Mode _bit11
427 #define G_Load _bit2 /* strobe */
430 /* input select register */
431 #define G_Gate_Select(a) (((a)&0x1f)<<7)
432 #define G_Source_Select(a) (((a)&0x1f)<<2)
433 #define G_Write_Acknowledges_Irq _bit1
434 #define G_Read_Acknowledges_Irq _bit0
436 /* same input select register, but with channel agnostic names */
437 #define G_Source_Polarity _bit15
438 #define G_Output_Polarity _bit14
439 #define G_OR_Gate _bit13
440 #define G_Gate_Select_Load_Source _bit12
444 #define G_Loading_On_TC _bit12
445 #define G_Output_Mode(a) (((a)&0x03)<<8)
446 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
447 #define G_Gating_Mode(a) (((a)&0x03)<<0)
449 /* same input mode register, but with channel agnostic names */
450 #define G_Load_Source_Select _bit7
451 #define G_Reload_Source_Switching _bit15
452 #define G_Loading_On_Gate _bit14
453 #define G_Gate_Polarity _bit13
455 #define G_Counting_Once(a) (((a)&0x03)<<10)
456 #define G_Stop_Mode(a) (((a)&0x03)<<5)
457 #define G_Gate_On_Both_Edges _bit2
459 /* G_Status_Register */
460 #define G1_Gate_Error_St _bit15
461 #define G0_Gate_Error_St _bit14
462 #define G1_TC_Error_St _bit13
463 #define G0_TC_Error_St _bit12
464 #define G1_No_Load_Between_Gates_St _bit11
465 #define G0_No_Load_Between_Gates_St _bit10
466 #define G1_Armed_St _bit9
467 #define G0_Armed_St _bit8
468 #define G1_Stale_Data_St _bit7
469 #define G0_Stale_Data_St _bit6
470 #define G1_Next_Load_Source_St _bit5
471 #define G0_Next_Load_Source_St _bit4
472 #define G1_Counting_St _bit3
473 #define G0_Counting_St _bit2
474 #define G1_Save_St _bit1
475 #define G0_Save_St _bit0
477 /* general purpose counter timer */
478 #define G0_Reset _bit2
479 #define G1_Reset _bit3
480 #define G0_TC_Interrupt_Enable _bit6
481 #define G1_TC_Interrupt_Enable _bit9
482 #define G0_Gate_Interrupt_Enable _bit8
483 #define G1_Gate_Interrupt_Enable _bit10
484 #define G0_Synchronized_Gate _bit8
485 #define G1_Synchronized_Gate _bit8
486 #define G0_Gate_Error_Confirm _bit5
487 #define G1_Gate_Error_Confirm _bit1
488 #define G0_TC_Error_Confirm _bit6
489 #define G1_TC_Error_Confirm _bit2
490 #define G0_TC_Interrupt_Ack _bit14
491 #define G1_TC_Interrupt_Ack _bit14
492 #define G0_Gate_Interrupt_Ack _bit15
493 #define G1_Gate_Interrupt_Ack _bit15
494 #define G_Autoincrement(a) ((a)<<0)
495 #define G_Autoincrement(a) ((a)<<0)
499 /*Analog_Trigger_Etc_Register*/
500 /*This is mainly a counter/timer register */
501 #define GPFO_1_Output_Enable _bit15
502 #define GPFO_0_Output_Enable _bit14
503 #define GPFO_0_Output_Select(a) ((a)<<11)
504 #define GPFO_1_Output_Select _bit7
506 /* Additional windowed registers unique to E series */
508 /* 16 bit registers shadowed from DAQ-STC */
509 #define Window_Address 0x00
510 #define Window_Data 0x02
512 #define Interrupt_A_Ack 0x04
513 #define AI_Status_1 0x04
514 #define Interrupt_B_Ack 0x06
515 #define AO_Status_1 0x06
516 #define AI_Command_2 0x08
517 #define G_Status 0x08
518 #define AO_Command_2 0x0a
519 #define AI_Status_2 0x0a
520 #define G0_Command 0x0c
521 #define AO_Status_2 0x0c
522 #define G1_Command 0x0e
523 #define DIO_Parallel_Input 0x0e
526 #define Configuration_Memory_Clear 82
527 #define ADC_FIFO_Clear 83
528 #define DAC_FIFO_Clear 84
531 /* i/o port offsets */
533 /* 8 bit registers */
534 #define XXX_Status 0x01
535 #define Serial_Command 0x0d
536 #define Misc_Command 0x0f
540 #define Configuration 0x1f
542 #define Channel_A_Mode 0x03
543 #define Channel_B_Mode 0x05
544 #define Channel_C_Mode 0x07
545 #define AI_AO_Select 0x09
546 #define G0_G1_Select 0x0b
548 /* 16 bit registers */
550 #define Configuration_Memory_Low 0x10
551 #define Configuration_Memory_High 0x12
552 #define ADC_FIFO_Data_Register 0x1c
554 #define AO_Configuration 0x16
555 #define AO_Bipolar _bit0
556 #define AO_Deglitch _bit1
557 #define AO_Ext_Ref _bit2
558 #define AO_Ground_Ref _bit3
559 #define AO_Channel(x) ((x) << 8)
561 #define DAC_FIFO_Data 0x1e
562 #define DAC0_Direct_Data 0x18
563 #define DAC1_Direct_Data 0x1a
566 /* 611x registers (these boards differ from the e-series) */
568 #define AI_Command_2_Register_611x 8
569 //#define AO_Status_1_Register_611x 4
570 #define DAC_FIFO_Data_611x 0x14
573 #define AI_Status_1_611x 0x02
574 #define AO_Status_1_611x 0x04
575 #define G_Status_611x 0x06
576 #define AI_Status_2_611x 0x08
577 #define AO_Status_2_611x 0x0a
578 #define DIO_Parallel_Input_611x 0x0c
583 #define AO_Window_Address_671x 0x18 /* W 16 */
584 #define AO_Window_Data_671x 0x1e /* W 16 */
586 /* 671x windowed registers */
588 #define DACx_Direct_Data_671x(x) (x) /* W 16 */
589 #define AO_Immediate_671x 0x11 /* W 16 */
593 #define SerDacLd(x) (0x08<<(x))
596 This is stuff unique to the NI E series drivers,
597 but I thought I'd put it here anyway.
600 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x };
601 enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
602 ad8804, ad8842, ad8804_debug };
604 typedef struct ni_board_struct{
612 int alwaysdither : 1;
626 int has_analog_trig : 1;
632 enum caldac_enum caldac[3];
635 static ni_board ni_boards[];
636 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
638 #define boardtype (*(ni_board *)dev->board_ptr)
640 #define NI_PRIVATE_COMMON \
641 unsigned short dio_output; \
642 unsigned short dio_control; \
653 int changain_state; \
654 unsigned int changain_spec; \
656 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
657 unsigned short ao[2]; \
658 unsigned short caldacs[12]; \
660 unsigned short ao_mode1; \
661 unsigned short ao_mode2; \
662 unsigned short ao_mode3; \
663 unsigned short ao_cmd1; \
664 unsigned short ao_cmd2; \
665 unsigned short ao_cmd3; \
666 unsigned short ao_trigger_select; \
668 unsigned short gpct_mode[2]; \
669 unsigned short gpct_command[2]; \
670 unsigned short gpct_input_select[2]; \
671 int gpct_cur_operation[2]; \
672 unsigned short an_trig_etc_reg; \
674 unsigned short ai_xorlist[512]; \
676 unsigned long serial_interval_ns; \
677 unsigned char serial_hw_mode; \
678 unsigned short clock_and_fout; \
680 unsigned short int_a_enable_reg; \
681 unsigned short int_b_enable_reg; \
682 unsigned short io_bidirection_pin_reg; \
684 unsigned short atrig_mode; \
685 unsigned short atrig_high; \
686 unsigned short atrig_low; \
688 #endif /* _COMEDI_NI_STC_H */
projects / comedi.git / blob