3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
49 /* Registers in the National Instruments DAQ-STC chip */
51 #define Interrupt_A_Ack_Register 2
52 #define G0_Gate_Interrupt_Ack _bit15
53 #define G0_TC_Interrupt_Ack _bit14
54 #define AI_Error_Interrupt_Ack _bit13
55 #define AI_STOP_Interrupt_Ack _bit12
56 #define AI_START_Interrupt_Ack _bit11
57 #define AI_START2_Interrupt_Ack _bit10
58 #define AI_START1_Interrupt_Ack _bit9
59 #define AI_SC_TC_Interrupt_Ack _bit8
60 #define AI_SC_TC_Error_Confirm _bit7
61 #define G0_TC_Error_Confirm _bit6
62 #define G0_Gate_Error_Confirm _bit5
64 #define AI_Status_1_Register 2
65 #define Interrupt_A_St 0x8000
66 #define AI_FIFO_Full_St 0x4000
67 #define AI_FIFO_Half_Full_St 0x2000
68 #define AI_FIFO_Empty_St 0x1000
69 #define AI_Overrun_St 0x0800
70 #define AI_Overflow_St 0x0400
71 #define AI_SC_TC_Error_St 0x0200
72 #define AI_START2_St 0x0100
73 #define AI_START1_St 0x0080
74 #define AI_SC_TC_St 0x0040
75 #define AI_START_St 0x0020
76 #define AI_STOP_St 0x0010
77 #define G0_TC_St 0x0008
78 #define G0_Gate_Interrupt_St 0x0004
79 #define AI_FIFO_Request_St 0x0002
80 #define Pass_Thru_0_Interrupt_St 0x0001
82 #define AI_Status_2_Register 5
84 #define Interrupt_B_Ack_Register 3
85 #define AO_BC_TC_Interrupt_Ack _bit8
87 #define AO_Status_1_Register 3
88 #define Interrupt_B_St _bit15
89 #define AO_FIFO_Full_St _bit14
90 #define AO_FIFO_Half_Full_St _bit13
91 #define AO_FIFO_Empty_St _bit12
92 #define AO_BC_TC_Error_St _bit11
93 #define AO_START_St _bit10
94 #define AO_Overrun_St _bit9
95 #define AO_START1_St _bit8
96 #define AO_BC_TC_St _bit7
97 #define AO_UC_TC_St _bit6
98 #define AO_UPDATE_St _bit5
99 #define AO_UI2_TC_St _bit4
100 #define G1_TC_St _bit3
101 #define G1_Gate_Interrupt_St _bit2
102 #define AO_FIFO_Request_St _bit1
103 #define Pass_Thru_1_Interrupt_St _bit0
106 #define AI_Command_2_Register 4
107 #define AI_End_On_SC_TC _bit15
108 #define AI_End_On_End_Of_Scan _bit14
109 #define AI_START1_Disable _bit11
110 #define AI_SC_Save_Trace _bit10
111 #define AI_SI_Switch_Load_On_SC_TC _bit9
112 #define AI_SI_Switch_Load_On_STOP _bit8
113 #define AI_SI_Switch_Load_On_TC _bit7
114 #define AI_SC_Switch_Load_On_TC _bit4
115 #define AI_STOP_Pulse _bit3
116 #define AI_START_Pulse _bit2
117 #define AI_START2_Pulse _bit1
118 #define AI_START1_Pulse _bit0
120 #define AO_Command_2_Register 5
121 #define AO_End_On_BC_TC(x) ((x)<<14)
122 #define AO_Start_Stop_Gate_Enable _bit13
123 #define AO_UC_Save_Trace _bit12
124 #define AO_BC_Gate_Enable _bit11
125 #define AO_BC_Save_Trace _bit10
126 #define AO_UI_Switch_Load_On_BC_TC _bit9
127 #define AO_UI_Switch_Load_On_Stop _bit8
128 #define AO_UI_Switch_Load_On_TC _bit7
129 #define AO_UC_Switch_Load_On_BC_TC _bit6
130 #define AO_UC_Switch_Load_On_TC _bit5
131 #define AO_BC_Switch_Load_On_TC _bit4
132 #define AO_Mute_B _bit3
133 #define AO_Mute_A _bit2
134 #define AO_UPDATE2_Pulse _bit1
135 #define AO_START1_Pulse _bit0
137 #define AO_Status_2_Register 6
139 #define DIO_Parallel_Input_Register 7
140 #define DIO_SDIN _bit4
142 #define AI_Command_1_Register 8
143 #define AI_Analog_Trigger_Reset _bit14
144 #define AI_Disarm _bit13
145 #define AI_SI2_Arm _bit12
146 #define AI_SI2_Load _bit11
147 #define AI_SI_Arm _bit10
148 #define AI_SI_Load _bit9
149 #define AI_DIV_Arm _bit8
150 #define AI_DIV_Load _bit7
151 #define AI_SC_Arm _bit6
152 #define AI_SC_Load _bit5
153 #define AI_SCAN_IN_PROG_Pulse _bit4
154 #define AI_EXTMUX_CLK_Pulse _bit3
155 #define AI_LOCALMUX_CLK_Pulse _bit2
156 #define AI_SC_TC_Pulse _bit1
157 #define AI_CONVERT_Pulse _bit0
159 #define AO_Command_1_Register 9
160 #define AO_Analog_Trigger_Reset _bit15
161 #define AO_START_Pulse _bit14
162 #define AO_Disarm _bit13
163 #define AO_UI2_Arm_Disarm _bit12
164 #define AO_UI2_Load _bit11
165 #define AO_UI_Arm _bit10
166 #define AO_UI_Load _bit9
167 #define AO_UC_Arm _bit8
168 #define AO_UC_Load _bit7
169 #define AO_BC_Arm _bit6
170 #define AO_BC_Load _bit5
171 #define AO_DAC1_Update_Mode _bit4
172 #define AO_LDAC1_Source_Select _bit3
173 #define AO_DAC0_Update_Mode _bit2
174 #define AO_LDAC0_Source_Select _bit1
175 #define AO_UPDATE_Pulse _bit0
178 #define DIO_Output_Register 10
179 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
180 #define DIO_Parallel_Data_Mask 0xff
181 #define DIO_SDOUT _bit0
182 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
183 #define DIO_Serial_Data_Mask 0xff00
185 #define DIO_Control_Register 11
186 #define DIO_Software_Serial_Control _bit11
187 #define DIO_HW_Serial_Timebase _bit10
188 #define DIO_HW_Serial_Enable _bit9
189 #define DIO_HW_Serial_Start _bit8
190 #define DIO_Pins_Dir(a) ((a)&0xff)
191 #define DIO_Pins_Dir_Mask 0xff
193 #define AI_Mode_1_Register 12
194 #define AI_CONVERT_Source_Select(a) ((a)<<11)
195 #define AI_SI_Source_select(a) ((a)<<6)
196 #define AI_CONVERT_Source_Polarity _bit5
197 #define AI_Start_Stop _bit3
198 #define AI_Mode_1_Reserved _bit2
199 #define AI_Continuous _bit1
200 #define AI_Trigger_Once _bit0
202 #define AI_Mode_2_Register 13
203 #define AI_SC_Gate_Enable _bit15
204 #define AI_Start_Stop_Gate_Enable _bit14
205 #define AI_Pre_Trigger _bit13
206 #define AI_External_MUX_Present _bit12
207 #define AI_SI2_Initial_Load_Source _bit9
208 #define AI_SI2_Reload_Mode _bit8
209 #define AI_SI_Initial_Load_Source _bit7
210 #define AI_SI_Reload_Mode(a) ((a)<<4)
211 #define AI_SI_Write_Switch _bit3
212 #define AI_SC_Initial_Load_Source _bit2
213 #define AI_SC_Reload_Mode _bit1
214 #define AI_SC_Write_Switch _bit0
216 #define AI_SI_Load_A_Registers 14
217 #define AI_SI_Load_B_Registers 16
218 #define AI_SC_Load_A_Registers 18
219 #define AI_SC_Load_B_Registers 20
220 #define AI_SI2_Load_A_Register 23
221 #define AI_SI2_Load_B_Register 25
223 #define Joint_Status_1_Register 27
224 #define DIO_Serial_IO_In_Progress_St _bit12
226 #define DIO_Serial_Input_Register 28
227 #define Joint_Status_2_Register 29
229 #define AO_Mode_1_Register 38
230 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
231 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
232 #define AO_Multiple_Channels _bit5
233 #define AO_UPDATE_Source_Polarity _bit4
234 #define AO_UI_Source_Polarity _bit3
235 #define AO_UC_Switch_Load_Every_TC _bit2
236 #define AO_Continuous _bit1
237 #define AO_Trigger_Once _bit0
239 #define AO_Mode_2_Register 39
240 #define AO_FIFO_Mode_Mask ( 0x3 << 14 )
241 enum AO_FIFO_Mode_Bits
243 AO_FIFO_Mode_HF_to_F = (3<<14),
244 AO_FIFO_Mode_F = (2<<14),
245 AO_FIFO_Mode_HF = (1<<14),
246 AO_FIFO_Mode_E = (0<<14),
248 #define AO_FIFO_Retransmit_Enable _bit13
249 #define AO_START1_Disable _bit12
250 #define AO_UC_Initial_Load_Source _bit11
251 #define AO_UC_Write_Switch _bit10
252 #define AO_UI2_Initial_Load_Source _bit9
253 #define AO_UI2_Reload_Mode _bit8
254 #define AO_UI_Initial_Load_Source _bit7
255 #define AO_UI_Reload_Mode(x) ((x)<<4)
256 #define AO_UI_Write_Switch _bit3
257 #define AO_BC_Initial_Load_Source _bit2
258 #define AO_BC_Reload_Mode _bit1
259 #define AO_BC_Write_Switch _bit0
261 #define AO_UI_Load_A_Register 40
262 #define AO_UI_Load_A_Register_High 40
263 #define AO_UI_Load_A_Register_Low 41
264 #define AO_BC_Load_A_Register 44
265 #define AO_BC_Load_A_Register_High 44
266 #define AO_BC_Load_A_Register_Low 45
267 #define AO_BC_Load_B_Register 46
268 #define AO_BC_Load_B_Register_High 46
269 #define AO_BC_Load_B_Register_Low 47
270 #define AO_UC_Load_A_Register 48
271 #define AO_UC_Load_A_Register_High 48
272 #define AO_UC_Load_A_Register_Low 49
274 #define Clock_and_FOUT_Register 56
275 #define FOUT_Enable _bit15
276 #define FOUT_Timebase_Select _bit14
277 #define DIO_Serial_Out_Divide_By_2 _bit13
278 #define Slow_Internal_Time_Divide_By_2 _bit12
279 #define Slow_Internal_Timebase _bit11
280 #define G_Source_Divide_By_2 _bit10
281 #define Clock_To_Board_Divide_By_2 _bit9
282 #define Clock_To_Board _bit8
283 #define AI_Output_Divide_By_2 _bit7
284 #define AI_Source_Divide_By_2 _bit6
285 #define AO_Output_Divide_By_2 _bit5
286 #define AO_Source_Divide_By_2 _bit4
287 #define FOUT_Divider(x) ((x)<<0)
289 #define IO_Bidirection_Pin_Register 57
291 #define Interrupt_Control_Register 59
292 #define Interrupt_B_Enable _bit15
293 #define Interrupt_B_Output_Select(x) ((x)<<12)
294 #define Interrupt_A_Enable _bit11
295 #define Interrupt_A_Output_Select(x) ((x)<<8)
296 #define Pass_Thru_0_Interrupt_Polarity _bit3
297 #define Pass_Thru_1_Interrupt_Polarity _bit2
298 #define Interrupt_Output_On_3_Pins _bit1
299 #define Interrupt_Output_Polarity _bit0
301 #define AI_Output_Control_Register 60
302 #define AI_START_Output_Select _bit10
303 #define AI_SCAN_IN_PROG_Output_Select(x) ((x)<<8)
304 #define AI_EXTMUX_CLK_Output_Select(x) ((x)<<6)
305 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
306 #define AI_SC_TC_Output_Select(x) ((x)<<2)
307 #define AI_CONVERT_Output_Select(x) ((x)<<0)
309 #define AI_START_STOP_Select_Register 62
310 #define AI_START_Polarity _bit15
311 #define AI_STOP_Polarity _bit14
312 #define AI_STOP_Sync _bit13
313 #define AI_STOP_Edge _bit12
314 #define AI_STOP_Select(a) ((a)<<7)
315 #define AI_START_Sync _bit6
316 #define AI_START_Edge _bit5
317 #define AI_START_Select(a) (a)
319 #define AI_Trigger_Select_Register 63
320 #define AI_START1_Polarity _bit15
321 #define AI_START2_Polarity _bit14
322 #define AI_START2_Sync _bit13
323 #define AI_START2_Edge _bit12
324 #define AI_START2_Select(a) ((a)<<7)
325 #define AI_START1_Sync _bit6
326 #define AI_START1_Edge _bit5
327 #define AI_START1_Select(a) (a)
329 #define AO_Start_Select_Register 66
330 #define AO_UI2_Software_Gate _bit15
331 #define AO_UI2_External_Gate_Polarity _bit14
332 #define AO_START_Polarity _bit13
333 #define AO_AOFREQ_Enable _bit12
334 #define AO_UI2_External_Gate_Select(a) ((a)<<7)
335 #define AO_START_Sync _bit6
336 #define AO_START_Edge _bit5
337 #define AO_START_Select(a) (a)
339 #define AO_Trigger_Select_Register 67
340 #define AO_UI2_External_Gate_Enable _bit15
341 #define AO_Delayed_START1 _bit14
342 #define AO_START1_Polarity _bit13
343 #define AO_UI2_Source_Polarity _bit12
344 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
345 #define AO_START1_Sync _bit6
346 #define AO_START1_Edge _bit5
347 #define AO_START1_Select(x) (((x)&0x1f)<<0)
349 #define AO_Mode_3_Register 70
350 #define AO_UI2_Switch_Load_Next_TC _bit13
351 #define AO_UC_Switch_Load_Every_BC_TC _bit12
352 #define AO_Trigger_Length _bit11
353 #define AO_Stop_On_Overrun_Error _bit5
354 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
355 #define AO_Stop_On_BC_TC_Error _bit3
356 #define AO_Not_An_UPDATE _bit2
357 #define AO_Software_Gate _bit1
359 #define Joint_Reset_Register 72
360 #define AO_Configuration_End _bit9
361 #define AI_Configuration_End _bit8
362 #define AO_Configuration_Start _bit5
363 #define AI_Configuration_Start _bit4
364 #define AO_Reset _bit1
365 #define AI_Reset _bit0
367 #define Interrupt_A_Enable_Register 73
368 #define Pass_Thru_0_Interrupt_Enable _bit9
369 #define G0_Gate_Interrupt_Enable _bit8
370 #define AI_FIFO_Interrupt_Enable _bit7
371 #define G0_TC_Interrupt_Enable _bit6
372 #define AI_Error_Interrupt_Enable _bit5
373 #define AI_STOP_Interrupt_Enable _bit4
374 #define AI_START_Interrupt_Enable _bit3
375 #define AI_START2_Interrupt_Enable _bit2
376 #define AI_START1_Interrupt_Enable _bit1
377 #define AI_SC_TC_Interrupt_Enable _bit0
379 #define Interrupt_B_Enable_Register 75
380 #define Pass_Thru_1_Interrupt_Enable _bit11
381 #define G1_Gate_Interrupt_Enable _bit10
382 #define G1_TC_Interrupt_Enable _bit9
383 #define AO_FIFO_Interrupt_Enable _bit8
384 #define AO_UI2_TC_Interrupt_Enable _bit7
385 #define AO_UC_TC_Interrupt_Enable _bit6
386 #define AO_Error_Interrupt_Enable _bit5
387 #define AO_STOP_Interrupt_Enable _bit4
388 #define AO_START_Interrupt_Enable _bit3
389 #define AO_UPDATE_Interrupt_Enable _bit2
390 #define AO_START1_Interrupt_Enable _bit1
391 #define AO_BC_TC_Interrupt_Enable _bit0
393 #define Second_IRQ_B_Enable_Register 76
394 #define AI_Personal_Register 77
395 #define AI_SHIFTIN_Pulse_Width _bit15
396 #define AI_EOC_Polarity _bit14
397 #define AI_SOC_Polarity _bit13
398 #define AI_SHIFTIN_Polarity _bit12
399 #define AI_CONVERT_Pulse_Timebase _bit11
400 #define AI_CONVERT_Pulse_Width _bit10
401 #define AI_CONVERT_Original_Pulse _bit9
402 #define AI_FIFO_Flags_Polarity _bit8
403 #define AI_Overrun_Mode _bit7
404 #define AI_EXTMUX_CLK_Pulse_Width _bit6
405 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
406 #define AI_AIFREQ_Polarity _bit4
408 #define AO_Personal_Register 78
409 enum AO_Personal_Bits
411 AO_BC_Source_Select = 1 << 4,
412 AO_UPDATE_Pulse_Width = 1 << 5,
413 AO_AOFREQ_Polarity = 1 << 9,
414 AO_FIFO_Enable = 1 << 10,
415 AO_TMRDACWR_Pulse_Width = 1 << 12,
417 #define Write_Strobe_0_Register 82
418 #define Write_Strobe_1_Register 83
419 #define Write_Strobe_2_Register 84
420 #define Write_Strobe_3_Register 85
422 #define AO_Output_Control_Register 86
423 #define AO_External_Gate_Enable _bit15
424 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
425 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
426 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
427 #define AO_External_Gate_Polarity _bit3
428 #define AO_UPDATE2_Output_Toggle _bit2
429 #define AO_UPDATE_Output_Select(x) (((x)&0x3)<<0)
431 #define AI_Mode_3_Register 87
432 #define AI_Trigger_Length _bit15
433 #define AI_Delay_START _bit14
434 #define AI_Software_Gate _bit13
435 #define AI_SI_Special_Trigger_Delay _bit12
436 #define AI_SI2_Source_Select _bit11
437 #define AI_Delayed_START2 _bit10
438 #define AI_Delayed_START1 _bit9
439 #define AI_External_Gate_Mode _bit8
440 #define AI_FIFO_Mode_HF_to_E (3<<6)
441 #define AI_FIFO_Mode_F (2<<6)
442 #define AI_FIFO_Mode_HF (1<<6)
443 #define AI_FIFO_Mode_NE (0<<6)
444 #define AI_External_Gate_Polarity _bit5
445 #define AI_External_Gate_Select(a) (a)
447 #define G_Autoincrement_Register(a) (68+(a))
448 #define G_Command_Register(a) (6+(a))
449 #define G_HW_Save_Register(a) (8+(a)*2)
450 #define G_HW_Save_Register_High(a) (8+(a)*2)
451 #define G_HW_Save_Register_Low(a) (9+(a)*2)
452 #define G_Input_Select_Register(a) (36+(a))
453 #define G_Load_A_Register(a) (28+(a)*4)
454 #define G_Load_A_Register_High(a) (28+(a)*4)
455 #define G_Load_A_Register_Low(a) (29+(a)*4)
456 #define G_Load_B_Register(a) (30+(a)*4)
457 #define G_Load_B_Register_High(a) (30+(a)*4)
458 #define G_Load_B_Register_Low(a) (31+(a)*4)
459 #define G_Mode_Register(a) (26+(a))
460 #define G_Save_Register(a) (12+(a)*2)
461 #define G_Save_Register_High(a) (12+(a)*2)
462 #define G_Save_Register_Low(a) (13+(a)*2)
463 #define G_Status_Register 4
464 #define Analog_Trigger_Etc_Register 61
466 /* command register */
467 #define G_Disarm_Copy _bit15 /* strobe */
468 #define G_Save_Trace_Copy _bit14
469 #define G_Arm_Copy _bit13 /* strobe */
470 #define G_Bank_Switch_Start _bit10 /* strobe */
471 #define G_Little_Big_Endian _bit9
472 #define G_Synchronized_Gate _bit8
473 #define G_Write_Switch _bit7
474 #define G_Up_Down(a) (((a)&0x03)<<5)
475 #define G_Disarm _bit4 /* strobe */
476 #define G_Analog_Trigger_Reset _bit3 /* strobe */
477 #define G_Save_Trace _bit1
478 #define G_Arm _bit0 /* strobe */
480 /*channel agnostic names for the command register #defines */
481 #define G_Bank_Switch_Enable _bit12
482 #define G_Bank_Switch_Mode _bit11
483 #define G_Load _bit2 /* strobe */
486 /* input select register */
487 #define G_Gate_Select(a) (((a)&0x1f)<<7)
488 #define G_Source_Select(a) (((a)&0x1f)<<2)
489 #define G_Write_Acknowledges_Irq _bit1
490 #define G_Read_Acknowledges_Irq _bit0
492 /* same input select register, but with channel agnostic names */
493 #define G_Source_Polarity _bit15
494 #define G_Output_Polarity _bit14
495 #define G_OR_Gate _bit13
496 #define G_Gate_Select_Load_Source _bit12
500 #define G_Loading_On_TC _bit12
501 #define G_Output_Mode(a) (((a)&0x03)<<8)
502 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
503 #define G_Gating_Mode(a) (((a)&0x03)<<0)
505 /* same input mode register, but with channel agnostic names */
506 #define G_Load_Source_Select _bit7
507 #define G_Reload_Source_Switching _bit15
508 #define G_Loading_On_Gate _bit14
509 #define G_Gate_Polarity _bit13
511 #define G_Counting_Once(a) (((a)&0x03)<<10)
512 #define G_Stop_Mode(a) (((a)&0x03)<<5)
513 #define G_Gate_On_Both_Edges _bit2
515 /* G_Status_Register */
516 #define G1_Gate_Error_St _bit15
517 #define G0_Gate_Error_St _bit14
518 #define G1_TC_Error_St _bit13
519 #define G0_TC_Error_St _bit12
520 #define G1_No_Load_Between_Gates_St _bit11
521 #define G0_No_Load_Between_Gates_St _bit10
522 #define G1_Armed_St _bit9
523 #define G0_Armed_St _bit8
524 #define G1_Stale_Data_St _bit7
525 #define G0_Stale_Data_St _bit6
526 #define G1_Next_Load_Source_St _bit5
527 #define G0_Next_Load_Source_St _bit4
528 #define G1_Counting_St _bit3
529 #define G0_Counting_St _bit2
530 #define G1_Save_St _bit1
531 #define G0_Save_St _bit0
533 /* general purpose counter timer */
534 #define G0_Reset _bit2
535 #define G1_Reset _bit3
536 #define G0_TC_Interrupt_Enable _bit6
537 #define G1_TC_Interrupt_Enable _bit9
538 #define G0_Gate_Interrupt_Enable _bit8
539 #define G1_Gate_Interrupt_Enable _bit10
540 #define G0_Synchronized_Gate _bit8
541 #define G1_Synchronized_Gate _bit8
542 #define G0_Gate_Error_Confirm _bit5
543 #define G1_Gate_Error_Confirm _bit1
544 #define G0_TC_Error_Confirm _bit6
545 #define G1_TC_Error_Confirm _bit2
546 #define G0_TC_Interrupt_Ack _bit14
547 #define G1_TC_Interrupt_Ack _bit14
548 #define G0_Gate_Interrupt_Ack _bit15
549 #define G1_Gate_Interrupt_Ack _bit15
550 #define G_Autoincrement(a) ((a)<<0)
551 #define G_Autoincrement(a) ((a)<<0)
555 /*Analog_Trigger_Etc_Register*/
556 /*This is mainly a counter/timer register */
557 #define GPFO_1_Output_Enable _bit15
558 #define GPFO_0_Output_Enable _bit14
559 #define GPFO_0_Output_Select(a) ((a)<<11)
560 #define GPFO_1_Output_Select _bit7
562 /* Additional windowed registers unique to E series */
564 /* 16 bit registers shadowed from DAQ-STC */
565 #define Window_Address 0x00
566 #define Window_Data 0x02
568 #define Interrupt_A_Ack 0x04
569 #define AI_Status_1 0x04
570 #define Interrupt_B_Ack 0x06
571 #define AO_Status_1 0x06
572 #define AI_Command_2 0x08
573 #define G_Status 0x08
574 #define AO_Command_2 0x0a
575 #define AI_Status_2 0x0a
576 #define G0_Command 0x0c
577 #define AO_Status_2 0x0c
578 #define G1_Command 0x0e
579 #define DIO_Parallel_Input 0x0e
582 #define Configuration_Memory_Clear 82
583 #define ADC_FIFO_Clear 83
584 #define DAC_FIFO_Clear 84
587 /* i/o port offsets */
589 /* 8 bit registers */
590 #define XXX_Status 0x01
591 #define Serial_Command 0x0d
592 #define Misc_Command 0x0f
596 #define Configuration 0x1f
598 #define Channel_A_Mode 0x03
599 #define Channel_B_Mode 0x05
600 #define Channel_C_Mode 0x07
601 #define AI_AO_Select 0x09
602 #define G0_G1_Select 0x0b
604 /* 16 bit registers */
606 #define Configuration_Memory_Low 0x10
607 enum Configuration_Memory_Low_Bits
610 AI_LAST_CHANNEL = 0x8000,
612 #define Configuration_Memory_High 0x12
613 enum Configuration_Memory_High_Bits
615 AI_AC_COUPLE = 0x800,
616 AI_DIFFERENTIAL = 0x1000,
620 static inline unsigned int AI_CONFIG_CHANNEL( unsigned int channel )
622 return ( channel & 0x3f );
625 #define ADC_FIFO_Data_Register 0x1c
627 #define AO_Configuration 0x16
628 #define AO_Bipolar _bit0
629 #define AO_Deglitch _bit1
630 #define AO_Ext_Ref _bit2
631 #define AO_Ground_Ref _bit3
632 #define AO_Channel(x) ((x) << 8)
634 #define DAC_FIFO_Data 0x1e
635 #define DAC0_Direct_Data 0x18
636 #define DAC1_Direct_Data 0x1a
639 /* 611x registers (these boards differ from the e-series) */
641 #define Magic_611x 0x19 /* w8 (new) */
642 #define Status_611x 0x01 /* r8 (additional bits) */
643 enum Status_611x_Bits
645 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
647 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
648 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
649 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
650 #define AO_FIFO_Offset_Load_611x 0x13 /* W32? */
651 #define AO_Configuration_611x 0x16 /* w16 */
652 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
653 #define AO_Window_Addr_611x 0x18 /* w16 */
654 #define AO_Window_Data_611x 0x1e /* w16 */
655 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
657 /* AO Windowed registers */
659 /* 671x, 611x registers */
661 #define AO_Window_Address_671x 0x18 /* W 16 */
662 #define AO_Window_Data_671x 0x1e /* W 16 */
664 /* 671xi, 611x windowed ao registers */
666 #define DACx_Direct_Data_671x(x) (x) /* W 16 */
667 #define AO_Immediate_671x 0x11 /* W 16 */
668 #define AO_Timed_611x 0x10 /* W 16 */
669 #define AO_Later_Single_Point_Updates 0x14 /* W 16 */
670 #define AO_Waveform_Generation_611x 0x15 /* W 16 */
671 #define AO_Misc_611x 0x16 /* W 16 */
672 enum AO_Misc_611x_Bits
677 #define SerDacLd(x) (0x08<<(x))
680 This is stuff unique to the NI E series drivers,
681 but I thought I'd put it here anyway.
684 /* our default usage of mite channels */
685 enum mite_dma_channel{
692 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x };
693 enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
694 ad8804, ad8842, ad8804_debug };
696 typedef struct ni_board_struct{
705 unsigned int alwaysdither : 1;
715 unsigned int ao_unipolar : 1;
716 unsigned int has_8255 : 1;
717 unsigned int has_analog_trig : 1;
718 unsigned int ao_671x : 1;
719 unsigned int reg_611x : 1;
721 enum caldac_enum caldac[3];
724 static ni_board ni_boards[];
725 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
727 #define boardtype (*(ni_board *)dev->board_ptr)
729 #define NI_PRIVATE_COMMON \
730 unsigned short dio_output; \
731 unsigned short dio_control; \
741 unsigned int ai_calib_source; \
743 int changain_state; \
744 unsigned int changain_spec; \
746 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
747 unsigned short ao[2]; \
748 unsigned short caldacs[12]; \
750 unsigned short ao_conf[2]; \
751 unsigned short ao_mode1; \
752 unsigned short ao_mode2; \
753 unsigned short ao_mode3; \
754 unsigned short ao_cmd1; \
755 unsigned short ao_cmd2; \
756 unsigned short ao_cmd3; \
757 unsigned short ao_trigger_select; \
759 unsigned short gpct_mode[2]; \
760 unsigned short gpct_command[2]; \
761 unsigned short gpct_input_select[2]; \
762 int gpct_cur_operation[2]; \
763 unsigned short an_trig_etc_reg; \
765 unsigned short ai_offset[512]; \
767 unsigned long serial_interval_ns; \
768 unsigned char serial_hw_mode; \
769 unsigned short clock_and_fout; \
771 volatile unsigned short int_a_enable_reg; \
772 volatile unsigned short int_b_enable_reg; \
773 unsigned short io_bidirection_pin_reg; \
775 unsigned short atrig_mode; \
776 unsigned short atrig_high; \
777 unsigned short atrig_low; \
779 #endif /* _COMEDI_NI_STC_H */