3 Register descriptions for NI DAQ-STC chip
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 DAQ-STC Technical Reference Manual
29 #ifndef _COMEDI_NI_STC_H
30 #define _COMEDI_NI_STC_H
51 #define NUM_PFI_OUTPUT_SELECT_REGS 6
53 /* Registers in the National Instruments DAQ-STC chip */
55 #define Interrupt_A_Ack_Register 2
56 #define G0_Gate_Interrupt_Ack _bit15
57 #define G0_TC_Interrupt_Ack _bit14
58 #define AI_Error_Interrupt_Ack _bit13
59 #define AI_STOP_Interrupt_Ack _bit12
60 #define AI_START_Interrupt_Ack _bit11
61 #define AI_START2_Interrupt_Ack _bit10
62 #define AI_START1_Interrupt_Ack _bit9
63 #define AI_SC_TC_Interrupt_Ack _bit8
64 #define AI_SC_TC_Error_Confirm _bit7
65 #define G0_TC_Error_Confirm _bit6
66 #define G0_Gate_Error_Confirm _bit5
68 #define AI_Status_1_Register 2
69 #define Interrupt_A_St 0x8000
70 #define AI_FIFO_Full_St 0x4000
71 #define AI_FIFO_Half_Full_St 0x2000
72 #define AI_FIFO_Empty_St 0x1000
73 #define AI_Overrun_St 0x0800
74 #define AI_Overflow_St 0x0400
75 #define AI_SC_TC_Error_St 0x0200
76 #define AI_START2_St 0x0100
77 #define AI_START1_St 0x0080
78 #define AI_SC_TC_St 0x0040
79 #define AI_START_St 0x0020
80 #define AI_STOP_St 0x0010
81 #define G0_TC_St 0x0008
82 #define G0_Gate_Interrupt_St 0x0004
83 #define AI_FIFO_Request_St 0x0002
84 #define Pass_Thru_0_Interrupt_St 0x0001
86 #define AI_Status_2_Register 5
88 #define Interrupt_B_Ack_Register 3
89 enum Interrupt_B_Ack_Bits
91 AO_BC_TC_Interrupt_Ack = _bit8,
92 AO_Error_Interrupt_Ack = _bit13,
95 #define AO_Status_1_Register 3
96 #define Interrupt_B_St _bit15
97 #define AO_FIFO_Full_St _bit14
98 #define AO_FIFO_Half_Full_St _bit13
99 #define AO_FIFO_Empty_St _bit12
100 #define AO_BC_TC_Error_St _bit11
101 #define AO_START_St _bit10
102 #define AO_Overrun_St _bit9
103 #define AO_START1_St _bit8
104 #define AO_BC_TC_St _bit7
105 #define AO_UC_TC_St _bit6
106 #define AO_UPDATE_St _bit5
107 #define AO_UI2_TC_St _bit4
108 #define G1_TC_St _bit3
109 #define G1_Gate_Interrupt_St _bit2
110 #define AO_FIFO_Request_St _bit1
111 #define Pass_Thru_1_Interrupt_St _bit0
114 #define AI_Command_2_Register 4
115 #define AI_End_On_SC_TC _bit15
116 #define AI_End_On_End_Of_Scan _bit14
117 #define AI_START1_Disable _bit11
118 #define AI_SC_Save_Trace _bit10
119 #define AI_SI_Switch_Load_On_SC_TC _bit9
120 #define AI_SI_Switch_Load_On_STOP _bit8
121 #define AI_SI_Switch_Load_On_TC _bit7
122 #define AI_SC_Switch_Load_On_TC _bit4
123 #define AI_STOP_Pulse _bit3
124 #define AI_START_Pulse _bit2
125 #define AI_START2_Pulse _bit1
126 #define AI_START1_Pulse _bit0
128 #define AO_Command_2_Register 5
129 #define AO_End_On_BC_TC(x) (((x) & 0x3) << 14)
130 #define AO_Start_Stop_Gate_Enable _bit13
131 #define AO_UC_Save_Trace _bit12
132 #define AO_BC_Gate_Enable _bit11
133 #define AO_BC_Save_Trace _bit10
134 #define AO_UI_Switch_Load_On_BC_TC _bit9
135 #define AO_UI_Switch_Load_On_Stop _bit8
136 #define AO_UI_Switch_Load_On_TC _bit7
137 #define AO_UC_Switch_Load_On_BC_TC _bit6
138 #define AO_UC_Switch_Load_On_TC _bit5
139 #define AO_BC_Switch_Load_On_TC _bit4
140 #define AO_Mute_B _bit3
141 #define AO_Mute_A _bit2
142 #define AO_UPDATE2_Pulse _bit1
143 #define AO_START1_Pulse _bit0
145 #define AO_Status_2_Register 6
147 #define DIO_Parallel_Input_Register 7
149 #define AI_Command_1_Register 8
150 #define AI_Analog_Trigger_Reset _bit14
151 #define AI_Disarm _bit13
152 #define AI_SI2_Arm _bit12
153 #define AI_SI2_Load _bit11
154 #define AI_SI_Arm _bit10
155 #define AI_SI_Load _bit9
156 #define AI_DIV_Arm _bit8
157 #define AI_DIV_Load _bit7
158 #define AI_SC_Arm _bit6
159 #define AI_SC_Load _bit5
160 #define AI_SCAN_IN_PROG_Pulse _bit4
161 #define AI_EXTMUX_CLK_Pulse _bit3
162 #define AI_LOCALMUX_CLK_Pulse _bit2
163 #define AI_SC_TC_Pulse _bit1
164 #define AI_CONVERT_Pulse _bit0
166 #define AO_Command_1_Register 9
167 #define AO_Analog_Trigger_Reset _bit15
168 #define AO_START_Pulse _bit14
169 #define AO_Disarm _bit13
170 #define AO_UI2_Arm_Disarm _bit12
171 #define AO_UI2_Load _bit11
172 #define AO_UI_Arm _bit10
173 #define AO_UI_Load _bit9
174 #define AO_UC_Arm _bit8
175 #define AO_UC_Load _bit7
176 #define AO_BC_Arm _bit6
177 #define AO_BC_Load _bit5
178 #define AO_DAC1_Update_Mode _bit4
179 #define AO_LDAC1_Source_Select _bit3
180 #define AO_DAC0_Update_Mode _bit2
181 #define AO_LDAC0_Source_Select _bit1
182 #define AO_UPDATE_Pulse _bit0
185 #define DIO_Output_Register 10
186 #define DIO_Parallel_Data_Out(a) ((a)&0xff)
187 #define DIO_Parallel_Data_Mask 0xff
188 #define DIO_SDOUT _bit0
189 #define DIO_SDIN _bit4
190 #define DIO_Serial_Data_Out(a) (((a)&0xff)<<8)
191 #define DIO_Serial_Data_Mask 0xff00
193 #define DIO_Control_Register 11
194 #define DIO_Software_Serial_Control _bit11
195 #define DIO_HW_Serial_Timebase _bit10
196 #define DIO_HW_Serial_Enable _bit9
197 #define DIO_HW_Serial_Start _bit8
198 #define DIO_Pins_Dir(a) ((a)&0xff)
199 #define DIO_Pins_Dir_Mask 0xff
201 #define AI_Mode_1_Register 12
202 #define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11)
203 #define AI_SI_Source_select(a) (((a) & 0x1f) << 6)
204 #define AI_CONVERT_Source_Polarity _bit5
205 #define AI_SI_Source_Polarity _bit4
206 #define AI_Start_Stop _bit3
207 #define AI_Mode_1_Reserved _bit2
208 #define AI_Continuous _bit1
209 #define AI_Trigger_Once _bit0
211 #define AI_Mode_2_Register 13
212 #define AI_SC_Gate_Enable _bit15
213 #define AI_Start_Stop_Gate_Enable _bit14
214 #define AI_Pre_Trigger _bit13
215 #define AI_External_MUX_Present _bit12
216 #define AI_SI2_Initial_Load_Source _bit9
217 #define AI_SI2_Reload_Mode _bit8
218 #define AI_SI_Initial_Load_Source _bit7
219 #define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4)
220 #define AI_SI_Write_Switch _bit3
221 #define AI_SC_Initial_Load_Source _bit2
222 #define AI_SC_Reload_Mode _bit1
223 #define AI_SC_Write_Switch _bit0
225 #define AI_SI_Load_A_Registers 14
226 #define AI_SI_Load_B_Registers 16
227 #define AI_SC_Load_A_Registers 18
228 #define AI_SC_Load_B_Registers 20
229 #define AI_SI_Save_Registers 64
230 #define AI_SC_Save_Registers 66
232 #define AI_SI2_Load_A_Register 23
233 #define AI_SI2_Load_B_Register 25
235 #define Joint_Status_1_Register 27
236 #define DIO_Serial_IO_In_Progress_St _bit12
238 #define DIO_Serial_Input_Register 28
239 #define Joint_Status_2_Register 29
240 enum Joint_Status_2_Bits
242 AO_TMRDACWRs_In_Progress_St = 0x20,
245 #define AO_Mode_1_Register 38
246 #define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11)
247 #define AO_UI_Source_Select(x) (((x)&0x1f)<<6)
248 #define AO_Multiple_Channels _bit5
249 #define AO_UPDATE_Source_Polarity _bit4
250 #define AO_UI_Source_Polarity _bit3
251 #define AO_UC_Switch_Load_Every_TC _bit2
252 #define AO_Continuous _bit1
253 #define AO_Trigger_Once _bit0
255 #define AO_Mode_2_Register 39
256 #define AO_FIFO_Mode_Mask ( 0x3 << 14 )
257 enum AO_FIFO_Mode_Bits
259 AO_FIFO_Mode_HF_to_F = (3<<14),
260 AO_FIFO_Mode_F = (2<<14),
261 AO_FIFO_Mode_HF = (1<<14),
262 AO_FIFO_Mode_E = (0<<14),
264 #define AO_FIFO_Retransmit_Enable _bit13
265 #define AO_START1_Disable _bit12
266 #define AO_UC_Initial_Load_Source _bit11
267 #define AO_UC_Write_Switch _bit10
268 #define AO_UI2_Initial_Load_Source _bit9
269 #define AO_UI2_Reload_Mode _bit8
270 #define AO_UI_Initial_Load_Source _bit7
271 #define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4)
272 #define AO_UI_Write_Switch _bit3
273 #define AO_BC_Initial_Load_Source _bit2
274 #define AO_BC_Reload_Mode _bit1
275 #define AO_BC_Write_Switch _bit0
277 #define AO_UI_Load_A_Register 40
278 #define AO_UI_Load_A_Register_High 40
279 #define AO_UI_Load_A_Register_Low 41
280 #define AO_UI_Load_B_Register 42
281 #define AO_UI_Save_Registers 16
282 #define AO_BC_Load_A_Register 44
283 #define AO_BC_Load_A_Register_High 44
284 #define AO_BC_Load_A_Register_Low 45
285 #define AO_BC_Load_B_Register 46
286 #define AO_BC_Load_B_Register_High 46
287 #define AO_BC_Load_B_Register_Low 47
288 #define AO_BC_Save_Registers 18
289 #define AO_UC_Load_A_Register 48
290 #define AO_UC_Load_A_Register_High 48
291 #define AO_UC_Load_A_Register_Low 49
292 #define AO_UC_Load_B_Register 50
293 #define AO_UC_Save_Registers 20
295 #define Clock_and_FOUT_Register 56
296 #define FOUT_Enable _bit15
297 #define FOUT_Timebase_Select _bit14
298 #define DIO_Serial_Out_Divide_By_2 _bit13
299 #define Slow_Internal_Time_Divide_By_2 _bit12
300 #define Slow_Internal_Timebase _bit11
301 #define G_Source_Divide_By_2 _bit10
302 #define Clock_To_Board_Divide_By_2 _bit9
303 #define Clock_To_Board _bit8
304 #define AI_Output_Divide_By_2 _bit7
305 #define AI_Source_Divide_By_2 _bit6
306 #define AO_Output_Divide_By_2 _bit5
307 #define AO_Source_Divide_By_2 _bit4
308 #define FOUT_Divider(x) (((x) & 0xf) << 0)
310 #define IO_Bidirection_Pin_Register 57
311 #define RTSI_Trig_Direction_Register 58
312 enum RTSI_Trig_Direction_Bits
314 Drive_RTSI_Clock_Bit = 0x1,
315 Use_RTSI_Clock_Bit = 0x2,
317 static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries)
319 unsigned max_channel;
320 unsigned base_bit_shift;
330 if(channel > max_channel)
332 rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, channel);
335 return 1 << (base_bit_shift + channel);
338 #define Interrupt_Control_Register 59
339 #define Interrupt_B_Enable _bit15
340 #define Interrupt_B_Output_Select(x) ((x)<<12)
341 #define Interrupt_A_Enable _bit11
342 #define Interrupt_A_Output_Select(x) ((x)<<8)
343 #define Pass_Thru_0_Interrupt_Polarity _bit3
344 #define Pass_Thru_1_Interrupt_Polarity _bit2
345 #define Interrupt_Output_On_3_Pins _bit1
346 #define Interrupt_Output_Polarity _bit0
348 #define AI_Output_Control_Register 60
349 #define AI_START_Output_Select _bit10
350 #define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
351 #define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6)
352 #define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4)
353 #define AI_SC_TC_Output_Select(x) ((x)<<2)
354 enum ai_convert_output_selection
356 AI_CONVERT_Output_High_Z = 0,
357 AI_CONVERT_Output_Ground = 1,
358 AI_CONVERT_Output_Enable_Low = 2,
359 AI_CONVERT_Output_Enable_High = 3
361 static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection selection)
363 return selection & 0x3;
366 #define AI_START_STOP_Select_Register 62
367 #define AI_START_Polarity _bit15
368 #define AI_STOP_Polarity _bit14
369 #define AI_STOP_Sync _bit13
370 #define AI_STOP_Edge _bit12
371 #define AI_STOP_Select(a) (((a) & 0x1f)<<7)
372 #define AI_START_Sync _bit6
373 #define AI_START_Edge _bit5
374 #define AI_START_Select(a) ((a) & 0x1f)
376 #define AI_Trigger_Select_Register 63
377 #define AI_START1_Polarity _bit15
378 #define AI_START2_Polarity _bit14
379 #define AI_START2_Sync _bit13
380 #define AI_START2_Edge _bit12
381 #define AI_START2_Select(a) (((a) & 0x1f) << 7)
382 #define AI_START1_Sync _bit6
383 #define AI_START1_Edge _bit5
384 #define AI_START1_Select(a) ((a) & 0x1f)
386 #define AI_DIV_Load_A_Register 64
388 #define AO_Start_Select_Register 66
389 #define AO_UI2_Software_Gate _bit15
390 #define AO_UI2_External_Gate_Polarity _bit14
391 #define AO_START_Polarity _bit13
392 #define AO_AOFREQ_Enable _bit12
393 #define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7)
394 #define AO_START_Sync _bit6
395 #define AO_START_Edge _bit5
396 #define AO_START_Select(a) ((a) & 0x1f)
398 #define AO_Trigger_Select_Register 67
399 #define AO_UI2_External_Gate_Enable _bit15
400 #define AO_Delayed_START1 _bit14
401 #define AO_START1_Polarity _bit13
402 #define AO_UI2_Source_Polarity _bit12
403 #define AO_UI2_Source_Select(x) (((x)&0x1f)<<7)
404 #define AO_START1_Sync _bit6
405 #define AO_START1_Edge _bit5
406 #define AO_START1_Select(x) (((x)&0x1f)<<0)
408 #define AO_Mode_3_Register 70
409 #define AO_UI2_Switch_Load_Next_TC _bit13
410 #define AO_UC_Switch_Load_Every_BC_TC _bit12
411 #define AO_Trigger_Length _bit11
412 #define AO_Stop_On_Overrun_Error _bit5
413 #define AO_Stop_On_BC_TC_Trigger_Error _bit4
414 #define AO_Stop_On_BC_TC_Error _bit3
415 #define AO_Not_An_UPDATE _bit2
416 #define AO_Software_Gate _bit1
417 #define AO_Last_Gate_Disable _bit0 /* M Series only */
419 #define Joint_Reset_Register 72
420 #define Software_Reset _bit11
421 #define AO_Configuration_End _bit9
422 #define AI_Configuration_End _bit8
423 #define AO_Configuration_Start _bit5
424 #define AI_Configuration_Start _bit4
425 #define G1_Reset _bit3
426 #define G0_Reset _bit2
427 #define AO_Reset _bit1
428 #define AI_Reset _bit0
430 #define Interrupt_A_Enable_Register 73
431 #define Pass_Thru_0_Interrupt_Enable _bit9
432 #define G0_Gate_Interrupt_Enable _bit8
433 #define AI_FIFO_Interrupt_Enable _bit7
434 #define G0_TC_Interrupt_Enable _bit6
435 #define AI_Error_Interrupt_Enable _bit5
436 #define AI_STOP_Interrupt_Enable _bit4
437 #define AI_START_Interrupt_Enable _bit3
438 #define AI_START2_Interrupt_Enable _bit2
439 #define AI_START1_Interrupt_Enable _bit1
440 #define AI_SC_TC_Interrupt_Enable _bit0
442 #define Interrupt_B_Enable_Register 75
443 #define Pass_Thru_1_Interrupt_Enable _bit11
444 #define G1_Gate_Interrupt_Enable _bit10
445 #define G1_TC_Interrupt_Enable _bit9
446 #define AO_FIFO_Interrupt_Enable _bit8
447 #define AO_UI2_TC_Interrupt_Enable _bit7
448 #define AO_UC_TC_Interrupt_Enable _bit6
449 #define AO_Error_Interrupt_Enable _bit5
450 #define AO_STOP_Interrupt_Enable _bit4
451 #define AO_START_Interrupt_Enable _bit3
452 #define AO_UPDATE_Interrupt_Enable _bit2
453 #define AO_START1_Interrupt_Enable _bit1
454 #define AO_BC_TC_Interrupt_Enable _bit0
456 #define Second_IRQ_B_Enable_Register 76
457 #define AI_Personal_Register 77
458 #define AI_SHIFTIN_Pulse_Width _bit15
459 #define AI_EOC_Polarity _bit14
460 #define AI_SOC_Polarity _bit13
461 #define AI_SHIFTIN_Polarity _bit12
462 #define AI_CONVERT_Pulse_Timebase _bit11
463 #define AI_CONVERT_Pulse_Width _bit10
464 #define AI_CONVERT_Original_Pulse _bit9
465 #define AI_FIFO_Flags_Polarity _bit8
466 #define AI_Overrun_Mode _bit7
467 #define AI_EXTMUX_CLK_Pulse_Width _bit6
468 #define AI_LOCALMUX_CLK_Pulse_Width _bit5
469 #define AI_AIFREQ_Polarity _bit4
471 #define AO_Personal_Register 78
472 enum AO_Personal_Bits
474 AO_Interval_Buffer_Mode = 1 << 3,
475 AO_BC_Source_Select = 1 << 4,
476 AO_UPDATE_Pulse_Width = 1 << 5,
477 AO_UPDATE_Pulse_Timebase = 1 << 6,
478 AO_UPDATE_Original_Pulse = 1 << 7,
479 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */
480 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */
481 AO_FIFO_Enable = 1 << 10,
482 AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */
483 AO_TMRDACWR_Pulse_Width = 1 << 12,
484 AO_Fast_CPU = 1 << 13, /* M Series: reserved */
485 AO_Number_Of_DAC_Packages = 1 << 14, // 1 for "single" mode, 0 for "dual"
486 AO_Multiple_DACS_Per_Package = 1 << 15 // m-series only
488 #define RTSI_Trig_A_Output_Register 79
489 #define RTSI_Trig_B_Output_Register 80
490 enum RTSI_Trig_B_Output_Bits
492 RTSI_Sub_Selection_1_Bit = 0x8000 // not for m-series
494 static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel, unsigned source)
496 return (source & 0xf) << ((rtsi_channel % 4) * 4);
498 static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel)
500 return 0xf << ((rtsi_channel % 4) * 4);
502 // inverse to RTSI_Trig_Output_Bits()
503 static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel, unsigned bits)
505 return (bits >> ((rtsi_channel % 4) * 4)) & 0xf;
508 #define RTSI_Board_Register 81
509 #define Write_Strobe_0_Register 82
510 #define Write_Strobe_1_Register 83
511 #define Write_Strobe_2_Register 84
512 #define Write_Strobe_3_Register 85
514 #define AO_Output_Control_Register 86
515 #define AO_External_Gate_Enable _bit15
516 #define AO_External_Gate_Select(x) (((x)&0x1f)<<10)
517 #define AO_Number_Of_Channels(x) (((x)&0xf)<<6)
518 #define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4)
519 #define AO_External_Gate_Polarity _bit3
520 #define AO_UPDATE2_Output_Toggle _bit2
521 enum ao_update_output_selection
523 AO_Update_Output_High_Z = 0,
524 AO_Update_Output_Ground = 1,
525 AO_Update_Output_Enable_Low = 2,
526 AO_Update_Output_Enable_High = 3
528 static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection selection)
530 return selection & 0x3;
533 #define AI_Mode_3_Register 87
534 #define AI_Trigger_Length _bit15
535 #define AI_Delay_START _bit14
536 #define AI_Software_Gate _bit13
537 #define AI_SI_Special_Trigger_Delay _bit12
538 #define AI_SI2_Source_Select _bit11
539 #define AI_Delayed_START2 _bit10
540 #define AI_Delayed_START1 _bit9
541 #define AI_External_Gate_Mode _bit8
542 #define AI_FIFO_Mode_HF_to_E (3<<6)
543 #define AI_FIFO_Mode_F (2<<6)
544 #define AI_FIFO_Mode_HF (1<<6)
545 #define AI_FIFO_Mode_NE (0<<6)
546 #define AI_External_Gate_Polarity _bit5
547 #define AI_External_Gate_Select(a) ((a) & 0x1f)
549 #define G_Autoincrement_Register(a) (68+(a))
550 #define G_Command_Register(a) (6+(a))
551 #define G_HW_Save_Register(a) (8+(a)*2)
552 #define G_HW_Save_Register_High(a) (8+(a)*2)
553 #define G_HW_Save_Register_Low(a) (9+(a)*2)
554 #define G_Input_Select_Register(a) (36+(a))
555 #define G_Load_A_Register(a) (28+(a)*4)
556 #define G_Load_A_Register_High(a) (28+(a)*4)
557 #define G_Load_A_Register_Low(a) (29+(a)*4)
558 #define G_Load_B_Register(a) (30+(a)*4)
559 #define G_Load_B_Register_High(a) (30+(a)*4)
560 #define G_Load_B_Register_Low(a) (31+(a)*4)
561 #define G_Mode_Register(a) (26+(a))
562 #define G_Save_Register(a) (12+(a)*2)
563 #define G_Save_Register_High(a) (12+(a)*2)
564 #define G_Save_Register_Low(a) (13+(a)*2)
565 #define G_Status_Register 4
566 #define Analog_Trigger_Etc_Register 61
568 /* command register */
569 #define G_Disarm_Copy _bit15 /* strobe */
570 #define G_Save_Trace_Copy _bit14
571 #define G_Arm_Copy _bit13 /* strobe */
572 #define G_Bank_Switch_Start _bit10 /* strobe */
573 #define G_Little_Big_Endian _bit9
574 #define G_Synchronized_Gate _bit8
575 #define G_Write_Switch _bit7
576 #define G_Up_Down(a) (((a)&0x03)<<5)
577 #define G_Disarm _bit4 /* strobe */
578 #define G_Analog_Trigger_Reset _bit3 /* strobe */
579 #define G_Save_Trace _bit1
580 #define G_Arm _bit0 /* strobe */
582 /*channel agnostic names for the command register #defines */
583 #define G_Bank_Switch_Enable _bit12
584 #define G_Bank_Switch_Mode _bit11
585 #define G_Load _bit2 /* strobe */
588 /* input select register */
589 #define G_Gate_Select(a) (((a)&0x1f)<<7)
590 #define G_Source_Select(a) (((a)&0x1f)<<2)
591 #define G_Write_Acknowledges_Irq _bit1
592 #define G_Read_Acknowledges_Irq _bit0
594 /* same input select register, but with channel agnostic names */
595 #define G_Source_Polarity _bit15
596 #define G_Output_Polarity _bit14
597 #define G_OR_Gate _bit13
598 #define G_Gate_Select_Load_Source _bit12
602 #define G_Loading_On_TC _bit12
603 #define G_Output_Mode(a) (((a)&0x03)<<8)
604 #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
605 #define G_Gating_Mode(a) (((a)&0x03)<<0)
607 /* same input mode register, but with channel agnostic names */
608 #define G_Load_Source_Select _bit7
609 #define G_Reload_Source_Switching _bit15
610 #define G_Loading_On_Gate _bit14
611 #define G_Gate_Polarity _bit13
613 #define G_Counting_Once(a) (((a)&0x03)<<10)
614 #define G_Stop_Mode(a) (((a)&0x03)<<5)
615 #define G_Gate_On_Both_Edges _bit2
617 /* G_Status_Register */
618 #define G1_Gate_Error_St _bit15
619 #define G0_Gate_Error_St _bit14
620 #define G1_TC_Error_St _bit13
621 #define G0_TC_Error_St _bit12
622 #define G1_No_Load_Between_Gates_St _bit11
623 #define G0_No_Load_Between_Gates_St _bit10
624 #define G1_Armed_St _bit9
625 #define G0_Armed_St _bit8
626 #define G1_Stale_Data_St _bit7
627 #define G0_Stale_Data_St _bit6
628 #define G1_Next_Load_Source_St _bit5
629 #define G0_Next_Load_Source_St _bit4
630 #define G1_Counting_St _bit3
631 #define G0_Counting_St _bit2
632 #define G1_Save_St _bit1
633 #define G0_Save_St _bit0
635 /* general purpose counter timer */
636 #define G0_TC_Interrupt_Enable _bit6
637 #define G1_TC_Interrupt_Enable _bit9
638 #define G0_Gate_Interrupt_Enable _bit8
639 #define G1_Gate_Interrupt_Enable _bit10
640 #define G0_Synchronized_Gate _bit8
641 #define G1_Synchronized_Gate _bit8
642 #define G0_Gate_Error_Confirm _bit5
643 #define G1_Gate_Error_Confirm _bit1
644 #define G0_TC_Error_Confirm _bit6
645 #define G1_TC_Error_Confirm _bit2
646 #define G0_TC_Interrupt_Ack _bit14
647 #define G1_TC_Interrupt_Ack _bit14
648 #define G0_Gate_Interrupt_Ack _bit15
649 #define G1_Gate_Interrupt_Ack _bit15
650 #define G_Autoincrement(a) ((a)<<0)
651 #define G_Autoincrement(a) ((a)<<0)
655 /*Analog_Trigger_Etc_Register*/
656 #define Analog_Trigger_Mode(x) ((x) & 0x7)
657 #define Analog_Trigger_Enable _bit3
658 #define Analog_Trigger_Drive _bit4
659 #define GPFO_1_Output_Select _bit7
660 #define GPFO_0_Output_Select(a) ((a)<<11)
661 #define GPFO_0_Output_Enable _bit14
662 #define GPFO_1_Output_Enable _bit15
664 /* Additional windowed registers unique to E series */
666 /* 16 bit registers shadowed from DAQ-STC */
667 #define Window_Address 0x00
668 #define Window_Data 0x02
670 #define Configuration_Memory_Clear 82
671 #define ADC_FIFO_Clear 83
672 #define DAC_FIFO_Clear 84
674 /* i/o port offsets */
676 /* 8 bit registers */
677 #define XXX_Status 0x01
681 AI_FIFO_LOWER_NOT_EMPTY = 0x8,
683 #define Serial_Command 0x0d
684 #define Misc_Command 0x0f
688 #define Configuration 0x1f
690 #define Channel_A_Mode 0x03
691 #define Channel_B_Mode 0x05
692 #define Channel_C_Mode 0x07
693 #define AI_AO_Select 0x09
694 enum AI_AO_Select_Bits
696 AI_DMA_Select_Shift = 0,
697 AI_DMA_Select_Mask = 0xf,
698 AO_DMA_Select_Shift = 4,
699 AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift
701 #define G0_G1_Select 0x0b
702 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
704 if(channel < 4) return 1 << channel;
705 if(channel == 4) return 0x3;
706 if(channel == 5) return 0x5;
710 static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, unsigned mite_channel)
712 BUG_ON(gpct_index > 1);
713 return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * gpct_index);
715 static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
717 BUG_ON(gpct_index > 1);
718 return 0xf << (4 * gpct_index);
722 /* 16 bit registers */
724 #define Configuration_Memory_Low 0x10
725 enum Configuration_Memory_Low_Bits
728 AI_LAST_CHANNEL = 0x8000,
730 #define Configuration_Memory_High 0x12
731 enum Configuration_Memory_High_Bits
733 AI_AC_COUPLE = 0x800,
734 AI_DIFFERENTIAL = 0x1000,
738 static inline unsigned int AI_CONFIG_CHANNEL( unsigned int channel )
740 return ( channel & 0x3f );
743 #define ADC_FIFO_Data_Register 0x1c
745 #define AO_Configuration 0x16
746 #define AO_Bipolar _bit0
747 #define AO_Deglitch _bit1
748 #define AO_Ext_Ref _bit2
749 #define AO_Ground_Ref _bit3
750 #define AO_Channel(x) ((x) << 8)
752 #define DAC_FIFO_Data 0x1e
753 #define DAC0_Direct_Data 0x18
754 #define DAC1_Direct_Data 0x1a
757 /* 611x registers (these boards differ from the e-series) */
759 #define Magic_611x 0x19 /* w8 (new) */
760 #define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
761 #define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
762 #define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
763 #define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
764 #define Cal_Gain_Select_611x 0x05 /* w8 (new) */
766 #define AO_Window_Address_611x 0x18
767 #define AO_Window_Data_611x 0x1e
770 #define Magic_6143 0x19 /* w8 */
771 #define G0G1_DMA_Select_6143 0x0B /* w8 */
772 #define PipelineDelay_6143 0x1f /* w8 */
773 #define EOC_Set_6143 0x1D /* w8 */
774 #define AIDMA_Select_6143 0x09 /* w8 */
775 #define AIFIFO_Data_6143 0x8C /* w32 */
776 #define AIFIFO_Flag_6143 0x84 /* w32 */
777 #define AIFIFO_Control_6143 0x88 /* w32 */
778 #define AIFIFO_Status_6143 0x88 /* w32 */
779 #define AIFIFO_DMAThreshold_6143 0x90 /* w32 */
780 #define AIFIFO_Words_Available_6143 0x94 /* w32 */
782 #define Calibration_Channel_6143 0x42 /* w16 */
783 #define Calibration_LowTime_6143 0x20 /* w16 */
784 #define Calibration_HighTime_6143 0x22 /* w16 */
785 #define Relay_Counter_Load_Val__6143 0x4C /* w32 */
786 #define Signature_6143 0x50 /* w32 */
787 #define Release_Date_6143 0x54 /* w32 */
788 #define Release_Oldest_Date_6143 0x58 /* w32 */
790 #define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */
791 #define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */
792 #define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */
793 #define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */
794 #define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */
795 #define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */
796 #define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */
797 #define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */
799 /* 671x, 611x registers */
801 /* 671xi, 611x windowed ao registers */
802 enum windowed_regs_67xx_61xx
804 AO_Immediate_671x = 0x11, /* W 16 */
805 AO_Timed_611x = 0x10, /* W 16 */
806 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */
807 AO_Later_Single_Point_Updates = 0x14, /* W 16 */
808 AO_Waveform_Generation_611x = 0x15, /* W 16 */
809 AO_Misc_611x = 0x16, /* W 16 */
810 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */
811 AO_Configuration_2_67xx = 0x18, /* W 16 */
812 CAL_ADC_Command_67xx = 0x19, /* W 8 */
813 CAL_ADC_Status_67xx = 0x1a, /* R 8 */
814 CAL_ADC_Data_67xx = 0x1b, /* R 16 */
815 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */
816 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */
818 static inline unsigned int DACx_Direct_Data_671x(int channel)
822 enum AO_Misc_611x_Bits
826 enum cs5529_configuration_bits
828 CSCFG_CAL_CONTROL_MASK = 0x7,
829 CSCFG_SELF_CAL_OFFSET = 0x1,
830 CSCFG_SELF_CAL_GAIN = 0x2,
831 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3,
832 CSCFG_SYSTEM_CAL_OFFSET = 0x5,
833 CSCFG_SYSTEM_CAL_GAIN = 0x6,
835 CSCFG_POWER_SAVE_SELECT = 1 << 4,
836 CSCFG_PORT_MODE = 1 << 5,
837 CSCFG_RESET_VALID = 1 << 6,
838 CSCFG_RESET = 1 << 7,
839 CSCFG_UNIPOLAR = 1 << 12,
840 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13,
841 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13,
842 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13,
843 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13,
844 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13,
845 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13,
846 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13,
847 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13,
848 CSCFG_WORD_RATE_MASK = 0x7 << 13,
849 CSCFG_LOW_POWER = 1 << 16,
851 static inline unsigned int CS5529_CONFIG_DOUT(int output)
853 return 1 << (18 + output);
855 static inline unsigned int CS5529_CONFIG_AOUT(int output)
857 return 1 << (22 + output);
859 enum cs5529_command_bits
861 CSCMD_POWER_SAVE = 0x1,
862 CSCMD_REGISTER_SELECT_MASK = 0xe,
863 CSCMD_OFFSET_REGISTER = 0x0,
864 CSCMD_GAIN_REGISTER = 0x2,
865 CSCMD_CONFIG_REGISTER = 0x4,
867 CSCMD_CONTINUOUS_CONVERSIONS = 0x20,
868 CSCMD_SINGLE_CONVERSION = 0x40,
869 CSCMD_COMMAND = 0x80,
871 enum cs5529_status_bits
874 CSS_OSC_DETECT = 0x2, /* indicates adc error */
877 #define SerDacLd(x) (0x08<<(x))
880 This is stuff unique to the NI E series drivers,
881 but I thought I'd put it here anyway.
884 enum{ ai_gain_16=0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, ai_gain_628x, ai_gain_6143};
885 enum caldac_enum { caldac_none=0, mb88341, dac8800, dac8043, ad8522,
886 ad8804, ad8842, ad8804_debug };
892 ni_reg_67xx_mask = 0x6,
893 ni_reg_6xxx_mask = 0x7,
897 ni_reg_m_series_mask = 0x18,
901 static comedi_lrange range_ni_E_ao_ext;
903 enum m_series_register_offsets
905 M_Offset_CDIO_DMA_Select = 0x7, // write
906 M_Offset_SCXI_Status = 0x7, // read
907 M_Offset_AI_AO_Select = 0x9, // write, same offset as e-series
908 M_Offset_SCXI_Serial_Data_In = 0x9, // read
909 M_Offset_G0_G1_Select = 0xb, // write, same offset as e-series
910 M_Offset_Misc_Command = 0xf,
911 M_Offset_SCXI_Serial_Data_Out = 0x11,
912 M_Offset_SCXI_Control = 0x13,
913 M_Offset_SCXI_Output_Enable = 0x15,
914 M_Offset_AI_FIFO_Data = 0x1c,
915 M_Offset_Static_Digital_Output = 0x24, // write
916 M_Offset_Static_Digital_Input = 0x24, // read
917 M_Offset_DIO_Direction = 0x28,
918 M_Offset_Cal_PWM = 0x40,
919 M_Offset_AI_Config_FIFO_Data = 0x5e,
920 M_Offset_Interrupt_C_Enable = 0x88, // write
921 M_Offset_Interrupt_C_Status = 0x88, // read
922 M_Offset_Analog_Trigger_Control = 0x8c,
923 M_Offset_AO_Serial_Interrupt_Enable = 0xa0,
924 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, // write
925 M_Offset_AO_Serial_Interrupt_Status = 0xa1, // read
926 M_Offset_AO_Calibration = 0xa3,
927 M_Offset_AO_FIFO_Data = 0xa4,
928 M_Offset_PFI_Filter = 0xb0,
929 M_Offset_RTSI_Filter = 0xb4,
930 M_Offset_SCXI_Legacy_Compatibility = 0xbc,
931 M_Offset_Interrupt_A_Ack = 0x104, // write
932 M_Offset_AI_Status_1 = 0x104, // read
933 M_Offset_Interrupt_B_Ack = 0x106, // write
934 M_Offset_AO_Status_1 = 0x106, // read
935 M_Offset_AI_Command_2 = 0x108, // write
936 M_Offset_G01_Status = 0x108, // read
937 M_Offset_AO_Command_2 = 0x10a,
938 M_Offset_AO_Status_2 = 0x10c, // read
939 M_Offset_G0_Command = 0x10c, // write
940 M_Offset_G1_Command = 0x10e, // write
941 M_Offset_G0_HW_Save = 0x110,
942 M_Offset_G0_HW_Save_High = 0x110,
943 M_Offset_AI_Command_1 = 0x110,
944 M_Offset_G0_HW_Save_Low = 0x112,
945 M_Offset_AO_Command_1 = 0x112,
946 M_Offset_G1_HW_Save = 0x114,
947 M_Offset_G1_HW_Save_High = 0x114,
948 M_Offset_G1_HW_Save_Low = 0x116,
949 M_Offset_AI_Mode_1 = 0x118,
950 M_Offset_G0_Save = 0x118,
951 M_Offset_G0_Save_High = 0x118,
952 M_Offset_AI_Mode_2 = 0x11a,
953 M_Offset_G0_Save_Low = 0x11a,
954 M_Offset_AI_SI_Load_A = 0x11c,
955 M_Offset_G1_Save = 0x11c,
956 M_Offset_G1_Save_High = 0x11c,
957 M_Offset_G1_Save_Low = 0x11e,
958 M_Offset_AI_SI_Load_B = 0x120, // write
959 M_Offset_AO_UI_Save = 0x120, // read
960 M_Offset_AI_SC_Load_A = 0x124, // write
961 M_Offset_AO_BC_Save = 0x124, // read
962 M_Offset_AI_SC_Load_B = 0x128, // write
963 M_Offset_AO_UC_Save = 0x128, //read
964 M_Offset_AI_SI2_Load_A = 0x12c,
965 M_Offset_AI_SI2_Load_B = 0x130,
966 M_Offset_G0_Mode = 0x134,
967 M_Offset_G1_Mode = 0x136, // write
968 M_Offset_Joint_Status_1 = 0x136, // read
969 M_Offset_G0_Load_A = 0x138,
970 M_Offset_Joint_Status_2 = 0x13a,
971 M_Offset_G0_Load_B = 0x13c,
972 M_Offset_G1_Load_A = 0x140,
973 M_Offset_G1_Load_B = 0x144,
974 M_Offset_G0_Input_Select = 0x148,
975 M_Offset_G1_Input_Select = 0x14a,
976 M_Offset_AO_Mode_1 = 0x14c,
977 M_Offset_AO_Mode_2 = 0x14e,
978 M_Offset_AO_UI_Load_A = 0x150,
979 M_Offset_AO_UI_Load_B = 0x154,
980 M_Offset_AO_BC_Load_A = 0x158,
981 M_Offset_AO_BC_Load_B = 0x15c,
982 M_Offset_AO_UC_Load_A = 0x160,
983 M_Offset_AO_UC_Load_B = 0x164,
984 M_Offset_Clock_and_FOUT = 0x170,
985 M_Offset_IO_Bidirection_Pin = 0x172,
986 M_Offset_RTSI_Trig_Direction = 0x174,
987 M_Offset_Interrupt_Control = 0x176,
988 M_Offset_AI_Output_Control = 0x178,
989 M_Offset_Analog_Trigger_Etc = 0x17a,
990 M_Offset_AI_START_STOP_Select = 0x17c,
991 M_Offset_AI_Trigger_Select = 0x17e,
992 M_Offset_AI_SI_Save = 0x180, // read
993 M_Offset_AI_DIV_Load_A = 0x180, // write
994 M_Offset_AI_SC_Save = 0x184, // read
995 M_Offset_AO_Start_Select = 0x184, // write
996 M_Offset_AO_Trigger_Select = 0x186,
997 M_Offset_AO_Mode_3 = 0x18c,
998 M_Offset_G0_Autoincrement = 0x188,
999 M_Offset_G1_Autoincrement = 0x18a,
1000 M_Offset_Joint_Reset = 0x190,
1001 M_Offset_Interrupt_A_Enable = 0x192,
1002 M_Offset_Interrupt_B_Enable = 0x196,
1003 M_Offset_AI_Personal = 0x19a,
1004 M_Offset_AO_Personal = 0x19c,
1005 M_Offset_RTSI_Trig_A_Output = 0x19e,
1006 M_Offset_RTSI_Trig_B_Output = 0x1a0,
1007 M_Offset_RTSI_Shared_MUX = 0x1a2,
1008 M_Offset_AO_Output_Control = 0x1ac,
1009 M_Offset_AI_Mode_3 = 0x1ae,
1010 M_Offset_Configuration_Memory_Clear = 0x1a4,
1011 M_Offset_AI_FIFO_Clear = 0x1a6,
1012 M_Offset_AO_FIFO_Clear = 0x1a8,
1013 M_Offset_G0_Counting_Mode = 0x1b0,
1014 M_Offset_G1_Counting_Mode = 0x1b2,
1015 M_Offset_G0_Second_Gate = 0x1b4,
1016 M_Offset_G1_Second_Gate = 0x1b6,
1017 M_Offset_G0_DMA_Config = 0x1b8, // write
1018 M_Offset_G0_DMA_Status = 0x1b8, // read
1019 M_Offset_G1_DMA_Config = 0x1ba, // write
1020 M_Offset_G1_DMA_Status = 0x1ba, // read
1021 M_Offset_G0_MSeries_ABZ = 0x1c0,
1022 M_Offset_G1_MSeries_ABZ = 0x1c2,
1023 M_Offset_Clock_and_Fout2 = 0x1c4,
1024 M_Offset_PLL_Control = 0x1c6,
1025 M_Offset_PLL_Status = 0x1c8,
1026 M_Offset_PFI_Output_Select_1 = 0x1d0,
1027 M_Offset_PFI_Output_Select_2 = 0x1d2,
1028 M_Offset_PFI_Output_Select_3 = 0x1d4,
1029 M_Offset_PFI_Output_Select_4 = 0x1d6,
1030 M_Offset_PFI_Output_Select_5 = 0x1d8,
1031 M_Offset_PFI_Output_Select_6 = 0x1da,
1032 M_Offset_PFI_DI = 0x1dc,
1033 M_Offset_PFI_DO = 0x1de,
1034 M_Offset_AI_Config_FIFO_Bypass = 0x218,
1035 M_Offset_SCXI_DIO_Enable = 0x21c,
1036 M_Offset_CDI_FIFO_Data = 0x220, // read
1037 M_Offset_CDO_FIFO_Data = 0x220, // write
1038 M_Offset_CDIO_Status = 0x224, // read
1039 M_Offset_CDIO_Command = 0x224, // write
1040 M_Offset_CDI_Mode = 0x228,
1041 M_Offset_CDO_Mode = 0x22c,
1042 M_Offset_CDI_Mask_Enable = 0x230,
1043 M_Offset_CDO_Mask_Enable = 0x234,
1045 static inline int M_Offset_AO_Waveform_Order(int channel)
1047 return 0xc2 + 0x4 * channel;
1049 static inline int M_Offset_AO_Config_Bank(int channel)
1051 return 0xc3 + 0x4 * channel;
1053 static inline int M_Offset_DAC_Direct_Data(int channel)
1055 return 0xc0 + 0x4 * channel;
1057 static inline int M_Offset_Gen_PWM(int channel)
1059 return 0x44 + 0x2 * channel;
1061 static inline int M_Offset_Static_AI_Control(int i)
1070 if(((unsigned)i) >= sizeof(offset) / sizeof(offset[0]))
1072 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, i);
1077 static inline int M_Offset_AO_Reference_Attenuation(int channel)
1086 if(((unsigned)channel) >= sizeof(offset) / sizeof(offset[0]))
1088 rt_printk("%s: invalid channel=%i\n", __FUNCTION__, channel);
1091 return offset[channel];
1093 static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
1095 if(n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS)
1097 rt_printk("%s: invalid pfi output select register=%i\n", __FUNCTION__, n);
1098 return M_Offset_PFI_Output_Select_1;
1100 return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
1103 enum MSeries_AI_Config_FIFO_Data_Bits
1105 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6,
1106 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0,
1107 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6,
1108 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6,
1109 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6,
1110 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6,
1111 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6,
1112 MSeries_AI_Config_Polarity_Bit = 0x1000, // 0 for 2's complement encoding
1113 MSeries_AI_Config_Dither_Bit = 0x2000,
1114 MSeries_AI_Config_Last_Channel_Bit = 0x4000,
1116 static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel)
1118 return channel & 0xf;
1120 static inline unsigned MSeries_AI_Config_Bank_Bits(unsigned channel)
1122 return channel & 0x30;
1124 static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range)
1126 return (range & 0x7) << 9;
1129 enum MSeries_Clock_and_Fout2_Bits
1131 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb,
1132 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14,
1133 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b,
1134 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d,
1135 MSeries_PLL_In_Source_Select_Mask = 0x1f,
1136 MSeries_Timebase1_Select_Bit = 0x20, // use PLL for timebase 1
1137 MSeries_Timebase3_Select_Bit = 0x40, // use PLL for timebase 3
1138 /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears
1139 to have no effect, at least on pxi-6281, which always uses
1140 20MHz rtsi clock frequency */
1141 MSeries_RTSI_10MHz_Bit = 0x80
1143 static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned RTSI_channel)
1145 if(RTSI_channel > 7)
1147 rt_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, RTSI_channel);
1150 if(RTSI_channel == 7) return MSeries_PLL_In_Source_Select_RTSI7_Bits;
1151 else return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
1154 enum MSeries_PLL_Control_Bits
1156 MSeries_PLL_Enable_Bit = 0x1000,
1157 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0,
1158 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000,
1159 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000,
1160 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000,
1162 static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor)
1164 static const unsigned max_divisor = 0x10;
1165 if(divisor < 1 || divisor > max_divisor)
1167 rt_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, divisor);
1170 return (divisor & 0xf) << 8;
1172 static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier)
1174 static const unsigned max_multiplier = 0x100;
1175 if(multiplier < 1 || multiplier > max_multiplier)
1177 rt_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, multiplier);
1180 return multiplier & 0xff;
1183 enum MSeries_PLL_Status
1185 MSeries_PLL_Locked_Bit = 0x1
1188 enum MSeries_AI_Config_FIFO_Bypass_Bits
1190 MSeries_AI_Bypass_Channel_Mask = 0x7,
1191 MSeries_AI_Bypass_Bank_Mask = 0x78,
1192 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380,
1193 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00,
1194 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000,
1195 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000,
1196 MSeries_AI_Bypass_Gain_Mask = 0x1c0000,
1197 MSeries_AI_Bypass_Dither_Bit = 0x200000,
1198 MSeries_AI_Bypass_Polarity_Bit = 0x400000, // 0 for 2's complement encoding
1199 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000
1201 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int calibration_source)
1203 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1205 static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int calibration_source)
1207 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask;
1209 static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain)
1211 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask;
1214 enum MSeries_AO_Config_Bank_Bits
1216 MSeries_AO_DAC_Offset_Select_Mask = 0x7,
1217 MSeries_AO_DAC_Offset_0V_Bits = 0x0,
1218 MSeries_AO_DAC_Offset_5V_Bits = 0x1,
1219 MSeries_AO_DAC_Reference_Mask = 0x38,
1220 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0,
1221 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8,
1222 MSeries_AO_Update_Timed_Bit = 0x40,
1223 MSeries_AO_Bipolar_Bit = 0x80 // turns on 2's complement encoding
1226 enum MSeries_AO_Reference_Attenuation_Bits
1228 MSeries_Attenuate_x5_Bit = 0x1
1231 static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count)
1233 return (count << 16) & 0xffff0000;
1236 static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count)
1238 return count & 0xffff;
1241 static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel)
1243 return 0x1f << (channel % 3) * 5;
1245 static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel, unsigned source)
1247 return (source & 0x1f) << ((channel % 3) * 5);
1249 // inverse to MSeries_PFI_Output_Select_Bits
1250 static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel, unsigned bits)
1252 return (bits >> ((channel % 3) * 5)) & 0x1f;
1255 enum MSeries_Gi_DMA_Config_Bits
1257 Gi_DMA_BankSW_Error_Bit = 0x10,
1258 Gi_DMA_Reset_Bit = 0x8,
1259 Gi_DMA_Int_Enable_Bit = 0x4,
1260 Gi_DMA_Write_Bit = 0x2,
1261 Gi_DMA_Enable_Bit = 0x1,
1264 #define M_SERIES_EEPROM_SIZE 1024
1266 typedef struct ni_board_struct{
1275 unsigned int alwaysdither : 1;
1282 comedi_lrange *ao_range_table;
1285 unsigned num_p0_dio_channels;
1288 unsigned int ao_unipolar : 1;
1289 unsigned int has_8255 : 1;
1290 unsigned int has_analog_trig : 1;
1292 enum caldac_enum caldac[3];
1295 static ni_board ni_boards[];
1296 #define n_ni_boards (sizeof(ni_boards)/sizeof(ni_board))
1298 #define boardtype (*(ni_board *)dev->board_ptr)
1300 #define MAX_N_AO_CHAN 8
1303 #define NI_PRIVATE_COMMON \
1304 uint16_t (*stc_readw)(comedi_device *dev, int register); \
1305 uint32_t (*stc_readl)(comedi_device *dev, int register); \
1306 void (*stc_writew)(comedi_device *dev, uint16_t value, int register); \
1307 void (*stc_writel)(comedi_device *dev, uint32_t value, int register); \
1309 unsigned short dio_output; \
1310 unsigned short dio_control; \
1317 int ai_continuous; \
1320 unsigned int ai_calib_source; \
1321 unsigned int ai_calib_source_enabled; \
1322 spinlock_t window_lock; \
1323 spinlock_t soft_reg_copy_lock; \
1324 spinlock_t mite_channel_lock; \
1326 int changain_state; \
1327 unsigned int changain_spec; \
1329 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; \
1330 unsigned short ao[MAX_N_AO_CHAN]; \
1331 unsigned short caldacs[MAX_N_CALDACS]; \
1333 unsigned short ai_cmd2; \
1335 unsigned short ao_conf[MAX_N_AO_CHAN]; \
1336 unsigned short ao_mode1; \
1337 unsigned short ao_mode2; \
1338 unsigned short ao_mode3; \
1339 unsigned short ao_cmd1; \
1340 unsigned short ao_cmd2; \
1341 unsigned short ao_cmd3; \
1342 unsigned short ao_trigger_select; \
1344 struct ni_gpct counters[NUM_GPCT]; \
1345 unsigned short an_trig_etc_reg; \
1347 unsigned ai_offset[512]; \
1349 unsigned long serial_interval_ns; \
1350 unsigned char serial_hw_mode; \
1351 unsigned short clock_and_fout; \
1352 unsigned short clock_and_fout2; \
1354 unsigned short int_a_enable_reg; \
1355 unsigned short int_b_enable_reg; \
1356 unsigned short io_bidirection_pin_reg; \
1357 unsigned short rtsi_trig_direction_reg; \
1358 unsigned short rtsi_trig_a_output_reg; \
1359 unsigned short rtsi_trig_b_output_reg; \
1360 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
1361 unsigned short ai_ao_select_reg; \
1362 unsigned short g0_g1_select_reg; \
1364 unsigned clock_ns; \
1365 unsigned clock_source; \
1367 unsigned short atrig_mode; \
1368 unsigned short atrig_high; \
1369 unsigned short atrig_low; \
1371 unsigned short pwm_up_count; \
1372 unsigned short pwm_down_count; \
1374 sampl_t ai_fifo_buffer[0x2000]; \
1375 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
1377 struct mite_struct *mite; \
1378 struct mite_channel *ai_mite_chan; \
1379 struct mite_channel *ao_mite_chan;\
1380 struct mite_channel *gpct_mite_chan[NUM_GPCT]; \
1381 struct mite_dma_descriptor_ring *ai_mite_ring; \
1382 struct mite_dma_descriptor_ring *ao_mite_ring; \
1383 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT];
1386 #endif /* _COMEDI_NI_STC_H */