comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55          - many printk's need to be changed to rt_printk()
  56 */
  57
  58 //#define DEBUG_INTERRUPT
  59 //#define DEBUG_STATUS_A
  60 //#define DEBUG_STATUS_B
  61
  62 #include "8255.h"
  63 #include "mite.h"
  64 #include "comedi_fc.h"
  65
  66 #ifndef MDPRINTK
  67 #define MDPRINTK(format,args...)
  68 #endif
  69
  70 /* A timeout count */
  71
  72 #define NI_TIMEOUT 1000
  73
  74 /* Note: this table must match the ai_gain_* definitions */
  75 static short ni_gainlkup[][16]={
  76         /* ai_gain_16 */
  77         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  78                 0x106, 0x107 },
  79         /* ai_gain_8 */
  80         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  81         /* ai_gain_14 */
  82         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  83                 0x107 },
  84         /* ai_gain_4 */
  85         { 0, 1, 4, 7 },
  86         /* ai_gain_611x */
  87         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  88         /* ai_gain_622x FIXME: guesses */
  89         { 1, 2, 3, 4},
  90         /* ai_gain_628x */
  91         { 1, 2, 3, 4, 5, 6, 7}
  92 };
  93
  94 static comedi_lrange range_ni_E_ai={    16, {
  95         RANGE( -10,     10      ),
  96         RANGE( -5,      5       ),
  97         RANGE( -2.5,    2.5     ),
  98         RANGE( -1,      1       ),
  99         RANGE( -0.5,    0.5     ),
 100         RANGE( -0.25,   0.25    ),
 101         RANGE( -0.1,    0.1     ),
 102         RANGE( -0.05,   0.05    ),
 103         RANGE( 0,       20      ),
 104         RANGE( 0,       10      ),
 105         RANGE( 0,       5       ),
 106         RANGE( 0,       2       ),
 107         RANGE( 0,       1       ),
 108         RANGE( 0,       0.5     ),
 109         RANGE( 0,       0.2     ),
 110         RANGE( 0,       0.1     ),
 111 }};
 112 static comedi_lrange range_ni_E_ai_limited={    8, {
 113         RANGE( -10,     10      ),
 114         RANGE( -5,      5       ),
 115         RANGE( -1,      1       ),
 116         RANGE( -0.1,    0.1     ),
 117         RANGE( 0,       10      ),
 118         RANGE( 0,       5       ),
 119         RANGE( 0,       1       ),
 120         RANGE( 0,       0.1     ),
 121 }};
 122 static comedi_lrange range_ni_E_ai_limited14={  14, {
 123         RANGE( -10,     10      ),
 124         RANGE( -5,      5       ),
 125         RANGE( -2,      2       ),
 126         RANGE( -1,      1       ),
 127         RANGE( -0.5,    0.5     ),
 128         RANGE( -0.2,    0.2     ),
 129         RANGE( -0.1,    0.1     ),
 130         RANGE( 0,       10      ),
 131         RANGE( 0,       5       ),
 132         RANGE( 0,       2       ),
 133         RANGE( 0,       1       ),
 134         RANGE( 0,       0.5     ),
 135         RANGE( 0,       0.2     ),
 136         RANGE( 0,       0.1     ),
 137 }};
 138 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 139         RANGE( -10,     10      ),
 140         RANGE( -5,      5       ),
 141         RANGE( -0.5,    0.5     ),
 142         RANGE( -0.05,   0.05    ),
 143 }};
 144 static comedi_lrange range_ni_E_ai_611x={ 8, {
 145         RANGE( -50,     50      ),
 146         RANGE( -20,     20      ),
 147         RANGE( -10,     10      ),
 148         RANGE( -5,      5       ),
 149         RANGE( -2,      2       ),
 150         RANGE( -1,      1       ),
 151         RANGE( -0.5,    0.5     ),
 152         RANGE( -0.2,    0.2     ),
 153 }};
 154 static comedi_lrange range_ni_M_ai_622x={ 4, {
 155         RANGE(-10, 10),
 156         RANGE(-5, 5),
 157         RANGE(-1, 1),
 158         RANGE(-0.2, 0.2),
 159 }};
 160 static comedi_lrange range_ni_M_ai_628x={ 7, {
 161         RANGE( -10,     10      ),
 162         RANGE( -5,      5       ),
 163         RANGE( -2,      2       ),
 164         RANGE( -1,      1       ),
 165         RANGE( -0.5,    0.5     ),
 166         RANGE( -0.2,    0.2     ),
 167         RANGE( -0.1,    0.1     ),
 168 }};
 169 static comedi_lrange range_ni_E_ao_ext = { 4, {
 170         RANGE( -10,     10      ),
 171         RANGE( 0,       10      ),
 172         RANGE_ext( -1,  1       ),
 173         RANGE_ext( 0,   1       ),
 174 }};
 175
 176 static comedi_lrange *ni_range_lkup[]={
 177         &range_ni_E_ai,
 178         &range_ni_E_ai_limited,
 179         &range_ni_E_ai_limited14,
 180         &range_ni_E_ai_bipolar4,
 181         &range_ni_E_ai_611x,
 182         &range_ni_M_ai_622x,
 183         &range_ni_M_ai_628x
 184 };
 185
 186
 187
 188 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 189         comedi_insn *insn,lsampl_t *data);
 190 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 191         comedi_insn *insn,lsampl_t *data);
 192
 193 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 194         comedi_insn *insn,lsampl_t *data);
 195 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 196         unsigned char data_out, unsigned char *data_in);
 197 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 198         unsigned char data_out, unsigned char *data_in);
 199
 200 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 201         comedi_insn *insn,lsampl_t *data);
 202 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 203         comedi_insn *insn,lsampl_t *data);
 204
 205 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 206         comedi_insn *insn,lsampl_t *data);
 207
 208 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 214 static int ni_read_eeprom(comedi_device *dev,int addr);
 215
 216 #ifdef DEBUG_STATUS_A
 217 static void ni_mio_print_status_a(int status);
 218 #else
 219 #define ni_mio_print_status_a(a)
 220 #endif
 221 #ifdef DEBUG_STATUS_B
 222 static void ni_mio_print_status_b(int status);
 223 #else
 224 #define ni_mio_print_status_b(a)
 225 #endif
 226
 227 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 228 #ifndef PCIDMA
 229 static void ni_handle_fifo_half_full(comedi_device *dev);
 230 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 231 #endif
 232 static void ni_handle_fifo_dregs(comedi_device *dev);
 233 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 234         unsigned int trignum);
 235 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 236         unsigned int *list);
 237 static void shutdown_ai_command( comedi_device *dev );
 238
 239 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 240         unsigned int trignum);
 241
 242 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 243
 244 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 245
 246 static int ni_ns_to_timer(int *nanosec,int round_mode);
 247
 248
 249 /*GPCT function def's*/
 250 static int GPCT_G_Watch(comedi_device *dev, int chan);
 251
 252 static void GPCT_Reset(comedi_device *dev, int chan);
 253 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 254 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 255 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 256 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 257 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 258 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 259 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 260 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 261
 262 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 263         comedi_insn *insn,lsampl_t *data);
 264 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 265         comedi_insn *insn,lsampl_t *data);
 266 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 267         comedi_insn *insn,lsampl_t *data);
 268
 269 static int init_cs5529(comedi_device *dev);
 270 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 271 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 272 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 273 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 274
 275 enum aimodes
 276 {
 277         AIMODE_NONE = 0,
 278         AIMODE_HALF_FULL = 1,
 279         AIMODE_SCAN = 2,
 280         AIMODE_SAMPLE = 3,
 281 };
 282
 283 #define SERIAL_DISABLED         0
 284 #define SERIAL_600NS            600
 285 #define SERIAL_1_2US            1200
 286 #define SERIAL_10US                     10000
 287
 288 static const int num_adc_stages_611x = 3;
 289
 290 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 291         unsigned int m_status);
 292 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 293         unsigned int m_status);
 294 static void get_last_sample_611x( comedi_device *dev );
 295 #ifdef PCIDMA
 296 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 297 static int ni_ai_drain_dma(comedi_device *dev );
 298 #endif
 299
 300 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 301 {
 302         devpriv->stc_writew(dev, data >> 16, reg);
 303         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 304 }
 305
 306 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 307 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 308 {
 309         unsigned long flags;
 310
 311         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 312         ni_writew(addr,AO_Window_Address_611x);
 313         ni_writew(data,AO_Window_Data_611x);
 314         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 315 }
 316
 317 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 318 {
 319         unsigned long flags;
 320
 321         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 322         ni_writew(addr,AO_Window_Address_611x);
 323         ni_writel(data,AO_Window_Data_611x);
 324         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 325 }
 326
 327 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 328 {
 329         unsigned long flags;
 330         unsigned short data;
 331
 332         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 333         ni_writew(addr, AO_Window_Address_611x);
 334         data = ni_readw(AO_Window_Data_611x);
 335         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 336         return data;
 337 }
 338
 339 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 340 * share registers (such as Interrupt_A_Register) without interfering with
 341 * each other.
 342 *
 343 * NOTE: the switch/case statements are optimized out for a constant argument
 344 * so this is actually quite fast---  If you must wrap another function around this
 345 * make it inline to avoid a large speed penalty.
 346 *
 347 * value should only be 1 or 0.
 348 */
 349 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 350 {
 351         unsigned long flags;
 352
 353         comedi_spin_lock_irqsave( &devpriv->window_lock, flags );
 354         switch (reg){
 355                 case Interrupt_A_Enable_Register:
 356                         if(value)
 357                                 devpriv->int_a_enable_reg |= bits;
 358                         else
 359                                 devpriv->int_a_enable_reg &= ~bits;
 360                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 361                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 362                         break;
 363                 case Interrupt_B_Enable_Register:
 364                         if(value)
 365                                 devpriv->int_b_enable_reg |= bits;
 366                         else
 367                                 devpriv->int_b_enable_reg &= ~bits;
 368                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 369                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 370                         break;
 371                 case IO_Bidirection_Pin_Register:
 372                         if(value)
 373                                 devpriv->io_bidirection_pin_reg |= bits;
 374                         else
 375                                 devpriv->io_bidirection_pin_reg &= ~bits;
 376                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 377                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 378                         break;
 379                 default:
 380                         printk("Warning ni_set_bits() called with invalid arguments\n");
 381                         printk("reg is %d\n",reg);
 382                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 383                         break;
 384         }
 385 }
 386
 387
 388 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 389 {
 390         comedi_device *dev=d;
 391         unsigned short a_status;
 392         unsigned short b_status;
 393         unsigned int m0_status;
 394         unsigned int m1_status;
 395         unsigned long flags;
 396 #ifdef PCIDMA
 397         struct mite_struct *mite = devpriv->mite;
 398 #endif
 399
 400         if(dev->attached == 0) return IRQ_NONE;
 401         // lock to avoid race with comedi_poll
 402         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 403         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 404         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 405 #ifdef PCIDMA
 406         m0_status=readl(mite->mite_io_addr + MITE_CHSR(AI_DMA_CHAN));
 407         m1_status=readl(mite->mite_io_addr + MITE_CHSR(AO_DMA_CHAN));
 408 #else
 409         m0_status = 0;
 410         m1_status = 0;
 411 #endif
 412
 413         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 414                 handle_a_interrupt(dev, a_status, m0_status);
 415         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 416                 handle_b_interrupt(dev, b_status, m1_status);
 417         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 418         return IRQ_HANDLED;
 419 }
 420
 421 #ifdef PCIDMA
 422 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 423 {
 424         int count;
 425         comedi_subdevice *s = dev->subdevices + 0;
 426         comedi_async *async = s->async;
 427         unsigned int nbytes, old_alloc_count;
 428         unsigned int bytes_per_scan = 2 * async->cmd.chanlist_len;
 429
 430         old_alloc_count = async->buf_write_alloc_count;
 431         // write alloc as much as we can
 432         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 433
 434         nbytes = mite_bytes_written_to_memory_lb(mite, AI_DMA_CHAN);
 435         rmb();
 436         if( (int)(mite_bytes_written_to_memory_ub(mite, AI_DMA_CHAN) - old_alloc_count) > 0 ){
 437                 printk("ni_mio_common: DMA overwrite of free area\n");
 438                 ni_ai_reset(dev,s);
 439                 async->events |= COMEDI_CB_OVERFLOW;
 440                 return;
 441         }
 442
 443         count = nbytes - async->buf_write_count;
 444         if( count <= 0 ){
 445                 /* it's possible count will be negative due to
 446                  * conservative value returned by mite_bytes_transferred */
 447                 return;
 448         }
 449         comedi_buf_write_free(async, count);
 450
 451         async->scan_progress += count;
 452         if( async->scan_progress >= bytes_per_scan )
 453         {
 454                 async->scan_progress %= bytes_per_scan;
 455                 async->events |= COMEDI_CB_EOS;
 456         }
 457         async->events |= COMEDI_CB_BLOCK;
 458 }
 459
 460 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 461 {
 462         int count;
 463         comedi_subdevice *s = dev->subdevices + 1;
 464         comedi_async *async = s->async;
 465         u32 nbytes_ub, nbytes_lb;
 466         unsigned int new_write_count;
 467         u32 stop_count = async->cmd.stop_arg * sizeof(sampl_t);
 468
 469         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 470
 471         new_write_count = async->buf_write_count;
 472         mb();
 473         nbytes_lb = mite_bytes_read_from_memory_lb(mite, AO_DMA_CHAN);
 474         if(async->cmd.stop_src == TRIG_COUNT &&
 475                 (int) (nbytes_lb - stop_count) > 0)
 476                 nbytes_lb = stop_count;
 477         mb();
 478         nbytes_ub = mite_bytes_read_from_memory_ub(mite, AO_DMA_CHAN);
 479         if(async->cmd.stop_src == TRIG_COUNT &&
 480                 (int) (nbytes_ub - stop_count) > 0)
 481                 nbytes_ub = stop_count;
 482         if((int)(nbytes_ub - devpriv->last_buf_write_count) > 0){
 483                 rt_printk("ni_mio_common: DMA underrun\n");
 484                 ni_ao_reset(dev,s);
 485                 async->events |= COMEDI_CB_OVERFLOW;
 486                 return;
 487         }
 488         mb();
 489         devpriv->last_buf_write_count = new_write_count;
 490
 491         count = nbytes_lb - async->buf_read_count;
 492         if(count < 0){
 493                 return;
 494         }
 495         comedi_buf_read_free(async, count);
 496
 497         async->events |= COMEDI_CB_BLOCK;
 498 }
 499
 500 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 501 {
 502         static const int timeout = 10000;
 503         int i;
 504
 505         for(i = 0; i < timeout; i++)
 506         {
 507                 unsigned short b_status;
 508
 509                 b_status = devpriv->stc_readw(dev,  AO_Status_1_Register );
 510                 if( b_status & AO_FIFO_Half_Full_St )
 511                         break;
 512                 /* if we poll too often, the pci bus activity seems
 513                  to slow the dma transfer down */
 514                 comedi_udelay(10);
 515         }
 516         if( i == timeout )
 517         {
 518                 comedi_error(dev, "timed out waiting for dma load");
 519                 return -EPIPE;
 520         }
 521         return 0;
 522 }
 523
 524 #endif //PCIDMA
 525 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 526 {
 527         if(devpriv->aimode == AIMODE_SCAN)
 528         {
 529 #ifdef PCIDMA
 530                 static const int timeout = 10;
 531                 int i;
 532
 533                 for(i = 0; i < timeout; i++)
 534                 {
 535                         ni_sync_ai_dma(devpriv->mite, dev);
 536                         if((s->async->events & COMEDI_CB_EOS)) break;
 537                         comedi_udelay(1);
 538                 }
 539 #else
 540                 ni_handle_fifo_dregs(dev);
 541                 s->async->events |= COMEDI_CB_EOS;
 542 #endif
 543         }
 544         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 545         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 546                 shutdown_ai_command( dev );
 547                 ni_ai_reset(dev, s);
 548         }
 549 }
 550
 551 static void shutdown_ai_command( comedi_device *dev )
 552 {
 553         comedi_subdevice *s = dev->subdevices + 0;
 554
 555 #ifdef PCIDMA
 556         ni_ai_drain_dma( dev );
 557         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 558 #endif
 559         ni_handle_fifo_dregs(dev);
 560         get_last_sample_611x(dev);
 561
 562         ni_set_bits(dev, Interrupt_A_Enable_Register,
 563                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 564                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 565                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 566                 AI_FIFO_Interrupt_Enable,0);
 567
 568         s->async->events |= COMEDI_CB_EOA;
 569 }
 570
 571 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 572         unsigned int m_status)
 573 {
 574         comedi_subdevice *s=dev->subdevices+0;
 575         unsigned short ack=0;
 576
 577         s->async->events = 0;
 578
 579 #ifdef DEBUG_INTERRUPT
 580         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 581                 status, m_status);
 582         ni_mio_print_status_a(status);
 583 #endif
 584
 585
 586 #ifdef PCIDMA
 587         /* Currently, mite.c requires us to handle LINKC and DONE */
 588         if(m_status & CHSR_LINKC){
 589                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 590                 ni_sync_ai_dma(devpriv->mite, dev);
 591         }
 592
 593         if(m_status & CHSR_DONE){
 594                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 595         }
 596
 597         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 598                 printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 599                 //mite_print_chsr(m_status);
 600                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 601                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 602                 //disable_irq(dev->irq);
 603         }
 604 #endif
 605
 606         /* test for all uncommon interrupt events at the same time */
 607         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 608                 if(status==0xffff){
 609                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 610                         /* we probably aren't even running a command now,
 611                          * so it's a good idea to be careful. */
 612                         if(s->subdev_flags&SDF_RUNNING){
 613                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 614                                 //comedi_event(dev,s,s->async->events);
 615                         }
 616                         return;
 617                 }
 618                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 619                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 620                                 status);
 621                         ni_mio_print_status_a(status);
 622
 623                         ni_ai_reset(dev,dev->subdevices);
 624
 625
 626                         shutdown_ai_command( dev );
 627
 628                         s->async->events |= COMEDI_CB_ERROR;
 629                         if(status & (AI_Overrun_St | AI_Overflow_St))
 630                                 s->async->events |= COMEDI_CB_OVERFLOW;
 631
 632                         comedi_event(dev,s,s->async->events);
 633
 634                         return;
 635                 }
 636                 if(status&AI_SC_TC_St){
 637 #ifdef DEBUG_INTERRUPT
 638                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 639 #endif
 640                         if(!devpriv->ai_continuous){
 641                                 shutdown_ai_command( dev );
 642                         }
 643                         ack|=AI_SC_TC_Interrupt_Ack;
 644                 }
 645                 if(status&AI_START1_St){
 646                         ack|=AI_START1_Interrupt_Ack;
 647                 }
 648         }
 649 #ifndef PCIDMA
 650         if(status&AI_FIFO_Half_Full_St){
 651                 int i;
 652                 static const int timeout = 10;
 653                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 654                  *fail to get the fifo less than half full, so loop to be sure.*/
 655                 for(i = 0; i < timeout; ++i)
 656                 {
 657                         ni_handle_fifo_half_full(dev);
 658                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 659                                 break;
 660                 }
 661         }
 662 #endif // !PCIDMA
 663
 664         if( (status & AI_STOP_St) ){
 665                 ni_handle_eos(dev, s);
 666                 /* we need to ack the START, also */
 667                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 668         }
 669 #if 0
 670         if(devpriv->aimode==AIMODE_SAMPLE){
 671                 ni_handle_fifo_dregs(dev);
 672
 673                 //s->async->events |= COMEDI_CB_SAMPLE;
 674         }
 675 #endif
 676         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 677
 678         comedi_event(dev,s,s->async->events);
 679
 680 #ifdef DEBUG_INTERRUPT
 681         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 682         if(status&Interrupt_A_St){
 683                 printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 684         }
 685 #endif
 686 }
 687
 688 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 689 {
 690         comedi_subdevice *s=dev->subdevices+1;
 691         //unsigned short ack=0;
 692 #ifdef DEBUG_INTERRUPT
 693         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 694                 b_status,m_status);
 695         ni_mio_print_status_b(b_status);
 696 #endif
 697
 698
 699 #ifdef PCIDMA
 700         /* Currently, mite.c requires us to handle LINKC and DONE */
 701         if(m_status & CHSR_LINKC){
 702                 mite_handle_b_linkc(devpriv->mite, dev);
 703         }
 704
 705         if(m_status & CHSR_DONE){
 706                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 707         }
 708
 709         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 710                 printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 711                 //mite_print_chsr(m_status);
 712                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 713                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 714        }
 715 #endif
 716
 717         if(b_status==0xffff)return;
 718         if(b_status&AO_Overrun_St){
 719                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 720                 ni_ao_reset(dev,s);
 721                 s->async->events |= COMEDI_CB_OVERFLOW;
 722         }
 723
 724         if(b_status&AO_BC_TC_St){
 725                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 726                 ni_ao_reset(dev,s);
 727                 s->async->events |= COMEDI_CB_EOA;
 728         }
 729
 730 #ifndef PCIDMA
 731         if(b_status&AO_FIFO_Request_St){
 732                 int ret;
 733
 734                 ret = ni_ao_fifo_half_empty(dev,s);
 735                 if(!ret){
 736                         rt_printk("ni_mio_common: AO buffer underrun\n");
 737                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 738                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 739                         s->async->events |= COMEDI_CB_OVERFLOW;
 740                 }
 741         }
 742 #endif
 743
 744         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 745         if(b_status&Interrupt_B_St){
 746                 if(b_status&AO_FIFO_Request_St){
 747                         rt_printk("ni_mio_common: AO buffer underrun\n");
 748                 }
 749                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 750                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 751                 ni_ao_reset(dev,s);
 752                 s->async->events |= COMEDI_CB_OVERFLOW;
 753         }
 754
 755         comedi_event(dev,s,s->async->events);
 756 }
 757
 758 #ifdef DEBUG_STATUS_A
 759 static char *status_a_strings[]={
 760         "passthru0","fifo","G0_gate","G0_TC",
 761         "stop","start","sc_tc","start1",
 762         "start2","sc_tc_error","overflow","overrun",
 763         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 764 };
 765
 766 static void ni_mio_print_status_a(int status)
 767 {
 768         int i;
 769
 770         rt_printk("A status:");
 771         for(i=15;i>=0;i--){
 772                 if(status&(1<<i)){
 773                         rt_printk(" %s",status_a_strings[i]);
 774                 }
 775         }
 776         rt_printk("\n");
 777 }
 778 #endif
 779
 780 #ifdef DEBUG_STATUS_B
 781 static char *status_b_strings[]={
 782         "passthru1","fifo","G1_gate","G1_TC",
 783         "UI2_TC","UPDATE","UC_TC","BC_TC",
 784         "start1","overrun","start","bc_tc_error",
 785         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 786 };
 787
 788 static void ni_mio_print_status_b(int status)
 789 {
 790         int i;
 791
 792         rt_printk("B status:");
 793         for(i=15;i>=0;i--){
 794                 if(status&(1<<i)){
 795                         rt_printk(" %s",status_b_strings[i]);
 796                 }
 797         }
 798         rt_printk("\n");
 799 }
 800 #endif
 801
 802 #ifndef PCIDMA
 803
 804 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 805 {
 806         comedi_async *async = s->async;
 807         comedi_cmd *cmd = &async->cmd;
 808         int chan;
 809         int i;
 810         sampl_t d;
 811         u32 packed_data;
 812         int range;
 813         int err = 1;
 814
 815         chan = async->cur_chan;
 816         for(i=0;i<n;i++){
 817                 err &= comedi_buf_get(async, &d);
 818                 if(err == 0) break;
 819
 820                 range = CR_RANGE(cmd->chanlist[chan]);
 821
 822                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 823                 {
 824                         packed_data = d & 0xffff;
 825                         /* 6711 only has 16 bit wide ao fifo */
 826                         if(boardtype.reg_type != ni_reg_6711)
 827                         {
 828                                 err &= comedi_buf_get(async, &d);
 829                                 if(err == 0) break;
 830                                 chan++;
 831                                 i++;
 832                                 packed_data |= ( d << 16 ) & 0xffff0000;
 833                         }
 834                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 835                 }else{
 836                         ni_writew(d, DAC_FIFO_Data);
 837                 }
 838                 chan++;
 839                 chan %= cmd->chanlist_len;
 840         }
 841         async->cur_chan = chan;
 842         if(err==0){
 843                 async->events |= COMEDI_CB_OVERFLOW;
 844         }
 845 }
 846
 847 /*
 848  *  There's a small problem if the FIFO gets really low and we
 849  *  don't have the data to fill it.  Basically, if after we fill
 850  *  the FIFO with all the data available, the FIFO is _still_
 851  *  less than half full, we never clear the interrupt.  If the
 852  *  IRQ is in edge mode, we never get another interrupt, because
 853  *  this one wasn't cleared.  If in level mode, we get flooded
 854  *  with interrupts that we can't fulfill, because nothing ever
 855  *  gets put into the buffer.
 856  *
 857  *  This kind of situation is recoverable, but it is easier to
 858  *  just pretend we had a FIFO underrun, since there is a good
 859  *  chance it will happen anyway.  This is _not_ the case for
 860  *  RT code, as RT code might purposely be running close to the
 861  *  metal.  Needs to be fixed eventually.
 862  */
 863 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 864 {
 865         int n;
 866
 867         n = comedi_buf_read_n_available(s);
 868         if(n==0){
 869                 s->async->events |= COMEDI_CB_OVERFLOW;
 870                 return 0;
 871         }
 872
 873         n /= sizeof(sampl_t);
 874         if(n > boardtype.ao_fifo_depth / 2)
 875                 n = boardtype.ao_fifo_depth / 2;
 876
 877         ni_ao_fifo_load(dev,s,n);
 878
 879         s->async->events |= COMEDI_CB_BLOCK;
 880
 881         return 1;
 882 }
 883
 884 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 885 {
 886         int n;
 887
 888         /* reset fifo */
 889         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
 890         if(boardtype.reg_type & ni_reg_6xxx_mask)
 891                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 892
 893         /* load some data */
 894         n = comedi_buf_read_n_available(s);
 895         if(n==0)return 0;
 896
 897         n /= sizeof(sampl_t);
 898         if(n > boardtype.ao_fifo_depth)
 899                 n = boardtype.ao_fifo_depth;
 900
 901         ni_ao_fifo_load(dev,s,n);
 902
 903         return n;
 904 }
 905
 906 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 907         int n)
 908 {
 909         comedi_async *async = s->async;
 910         int i;
 911
 912         if(boardtype.reg_type == ni_reg_611x){
 913                 sampl_t data[2];
 914                 u32 dl;
 915
 916                 for( i = 0; i < n / 2; i++ ){
 917                         dl=ni_readl(ADC_FIFO_Data_611x);
 918                         /* This may get the hi/lo data in the wrong order */
 919                         data[0] = (dl>>16) & 0xffff;
 920                         data[1] = dl & 0xffff;
 921                         cfc_write_array_to_buffer(s, data, sizeof(data));
 922                 }
 923                 /* Check if there's a single sample stuck in the FIFO */
 924                 if( n % 2){
 925                         dl=ni_readl(ADC_FIFO_Data_611x);
 926                         data[0] = dl & 0xffff;
 927                         cfc_write_to_buffer(s, data[0]);
 928                 }
 929         }else{
 930                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
 931                 {
 932                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
 933                         async->events |= COMEDI_CB_ERROR;
 934                         return;
 935                 }
 936                 for(i = 0; i < n; i++){
 937                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
 938                 }
 939                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
 940                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
 941         }
 942 }
 943
 944 static void ni_handle_fifo_half_full(comedi_device *dev)
 945 {
 946         int n;
 947         comedi_subdevice *s=dev->subdevices+0;
 948
 949         n=boardtype.ai_fifo_depth/2;
 950
 951         ni_ai_fifo_read(dev,s,n);
 952 }
 953 #endif
 954
 955 #ifdef PCIDMA
 956 static int ni_ai_drain_dma(comedi_device *dev )
 957 {
 958         struct mite_struct *mite = devpriv->mite;
 959         int i;
 960         static const int timeout = 10000;
 961
 962         for( i = 0; i < timeout; i++ )
 963         {
 964                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
 965                         mite_bytes_in_transit(mite, AI_DMA_CHAN) == 0)
 966                         break;
 967                 comedi_udelay(2);
 968         }
 969         if(i == timeout)
 970         {
 971                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
 972                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 973                         mite_bytes_in_transit(mite, AI_DMA_CHAN), devpriv->stc_readw(dev, AI_Status_1_Register));
 974                 return -1;
 975         }
 976
 977         ni_sync_ai_dma( mite, dev );
 978
 979         return 0;
 980 }
 981 #endif
 982 /*
 983    Empties the AI fifo
 984 */
 985 static void ni_handle_fifo_dregs(comedi_device *dev)
 986 {
 987         comedi_subdevice *s=dev->subdevices+0;
 988         sampl_t data[2];
 989         u32 dl;
 990         short fifo_empty;
 991         int i;
 992
 993         if(boardtype.reg_type == ni_reg_611x){
 994                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
 995                         dl=ni_readl(ADC_FIFO_Data_611x);
 996
 997                         /* This may get the hi/lo data in the wrong order */
 998                         data[0] = (dl>>16);
 999                         data[1] = (dl&0xffff);
1000                         cfc_write_array_to_buffer(s, data, sizeof(data));
1001                 }
1002         }else{
1003                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1004                 while(fifo_empty == 0)
1005                 {
1006                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1007                         {
1008                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1009                                 if(fifo_empty) break;
1010                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1011                         }
1012                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1013                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1014                 }
1015         }
1016 }
1017
1018 static void get_last_sample_611x( comedi_device *dev )
1019 {
1020         comedi_subdevice *s=dev->subdevices+0;
1021         sampl_t data;
1022         u32 dl;
1023
1024         if(boardtype.reg_type != ni_reg_611x) return;
1025
1026         /* Check if there's a single sample stuck in the FIFO */
1027         if(ni_readb(XXX_Status)&0x80){
1028                 dl=ni_readl(ADC_FIFO_Data_611x);
1029                 data = (dl&0xffff);
1030                 cfc_write_to_buffer(s, data);
1031         }
1032 }
1033
1034 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1035         void *data, unsigned int num_bytes, unsigned int chan_index )
1036 {
1037         comedi_async *async = s->async;
1038         unsigned int i;
1039         unsigned int length = num_bytes / bytes_per_sample(s);
1040         sampl_t *array = data;
1041         lsampl_t *larray = data;
1042
1043         for(i = 0; i < length; i++)
1044         {
1045 #ifdef PCIDMA
1046                 if(s->subdev_flags & SDF_LSAMPL)
1047                         larray[i] = le32_to_cpu(larray[i]);
1048                 else
1049                         array[i] = le16_to_cpu(array[i]);
1050 #endif
1051                 if(s->subdev_flags & SDF_LSAMPL)
1052                         larray[i] += devpriv->ai_offset[chan_index];
1053                 else
1054                         array[i] += devpriv->ai_offset[chan_index];
1055                 chan_index++;
1056                 chan_index %= async->cmd.chanlist_len;
1057         }
1058 }
1059
1060 #ifdef PCIDMA
1061
1062 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1063 {
1064         struct mite_struct *mite = devpriv->mite;
1065         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1066         comedi_subdevice *s = dev->subdevices + 0;
1067
1068         /* write alloc the entire buffer */
1069         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1070
1071         mite_chan->current_link = 0;
1072         mite_chan->dir = COMEDI_INPUT;
1073         switch(boardtype.reg_type)
1074         {
1075         case ni_reg_611x:
1076                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1077                 break;
1078         case ni_reg_m_series:
1079                 if(boardtype.adbits > 16)
1080                         mite_prep_dma(mite, AI_DMA_CHAN, 32, 32);
1081                 else
1082                         mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);       //guess
1083                 break;
1084         default:
1085                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1086                 break;
1087         };
1088         /*start the MITE*/
1089         mite_dma_arm(mite, AI_DMA_CHAN);
1090 }
1091
1092 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1093 {
1094         struct mite_struct *mite = devpriv->mite;
1095         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1096         comedi_subdevice *s = dev->subdevices + 1;
1097
1098         devpriv->last_buf_write_count = s->async->buf_write_count;
1099
1100         mite_chan->current_link = 0;
1101         mite_chan->dir = COMEDI_OUTPUT;
1102         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1103                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1104         else
1105                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1106
1107         /*start the MITE*/
1108         mite_dma_arm(mite, AO_DMA_CHAN);
1109 }
1110
1111 #endif // PCIDMA
1112
1113 /*
1114    used for both cancel ioctl and board initialization
1115
1116    this is pretty harsh for a cancel, but it works...
1117  */
1118
1119 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1120 {
1121 #ifdef PCIDMA
1122         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1123 #endif
1124         /* ai configuration */
1125         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1126
1127         ni_set_bits(dev, Interrupt_A_Enable_Register,
1128                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1129                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1130                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1131                 AI_FIFO_Interrupt_Enable,0);
1132
1133         devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
1134
1135         ni_writeb(0, Misc_Command);
1136
1137         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1138         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1139                 AI_Mode_1_Register);
1140         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1141         /* generate FIFO interrupts on non-empty */
1142         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1143         if(boardtype.reg_type == ni_reg_611x){
1144                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1145                         AI_SOC_Polarity |
1146                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1147                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1148                         AI_EXTMUX_CLK_Output_Select(0) |
1149                         AI_LOCALMUX_CLK_Output_Select(2) |
1150                         AI_SC_TC_Output_Select(3) |
1151                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1152         }else{
1153                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1154                         AI_SOC_Polarity |
1155                         AI_CONVERT_Pulse_Width |
1156                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1157                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1158                         AI_EXTMUX_CLK_Output_Select(0) |
1159                         AI_LOCALMUX_CLK_Output_Select(2) |
1160                         AI_SC_TC_Output_Select(3) |
1161                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1162         }
1163         /* the following registers should not be changed, because there
1164          * are no backup registers in devpriv.  If you want to change
1165          * any of these, add a backup register and other appropriate code:
1166          *      AI_Mode_1_Register
1167          *      AI_Mode_3_Register
1168          *      AI_Personal_Register
1169          *      AI_Output_Control_Register
1170         */
1171         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1172                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1173                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1174                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1175
1176         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1177
1178         return 0;
1179 }
1180
1181 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1182 {
1183         unsigned long flags = 0;
1184         int count;
1185
1186         // lock to avoid race with interrupt handler
1187         if(in_interrupt() == 0)
1188                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1189 #ifndef PCIDMA
1190         ni_handle_fifo_dregs(dev);
1191 #else
1192         ni_sync_ai_dma(devpriv->mite, dev);
1193 #endif
1194         count = s->async->buf_write_count - s->async->buf_read_count;
1195         if(in_interrupt() == 0)
1196                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1197
1198         return count;
1199 }
1200
1201
1202 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1203 {
1204         int i,n;
1205         unsigned int mask;
1206         unsigned signbits;
1207         unsigned short d;
1208
1209         ni_load_channelgain_list(dev,1,&insn->chanspec);
1210
1211         devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
1212
1213         mask=(1<<boardtype.adbits)-1;
1214         signbits=devpriv->ai_offset[0];
1215         if(boardtype.reg_type == ni_reg_611x){
1216                 for(n=0; n < num_adc_stages_611x; n++){
1217                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1218                         comedi_udelay(1);
1219                 }
1220                 for(n=0; n<insn->n; n++){
1221                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1222                         /* The 611x has screwy 32-bit FIFOs. */
1223                         d = 0;
1224                         for(i=0; i<NI_TIMEOUT; i++){
1225                                 if(ni_readb(XXX_Status)&0x80)
1226                                 {
1227                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1228                                         break;
1229                                 }
1230                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1231                                 {
1232                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1233                                         break;
1234                                 }
1235                         }
1236                         if(i==NI_TIMEOUT){
1237                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1238                                 return -ETIME;
1239                         }
1240                         d += signbits;
1241                         data[ n ] = d;
1242                 }
1243         }else{
1244                 for(n=0;n<insn->n;n++){
1245                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1246                         for(i=0;i<NI_TIMEOUT;i++){
1247                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1248                                         break;
1249                         }
1250                         if(i==NI_TIMEOUT){
1251                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1252                                 return -ETIME;
1253                         }
1254                         if(boardtype.reg_type == ni_reg_m_series)
1255                         {
1256                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data);
1257                                 data[n] += signbits;
1258                         }else
1259                         {
1260                                 d = ni_readw(ADC_FIFO_Data_Register);
1261                                 d += signbits; /* subtle: needs to be short addition */
1262                                 data[n] = d;
1263                         }
1264                 }
1265         }
1266         return insn->n;
1267 }
1268
1269 /*
1270  * Notes on the 6110 and 6111:
1271  * These boards a slightly different than the rest of the series, since
1272  * they have multiple A/D converters.
1273  * From the driver side, the configuration memory is a
1274  * little different.
1275  * Configuration Memory Low:
1276  *   bits 15-9: same
1277  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1278  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1279  *       1001 gain=0.1 (+/- 50)
1280  *       1010 0.2
1281  *       1011 0.1
1282  *       0001 1
1283  *       0010 2
1284  *       0011 5
1285  *       0100 10
1286  *       0101 20
1287  *       0110 50
1288  * Configuration Memory High:
1289  *   bits 12-14: Channel Type
1290  *       001 for differential
1291  *       000 for calibration
1292  *   bit 11: coupling  (this is not currently handled)
1293  *       1 AC coupling
1294  *       0 DC coupling
1295  *   bits 0-2: channel
1296  *       valid channels are 0-3
1297  */
1298 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1299         unsigned int *list)
1300 {
1301         unsigned int chan,range,aref;
1302         unsigned int i;
1303         unsigned int hi,lo;
1304         unsigned offset;
1305         unsigned int dither;
1306
1307         if(n_chan == 1 && boardtype.reg_type != ni_reg_611x){
1308                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1309                         // ready to go.
1310                         return;
1311                 }
1312                 devpriv->changain_state=1;
1313                 devpriv->changain_spec=list[0];
1314         }else{
1315                 devpriv->changain_state=0;
1316         }
1317
1318         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1319
1320         offset=1<<(boardtype.adbits-1);
1321         for(i=0;i<n_chan;i++){
1322                 if(list[i]&CR_ALT_SOURCE){
1323                         chan=devpriv->ai_calib_source;
1324                 }else{
1325                         chan=CR_CHAN(list[i]);
1326                 }
1327                 aref=CR_AREF(list[i]);
1328                 range=CR_RANGE(list[i]);
1329                 dither=((list[i]&CR_ALT_FILTER)!=0);
1330
1331                 /* fix the external/internal range differences */
1332                 range = ni_gainlkup[boardtype.gainlkup][range];
1333                 if(boardtype.reg_type == ni_reg_611x)
1334                         devpriv->ai_offset[i] = offset;
1335                 else
1336                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1337
1338                 hi = 0;
1339                 if( ( list[i] & CR_ALT_SOURCE ) )
1340                 {
1341                         if(boardtype.reg_type == ni_reg_611x)
1342                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1343                 }else
1344                 {
1345                         if(boardtype.reg_type == ni_reg_611x)
1346                                 aref = AREF_DIFF;
1347                         switch( aref )
1348                         {
1349                                 case AREF_DIFF:
1350                                         hi |= AI_DIFFERENTIAL;
1351                                         break;
1352                                 case AREF_COMMON:
1353                                         hi |= AI_COMMON;
1354                                         break;
1355                                 case AREF_GROUND:
1356                                         hi |= AI_GROUND;
1357                                         break;
1358                                 case AREF_OTHER:
1359                                         break;
1360                         }
1361                 }
1362                 hi |= AI_CONFIG_CHANNEL( chan );
1363
1364                 ni_writew(hi,Configuration_Memory_High);
1365
1366                 lo = range;
1367                 if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1368                 if( dither ) lo |= AI_DITHER;
1369
1370                 ni_writew(lo,Configuration_Memory_Low);
1371         }
1372
1373         /* prime the channel/gain list */
1374         if(boardtype.reg_type != ni_reg_611x){
1375                 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1376                 for(i=0;i<NI_TIMEOUT;i++){
1377                         if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St)){
1378                                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
1379                                 return;
1380                         }
1381                         comedi_udelay(1);
1382                 }
1383                 rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1384         }
1385 }
1386
1387 #define TIMER_BASE 50 /* 20 Mhz base */
1388
1389 static int ni_ns_to_timer(int *nanosec,int round_mode)
1390 {
1391         int divider,base;
1392
1393         base=TIMER_BASE;
1394
1395         switch(round_mode){
1396         case TRIG_ROUND_NEAREST:
1397         default:
1398                 divider=(*nanosec+base/2)/base;
1399                 break;
1400         case TRIG_ROUND_DOWN:
1401                 divider=(*nanosec)/base;
1402                 break;
1403         case TRIG_ROUND_UP:
1404                 divider=(*nanosec+base-1)/base;
1405                 break;
1406         }
1407
1408         *nanosec=base*divider;
1409         return divider-1;
1410 }
1411
1412 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1413 {
1414         int err=0;
1415         int tmp;
1416         int sources;
1417
1418         /* step 1: make sure trigger sources are trivially valid */
1419
1420         tmp=cmd->start_src;
1421         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1422         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1423
1424         tmp=cmd->scan_begin_src;
1425         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1426         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1427
1428         tmp=cmd->convert_src;
1429         sources = TRIG_TIMER | TRIG_EXT;
1430         if(boardtype.reg_type == ni_reg_611x) sources |= TRIG_NOW;
1431         cmd->convert_src &= sources;
1432         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1433
1434         tmp=cmd->scan_end_src;
1435         cmd->scan_end_src &= TRIG_COUNT;
1436         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1437
1438         tmp=cmd->stop_src;
1439         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1440         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1441
1442         if(err)return 1;
1443
1444         /* step 2: make sure trigger sources are unique and mutually compatible */
1445
1446         /* note that mutual compatiblity is not an issue here */
1447         if(cmd->start_src!=TRIG_NOW &&
1448            cmd->start_src!=TRIG_INT &&
1449            cmd->start_src!=TRIG_EXT)err++;
1450         if(cmd->scan_begin_src!=TRIG_TIMER &&
1451            cmd->scan_begin_src!=TRIG_EXT &&
1452            cmd->scan_begin_src!=TRIG_OTHER)err++;
1453         if(cmd->convert_src!=TRIG_TIMER &&
1454            cmd->convert_src!=TRIG_EXT &&
1455            cmd->convert_src!=TRIG_NOW)err++;
1456         if(cmd->stop_src!=TRIG_COUNT &&
1457            cmd->stop_src!=TRIG_NONE)err++;
1458
1459         if(err)return 2;
1460
1461         /* step 3: make sure arguments are trivially compatible */
1462
1463         if(cmd->start_src==TRIG_EXT){
1464                 /* external trigger */
1465                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1466
1467                 if(tmp > 9) tmp = 9;
1468                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1469                 if(cmd->start_arg != tmp){
1470                         cmd->start_arg = tmp;
1471                         err++;
1472                 }
1473         }else{
1474                 if(cmd->start_arg!=0){
1475                         /* true for both TRIG_NOW and TRIG_INT */
1476                         cmd->start_arg=0;
1477                         err++;
1478                 }
1479         }
1480         if(cmd->scan_begin_src==TRIG_TIMER){
1481                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1482                         cmd->scan_begin_arg=boardtype.ai_speed;
1483                         err++;
1484                 }
1485                 if(cmd->scan_begin_arg>TIMER_BASE*0xffffff){
1486                         cmd->scan_begin_arg=TIMER_BASE*0xffffff;
1487                         err++;
1488                 }
1489         }else if(cmd->scan_begin_src==TRIG_EXT){
1490                 /* external trigger */
1491                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1492
1493                 if(tmp>9)tmp=9;
1494                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1495                 if(cmd->scan_begin_arg!=tmp){
1496                         cmd->scan_begin_arg = tmp;
1497                         err++;
1498                 }
1499         }else{ /* TRIG_OTHER */
1500                 if(cmd->scan_begin_arg){
1501                         cmd->scan_begin_arg=0;
1502                         err++;
1503                 }
1504         }
1505         if(cmd->convert_src==TRIG_TIMER){
1506                 if(boardtype.reg_type == ni_reg_611x){
1507                         if(cmd->convert_arg != 0){
1508                                 cmd->convert_arg = 0;
1509                                 err++;
1510                         }
1511                 }else{
1512                         if(cmd->convert_arg<boardtype.ai_speed){
1513                                 cmd->convert_arg=boardtype.ai_speed;
1514                                 err++;
1515                         }
1516                         if(cmd->convert_arg>TIMER_BASE*0xffff){
1517                                 cmd->convert_arg=TIMER_BASE*0xffff;
1518                                 err++;
1519                         }
1520                 }
1521         }else if(cmd->convert_src == TRIG_EXT){
1522                 /* external trigger */
1523                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1524
1525                 if(tmp>9)tmp=9;
1526                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1527                 if(cmd->convert_arg!=tmp){
1528                         cmd->convert_arg = tmp;
1529                         err++;
1530                 }
1531         }else if(cmd->convert_src == TRIG_NOW){
1532                 if(cmd->convert_arg != 0){
1533                         cmd->convert_arg = 0;
1534                         err++;
1535                 }
1536         }
1537
1538         if(cmd->scan_end_arg!=cmd->chanlist_len){
1539                 cmd->scan_end_arg=cmd->chanlist_len;
1540                 err++;
1541         }
1542         if(cmd->stop_src==TRIG_COUNT){
1543                 unsigned int max_count = 0x01000000;
1544
1545                 if(boardtype.reg_type == ni_reg_611x )
1546                         max_count -= num_adc_stages_611x;
1547                 if(cmd->stop_arg > max_count){
1548                         cmd->stop_arg = max_count;
1549                         err++;
1550                 }
1551                 if(cmd->stop_arg < 1){
1552                         cmd->stop_arg = 1;
1553                         err++;
1554                 }
1555         }else{
1556                 /* TRIG_NONE */
1557                 if(cmd->stop_arg!=0){
1558                         cmd->stop_arg=0;
1559                         err++;
1560                 }
1561         }
1562
1563         if(err)return 3;
1564
1565         /* step 4: fix up any arguments */
1566
1567         if(cmd->scan_begin_src==TRIG_TIMER){
1568                 tmp=cmd->scan_begin_arg;
1569                 ni_ns_to_timer(&cmd->scan_begin_arg,cmd->flags&TRIG_ROUND_MASK);
1570                 if(tmp!=cmd->scan_begin_arg)err++;
1571         }
1572         if(cmd->convert_src==TRIG_TIMER){
1573                 if(boardtype.reg_type != ni_reg_611x){
1574                         tmp=cmd->convert_arg;
1575                         ni_ns_to_timer(&cmd->convert_arg,cmd->flags&TRIG_ROUND_MASK);
1576                         if(tmp!=cmd->convert_arg)err++;
1577                         if(cmd->scan_begin_src==TRIG_TIMER &&
1578                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1579                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1580                                 err++;
1581                         }
1582                 }
1583         }
1584
1585         if(err)return 4;
1586
1587         return 0;
1588 }
1589
1590 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1591 {
1592         comedi_cmd *cmd=&s->async->cmd;
1593         int timer;
1594         int mode1=0; /* mode1 is needed for both stop and convert */
1595         int mode2=0;
1596         int start_stop_select=0;
1597         unsigned int stop_count;
1598         int interrupt_a_enable=0;
1599
1600         MDPRINTK("ni_ai_cmd\n");
1601         if(dev->irq == 0)
1602         {
1603                 comedi_error(dev, "cannot run command without an irq");
1604                 return -EIO;
1605         }
1606         devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
1607
1608         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1609
1610         /* start configuration */
1611         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1612
1613         /* disable analog triggering for now, since it
1614          * interferes with the use of pfi0 */
1615         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1616         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1617
1618         switch(cmd->start_src){
1619                 case TRIG_INT:
1620                 case TRIG_NOW:
1621                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1622                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1623                                 AI_Trigger_Select_Register);
1624                         break;
1625                 case TRIG_EXT:
1626                 {
1627                         int chan = CR_CHAN(cmd->start_arg);
1628                         unsigned int bits = AI_START2_Select(0)|
1629                                 AI_START1_Sync |
1630                                 AI_START1_Select(chan + 1);
1631
1632                         if(cmd->start_arg & CR_INVERT)
1633                                 bits |= AI_START1_Polarity;
1634                         if(cmd->start_arg & CR_EDGE)
1635                                 bits |= AI_START1_Edge;
1636                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1637                         break;
1638                 }
1639         }
1640
1641         mode2 &= ~AI_Pre_Trigger;
1642         mode2 &= ~AI_SC_Initial_Load_Source;
1643         mode2 &= ~AI_SC_Reload_Mode;
1644         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1645
1646         if(cmd->chanlist_len == 1 || boardtype.reg_type == ni_reg_611x){
1647                 start_stop_select |= AI_STOP_Polarity;
1648                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1649                 start_stop_select |= AI_STOP_Sync;
1650         }else
1651         {
1652                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
1653         }
1654         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1655
1656         devpriv->ai_cmd2 = 0;
1657         switch(cmd->stop_src){
1658         case TRIG_COUNT:
1659                 stop_count = cmd->stop_arg - 1;
1660
1661                 if(boardtype.reg_type == ni_reg_611x){
1662                         // have to take 3 stage adc pipeline into account
1663                         stop_count += num_adc_stages_611x;
1664                 }
1665                 /* stage number of scans */
1666                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
1667
1668                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1669                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1670                 /* load SC (Scan Count) */
1671                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1672
1673                 devpriv->ai_continuous = 0;
1674                 if( stop_count == 0 ){
1675                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1676                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1677                         // this is required to get the last sample for chanlist_len > 1, not sure why
1678                         if(cmd->chanlist_len > 1)
1679                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
1680                 }
1681                 break;
1682         case TRIG_NONE:
1683                 /* stage number of scans */
1684                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
1685
1686                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1687                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1688
1689                 /* load SC (Scan Count) */
1690                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1691
1692                 devpriv->ai_continuous = 1;
1693
1694                 break;
1695         }
1696
1697         switch(cmd->scan_begin_src){
1698         case TRIG_TIMER:
1699                 /*
1700                         stop bits for non 611x boards
1701                         AI_SI_Special_Trigger_Delay=0
1702                         AI_Pre_Trigger=0
1703                         AI_START_STOP_Select_Register:
1704                         AI_START_Polarity=0 (?) rising edge
1705                         AI_START_Edge=1         edge triggered
1706                         AI_START_Sync=1 (?)
1707                         AI_START_Select=0               SI_TC
1708                         AI_STOP_Polarity=0              rising edge
1709                         AI_STOP_Edge=0          level
1710                         AI_STOP_Sync=1
1711                         AI_STOP_Select=19               external pin (configuration mem)
1712                  */
1713                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1714                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1715
1716                 mode2 |= AI_SI_Reload_Mode(0);
1717                 /* AI_SI_Initial_Load_Source=A */
1718                 mode2 &= ~AI_SI_Initial_Load_Source;
1719                 //mode2 |= AI_SC_Reload_Mode;
1720                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1721
1722                 /* load SI */
1723                 timer=ni_ns_to_timer(&cmd->scan_begin_arg,TRIG_ROUND_NEAREST);
1724                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
1725                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
1726                 break;
1727         case TRIG_EXT:
1728                 if( cmd->scan_begin_arg & CR_EDGE )
1729                         start_stop_select |= AI_START_Edge;
1730                 /* AI_START_Polarity==1 is falling edge */
1731                 if( cmd->scan_begin_arg & CR_INVERT )
1732                         start_stop_select |= AI_START_Polarity;
1733                 if( cmd->scan_begin_src != cmd->convert_src ||
1734                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1735                         start_stop_select |= AI_START_Sync;
1736                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
1737                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1738                 break;
1739         }
1740
1741         switch(cmd->convert_src){
1742         case TRIG_TIMER:
1743         case TRIG_NOW:
1744                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
1745                         timer = 1;
1746                 else
1747                         timer=ni_ns_to_timer(&cmd->convert_arg, TRIG_ROUND_NEAREST);
1748                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
1749                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
1750
1751                 /* AI_SI2_Reload_Mode = alternate */
1752                 /* AI_SI2_Initial_Load_Source = A */
1753                 mode2 &= ~AI_SI2_Initial_Load_Source;
1754                 mode2 |= AI_SI2_Reload_Mode;
1755                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
1756
1757                 /* AI_SI2_Load */
1758                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
1759
1760                 mode2 |= AI_SI2_Reload_Mode; // alternate
1761                 mode2 |= AI_SI2_Initial_Load_Source; // B
1762
1763                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
1764                 break;
1765         case TRIG_EXT:
1766                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
1767                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
1768                         mode1 |= AI_CONVERT_Source_Polarity;
1769                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1770
1771                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
1772                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1773
1774                 break;
1775         }
1776
1777         if(dev->irq){
1778
1779                 /* interrupt on FIFO, errors, SC_TC */
1780                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
1781                         AI_SC_TC_Interrupt_Enable;
1782
1783 #ifndef PCIDMA
1784                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
1785 #endif
1786
1787                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
1788                         /* wake on end-of-scan */
1789                         devpriv->aimode=AIMODE_SCAN;
1790                 }else{
1791                         devpriv->aimode=AIMODE_HALF_FULL;
1792                 }
1793
1794                 switch(devpriv->aimode){
1795                 case AIMODE_HALF_FULL:
1796                         /*generate FIFO interrupts and DMA requests on half-full */
1797 #ifdef PCIDMA
1798                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
1799 #else
1800                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
1801 #endif
1802                         break;
1803                 case AIMODE_SAMPLE:
1804                         /*generate FIFO interrupts on non-empty */
1805                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
1806                         break;
1807                 case AIMODE_SCAN:
1808 #ifdef PCIDMA
1809                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
1810 #else
1811                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
1812 #endif
1813                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1814                         break;
1815                 default:
1816                         break;
1817                 }
1818
1819                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
1820
1821                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
1822
1823                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
1824         }else{
1825                 /* interrupt on nothing */
1826                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
1827
1828                 /* XXX start polling if necessary */
1829                 MDPRINTK("interrupting on nothing\n");
1830         }
1831
1832         /* end configuration */
1833         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1834
1835         switch(cmd->scan_begin_src){
1836         case TRIG_TIMER:
1837                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
1838                         AI_Command_1_Register);
1839                 break;
1840         case TRIG_EXT:
1841                 /* XXX AI_SI_Arm? */
1842                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
1843                         AI_Command_1_Register);
1844                 break;
1845         }
1846
1847 #ifdef PCIDMA
1848         ni_ai_setup_MITE_dma(dev,cmd);
1849         //mite_dump_regs(devpriv->mite);
1850 #endif
1851
1852         switch(cmd->start_src){
1853         case TRIG_NOW:
1854                 /* AI_START1_Pulse */
1855                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
1856                 s->async->inttrig=NULL;
1857                 break;
1858         case TRIG_EXT:
1859                 s->async->inttrig=NULL;
1860                 break;
1861         case TRIG_INT:
1862                 s->async->inttrig=ni_ai_inttrig;
1863                 break;
1864         }
1865
1866         MDPRINTK("exit ni_ai_cmd\n");
1867
1868         return 0;
1869 }
1870
1871 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
1872         unsigned int trignum)
1873 {
1874         if(trignum!=0)return -EINVAL;
1875
1876         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
1877         s->async->inttrig=NULL;
1878
1879         return 1;
1880 }
1881
1882 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
1883         comedi_insn *insn, lsampl_t *data);
1884
1885 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
1886         comedi_insn *insn, lsampl_t *data)
1887 {
1888         if(insn->n<1)return -EINVAL;
1889
1890         switch(data[0]){
1891         case INSN_CONFIG_ANALOG_TRIG:
1892                 return ni_ai_config_analog_trig(dev,s,insn,data);
1893         case INSN_CONFIG_ALT_SOURCE:
1894                 {
1895                 unsigned int calib_source;
1896                 unsigned int calib_source_adjust;
1897
1898                 calib_source = data[1] & 0xf;
1899                 calib_source_adjust = ( data[1] >> 4 ) & 0xff;
1900
1901                 if(calib_source >= 8)
1902                         return -EINVAL;
1903                 devpriv->ai_calib_source = calib_source;
1904                 if(boardtype.reg_type == ni_reg_611x){
1905                         ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
1906                 }
1907                 return 2;
1908                 }
1909         default:
1910                 break;
1911         }
1912
1913         return -EINVAL;
1914 }
1915
1916 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
1917         comedi_insn *insn, lsampl_t *data)
1918 {
1919         unsigned int a,b,modebits;
1920         int err=0;
1921
1922         /* data[1] is flags
1923          * data[2] is analog line
1924          * data[3] is set level
1925          * data[4] is reset level */
1926         if(!boardtype.has_analog_trig)return -EINVAL;
1927         if(insn->n!=5)return -EINVAL;
1928         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
1929                 data[1]&=~(COMEDI_EV_SCAN_BEGIN&0xffff);
1930                 err++;
1931         }
1932         if(data[2]>=boardtype.n_adchan){
1933                 data[2]=boardtype.n_adchan-1;
1934                 err++;
1935         }
1936         if(data[3]>255){ /* a */
1937                 data[3]=255;
1938                 err++;
1939         }
1940         if(data[4]>255){ /* b */
1941                 data[4]=255;
1942                 err++;
1943         }
1944         /*
1945          * 00 ignore
1946          * 01 set
1947          * 10 reset
1948          *
1949          * modes:
1950          *   1 level:                    +b-   +a-
1951          *     high mode                00 00 01 10
1952          *     low mode                 00 00 10 01
1953          *   2 level: (a<b)
1954          *     hysteresis low mode      10 00 00 01
1955          *     hysteresis high mode     01 00 00 10
1956          *     middle mode              10 01 01 10
1957          */
1958
1959         a=data[3];
1960         b=data[4];
1961         modebits=data[1]&0xff;
1962         if(modebits&0xf0){
1963                 /* two level mode */
1964                 if(b<a){
1965                         /* swap order */
1966                         a=data[4];
1967                         b=data[3];
1968                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
1969                 }
1970                 devpriv->atrig_low = a;
1971                 devpriv->atrig_high = b;
1972                 switch(modebits){
1973                 case 0x81:      /* low hysteresis mode */
1974                         devpriv->atrig_mode = 6;
1975                         break;
1976                 case 0x42:      /* high hysteresis mode */
1977                         devpriv->atrig_mode = 3;
1978                         break;
1979                 case 0x96:      /* middle window mode */
1980                         devpriv->atrig_mode = 2;
1981                         break;
1982                 default:
1983                         data[1]&=~0xff;
1984                         err++;
1985                 }
1986         }else{
1987                 /* one level mode */
1988                 if(b!=0){
1989                         data[4]=0;
1990                         err++;
1991                 }
1992                 switch(modebits){
1993                 case 0x06:      /* high window mode */
1994                         devpriv->atrig_high = a;
1995                         devpriv->atrig_mode = 0;
1996                         break;
1997                 case 0x09:      /* low window mode */
1998                         devpriv->atrig_low = a;
1999                         devpriv->atrig_mode = 1;
2000                         break;
2001                 default:
2002                         data[1]&=~0xff;
2003                         err++;
2004                 }
2005         }
2006         if(err)return -EAGAIN;
2007         return 5;
2008 }
2009
2010 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2011 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2012         void *data, unsigned int num_bytes, unsigned int chan_index )
2013 {
2014         comedi_async *async = s->async;
2015         unsigned int range;
2016         unsigned int i;
2017         unsigned int offset;
2018         unsigned int length = num_bytes / sizeof( sampl_t );
2019         sampl_t *array = data;
2020
2021         offset = 1 << (boardtype.aobits - 1);
2022         for(i = 0; i < length; i++)
2023         {
2024                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2025                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2026                         array[i] -= offset;
2027 #ifdef PCIDMA
2028                 array[i] = cpu_to_le16( array[i] );
2029 #endif
2030                 chan_index++;
2031                 chan_index %= async->cmd.chanlist_len;
2032         }
2033 }
2034
2035 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2036         unsigned int chanspec[], unsigned int n_chans)
2037 {
2038         unsigned int range;
2039         unsigned int chan;
2040         unsigned int conf;
2041         int i;
2042         int invert = 0;
2043
2044         for(i=0;i<n_chans;i++){
2045                 chan = CR_CHAN(chanspec[i]);
2046                 range = CR_RANGE(chanspec[i]);
2047                 if(boardtype.reg_type == ni_reg_m_series)
2048                 {
2049                         comedi_krange *krange = s->range_table->range + range;
2050                         invert = 0;
2051                         conf = 0;
2052                         switch(krange->max - krange->min)
2053                         {
2054                         case 20000000:
2055                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2056                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2057                                 break;
2058                         case 10000000:
2059                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2060                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2061                                 break;
2062                         case 4000000:
2063                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2064                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2065                                 break;
2066                         case 2000000:
2067                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2068                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2069                                 break;
2070                         default:
2071                                 rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2072                                 break;
2073                         }
2074                         switch(krange->max + krange->min)
2075                         {
2076                         case 0:
2077                                 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2078                                 break;
2079                         case 10000000:
2080                                 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2081                                 break;
2082                         default:
2083                                 rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2084                                 break;
2085                         }
2086                         ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2087                 }else
2088                 {
2089                         conf = AO_Channel(chan);
2090
2091                         if(boardtype.ao_unipolar){
2092                                 if((range&1) == 0){
2093                                         conf |= AO_Bipolar;
2094                                         invert = (1<<(boardtype.aobits-1));
2095                                 }else{
2096                                         invert = 0;
2097                                 }
2098                                 if(range&2)
2099                                         conf |= AO_Ext_Ref;
2100                         }else{
2101                                 conf |= AO_Bipolar;
2102                                 invert = (1<<(boardtype.aobits-1));
2103                         }
2104
2105                         /* not all boards can deglitch, but this shouldn't hurt */
2106                         if(chanspec[i] & CR_DEGLITCH)
2107                                 conf |= AO_Deglitch;
2108
2109                         /* analog reference */
2110                         /* AREF_OTHER connects AO ground to AI ground, i think */
2111                         conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2112
2113                         ni_writew(conf,AO_Configuration);
2114                 }
2115                 devpriv->ao_conf[chan] = conf;
2116         }
2117         return invert;
2118 }
2119
2120 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2121         comedi_insn *insn,lsampl_t *data)
2122 {
2123         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2124
2125         return 1;
2126 }
2127
2128 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2129         comedi_insn *insn,lsampl_t *data)
2130 {
2131         unsigned int chan = CR_CHAN(insn->chanspec);
2132         unsigned int invert;
2133
2134         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2135
2136         devpriv->ao[chan] = data[0];
2137
2138         if(boardtype.reg_type == ni_reg_m_series)
2139         {
2140                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2141         }
2142         else
2143                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2144
2145         return 1;
2146 }
2147
2148 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2149         comedi_insn *insn,lsampl_t *data)
2150 {
2151         unsigned int chan = CR_CHAN(insn->chanspec);
2152         unsigned int invert;
2153
2154         ao_win_out(1 << chan, AO_Immediate_671x);
2155         invert = 1 << (boardtype.aobits - 1);
2156
2157         ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2158
2159         devpriv->ao[chan] = data[0];
2160         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2161
2162         return 1;
2163 }
2164
2165 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2166         unsigned int trignum)
2167 {
2168         int ret;
2169         int interrupt_b_bits;
2170         int i;
2171         static const int timeout = 1000;
2172
2173         if(trignum!=0)return -EINVAL;
2174
2175         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2176         interrupt_b_bits = AO_Error_Interrupt_Enable;
2177 #ifdef PCIDMA
2178         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2179         if(boardtype.reg_type & ni_reg_6xxx_mask)
2180                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2181         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2182         ret = ni_ao_wait_for_dma_load(dev);
2183         if(ret < 0) return ret;
2184
2185 #else
2186         ret = ni_ao_prep_fifo(dev,s);
2187         if(ret==0)return -EPIPE;
2188
2189         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2190 #endif
2191
2192         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2193         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2194         /* wait for DACs to be loaded */
2195         for(i = 0; i < timeout; i++)
2196         {
2197                 comedi_udelay(10);
2198                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2199                         break;
2200         }
2201         if(i == timeout)
2202         {
2203                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2204                 return -EIO;
2205         }
2206         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2207         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2208
2209         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2210
2211         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2212                 AO_Command_1_Register);
2213
2214         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2215
2216         s->async->inttrig=NULL;
2217
2218         return 0;
2219 }
2220
2221 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2222 {
2223         comedi_cmd *cmd = &s->async->cmd;
2224         int trigvar;
2225         int bits;
2226         int i;
2227
2228         if(dev->irq == 0)
2229         {
2230                 comedi_error(dev, "cannot run command without an irq");
2231                 return -EIO;
2232         }
2233         trigvar = ni_ns_to_timer(&cmd->scan_begin_arg,TRIG_ROUND_NEAREST);
2234
2235         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2236
2237         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2238
2239         if(boardtype.reg_type & ni_reg_6xxx_mask)
2240         {
2241                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2242
2243                 bits = 0;
2244                 for(i = 0; i < cmd->chanlist_len; i++)
2245                 {
2246                         int chan;
2247
2248                         chan = CR_CHAN(cmd->chanlist[i]);
2249                         bits |= 1 << chan;
2250                         ao_win_out(chan, AO_Waveform_Generation_611x);
2251                 }
2252                 ao_win_out(bits, AO_Timed_611x);
2253         }
2254
2255         ni_ao_config_chanlist(dev,s,cmd->chanlist,cmd->chanlist_len);
2256
2257         if(cmd->stop_src==TRIG_NONE){
2258                 devpriv->ao_mode1|=AO_Continuous;
2259                 devpriv->ao_mode1&=~AO_Trigger_Once;
2260         }else{
2261                 devpriv->ao_mode1&=~AO_Continuous;
2262                 devpriv->ao_mode1|=AO_Trigger_Once;
2263         }
2264         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2265         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2266         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2267         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2268         devpriv->ao_mode3&=~AO_Trigger_Length;
2269         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2270
2271         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2272         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2273         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2274         if(cmd->stop_src==TRIG_NONE){
2275                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2276         }else{
2277                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2278         }
2279         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2280         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2281         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2282         switch(cmd->stop_src){
2283         case TRIG_COUNT:
2284                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2285                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2286                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2287                 break;
2288         case TRIG_NONE:
2289                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2290                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2291                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2292                 break;
2293         default:
2294                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2295                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2296                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2297         }
2298
2299         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2300         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2301         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2302         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2303         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2304         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2305         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2306         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2307         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2308
2309         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2310                 if(cmd->scan_end_arg>1){
2311                         devpriv->ao_mode1|=AO_Multiple_Channels;
2312                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2313                                 AO_UPDATE_Output_Select(1),
2314                                 AO_Output_Control_Register);
2315                 }else{
2316                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2317                         devpriv->stc_writew(dev, AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]))|
2318                                 AO_UPDATE_Output_Select(1),
2319                                 AO_Output_Control_Register);
2320                 }
2321                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2322         }
2323
2324         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2325
2326         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2327         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2328
2329         devpriv->ao_mode2 &= AO_FIFO_Mode_Mask;
2330 #ifdef PCIDMA
2331         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2332 #else
2333         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2334 #endif
2335         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2336         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2337
2338         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2339                 AO_TMRDACWR_Pulse_Width;
2340         if( boardtype.ao_fifo_depth )
2341                 bits |= AO_FIFO_Enable;
2342         else
2343                 bits |= AO_DMA_PIO_Control;
2344         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2345         // enable sending of ao dma requests
2346         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2347
2348         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2349
2350         if(cmd->stop_src==TRIG_COUNT) {
2351                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2352                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2353                         AO_BC_TC_Interrupt_Enable, 1);
2354         }
2355
2356         s->async->inttrig=ni_ao_inttrig;
2357
2358         return 0;
2359 }
2360
2361 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2362 {
2363         int err=0;
2364         int tmp;
2365
2366         /* step 1: make sure trigger sources are trivially valid */
2367
2368         tmp=cmd->start_src;
2369         cmd->start_src &= TRIG_INT;
2370         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2371
2372         tmp=cmd->scan_begin_src;
2373         cmd->scan_begin_src &= TRIG_TIMER;
2374         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2375
2376         tmp=cmd->convert_src;
2377         cmd->convert_src &= TRIG_NOW;
2378         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2379
2380         tmp=cmd->scan_end_src;
2381         cmd->scan_end_src &= TRIG_COUNT;
2382         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2383
2384         tmp=cmd->stop_src;
2385         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2386         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2387
2388         if(err)return 1;
2389
2390         /* step 2: make sure trigger sources are unique and mutually compatible */
2391
2392         if(cmd->stop_src!=TRIG_COUNT &&
2393            cmd->stop_src!=TRIG_NONE)err++;
2394
2395         if(err)return 2;
2396
2397         /* step 3: make sure arguments are trivially compatible */
2398
2399         if(cmd->start_arg!=0){
2400                 cmd->start_arg=0;
2401                 err++;
2402         }
2403 #if 0
2404         /* XXX need ao_speed */
2405         if(cmd->scan_begin_arg<boardtype.ao_speed){
2406                 cmd->scan_begin_arg=boardtype.ao_speed;
2407                 err++;
2408         }
2409 #endif
2410         if(cmd->scan_begin_arg>TIMER_BASE*0xffffff){ /* XXX check */
2411                 cmd->scan_begin_arg=TIMER_BASE*0xffffff;
2412                 err++;
2413         }
2414         if(cmd->convert_arg!=0){
2415                 cmd->convert_arg=0;
2416                 err++;
2417         }
2418         if(cmd->scan_end_arg!=cmd->chanlist_len){
2419                 cmd->scan_end_arg=cmd->chanlist_len;
2420                 err++;
2421         }
2422         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2423                 if(cmd->stop_arg>0x00ffffff){
2424                         cmd->stop_arg=0x00ffffff;
2425                         err++;
2426                 }
2427         }else{
2428                 /* TRIG_NONE */
2429                 if(cmd->stop_arg!=0){
2430                         cmd->stop_arg=0;
2431                         err++;
2432                 }
2433         }
2434
2435         if(err)return 3;
2436
2437         /* step 4: fix up any arguments */
2438
2439         tmp = cmd->scan_begin_arg;
2440         ni_ns_to_timer(&cmd->scan_begin_arg,cmd->flags&TRIG_ROUND_MASK);
2441         if(tmp!=cmd->scan_begin_arg)err++;
2442
2443         if(err)return 4;
2444
2445         /* step 5: fix up chanlist */
2446
2447         if(err)return 5;
2448
2449         return 0;
2450 }
2451
2452
2453 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2454 {
2455         //devpriv->ao0p=0x0000;
2456         //ni_writew(devpriv->ao0p,AO_Configuration);
2457
2458         //devpriv->ao1p=AO_Channel(1);
2459         //ni_writew(devpriv->ao1p,AO_Configuration);
2460
2461 #ifdef PCIDMA
2462         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2463         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
2464 #endif
2465
2466         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2467         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2468         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2469         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2470         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2471         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2472                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2473         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2474         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2475         devpriv->ao_cmd1=0;
2476         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2477         devpriv->ao_cmd2=0;
2478         devpriv->ao_mode1=0;
2479         devpriv->ao_mode2=0;
2480         if(boardtype.reg_type == ni_reg_m_series)
2481                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2482         else
2483                 devpriv->ao_mode3 = 0;
2484         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2485         devpriv->ao_trigger_select=0;
2486         if(boardtype.reg_type & ni_reg_6xxx_mask){
2487                 ao_win_out(0x3, AO_Immediate_671x);
2488                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2489         }
2490         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2491
2492         return 0;
2493 }
2494
2495 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2496         comedi_insn *insn,lsampl_t *data)
2497 {
2498 #ifdef DEBUG_DIO
2499         printk("ni_dio_insn_config() chan=%d io=%d\n",
2500                 CR_CHAN(insn->chanspec),data[0]);
2501 #endif
2502         switch(data[0]){
2503         case INSN_CONFIG_DIO_OUTPUT:
2504                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2505                 break;
2506         case INSN_CONFIG_DIO_INPUT:
2507                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2508                 break;
2509         case INSN_CONFIG_DIO_QUERY:
2510                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2511                 return insn->n;
2512                 break;
2513         default:
2514                 return -EINVAL;
2515         }
2516
2517         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2518         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2519         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2520
2521         return 1;
2522 }
2523
2524 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2525         comedi_insn *insn,lsampl_t *data)
2526 {
2527 #ifdef DEBUG_DIO
2528         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2529 #endif
2530         if(insn->n!=2)return -EINVAL;
2531         if(data[0]){
2532                 /* Perform check to make sure we're not using the
2533                    serial part of the dio */
2534                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2535                         return -EBUSY;
2536
2537                 s->state &= ~data[0];
2538                 s->state |= (data[0]&data[1]);
2539                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2540                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2541                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2542         }
2543         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2544
2545         return 2;
2546 }
2547
2548 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2549                                  comedi_insn *insn,lsampl_t *data)
2550 {
2551         int err = insn->n;
2552         unsigned char byte_out, byte_in;
2553
2554         if(insn->n!=2)return -EINVAL;
2555
2556         switch(data[0]) {
2557         case INSN_CONFIG_SERIAL_CLOCK:
2558
2559 #ifdef DEBUG_DIO
2560                 printk("SPI serial clock Config cd\n", data[1]);
2561 #endif
2562                 devpriv->serial_hw_mode = 1;
2563                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2564
2565                 if(data[1] == SERIAL_DISABLED) {
2566                         devpriv->serial_hw_mode = 0;
2567                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2568                                                   DIO_Software_Serial_Control);
2569                         data[1] = SERIAL_DISABLED;
2570                         devpriv->serial_interval_ns = data[1];
2571                 }
2572                 else if(data[1] <= SERIAL_600NS) {
2573                         /* Warning: this clock speed is too fast to reliably
2574                         control SCXI. */
2575                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2576                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2577                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2578                         data[1] = SERIAL_600NS;
2579                         devpriv->serial_interval_ns = data[1];
2580                 }
2581                 else if(data[1] <= SERIAL_1_2US) {
2582                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2583                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2584                                 DIO_Serial_Out_Divide_By_2;
2585                         data[1] = SERIAL_1_2US;
2586                         devpriv->serial_interval_ns = data[1];
2587                 }
2588                 else if(data[1] <= SERIAL_10US) {
2589                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2590                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2591                                 DIO_Serial_Out_Divide_By_2;
2592                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2593                         600ns/1.2us. If you turn divide_by_2 off with the
2594                         slow clock, you will still get 10us, except then
2595                         all your delays are wrong. */
2596                         data[1] = SERIAL_10US;
2597                         devpriv->serial_interval_ns = data[1];
2598                 }
2599                 else {
2600                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2601                                                   DIO_Software_Serial_Control);
2602                         devpriv->serial_hw_mode = 0;
2603                         data[1] = (data[1] / 1000) * 1000;
2604                         devpriv->serial_interval_ns = data[1];
2605                 }
2606
2607                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2608                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
2609                 return 1;
2610
2611         break;
2612
2613         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2614
2615                 if(devpriv->serial_interval_ns == 0) {
2616                         return -EINVAL;
2617                 }
2618
2619                 byte_out = data[1] & 0xFF;
2620
2621                 if(devpriv->serial_hw_mode) {
2622                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2623                 } else if(devpriv->serial_interval_ns > 0) {
2624                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2625                 } else {
2626                         printk("ni_serial_insn_config: serial disabled!\n");
2627                         return -EINVAL;
2628                 }
2629                 if(err < 0) return err;
2630                 data[1] = byte_in & 0xFF;
2631                 return insn->n;
2632
2633         break;
2634         default:
2635                 return -EINVAL;
2636         }
2637
2638 }
2639
2640 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2641                                    unsigned char data_out,
2642                                    unsigned char *data_in)
2643 {
2644         unsigned int status1;
2645         int err = 0, count = 20;
2646
2647 #ifdef DEBUG_DIO
2648         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
2649 #endif
2650
2651         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
2652         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
2653         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2654
2655         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
2656         if(status1 & DIO_Serial_IO_In_Progress_St) {
2657                 err = -EBUSY;
2658                 goto Error;
2659         }
2660
2661         devpriv->dio_control |= DIO_HW_Serial_Start;
2662         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2663         devpriv->dio_control &= ~DIO_HW_Serial_Start;
2664
2665         /* Wait until STC says we're done, but don't loop infinitely. */
2666         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
2667                 /* Delay one bit per loop */
2668                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2669                 if(--count < 0) {
2670                         printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
2671                         err = -ETIME;
2672                         goto Error;
2673                 }
2674         }
2675
2676         /* Delay for last bit. This delay is absolutely necessary, because
2677            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
2678         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2679
2680         if(data_in != NULL) {
2681                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
2682 #ifdef DEBUG_DIO
2683                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
2684 #endif
2685         }
2686
2687  Error:
2688         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2689
2690         return err;
2691 }
2692
2693 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2694                                    unsigned char data_out,
2695                                    unsigned char *data_in)
2696 {
2697         unsigned char mask, input = 0;
2698
2699 #ifdef DEBUG_DIO
2700         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
2701 #endif
2702
2703         /* Wait for one bit before transfer */
2704         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2705
2706         for(mask = 0x80; mask; mask >>= 1) {
2707                 /* Output current bit; note that we cannot touch s->state
2708            because it is a per-subdevice field, and serial is
2709                    a separate subdevice from DIO. */
2710                 devpriv->dio_output &= ~DIO_SDOUT;
2711                 if(data_out & mask) {
2712                         devpriv->dio_output |= DIO_SDOUT;
2713                 }
2714                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2715
2716                 /* Assert SDCLK (active low, inverted), wait for half of
2717                    the delay, deassert SDCLK, and wait for the other half. */
2718                 devpriv->dio_control |= DIO_Software_Serial_Control;
2719                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2720
2721                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
2722
2723                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
2724                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2725
2726                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
2727
2728                 /* Input current bit */
2729                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
2730 /*                      printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
2731                         input |= mask;
2732                 }
2733         }
2734 #ifdef DEBUG_DIO
2735         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
2736 #endif
2737         if(data_in) *data_in = input;
2738
2739         return 0;
2740 }
2741
2742 static void mio_common_detach(comedi_device *dev)
2743 {
2744         if(dev->subdevices && boardtype.has_8255)
2745                 subdev_8255_cleanup(dev,dev->subdevices+3);
2746 }
2747
2748 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
2749 {
2750         int i;
2751
2752         for(i = 0; i < s->n_chan; i++)
2753                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
2754 }
2755
2756 static int ni_alloc_private(comedi_device *dev)
2757 {
2758         int ret;
2759
2760         ret = alloc_private(dev, sizeof(ni_private));
2761         if(ret < 0) return ret;
2762
2763         spin_lock_init(&devpriv->window_lock);
2764
2765         return 0;
2766 };
2767
2768 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
2769 {
2770         comedi_subdevice *s;
2771         int bits;
2772
2773         if(boardtype.n_aochan > MAX_N_AO_CHAN)
2774         {
2775                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
2776                 return -EINVAL;
2777         }
2778
2779         if(alloc_subdevices(dev, 10) < 0)
2780                 return -ENOMEM;
2781
2782         /* analog input subdevice */
2783
2784         s=dev->subdevices+0;
2785         dev->read_subdev=s;
2786         if(boardtype.n_adchan){
2787                 s->type=COMEDI_SUBD_AI;
2788                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER;
2789                 if(boardtype.reg_type != ni_reg_611x)
2790                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
2791                 if(boardtype.adbits > 16)
2792                         s->subdev_flags |= SDF_LSAMPL;
2793                 s->n_chan=boardtype.n_adchan;
2794                 s->len_chanlist=512;
2795                 s->maxdata=(1<<boardtype.adbits)-1;
2796                 s->range_table=ni_range_lkup[boardtype.gainlkup];
2797                 s->insn_read=ni_ai_insn_read;
2798                 s->insn_config=ni_ai_insn_config;
2799                 s->do_cmdtest=ni_ai_cmdtest;
2800                 s->do_cmd=ni_ai_cmd;
2801                 s->cancel=ni_ai_reset;
2802                 s->poll=ni_ai_poll;
2803                 s->munge=ni_ai_munge;
2804         }else{
2805                 s->type=COMEDI_SUBD_UNUSED;
2806         }
2807
2808         /* analog output subdevice */
2809
2810         s=dev->subdevices+1;
2811         if(boardtype.n_aochan){
2812                 dev->write_subdev=s;
2813                 s->type=COMEDI_SUBD_AO;
2814                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
2815                 s->n_chan=boardtype.n_aochan;
2816                 s->maxdata=(1<<boardtype.aobits)-1;
2817                 s->range_table = boardtype.ao_range_table;
2818                 s->insn_read=ni_ao_insn_read;
2819                 if(boardtype.reg_type & ni_reg_6xxx_mask){
2820                         s->insn_write=ni_ao_insn_write_671x;
2821                 }else{
2822                         s->insn_write=ni_ao_insn_write;
2823                 }
2824 #ifdef PCIDMA
2825                 if(boardtype.n_aochan){
2826 #else
2827                 if(boardtype.ao_fifo_depth){
2828 #endif
2829                         s->do_cmd=ni_ao_cmd;
2830                         s->do_cmdtest=ni_ao_cmdtest;
2831                         s->len_chanlist = boardtype.n_aochan;
2832                         if(boardtype.reg_type != ni_reg_m_series)
2833                                 s->munge=ni_ao_munge;
2834                 }
2835                 s->cancel=ni_ao_reset;
2836         }else{
2837                 s->type=COMEDI_SUBD_UNUSED;
2838         }
2839         if((boardtype.reg_type & ni_reg_67xx_mask))
2840                 init_ao_67xx(dev, s);
2841
2842         /* digital i/o subdevice */
2843
2844         s=dev->subdevices+2;
2845         s->type=COMEDI_SUBD_DIO;
2846         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
2847         s->n_chan=8;
2848         s->maxdata=1;
2849         s->range_table=&range_digital;
2850         s->io_bits=0;           /* all bits input */
2851         s->insn_bits=ni_dio_insn_bits;
2852         s->insn_config=ni_dio_insn_config;
2853
2854         /* dio setup */
2855         devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
2856         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2857
2858         /* 8255 device */
2859         s=dev->subdevices+3;
2860         if(boardtype.has_8255){
2861                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
2862         }else{
2863                 s->type=COMEDI_SUBD_UNUSED;
2864         }
2865
2866         /* general purpose counter/timer device */
2867         s=dev->subdevices+4;
2868         s->type=COMEDI_SUBD_COUNTER;
2869         s->subdev_flags=SDF_READABLE|SDF_WRITABLE;
2870         s->insn_read=  ni_gpct_insn_read;
2871         s->insn_write= ni_gpct_insn_write;
2872         s->insn_config=ni_gpct_insn_config;
2873         s->n_chan=2;
2874         s->maxdata=1;
2875         devpriv->an_trig_etc_reg = 0;
2876         GPCT_Reset(dev,0);
2877         GPCT_Reset(dev,1);
2878
2879         /* calibration subdevice -- ai and ao */
2880         s=dev->subdevices+5;
2881         s->type=COMEDI_SUBD_CALIB;
2882         s->subdev_flags=SDF_WRITABLE|SDF_INTERNAL;
2883         s->insn_read=ni_calib_insn_read;
2884         s->insn_write=ni_calib_insn_write;
2885         caldac_setup(dev,s);
2886
2887         /* EEPROM */
2888         s=dev->subdevices+6;
2889         s->type=COMEDI_SUBD_MEMORY;
2890         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
2891         s->n_chan=512;
2892         s->maxdata=0xff;
2893         s->insn_read=ni_eeprom_insn_read;
2894
2895         /* PFI */
2896         s=dev->subdevices+7;
2897         s->type=COMEDI_SUBD_DIO;
2898         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
2899         s->n_chan=10;
2900         s->maxdata=1;
2901         s->insn_bits = ni_pfi_insn_bits;
2902         s->insn_config = ni_pfi_insn_config;
2903         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
2904
2905         /* cs5529 calibration adc */
2906         s = dev->subdevices + 8;
2907         if(boardtype.reg_type & ni_reg_67xx_mask)
2908         {
2909                 s->type = COMEDI_SUBD_AI;
2910                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
2911                 // one channel for each analog output channel
2912                 s->n_chan = boardtype.n_aochan;
2913                 s->maxdata = (1 << 16) - 1;
2914                 s->range_table = &range_unknown; /* XXX */
2915                 s->insn_read=cs5529_ai_insn_read;
2916                 s->insn_config=NULL;
2917                 init_cs5529(dev);
2918         }else
2919         {
2920                 s->type=COMEDI_SUBD_UNUSED;
2921         }
2922
2923         /* Serial */
2924         s=dev->subdevices+9;
2925         s->type=COMEDI_SUBD_SERIAL;
2926         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
2927         s->n_chan=1;
2928         s->maxdata=0xff;
2929         s->insn_config = ni_serial_insn_config;
2930         devpriv->serial_interval_ns = 0;
2931         devpriv->serial_hw_mode = 0;
2932
2933         /* ai configuration */
2934         ni_ai_reset(dev,dev->subdevices+0);
2935         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2936                 devpriv->clock_and_fout =
2937                         Slow_Internal_Time_Divide_By_2 |
2938                         Slow_Internal_Timebase |
2939                         Clock_To_Board_Divide_By_2 |
2940                         Clock_To_Board |
2941                         AI_Output_Divide_By_2 |
2942                         AO_Output_Divide_By_2;
2943         }else{
2944                 devpriv->clock_and_fout =
2945                         Slow_Internal_Time_Divide_By_2 |
2946                         Slow_Internal_Timebase |
2947                         Clock_To_Board_Divide_By_2 |
2948                         Clock_To_Board;
2949         }
2950         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
2951
2952         /* analog output configuration */
2953         ni_ao_reset(dev,dev->subdevices + 1);
2954
2955         if(dev->irq){
2956                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
2957                         (Interrupt_Output_On_3_Pins&0) |
2958                         Interrupt_A_Enable |
2959                         Interrupt_B_Enable |
2960                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
2961                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
2962                         Interrupt_Control_Register
2963                 );
2964         }
2965
2966         /* DMA setup */
2967         /* tell the STC which dma channels to use for AI and AO */
2968         bits = 1 << ( AI_DMA_CHAN );
2969         bits |= 1 << ( AO_DMA_CHAN + 4 );
2970         ni_writeb( bits, AI_AO_Select);
2971         /* tell the STC which dma channels to use for
2972          * General purpose counters 0 and 1 */
2973         bits = 1 << ( GPC0_DMA_CHAN );
2974         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
2975         ni_writeb( bits, G0_G1_Select);
2976
2977         if(boardtype.reg_type & ni_reg_6xxx_mask)
2978         {
2979                 ni_writeb( 0, Magic_611x );
2980         }else if(boardtype.reg_type == ni_reg_m_series)
2981         {
2982                 int channel;
2983                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
2984                 {
2985                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
2986                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
2987                 }
2988                 ni_writeb(0x0, M_Offset_AO_Calibration);
2989         }
2990
2991         printk("\n");
2992
2993         return 0;
2994 }
2995
2996
2997
2998 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
2999 {
3000         comedi_device *dev=(comedi_device *)arg;
3001
3002         if(dir){
3003                 ni_writeb(data,Port_A+2*port);
3004                 return 0;
3005         }else{
3006                 return ni_readb(Port_A+2*port);
3007         }
3008 }
3009
3010 /*
3011         presents the EEPROM as a subdevice
3012 */
3013
3014 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3015         comedi_insn *insn,lsampl_t *data)
3016 {
3017         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3018
3019         return 1;
3020 }
3021
3022 /*
3023         reads bytes out of eeprom
3024 */
3025
3026 static int ni_read_eeprom(comedi_device *dev,int addr)
3027 {
3028         int bit;
3029         int bitstring;
3030
3031         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3032         ni_writeb(0x04,Serial_Command);
3033         for(bit=0x8000;bit;bit>>=1){
3034                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3035                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3036         }
3037         bitstring=0;
3038         for(bit=0x80;bit;bit>>=1){
3039                 ni_writeb(0x04,Serial_Command);
3040                 ni_writeb(0x05,Serial_Command);
3041                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3042         }
3043         ni_writeb(0x00,Serial_Command);
3044
3045         return bitstring;
3046 }
3047
3048 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3049 /*
3050         calibration subdevice
3051 */
3052 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3053         comedi_insn *insn,lsampl_t *data)
3054 {
3055         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3056
3057         return 1;
3058 }
3059
3060 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3061         comedi_insn *insn,lsampl_t *data)
3062 {
3063         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3064
3065         return 1;
3066 }
3067
3068 static int pack_mb88341(int addr,int val,int *bitstring);
3069 static int pack_dac8800(int addr,int val,int *bitstring);
3070 static int pack_dac8043(int addr,int val,int *bitstring);
3071 static int pack_ad8522(int addr,int val,int *bitstring);
3072 static int pack_ad8804(int addr,int val,int *bitstring);
3073 static int pack_ad8842(int addr,int val,int *bitstring);
3074
3075 struct caldac_struct{
3076         int n_chans;
3077         int n_bits;
3078         int (*packbits)(int,int,int *);
3079 };
3080
3081 static struct caldac_struct caldacs[] = {
3082         [mb88341] = { 12, 8, pack_mb88341 },
3083         [dac8800] = { 8, 8, pack_dac8800 },
3084         [dac8043] = { 1, 12, pack_dac8043 },
3085         [ad8522]  = { 2, 12, pack_ad8522 },
3086         [ad8804] = { 12, 8, pack_ad8804 },
3087         [ad8842] = { 8, 8, pack_ad8842 },
3088         [ad8804_debug] = { 16, 8, pack_ad8804 },
3089 };
3090
3091 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3092 {
3093         int i,j;
3094         int n_dacs;
3095         int n_chans=0;
3096         int n_bits;
3097         int diffbits=0;
3098         int type;
3099         int chan;
3100
3101         type = boardtype.caldac[0];
3102         if(type==caldac_none)return;
3103         n_bits=caldacs[type].n_bits;
3104         for(i=0;i<3;i++){
3105                 type = boardtype.caldac[i];
3106                 if(type==caldac_none)break;
3107                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3108                 n_chans+=caldacs[type].n_chans;
3109         }
3110         n_dacs=i;
3111         s->n_chan=n_chans;
3112
3113         if(diffbits){
3114
3115                 if(n_chans>MAX_N_CALDACS){
3116                         printk("BUG! MAX_N_CALDACS too small\n");
3117                 }
3118                 s->maxdata_list=devpriv->caldac_maxdata_list;
3119                 chan=0;
3120                 for(i=0;i<n_dacs;i++){
3121                         type = boardtype.caldac[i];
3122                         for(j=0;j<caldacs[type].n_chans;j++){
3123                                 s->maxdata_list[chan]=
3124                                         (1<<caldacs[type].n_bits)-1;
3125                                 chan++;
3126                         }
3127                 }
3128
3129                 for( chan = 0; chan < s->n_chan; chan++ )
3130                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3131         }else{
3132                 type = boardtype.caldac[0];
3133                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3134
3135                 for( chan = 0; chan < s->n_chan; chan++ )
3136                         ni_write_caldac( dev, i, s->maxdata / 2 );
3137         }
3138 }
3139
3140 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3141 {
3142         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3143         int i;
3144         int type;
3145
3146         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3147         if( devpriv->caldacs[ addr ] == val ) return;
3148         devpriv->caldacs[ addr ] = val;
3149
3150         for(i=0;i<3;i++){
3151                 type = boardtype.caldac[i];
3152                 if(type==caldac_none)break;
3153                 if(addr<caldacs[type].n_chans){
3154                         bits=caldacs[type].packbits(addr,val,&bitstring);
3155                         loadbit=SerDacLd(i);
3156                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3157                         break;
3158                 }
3159                 addr-=caldacs[type].n_chans;
3160         }
3161
3162         for(bit=1<<(bits-1);bit;bit>>=1){
3163                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3164                 comedi_udelay(1);
3165                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3166                 comedi_udelay(1);
3167         }
3168         ni_writeb(loadbit,Serial_Command);
3169         comedi_udelay(1);
3170         ni_writeb(0,Serial_Command);
3171 }
3172
3173
3174
3175 static int pack_mb88341(int addr,int val,int *bitstring)
3176 {
3177         /*
3178            Fujitsu MB 88341
3179            Note that address bits are reversed.  Thanks to
3180            Ingo Keen for noticing this.
3181
3182            Note also that the 88341 expects address values from
3183            1-12, whereas we use channel numbers 0-11.  The NI
3184            docs use 1-12, also, so be careful here.
3185         */
3186         addr++;
3187         *bitstring=((addr&0x1)<<11) |
3188                   ((addr&0x2)<<9)  |
3189                   ((addr&0x4)<<7)  |
3190                   ((addr&0x8)<<5)  |
3191                   (val&0xff);
3192         return 12;
3193 }
3194
3195 static int pack_dac8800(int addr,int val,int *bitstring)
3196 {
3197         *bitstring=((addr&0x7)<<8)|(val&0xff);
3198         return 11;
3199 }
3200
3201 static int pack_dac8043(int addr,int val,int *bitstring)
3202 {
3203         *bitstring=val&0xfff;
3204         return 12;
3205 }
3206
3207 static int pack_ad8522(int addr,int val,int *bitstring)
3208 {
3209         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3210         return 16;
3211 }
3212
3213 static int pack_ad8804(int addr,int val,int *bitstring)
3214 {
3215         *bitstring=((addr&0xf)<<8) | (val&0xff);
3216         return 12;
3217 }
3218
3219 static int pack_ad8842(int addr,int val,int *bitstring)
3220 {
3221         *bitstring=((addr+1)<<8) | (val&0xff);
3222         return 12;
3223 }
3224
3225
3226
3227
3228
3229 /*
3230  *
3231  *  General Purpose Counter/Timer section
3232  *
3233  */
3234
3235 /*
3236  * Low level stuff...Each STC counter has two 24 bit load registers
3237  * (A&B).  Just make it easier to access them.
3238  *
3239  * These are inlined _only_ because they are used once in subsequent
3240  * code.  Otherwise they should not be inlined.
3241  */
3242 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3243 {
3244         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_A_Register(chan));
3245 }
3246
3247 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3248 {
3249         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_B_Register(chan));
3250 }
3251
3252 /*  Load a value into the counter, using register A as the intermediate step.
3253 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3254 *  reset its value.
3255 */
3256 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3257 {
3258         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3259         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3260         GPCT_Load_A(dev,chan,value);
3261         devpriv->stc_writew(dev,  devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3262 }
3263
3264 /*
3265  *      Read the GPCTs current value.
3266  */
3267 static int GPCT_G_Watch(comedi_device *dev, int chan)
3268 {
3269         unsigned int hi1,hi2,lo;
3270
3271         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3272         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3273
3274         devpriv->gpct_command[chan] |= G_Save_Trace;
3275         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
3276
3277         /* This procedure is used because the two registers cannot
3278          * be read atomically. */
3279         do{
3280                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3281                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
3282                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3283         }while(hi1!=hi2);
3284
3285         return (hi1<<16)|lo;
3286 }
3287
3288
3289 static int GPCT_Disarm(comedi_device *dev, int chan)
3290 {
3291         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3292         return 0;
3293 }
3294
3295
3296 static int GPCT_Arm(comedi_device *dev, int chan)
3297 {
3298         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3299         /* If the counter is doing pulse width measurement, then make
3300          sure that the counter did not start counting right away.  This would
3301          indicate that we started acquiring the pulse after it had already
3302          started and our measurement would be inaccurate */
3303         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3304                 int g_status;
3305
3306                 g_status=devpriv->stc_readw(dev, G_Status_Register);
3307
3308                 if(chan == 0){
3309                         //TIM 5/2/01 possible error with very short pulses
3310                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3311                                 //error: we missed the beginning of the pulse
3312                                 return -EINVAL; //there is probably a more accurate error code...
3313                         }
3314                 }else{
3315                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3316                                 //error: we missed the beginning of the pulse
3317                                 return -EINVAL;
3318                         }
3319                 }
3320         }
3321         return 0;
3322 }
3323
3324 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3325 {
3326         //printk("GPCT_Set_Source...");
3327         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3328         switch(source) {
3329                 case GPCT_INT_CLOCK:
3330                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3331                 break;
3332         case GPCT_EXT_PIN:
3333                 if(chan==0)
3334                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3335                 else
3336                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3337                 break;
3338         default:
3339                 return -EINVAL;
3340         }
3341         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3342         //printk("exit GPCT_Set_Source\n");
3343         return 0;
3344 }
3345
3346 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3347 {
3348         //printk("GPCT_Set_Gate...");
3349         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3350         switch(gate) {
3351         case GPCT_NO_GATE:
3352                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3353                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3354                 break;
3355         case GPCT_EXT_PIN:
3356                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3357                 if(chan==0){
3358                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3359                 }else{
3360                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3361                 }
3362                 break;
3363         default:
3364                 return -EINVAL;
3365         }
3366         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3367         devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3368         //printk("exit GPCT_Set_Gate\n");
3369         return 0;
3370 }
3371
3372 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3373 {
3374         //printk("GPCT_Set_Direction...");
3375
3376         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3377         switch (direction) {
3378                 case GPCT_UP:
3379                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3380                         break;
3381                 case GPCT_DOWN:
3382                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3383                         break;
3384                 case GPCT_HWUD:
3385                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3386                         break;
3387                 default:
3388                         printk("Error direction=0x%08x..",direction);
3389                         return -EINVAL;
3390         }
3391         devpriv->stc_writew(dev, devpriv->gpct_command[chan], G_Command_Register(chan));
3392         //TIM 4/23/01 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3393         //printk("exit GPCT_Set_Direction\n");
3394         return 0;
3395 }
3396
3397 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3398 {
3399
3400         //NOTE: possible residual bits from multibit masks can corrupt
3401         //If you config for several measurements between Resets, watch out!
3402
3403         //printk("GPCT_Event_Counting...");
3404
3405         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3406
3407         // Gating_Mode = 1
3408         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3409         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3410
3411         // Trigger_Mode_For_Edge_Gate = 1
3412         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3413         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3414
3415         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3416         //printk("exit GPCT_Event_Counting\n");
3417 }
3418
3419 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3420 {
3421         //printk("GPCT_Period_Meas...");
3422
3423         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3424
3425
3426         //NOTE: possible residual bits from multibit masks can corrupt
3427         //If you config for several measurements between Resets, watch out!
3428         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3429         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3430
3431         // Output_Mode = 3
3432         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3433         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3434
3435
3436         //Gating Mode=2
3437         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3438         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
3439
3440         // Trigger_Mode_For_Edge_Gate=0
3441         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3442         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
3443
3444         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3445         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3446         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3447         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3448
3449         // Stop_Mode = 2
3450         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3451         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3452
3453         // Counting_Once = 2
3454         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3455         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3456
3457         // Up_Down = 1
3458         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3459         devpriv->gpct_command[chan] |= G_Up_Down(1);
3460
3461         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3462         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3463         //printk("exit GPCT_Period_Meas\n");
3464 }
3465
3466 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
3467 {
3468         //printk("GPCT_Pulse_Width_Meas...");
3469
3470         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
3471
3472         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3473         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3474
3475         // Output_Mode = 3
3476         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3477         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3478
3479         //Gating Mode=1
3480         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3481         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
3482
3483         // Trigger_Mode_For_Edge_Gate=2
3484         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3485         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
3486
3487
3488         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
3489         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
3490
3491         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3492         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3493
3494         // Stop_Mode = 0
3495         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3496         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3497
3498         // Counting_Once = 2
3499         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3500         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3501
3502         // Up_Down = 1
3503         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3504         devpriv->gpct_command[chan] |= G_Up_Down(1);
3505
3506         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3507         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3508
3509         //printk("exit GPCT_Pulse_Width_Meas\n");
3510 }
3511
3512 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
3513 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
3514 be modified to send a pulse in response to a trigger event at its gate.*/
3515 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
3516 {
3517         //printk("GPCT_Gen_Cont...");
3518
3519         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
3520
3521         // Set length of the pulse
3522         GPCT_Load_B(dev,chan, length-1);
3523
3524         //Load next time using B, This is reset by GPCT_Load_Using_A()
3525         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
3526
3527         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3528         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3529
3530         // Output_Mode = 3
3531         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3532         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
3533
3534         //Gating Mode=0 for untriggered single pulse
3535         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3536         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
3537
3538         // Trigger_Mode_For_Edge_Gate=0
3539         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3540         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3541
3542
3543         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3544         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3545         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
3546         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3547
3548         // Stop_Mode = 2
3549         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3550         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
3551
3552         // Counting_Once = 2
3553         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3554         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
3555
3556         // Up_Down = 1
3557         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3558         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
3559
3560         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3561         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3562
3563         //printk("exit GPCT_Gen_Cont\n");
3564 }
3565
3566 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
3567 {
3568         //printk("GPCT_Gen_Cont...");
3569
3570         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
3571
3572         // Set length of the pulse
3573         GPCT_Load_B(dev,chan, length-1);
3574
3575         //Load next time using B, This is reset by GPCT_Load_Using_A()
3576         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
3577
3578         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3579         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3580
3581         // Output_Mode = 3
3582         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3583         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
3584
3585         //Gating Mode=0 for untriggered single pulse
3586         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3587         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
3588
3589         // Trigger_Mode_For_Edge_Gate=0
3590         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3591         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3592
3593
3594         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3595         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3596         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
3597         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3598
3599         // Stop_Mode = 2
3600         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3601         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
3602
3603         // Counting_Once = 2
3604         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3605         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
3606
3607         // Up_Down = 1
3608         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3609         devpriv->gpct_command[chan] |= G_Up_Down(0);
3610
3611         //TIM 4/26/01
3612         //This seems pretty unsafe since I don't think it is cleared anywhere.
3613         //I don't think this is working
3614         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
3615         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
3616
3617
3618         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3619         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3620
3621         //printk("exit GPCT_Gen_Cont\n");
3622 }
3623
3624 static void GPCT_Reset(comedi_device *dev, int chan)
3625 {
3626         int temp_ack_reg=0;
3627
3628         //printk("GPCT_Reset...");
3629         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
3630
3631         switch (chan) {
3632                 case 0:
3633                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
3634                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
3635                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
3636                         temp_ack_reg |= G0_Gate_Error_Confirm;
3637                         temp_ack_reg |= G0_TC_Error_Confirm;
3638                         temp_ack_reg |= G0_TC_Interrupt_Ack;
3639                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
3640                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
3641
3642                         //problem...this interferes with the other ctr...
3643                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
3644                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
3645                         break;
3646                 case 1:
3647                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
3648                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
3649                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
3650                         temp_ack_reg |= G1_Gate_Error_Confirm;
3651                         temp_ack_reg |= G1_TC_Error_Confirm;
3652                         temp_ack_reg |= G1_TC_Interrupt_Ack;
3653                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
3654                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
3655
3656                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
3657                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
3658                         break;
3659         };
3660
3661         devpriv->gpct_mode[chan] = 0;
3662         devpriv->gpct_input_select[chan] = 0;
3663         devpriv->gpct_command[chan] = 0;
3664
3665         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
3666
3667         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3668         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
3669         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
3670
3671         //printk("exit GPCT_Reset\n");
3672 }
3673
3674 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
3675         comedi_insn *insn,lsampl_t *data)
3676 {
3677         int retval=0;
3678         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
3679         switch(data[0]){
3680         case GPCT_RESET:
3681                 if(insn->n!=1)return -EINVAL;
3682                 GPCT_Reset(dev,insn->chanspec);
3683                 break;
3684         case GPCT_SET_SOURCE:
3685                 if(insn->n!=2)return -EINVAL;
3686                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
3687                 break;
3688         case GPCT_SET_GATE:
3689                 if(insn->n!=2)return -EINVAL;
3690                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
3691                 break;
3692         case GPCT_SET_DIRECTION:
3693                 if(insn->n!=2) return -EINVAL;
3694                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
3695                 break;
3696         case GPCT_GET_INT_CLK_FRQ:
3697                 if(insn->n!=2) return -EINVAL;
3698                 //There are actually 2 internal clocks on the STC, we always
3699                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
3700                 //NOTE: This is not the final interface, ideally the user
3701                 //will never need to know the int. clk. freq.
3702                 data[1]=50;//50ns = 20MHz = internal timebase of STC
3703                 break;
3704         case GPCT_SET_OPERATION:
3705                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
3706                 switch(data[1]){
3707                         case GPCT_SIMPLE_EVENT:
3708                                 GPCT_Event_Counting(dev,insn->chanspec);
3709                                 break;
3710                         case GPCT_SINGLE_PERIOD:
3711                                 GPCT_Period_Meas(dev,insn->chanspec);
3712                                 break;
3713                         case GPCT_SINGLE_PW:
3714                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
3715                                 break;
3716                         case GPCT_SINGLE_PULSE_OUT:
3717                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
3718                                 break;
3719                         case GPCT_CONT_PULSE_OUT:
3720                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
3721                                 break;
3722                         default:
3723                                 printk("unsupported GPCT operation!\n");
3724                                 return -EINVAL;
3725                 }
3726                 break;
3727         case GPCT_ARM:
3728                 if(insn->n!=1)return -EINVAL;
3729                 retval=GPCT_Arm(dev,insn->chanspec);
3730                 break;
3731         case GPCT_DISARM:
3732                 if(insn->n!=1)return -EINVAL;
3733                 retval=GPCT_Disarm(dev,insn->chanspec);
3734                 break;
3735         default:
3736                 return -EINVAL;
3737         }
3738
3739         //catch any errors from return values
3740         if(retval==0){
3741                 return insn->n;
3742         }else{
3743                 if(data[0]!=GPCT_ARM){
3744                         printk("error: retval was %d\n",retval);
3745                         printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
3746                 }
3747
3748                 return retval;
3749         }
3750 }
3751
3752 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
3753         comedi_insn *insn,lsampl_t *data) {
3754
3755         int chan=insn->chanspec;
3756         int cur_op = devpriv->gpct_cur_operation[chan];
3757
3758         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
3759         if(insn->n!=1)return -EINVAL;
3760
3761         data[0] = GPCT_G_Watch(dev,insn->chanspec);
3762
3763         /* for certain modes (period and pulse width measurment), the value
3764         in the counter is not valid until the counter stops.  If the value is
3765         invalid, return a 0 */
3766         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
3767                 /* is the counter still running? */
3768                 if(devpriv->stc_readw(dev, G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
3769                         data[0]=0;
3770         }
3771         return 1;
3772 }
3773
3774 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
3775         comedi_insn *insn,lsampl_t *data) {
3776
3777         //printk("in ni_gpct_insn_write");
3778         if(insn->n!=1)return -EINVAL;
3779         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
3780         return 1;
3781 }
3782
3783
3784 /*
3785  *
3786  *  Programmable Function Inputs
3787  *
3788  */
3789
3790 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
3791         comedi_insn *insn,lsampl_t *data)
3792 {
3793         if(insn->n!=2)return -EINVAL;
3794
3795         data[1] = 0;
3796
3797         return 2;
3798 }
3799
3800 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
3801         comedi_insn *insn,lsampl_t *data)
3802 {
3803         unsigned int chan;
3804
3805         if(insn->n!=1)return -EINVAL;
3806
3807         chan = CR_CHAN(insn->chanspec);
3808         if(chan>10)return -EINVAL;
3809
3810         switch(data[0]){
3811         case COMEDI_OUTPUT:
3812                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
3813                 break;
3814         case COMEDI_INPUT:
3815                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
3816                 break;
3817         case INSN_CONFIG_DIO_QUERY:
3818                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
3819                 return insn->n;
3820                 break;
3821         default:
3822                 return -EINVAL;
3823         }
3824
3825         return 1;
3826 }
3827
3828 static int cs5529_wait_for_idle(comedi_device *dev)
3829 {
3830         unsigned short status;
3831         const int timeout = HZ;
3832         int i;
3833
3834         for(i = 0; i < timeout; i++)
3835         {
3836                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
3837                 if((status & CSS_ADC_BUSY) == 0)
3838                 {
3839                         break;
3840                 }
3841                 set_current_state(TASK_INTERRUPTIBLE);
3842                 if(schedule_timeout(1))
3843                 {
3844                         return -EIO;
3845                 }
3846         }
3847 //printk("looped %i times waiting for idle\n", i);
3848         if(i == timeout)
3849         {
3850                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
3851                 return -ETIME;
3852         }
3853         return 0;
3854 }
3855
3856 static void cs5529_command(comedi_device *dev, unsigned short value)
3857 {
3858         static const int timeout = 100;
3859         int i;
3860
3861         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
3862         /* give time for command to start being serially clocked into cs5529.
3863          * this insures that the CSS_ADC_BUSY bit will get properly
3864          * set before we exit this function.
3865         */
3866         for(i = 0; i < timeout; i++)
3867         {
3868                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
3869                         break;
3870                 comedi_udelay(1);
3871         }
3872 //printk("looped %i times writing command to cs5529\n", i);
3873         if(i == timeout)
3874         {
3875                 comedi_error(dev, "possible problem - never saw adc go busy?");
3876         }
3877 }
3878
3879 /* write to cs5529 register */
3880 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
3881 {
3882         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
3883         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
3884         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
3885         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
3886         if(cs5529_wait_for_idle(dev))
3887                 comedi_error(dev, "time or signal in cs5529_config_write()");
3888 }
3889
3890 /* read from cs5529 register */
3891 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
3892 {
3893         unsigned int value;
3894
3895         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
3896         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
3897         if(cs5529_wait_for_idle(dev))
3898                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
3899         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
3900         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
3901         return value;
3902 }
3903
3904 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
3905 {
3906         int retval;
3907         unsigned short status;
3908
3909         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
3910         retval = cs5529_wait_for_idle(dev);
3911         if(retval)
3912         {
3913                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
3914                 return -ETIME;
3915         }
3916         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
3917         if(status & CSS_OSC_DETECT)
3918         {
3919                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
3920                 return -EIO;
3921         }
3922         if(status & CSS_OVERRANGE)
3923         {
3924                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
3925         }
3926         if(data)
3927         {
3928                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
3929                 /* cs5529 returns 16 bit signed data in bipolar mode */
3930                 *data ^= (1 << 15);
3931         }
3932         return 0;
3933 }
3934
3935 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
3936 {
3937         int n, retval;
3938         unsigned short sample;
3939         unsigned int channel_select;
3940         const unsigned int INTERNAL_REF = 0x1000;
3941
3942         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
3943          * do nothing. bit 12 seems to chooses internal reference voltage, bit
3944          * 13 causes the adc input to go overrange (maybe reads external reference?) */
3945         if(insn->chanspec & CR_ALT_SOURCE)
3946                 channel_select = INTERNAL_REF;
3947         else
3948                 channel_select = CR_CHAN(insn->chanspec);
3949         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
3950
3951         for(n = 0; n < insn->n; n++)
3952         {
3953                 retval = cs5529_do_conversion(dev, &sample);
3954                 if(retval < 0) return retval;
3955                 data[n] = sample;
3956         }
3957         return insn->n;
3958 }
3959
3960 static int init_cs5529(comedi_device *dev)
3961 {
3962         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
3963
3964 #if 1
3965         /* do self-calibration */
3966         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
3967         /* need to force a conversion for calibration to run */
3968         cs5529_do_conversion(dev, NULL);
3969 #else
3970         /* force gain calibration to 1 */
3971         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
3972         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
3973         if(cs5529_wait_for_idle(dev))
3974                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
3975 #endif
3976         if(0)
3977         {
3978                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
3979                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
3980                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
3981         }
3982         return 0;
3983 }
3984
3985