comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode);
 264
 265
 266 /*GPCT function def's*/
 267 static int GPCT_G_Watch(comedi_device *dev, int chan);
 268
 269 static void GPCT_Reset(comedi_device *dev, int chan);
 270 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 271 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 272 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 273 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 274 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 275 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 276 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 277 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 278
 279 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 280         comedi_insn *insn,lsampl_t *data);
 281 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 282         comedi_insn *insn,lsampl_t *data);
 283 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 284         comedi_insn *insn,lsampl_t *data);
 285
 286 static int init_cs5529(comedi_device *dev);
 287 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 288 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 289 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 290 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 291
 292 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 293         comedi_insn *insn,lsampl_t *data);
 294 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 295         comedi_insn *insn, lsampl_t *data);
 296
 297 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 298
 299 enum aimodes
 300 {
 301         AIMODE_NONE = 0,
 302         AIMODE_HALF_FULL = 1,
 303         AIMODE_SCAN = 2,
 304         AIMODE_SAMPLE = 3,
 305 };
 306
 307 #define SERIAL_DISABLED         0
 308 #define SERIAL_600NS            600
 309 #define SERIAL_1_2US            1200
 310 #define SERIAL_10US                     10000
 311
 312 static const int num_adc_stages_611x = 3;
 313
 314 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 315         unsigned int m_status);
 316 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 317         unsigned int m_status);
 318 static void get_last_sample_611x( comedi_device *dev );
 319 static void get_last_sample_6143( comedi_device *dev );
 320 #ifdef PCIDMA
 321 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 322 static int ni_ai_drain_dma(comedi_device *dev );
 323 #endif
 324
 325 static void ni_flush_ai_fifo(comedi_device *dev){
 326         if(boardtype.reg_type == ni_reg_6143){
 327                 // Flush the 6143 data FIFO
 328                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 329                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 330                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 331         }
 332         else {
 333                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 334         }
 335 }
 336
 337 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 338 {
 339         devpriv->stc_writew(dev, data >> 16, reg);
 340         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 341 }
 342
 343 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 344 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 345 {
 346         unsigned long flags;
 347
 348         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 349         ni_writew(addr,AO_Window_Address_611x);
 350         ni_writew(data,AO_Window_Data_611x);
 351         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 352 }
 353
 354 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 355 {
 356         unsigned long flags;
 357
 358         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 359         ni_writew(addr,AO_Window_Address_611x);
 360         ni_writel(data,AO_Window_Data_611x);
 361         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 362 }
 363
 364 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 365 {
 366         unsigned long flags;
 367         unsigned short data;
 368
 369         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 370         ni_writew(addr, AO_Window_Address_611x);
 371         data = ni_readw(AO_Window_Data_611x);
 372         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 373         return data;
 374 }
 375
 376 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 377 * share registers (such as Interrupt_A_Register) without interfering with
 378 * each other.
 379 *
 380 * NOTE: the switch/case statements are optimized out for a constant argument
 381 * so this is actually quite fast---  If you must wrap another function around this
 382 * make it inline to avoid a large speed penalty.
 383 *
 384 * value should only be 1 or 0.
 385 */
 386 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 387 {
 388         unsigned long flags;
 389
 390         comedi_spin_lock_irqsave( &devpriv->window_lock, flags );
 391         switch (reg){
 392                 case Interrupt_A_Enable_Register:
 393                         if(value)
 394                                 devpriv->int_a_enable_reg |= bits;
 395                         else
 396                                 devpriv->int_a_enable_reg &= ~bits;
 397                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 398                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 399                         break;
 400                 case Interrupt_B_Enable_Register:
 401                         if(value)
 402                                 devpriv->int_b_enable_reg |= bits;
 403                         else
 404                                 devpriv->int_b_enable_reg &= ~bits;
 405                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 406                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 407                         break;
 408                 case IO_Bidirection_Pin_Register:
 409                         if(value)
 410                                 devpriv->io_bidirection_pin_reg |= bits;
 411                         else
 412                                 devpriv->io_bidirection_pin_reg &= ~bits;
 413                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 414                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 415                         break;
 416                 default:
 417                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 418                         rt_printk("reg is %d\n",reg);
 419                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 420                         break;
 421         }
 422 }
 423
 424
 425 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 426 {
 427         comedi_device *dev=d;
 428         unsigned short a_status;
 429         unsigned short b_status;
 430         unsigned int m0_status;
 431         unsigned int m1_status;
 432         unsigned long flags;
 433 #ifdef PCIDMA
 434         struct mite_struct *mite = devpriv->mite;
 435 #endif
 436
 437         if(dev->attached == 0) return IRQ_NONE;
 438         // lock to avoid race with comedi_poll
 439         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 440         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 441         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 442 #ifdef PCIDMA
 443         m0_status=readl(mite->mite_io_addr + MITE_CHSR(AI_DMA_CHAN));
 444         m1_status=readl(mite->mite_io_addr + MITE_CHSR(AO_DMA_CHAN));
 445 #else
 446         m0_status = 0;
 447         m1_status = 0;
 448 #endif
 449
 450         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 451                 handle_a_interrupt(dev, a_status, m0_status);
 452         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 453                 handle_b_interrupt(dev, b_status, m1_status);
 454         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 455         return IRQ_HANDLED;
 456 }
 457
 458 #ifdef PCIDMA
 459 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 460 {
 461         int count;
 462         comedi_subdevice *s = dev->subdevices + 0;
 463         comedi_async *async = s->async;
 464         unsigned int nbytes, old_alloc_count;
 465         unsigned int bytes_per_scan = bytes_per_sample(s) * async->cmd.chanlist_len;
 466
 467         old_alloc_count = async->buf_write_alloc_count;
 468         // write alloc as much as we can
 469         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 470
 471         nbytes = mite_bytes_written_to_memory_lb(mite, AI_DMA_CHAN);
 472         rmb();
 473         if( (int)(mite_bytes_written_to_memory_ub(mite, AI_DMA_CHAN) - old_alloc_count) > 0 ){
 474                 rt_printk("ni_mio_common: DMA overwrite of free area\n");
 475                 ni_ai_reset(dev,s);
 476                 async->events |= COMEDI_CB_OVERFLOW;
 477                 return;
 478         }
 479
 480         count = nbytes - async->buf_write_count;
 481         if( count <= 0 ){
 482                 /* it's possible count will be negative due to
 483                  * conservative value returned by mite_bytes_transferred */
 484                 return;
 485         }
 486         comedi_buf_write_free(async, count);
 487
 488         async->scan_progress += count;
 489         if( async->scan_progress >= bytes_per_scan )
 490         {
 491                 async->scan_progress %= bytes_per_scan;
 492                 async->events |= COMEDI_CB_EOS;
 493         }
 494         async->events |= COMEDI_CB_BLOCK;
 495 }
 496
 497 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 498 {
 499         int count;
 500         comedi_subdevice *s = dev->subdevices + 1;
 501         comedi_async *async = s->async;
 502         u32 nbytes_ub, nbytes_lb;
 503         unsigned int new_write_count;
 504         u32 stop_count = async->cmd.stop_arg * sizeof(sampl_t);
 505
 506         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 507
 508         new_write_count = async->buf_write_count;
 509         mb();
 510         nbytes_lb = mite_bytes_read_from_memory_lb(mite, AO_DMA_CHAN);
 511         if(async->cmd.stop_src == TRIG_COUNT &&
 512                 (int) (nbytes_lb - stop_count) > 0)
 513                 nbytes_lb = stop_count;
 514         mb();
 515         nbytes_ub = mite_bytes_read_from_memory_ub(mite, AO_DMA_CHAN);
 516         if(async->cmd.stop_src == TRIG_COUNT &&
 517                 (int) (nbytes_ub - stop_count) > 0)
 518                 nbytes_ub = stop_count;
 519         if((int)(nbytes_ub - devpriv->last_buf_write_count) > 0){
 520                 rt_printk("ni_mio_common: DMA underrun\n");
 521                 ni_ao_reset(dev,s);
 522                 async->events |= COMEDI_CB_OVERFLOW;
 523                 return;
 524         }
 525         mb();
 526         devpriv->last_buf_write_count = new_write_count;
 527
 528         count = nbytes_lb - async->buf_read_count;
 529         if(count < 0){
 530                 return;
 531         }
 532         comedi_buf_read_free(async, count);
 533
 534         async->events |= COMEDI_CB_BLOCK;
 535 }
 536
 537 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 538 {
 539         static const int timeout = 10000;
 540         int i;
 541
 542         for(i = 0; i < timeout; i++)
 543         {
 544                 unsigned short b_status;
 545
 546                 b_status = devpriv->stc_readw(dev,  AO_Status_1_Register );
 547                 if( b_status & AO_FIFO_Half_Full_St )
 548                         break;
 549                 /* if we poll too often, the pci bus activity seems
 550                  to slow the dma transfer down */
 551                 comedi_udelay(10);
 552         }
 553         if( i == timeout )
 554         {
 555                 comedi_error(dev, "timed out waiting for dma load");
 556                 return -EPIPE;
 557         }
 558         return 0;
 559 }
 560
 561 #endif //PCIDMA
 562 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 563 {
 564         if(devpriv->aimode == AIMODE_SCAN)
 565         {
 566 #ifdef PCIDMA
 567                 static const int timeout = 10;
 568                 int i;
 569
 570                 for(i = 0; i < timeout; i++)
 571                 {
 572                         ni_sync_ai_dma(devpriv->mite, dev);
 573                         if((s->async->events & COMEDI_CB_EOS)) break;
 574                         comedi_udelay(1);
 575                 }
 576 #else
 577                 ni_handle_fifo_dregs(dev);
 578                 s->async->events |= COMEDI_CB_EOS;
 579 #endif
 580         }
 581         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 582         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 583                 shutdown_ai_command( dev );
 584                 ni_ai_reset(dev, s);
 585         }
 586 }
 587
 588 static void shutdown_ai_command( comedi_device *dev )
 589 {
 590         comedi_subdevice *s = dev->subdevices + 0;
 591
 592 #ifdef PCIDMA
 593         ni_ai_drain_dma( dev );
 594         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 595 #endif
 596         ni_handle_fifo_dregs(dev);
 597         get_last_sample_611x(dev);
 598         get_last_sample_6143(dev);
 599
 600         ni_set_bits(dev, Interrupt_A_Enable_Register,
 601                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 602                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 603                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 604                 AI_FIFO_Interrupt_Enable,0);
 605
 606         s->async->events |= COMEDI_CB_EOA;
 607 }
 608
 609 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 610         unsigned int m_status)
 611 {
 612         comedi_subdevice *s=dev->subdevices+0;
 613         unsigned short ack=0;
 614
 615         s->async->events = 0;
 616
 617 #ifdef DEBUG_INTERRUPT
 618         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 619                 status, m_status);
 620         ni_mio_print_status_a(status);
 621 #endif
 622
 623
 624 #ifdef PCIDMA
 625         /* Currently, mite.c requires us to handle LINKC and DONE */
 626         if(m_status & CHSR_LINKC){
 627                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 628                 ni_sync_ai_dma(devpriv->mite, dev);
 629         }
 630
 631         if(m_status & CHSR_DONE){
 632                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 633         }
 634
 635         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 636                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 637                 //mite_print_chsr(m_status);
 638                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 639                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 640                 //disable_irq(dev->irq);
 641         }
 642 #endif
 643
 644         /* test for all uncommon interrupt events at the same time */
 645         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 646                 if(status==0xffff){
 647                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 648                         /* we probably aren't even running a command now,
 649                          * so it's a good idea to be careful. */
 650                         if(s->subdev_flags&SDF_RUNNING){
 651                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 652                                 //comedi_event(dev,s,s->async->events);
 653                         }
 654                         return;
 655                 }
 656                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 657                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 658                                 status);
 659                         ni_mio_print_status_a(status);
 660
 661                         ni_ai_reset(dev,dev->subdevices);
 662
 663
 664                         shutdown_ai_command( dev );
 665
 666                         s->async->events |= COMEDI_CB_ERROR;
 667                         if(status & (AI_Overrun_St | AI_Overflow_St))
 668                                 s->async->events |= COMEDI_CB_OVERFLOW;
 669
 670                         comedi_event(dev,s,s->async->events);
 671
 672                         return;
 673                 }
 674                 if(status&AI_SC_TC_St){
 675 #ifdef DEBUG_INTERRUPT
 676                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 677 #endif
 678                         if(!devpriv->ai_continuous){
 679                                 shutdown_ai_command( dev );
 680                         }
 681                         ack|=AI_SC_TC_Interrupt_Ack;
 682                 }
 683                 if(status&AI_START1_St){
 684                         ack|=AI_START1_Interrupt_Ack;
 685                 }
 686         }
 687 #ifndef PCIDMA
 688         if(status&AI_FIFO_Half_Full_St){
 689                 int i;
 690                 static const int timeout = 10;
 691                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 692                  *fail to get the fifo less than half full, so loop to be sure.*/
 693                 for(i = 0; i < timeout; ++i)
 694                 {
 695                         ni_handle_fifo_half_full(dev);
 696                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 697                                 break;
 698                 }
 699         }
 700 #endif // !PCIDMA
 701
 702         if( (status & AI_STOP_St) ){
 703                 ni_handle_eos(dev, s);
 704                 /* we need to ack the START, also */
 705                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 706         }
 707 #if 0
 708         if(devpriv->aimode==AIMODE_SAMPLE){
 709                 ni_handle_fifo_dregs(dev);
 710
 711                 //s->async->events |= COMEDI_CB_SAMPLE;
 712         }
 713 #endif
 714         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 715
 716         comedi_event(dev,s,s->async->events);
 717
 718 #ifdef DEBUG_INTERRUPT
 719         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 720         if(status&Interrupt_A_St){
 721                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 722         }
 723 #endif
 724 }
 725
 726 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 727 {
 728         comedi_subdevice *s=dev->subdevices+1;
 729         //unsigned short ack=0;
 730 #ifdef DEBUG_INTERRUPT
 731         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 732                 b_status,m_status);
 733         ni_mio_print_status_b(b_status);
 734 #endif
 735
 736
 737 #ifdef PCIDMA
 738         /* Currently, mite.c requires us to handle LINKC and DONE */
 739         if(m_status & CHSR_LINKC){
 740                 mite_handle_b_linkc(devpriv->mite, dev);
 741         }
 742
 743         if(m_status & CHSR_DONE){
 744                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 745         }
 746
 747         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 748                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 749                 //mite_print_chsr(m_status);
 750                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 751                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 752        }
 753 #endif
 754
 755         if(b_status==0xffff)return;
 756         if(b_status&AO_Overrun_St){
 757                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 758                 ni_ao_reset(dev,s);
 759                 s->async->events |= COMEDI_CB_OVERFLOW;
 760         }
 761
 762         if(b_status&AO_BC_TC_St){
 763                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 764                 ni_ao_reset(dev,s);
 765                 s->async->events |= COMEDI_CB_EOA;
 766         }
 767
 768 #ifndef PCIDMA
 769         if(b_status&AO_FIFO_Request_St){
 770                 int ret;
 771
 772                 ret = ni_ao_fifo_half_empty(dev,s);
 773                 if(!ret){
 774                         rt_printk("ni_mio_common: AO buffer underrun\n");
 775                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 776                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 777                         s->async->events |= COMEDI_CB_OVERFLOW;
 778                 }
 779         }
 780 #endif
 781
 782         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 783         if(b_status&Interrupt_B_St){
 784                 if(b_status&AO_FIFO_Request_St){
 785                         rt_printk("ni_mio_common: AO buffer underrun\n");
 786                 }
 787                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 788                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 789                 ni_ao_reset(dev,s);
 790                 s->async->events |= COMEDI_CB_OVERFLOW;
 791         }
 792
 793         comedi_event(dev,s,s->async->events);
 794 }
 795
 796 #ifdef DEBUG_STATUS_A
 797 static char *status_a_strings[]={
 798         "passthru0","fifo","G0_gate","G0_TC",
 799         "stop","start","sc_tc","start1",
 800         "start2","sc_tc_error","overflow","overrun",
 801         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 802 };
 803
 804 static void ni_mio_print_status_a(int status)
 805 {
 806         int i;
 807
 808         rt_printk("A status:");
 809         for(i=15;i>=0;i--){
 810                 if(status&(1<<i)){
 811                         rt_printk(" %s",status_a_strings[i]);
 812                 }
 813         }
 814         rt_printk("\n");
 815 }
 816 #endif
 817
 818 #ifdef DEBUG_STATUS_B
 819 static char *status_b_strings[]={
 820         "passthru1","fifo","G1_gate","G1_TC",
 821         "UI2_TC","UPDATE","UC_TC","BC_TC",
 822         "start1","overrun","start","bc_tc_error",
 823         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 824 };
 825
 826 static void ni_mio_print_status_b(int status)
 827 {
 828         int i;
 829
 830         rt_printk("B status:");
 831         for(i=15;i>=0;i--){
 832                 if(status&(1<<i)){
 833                         rt_printk(" %s",status_b_strings[i]);
 834                 }
 835         }
 836         rt_printk("\n");
 837 }
 838 #endif
 839
 840 #ifndef PCIDMA
 841
 842 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 843 {
 844         comedi_async *async = s->async;
 845         comedi_cmd *cmd = &async->cmd;
 846         int chan;
 847         int i;
 848         sampl_t d;
 849         u32 packed_data;
 850         int range;
 851         int err = 1;
 852
 853         chan = async->cur_chan;
 854         for(i=0;i<n;i++){
 855                 err &= comedi_buf_get(async, &d);
 856                 if(err == 0) break;
 857
 858                 range = CR_RANGE(cmd->chanlist[chan]);
 859
 860                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 861                 {
 862                         packed_data = d & 0xffff;
 863                         /* 6711 only has 16 bit wide ao fifo */
 864                         if(boardtype.reg_type != ni_reg_6711)
 865                         {
 866                                 err &= comedi_buf_get(async, &d);
 867                                 if(err == 0) break;
 868                                 chan++;
 869                                 i++;
 870                                 packed_data |= ( d << 16 ) & 0xffff0000;
 871                         }
 872                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 873                 }else{
 874                         ni_writew(d, DAC_FIFO_Data);
 875                 }
 876                 chan++;
 877                 chan %= cmd->chanlist_len;
 878         }
 879         async->cur_chan = chan;
 880         if(err==0){
 881                 async->events |= COMEDI_CB_OVERFLOW;
 882         }
 883 }
 884
 885 /*
 886  *  There's a small problem if the FIFO gets really low and we
 887  *  don't have the data to fill it.  Basically, if after we fill
 888  *  the FIFO with all the data available, the FIFO is _still_
 889  *  less than half full, we never clear the interrupt.  If the
 890  *  IRQ is in edge mode, we never get another interrupt, because
 891  *  this one wasn't cleared.  If in level mode, we get flooded
 892  *  with interrupts that we can't fulfill, because nothing ever
 893  *  gets put into the buffer.
 894  *
 895  *  This kind of situation is recoverable, but it is easier to
 896  *  just pretend we had a FIFO underrun, since there is a good
 897  *  chance it will happen anyway.  This is _not_ the case for
 898  *  RT code, as RT code might purposely be running close to the
 899  *  metal.  Needs to be fixed eventually.
 900  */
 901 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 902 {
 903         int n;
 904
 905         n = comedi_buf_read_n_available(s);
 906         if(n==0){
 907                 s->async->events |= COMEDI_CB_OVERFLOW;
 908                 return 0;
 909         }
 910
 911         n /= sizeof(sampl_t);
 912         if(n > boardtype.ao_fifo_depth / 2)
 913                 n = boardtype.ao_fifo_depth / 2;
 914
 915         ni_ao_fifo_load(dev,s,n);
 916
 917         s->async->events |= COMEDI_CB_BLOCK;
 918
 919         return 1;
 920 }
 921
 922 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 923 {
 924         int n;
 925
 926         /* reset fifo */
 927         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
 928         if(boardtype.reg_type & ni_reg_6xxx_mask)
 929                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 930
 931         /* load some data */
 932         n = comedi_buf_read_n_available(s);
 933         if(n==0)return 0;
 934
 935         n /= sizeof(sampl_t);
 936         if(n > boardtype.ao_fifo_depth)
 937                 n = boardtype.ao_fifo_depth;
 938
 939         ni_ao_fifo_load(dev,s,n);
 940
 941         return n;
 942 }
 943
 944 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 945         int n)
 946 {
 947         comedi_async *async = s->async;
 948         int i;
 949
 950         if(boardtype.reg_type == ni_reg_611x){
 951                 sampl_t data[2];
 952                 u32 dl;
 953
 954                 for( i = 0; i < n / 2; i++ ){
 955                         dl=ni_readl(ADC_FIFO_Data_611x);
 956                         /* This may get the hi/lo data in the wrong order */
 957                         data[0] = (dl>>16) & 0xffff;
 958                         data[1] = dl & 0xffff;
 959                         cfc_write_array_to_buffer(s, data, sizeof(data));
 960                 }
 961                 /* Check if there's a single sample stuck in the FIFO */
 962                 if( n % 2){
 963                         dl=ni_readl(ADC_FIFO_Data_611x);
 964                         data[0] = dl & 0xffff;
 965                         cfc_write_to_buffer(s, data[0]);
 966                 }
 967         } else if(boardtype.reg_type == ni_reg_6143){
 968                 sampl_t data[2];
 969                 u32     dl;
 970
 971                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
 972                 for(i = 0; i < n / 2; i++){
 973                         dl = ni_readl(AIFIFO_Data_6143);
 974
 975                         data[0] = (dl >> 16) & 0xffff;
 976                         data[1] = dl & 0xffff;
 977                         cfc_write_array_to_buffer(s, data, sizeof(data));
 978                 }
 979                 if(n % 2){
 980                         /* Assume there is a single sample stuck in the FIFO */
 981                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
 982                         dl = ni_readl(AIFIFO_Data_6143);
 983                         data[0] = (dl >> 16) & 0xffff;
 984                         cfc_write_to_buffer(s, data[0]);
 985                 }
 986         } else{
 987                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
 988                 {
 989                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
 990                         async->events |= COMEDI_CB_ERROR;
 991                         return;
 992                 }
 993                 for(i = 0; i < n; i++){
 994                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
 995                 }
 996                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
 997                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
 998         }
 999 }
1000
1001 static void ni_handle_fifo_half_full(comedi_device *dev)
1002 {
1003         int n;
1004         comedi_subdevice *s=dev->subdevices+0;
1005
1006         n=boardtype.ai_fifo_depth/2;
1007
1008         ni_ai_fifo_read(dev,s,n);
1009 }
1010 #endif
1011
1012 #ifdef PCIDMA
1013 static int ni_ai_drain_dma(comedi_device *dev )
1014 {
1015         struct mite_struct *mite = devpriv->mite;
1016         int i;
1017         static const int timeout = 10000;
1018
1019         for( i = 0; i < timeout; i++ )
1020         {
1021                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1022                         mite_bytes_in_transit(mite, AI_DMA_CHAN) == 0)
1023                         break;
1024                 comedi_udelay(2);
1025         }
1026         if(i == timeout)
1027         {
1028                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1029                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1030                         mite_bytes_in_transit(mite, AI_DMA_CHAN), devpriv->stc_readw(dev, AI_Status_1_Register));
1031                 return -1;
1032         }
1033
1034         ni_sync_ai_dma( mite, dev );
1035
1036         return 0;
1037 }
1038 #endif
1039 /*
1040    Empties the AI fifo
1041 */
1042 static void ni_handle_fifo_dregs(comedi_device *dev)
1043 {
1044         comedi_subdevice *s=dev->subdevices+0;
1045         sampl_t data[2];
1046         u32 dl;
1047         short fifo_empty;
1048         int i;
1049
1050         if(boardtype.reg_type == ni_reg_611x){
1051                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1052                         dl=ni_readl(ADC_FIFO_Data_611x);
1053
1054                         /* This may get the hi/lo data in the wrong order */
1055                         data[0] = (dl>>16);
1056                         data[1] = (dl&0xffff);
1057                         cfc_write_array_to_buffer(s, data, sizeof(data));
1058                 }
1059         }else if(boardtype.reg_type == ni_reg_6143){
1060                 i = 0;
1061                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1062                         dl = ni_readl(AIFIFO_Data_6143);
1063
1064                         /* This may get the hi/lo data in the wrong order */
1065                         data[0] = (dl >> 16);
1066                         data[1] = (dl & 0xffff);
1067                         cfc_write_array_to_buffer(s, data, sizeof(data));
1068                         i += 2;
1069                 }
1070                 // Check if stranded sample is present
1071                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1072                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1073                         dl = ni_readl(AIFIFO_Data_6143);
1074                         data[0] = (dl >> 16) & 0xffff;
1075                         cfc_write_to_buffer(s, data[0]);
1076                 }
1077
1078         }else{
1079                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1080                 while(fifo_empty == 0)
1081                 {
1082                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1083                         {
1084                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1085                                 if(fifo_empty) break;
1086                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1087                         }
1088                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1089                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1090                 }
1091         }
1092 }
1093
1094 static void get_last_sample_611x( comedi_device *dev )
1095 {
1096         comedi_subdevice *s=dev->subdevices+0;
1097         sampl_t data;
1098         u32 dl;
1099
1100         if(boardtype.reg_type != ni_reg_611x) return;
1101
1102         /* Check if there's a single sample stuck in the FIFO */
1103         if(ni_readb(XXX_Status)&0x80){
1104                 dl=ni_readl(ADC_FIFO_Data_611x);
1105                 data = (dl&0xffff);
1106                 cfc_write_to_buffer(s, data);
1107         }
1108 }
1109
1110 static void get_last_sample_6143(comedi_device* dev)
1111 {
1112         comedi_subdevice*       s = dev->subdevices + 0;
1113         sampl_t                 data;
1114         u32                     dl;
1115
1116         if(boardtype.reg_type != ni_reg_6143) return;
1117
1118         /* Check if there's a single sample stuck in the FIFO */
1119         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1120                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1121                 dl = ni_readl(AIFIFO_Data_6143);
1122
1123                 /* This may get the hi/lo data in the wrong order */
1124                 data = (dl >> 16) & 0xffff;
1125                 cfc_write_to_buffer(s, data);
1126         }
1127 }
1128
1129 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1130         void *data, unsigned int num_bytes, unsigned int chan_index )
1131 {
1132         comedi_async *async = s->async;
1133         unsigned int i;
1134         unsigned int length = num_bytes / bytes_per_sample(s);
1135         sampl_t *array = data;
1136         lsampl_t *larray = data;
1137         for(i = 0; i < length; i++)
1138         {
1139 #ifdef PCIDMA
1140                 if(s->subdev_flags & SDF_LSAMPL)
1141                         larray[i] = le32_to_cpu(larray[i]);
1142                 else
1143                         array[i] = le16_to_cpu(array[i]);
1144 #endif
1145                 if(s->subdev_flags & SDF_LSAMPL)
1146                         larray[i] += devpriv->ai_offset[chan_index];
1147                 else
1148                         array[i] += devpriv->ai_offset[chan_index];
1149                 chan_index++;
1150                 chan_index %= async->cmd.chanlist_len;
1151         }
1152 }
1153
1154 #ifdef PCIDMA
1155
1156 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1157 {
1158         struct mite_struct *mite = devpriv->mite;
1159         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1160         comedi_subdevice *s = dev->subdevices + 0;
1161
1162         /* write alloc the entire buffer */
1163         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1164
1165         mite_chan->current_link = 0;
1166         mite_chan->dir = COMEDI_INPUT;
1167         switch(boardtype.reg_type)
1168         {
1169         case ni_reg_611x:
1170         case ni_reg_6143:
1171                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1172                 break;
1173         case ni_reg_m_series:
1174                 if(boardtype.adbits > 16)
1175                         mite_prep_dma(mite, AI_DMA_CHAN, 32, 32);
1176                 else
1177                         mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);       //guess
1178                 break;
1179         default:
1180                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1181                 break;
1182         };
1183         /*start the MITE*/
1184         mite_dma_arm(mite, AI_DMA_CHAN);
1185 }
1186
1187 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1188 {
1189         struct mite_struct *mite = devpriv->mite;
1190         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1191         comedi_subdevice *s = dev->subdevices + 1;
1192
1193         devpriv->last_buf_write_count = s->async->buf_write_count;
1194
1195         mite_chan->current_link = 0;
1196         mite_chan->dir = COMEDI_OUTPUT;
1197         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1198                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1199         else
1200                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1201
1202         /*start the MITE*/
1203         mite_dma_arm(mite, AO_DMA_CHAN);
1204 }
1205
1206 #endif // PCIDMA
1207
1208 /*
1209    used for both cancel ioctl and board initialization
1210
1211    this is pretty harsh for a cancel, but it works...
1212  */
1213
1214 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1215 {
1216 #ifdef PCIDMA
1217         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1218 #endif
1219         /* ai configuration */
1220         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1221
1222         ni_set_bits(dev, Interrupt_A_Enable_Register,
1223                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1224                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1225                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1226                 AI_FIFO_Interrupt_Enable,0);
1227
1228         ni_flush_ai_fifo(dev);
1229
1230         if(boardtype.reg_type != ni_reg_6143)
1231                 ni_writeb(0, Misc_Command);
1232
1233         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1234         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1235                 AI_Mode_1_Register);
1236         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1237         /* generate FIFO interrupts on non-empty */
1238         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1239         if(boardtype.reg_type == ni_reg_611x){
1240                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1241                         AI_SOC_Polarity |
1242                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1243                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1244                         AI_EXTMUX_CLK_Output_Select(0) |
1245                         AI_LOCALMUX_CLK_Output_Select(2) |
1246                         AI_SC_TC_Output_Select(3) |
1247                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1248         }else if(boardtype.reg_type == ni_reg_6143){
1249                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1250                         AI_SOC_Polarity |
1251                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1252                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1253                         AI_EXTMUX_CLK_Output_Select(0) |
1254                         AI_LOCALMUX_CLK_Output_Select(2) |
1255                         AI_SC_TC_Output_Select(3) |
1256                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1257         }else{
1258                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1259                         AI_SOC_Polarity |
1260                         AI_CONVERT_Pulse_Width |
1261                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1262                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1263                         AI_EXTMUX_CLK_Output_Select(0) |
1264                         AI_LOCALMUX_CLK_Output_Select(2) |
1265                         AI_SC_TC_Output_Select(3) |
1266                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1267         }
1268         /* the following registers should not be changed, because there
1269          * are no backup registers in devpriv.  If you want to change
1270          * any of these, add a backup register and other appropriate code:
1271          *      AI_Mode_1_Register
1272          *      AI_Mode_3_Register
1273          *      AI_Personal_Register
1274          *      AI_Output_Control_Register
1275         */
1276         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1277                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1278                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1279                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1280
1281         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1282
1283         return 0;
1284 }
1285
1286 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1287 {
1288         unsigned long flags = 0;
1289         int count;
1290
1291         // lock to avoid race with interrupt handler
1292         if(in_interrupt() == 0)
1293                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1294 #ifndef PCIDMA
1295         ni_handle_fifo_dregs(dev);
1296 #else
1297         ni_sync_ai_dma(devpriv->mite, dev);
1298 #endif
1299         count = s->async->buf_write_count - s->async->buf_read_count;
1300         if(in_interrupt() == 0)
1301                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1302
1303         return count;
1304 }
1305
1306
1307 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1308 {
1309         int i,n;
1310         const unsigned int mask = (1 << boardtype.adbits) - 1;
1311         unsigned signbits;
1312         unsigned short d;
1313         unsigned long dl;
1314
1315         ni_load_channelgain_list(dev,1,&insn->chanspec);
1316
1317         ni_flush_ai_fifo(dev);
1318
1319         signbits=devpriv->ai_offset[0];
1320         if(boardtype.reg_type == ni_reg_611x){
1321                 for(n=0; n < num_adc_stages_611x; n++){
1322                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1323                         comedi_udelay(1);
1324                 }
1325                 for(n=0; n<insn->n; n++){
1326                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1327                         /* The 611x has screwy 32-bit FIFOs. */
1328                         d = 0;
1329                         for(i=0; i<NI_TIMEOUT; i++){
1330                                 if(ni_readb(XXX_Status)&0x80)
1331                                 {
1332                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1333                                         break;
1334                                 }
1335                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1336                                 {
1337                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1338                                         break;
1339                                 }
1340                         }
1341                         if(i==NI_TIMEOUT){
1342                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1343                                 return -ETIME;
1344                         }
1345                         d += signbits;
1346                         data[ n ] = d;
1347                 }
1348         }else if(boardtype.reg_type == ni_reg_6143){
1349                 for(n = 0; n < insn->n; n++){
1350                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1351
1352                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1353                         dl = 0;
1354                         for(i = 0; i < NI_TIMEOUT; i++){
1355                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1356                                 {
1357                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1358                                         dl = ni_readl(AIFIFO_Data_6143);
1359                                         break;
1360                                 }
1361                         }
1362                         if(i == NI_TIMEOUT){
1363                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1364                                 return -ETIME;
1365                         }
1366                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1367                 }
1368         }else{
1369                 for(n=0;n<insn->n;n++){
1370                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1371                         for(i=0;i<NI_TIMEOUT;i++){
1372                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1373                                         break;
1374                         }
1375                         if(i==NI_TIMEOUT){
1376                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1377                                 return -ETIME;
1378                         }
1379                         if(boardtype.reg_type == ni_reg_m_series)
1380                         {
1381                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1382                         }else
1383                         {
1384                                 d = ni_readw(ADC_FIFO_Data_Register);
1385                                 d += signbits; /* subtle: needs to be short addition */
1386                                 data[n] = d;
1387                         }
1388                 }
1389         }
1390         return insn->n;
1391 }
1392
1393 void ni_prime_channelgain_list(comedi_device *dev)
1394 {
1395         int i;
1396         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1397         for(i = 0; i < NI_TIMEOUT; ++i)
1398         {
1399                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1400                 {
1401                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1402                         return;
1403                 }
1404                 comedi_udelay(1);
1405         }
1406         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1407 }
1408
1409 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1410         unsigned int *list)
1411 {
1412         unsigned int chan, range, aref;
1413         unsigned int i;
1414         unsigned config_bits = 0;
1415         unsigned offset;
1416         unsigned int dither;
1417         unsigned range_code;
1418
1419         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1420
1421 //      offset = 1 << (boardtype.adbits - 1);
1422         if((list[0] & CR_ALT_SOURCE))
1423         {
1424                 chan = CR_CHAN(list[0]);
1425                 range = CR_RANGE(list[0]);
1426                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1427                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1428                 unsigned bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1429                 bypass_bits |= chan;
1430                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1431                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1432                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1433                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1434                 if(dither)
1435                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1436                 // don't use 2's complement encoding
1437                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1438                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1439         }else
1440         {
1441                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1442         }
1443         offset = 0;
1444         for(i = 0; i < n_chan; i++)
1445         {
1446                 chan = CR_CHAN(list[i]);
1447                 aref = CR_AREF(list[i]);
1448                 range = CR_RANGE(list[i]);
1449                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1450
1451                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1452                 devpriv->ai_offset[i] = offset;
1453
1454                 switch( aref )
1455                 {
1456                         case AREF_DIFF:
1457                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1458                                 break;
1459                         case AREF_COMMON:
1460                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1461                                 break;
1462                         case AREF_GROUND:
1463                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1464                                 break;
1465                         case AREF_OTHER:
1466                                 break;
1467                 }
1468                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1469                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1470                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1471                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1472                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1473                 // don't use 2's complement encoding
1474                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1475                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1476         }
1477         ni_prime_channelgain_list(dev);
1478 }
1479
1480 /*
1481  * Notes on the 6110 and 6111:
1482  * These boards a slightly different than the rest of the series, since
1483  * they have multiple A/D converters.
1484  * From the driver side, the configuration memory is a
1485  * little different.
1486  * Configuration Memory Low:
1487  *   bits 15-9: same
1488  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1489  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1490  *       1001 gain=0.1 (+/- 50)
1491  *       1010 0.2
1492  *       1011 0.1
1493  *       0001 1
1494  *       0010 2
1495  *       0011 5
1496  *       0100 10
1497  *       0101 20
1498  *       0110 50
1499  * Configuration Memory High:
1500  *   bits 12-14: Channel Type
1501  *       001 for differential
1502  *       000 for calibration
1503  *   bit 11: coupling  (this is not currently handled)
1504  *       1 AC coupling
1505  *       0 DC coupling
1506  *   bits 0-2: channel
1507  *       valid channels are 0-3
1508  */
1509 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1510         unsigned int *list)
1511 {
1512         unsigned int chan,range,aref;
1513         unsigned int i;
1514         unsigned int hi,lo;
1515         unsigned offset;
1516         unsigned int dither;
1517
1518         if(boardtype.reg_type == ni_reg_m_series)
1519         {
1520                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1521                 return;
1522         }
1523         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1524                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1525                         // ready to go.
1526                         return;
1527                 }
1528                 devpriv->changain_state=1;
1529                 devpriv->changain_spec=list[0];
1530         }else{
1531                 devpriv->changain_state=0;
1532         }
1533
1534         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1535
1536         // Set up Calibration mode if required
1537         if(boardtype.reg_type == ni_reg_6143){
1538                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1539                         // Strobe Relay enable bit
1540                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1541                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1542                         devpriv->ai_calib_source_enabled = 1;
1543                         msleep_interruptible(100);      // Allow relays to change
1544                 }
1545                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1546                         // Strobe Relay disable bit
1547                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1548                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1549                         devpriv->ai_calib_source_enabled = 0;
1550                         msleep_interruptible(100);      // Allow relays to change
1551                 }
1552         }
1553
1554         offset=1<<(boardtype.adbits-1);
1555         for(i=0;i<n_chan;i++){
1556                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1557                         chan=devpriv->ai_calib_source;
1558                 }else{
1559                         chan=CR_CHAN(list[i]);
1560                 }
1561                 aref=CR_AREF(list[i]);
1562                 range=CR_RANGE(list[i]);
1563                 dither=((list[i]&CR_ALT_FILTER)!=0);
1564
1565                 /* fix the external/internal range differences */
1566                 range = ni_gainlkup[boardtype.gainlkup][range];
1567                 if(boardtype.reg_type == ni_reg_611x)
1568                         devpriv->ai_offset[i] = offset;
1569                 else
1570                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1571
1572                 hi = 0;
1573                 if( ( list[i] & CR_ALT_SOURCE ) )
1574                 {
1575                         if(boardtype.reg_type == ni_reg_611x)
1576                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1577                 }else
1578                 {
1579                         if(boardtype.reg_type == ni_reg_611x)
1580                                 aref = AREF_DIFF;
1581                         else if(boardtype.reg_type == ni_reg_6143)
1582                                 aref = AREF_OTHER;
1583                         switch( aref )
1584                         {
1585                                 case AREF_DIFF:
1586                                         hi |= AI_DIFFERENTIAL;
1587                                         break;
1588                                 case AREF_COMMON:
1589                                         hi |= AI_COMMON;
1590                                         break;
1591                                 case AREF_GROUND:
1592                                         hi |= AI_GROUND;
1593                                         break;
1594                                 case AREF_OTHER:
1595                                         break;
1596                         }
1597                 }
1598                 hi |= AI_CONFIG_CHANNEL( chan );
1599
1600                 ni_writew(hi,Configuration_Memory_High);
1601
1602                 if(boardtype.reg_type != ni_reg_6143){
1603                         lo = range;
1604                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1605                         if( dither ) lo |= AI_DITHER;
1606
1607                         ni_writew(lo,Configuration_Memory_Low);
1608                 }
1609         }
1610
1611         /* prime the channel/gain list */
1612         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1613                 ni_prime_channelgain_list(dev);
1614         }
1615 }
1616
1617 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode)
1618 {
1619         int divider;
1620         switch(round_mode)
1621         {
1622         case TRIG_ROUND_NEAREST:
1623         default:
1624                 divider = (*nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1625                 break;
1626         case TRIG_ROUND_DOWN:
1627                 divider = (*nanosec) / devpriv->clock_ns;
1628                 break;
1629         case TRIG_ROUND_UP:
1630                 divider=(*nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1631                 break;
1632         }
1633
1634         *nanosec = devpriv->clock_ns * divider;
1635         return divider - 1;
1636 }
1637
1638 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1639 {
1640         int err=0;
1641         int tmp;
1642         int sources;
1643
1644         /* step 1: make sure trigger sources are trivially valid */
1645
1646         tmp=cmd->start_src;
1647         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1648         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1649
1650         tmp=cmd->scan_begin_src;
1651         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1652         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1653
1654         tmp=cmd->convert_src;
1655         sources = TRIG_TIMER | TRIG_EXT;
1656         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1657         cmd->convert_src &= sources;
1658         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1659
1660         tmp=cmd->scan_end_src;
1661         cmd->scan_end_src &= TRIG_COUNT;
1662         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1663
1664         tmp=cmd->stop_src;
1665         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1666         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1667
1668         if(err)return 1;
1669
1670         /* step 2: make sure trigger sources are unique and mutually compatible */
1671
1672         /* note that mutual compatiblity is not an issue here */
1673         if(cmd->start_src!=TRIG_NOW &&
1674            cmd->start_src!=TRIG_INT &&
1675            cmd->start_src!=TRIG_EXT)err++;
1676         if(cmd->scan_begin_src!=TRIG_TIMER &&
1677            cmd->scan_begin_src!=TRIG_EXT &&
1678            cmd->scan_begin_src!=TRIG_OTHER)err++;
1679         if(cmd->convert_src!=TRIG_TIMER &&
1680            cmd->convert_src!=TRIG_EXT &&
1681            cmd->convert_src!=TRIG_NOW)err++;
1682         if(cmd->stop_src!=TRIG_COUNT &&
1683            cmd->stop_src!=TRIG_NONE)err++;
1684
1685         if(err)return 2;
1686
1687         /* step 3: make sure arguments are trivially compatible */
1688
1689         if(cmd->start_src==TRIG_EXT){
1690                 /* external trigger */
1691                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1692
1693                 if(tmp > 16) tmp = 16;
1694                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1695                 if(cmd->start_arg != tmp){
1696                         cmd->start_arg = tmp;
1697                         err++;
1698                 }
1699         }else{
1700                 if(cmd->start_arg!=0){
1701                         /* true for both TRIG_NOW and TRIG_INT */
1702                         cmd->start_arg=0;
1703                         err++;
1704                 }
1705         }
1706         if(cmd->scan_begin_src==TRIG_TIMER){
1707                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1708                         cmd->scan_begin_arg=boardtype.ai_speed;
1709                         err++;
1710                 }
1711                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1712                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1713                         err++;
1714                 }
1715         }else if(cmd->scan_begin_src==TRIG_EXT){
1716                 /* external trigger */
1717                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1718
1719                 if(tmp>16)tmp=16;
1720                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1721                 if(cmd->scan_begin_arg!=tmp){
1722                         cmd->scan_begin_arg = tmp;
1723                         err++;
1724                 }
1725         }else{ /* TRIG_OTHER */
1726                 if(cmd->scan_begin_arg){
1727                         cmd->scan_begin_arg=0;
1728                         err++;
1729                 }
1730         }
1731         if(cmd->convert_src==TRIG_TIMER){
1732                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1733                         if(cmd->convert_arg != 0){
1734                                 cmd->convert_arg = 0;
1735                                 err++;
1736                         }
1737                 }else{
1738                         if(cmd->convert_arg<boardtype.ai_speed){
1739                                 cmd->convert_arg=boardtype.ai_speed;
1740                                 err++;
1741                         }
1742                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1743                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1744                                 err++;
1745                         }
1746                 }
1747         }else if(cmd->convert_src == TRIG_EXT){
1748                 /* external trigger */
1749                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1750
1751                 if(tmp>16)tmp=16;
1752                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1753                 if(cmd->convert_arg!=tmp){
1754                         cmd->convert_arg = tmp;
1755                         err++;
1756                 }
1757         }else if(cmd->convert_src == TRIG_NOW){
1758                 if(cmd->convert_arg != 0){
1759                         cmd->convert_arg = 0;
1760                         err++;
1761                 }
1762         }
1763
1764         if(cmd->scan_end_arg!=cmd->chanlist_len){
1765                 cmd->scan_end_arg=cmd->chanlist_len;
1766                 err++;
1767         }
1768         if(cmd->stop_src==TRIG_COUNT){
1769                 unsigned int max_count = 0x01000000;
1770
1771                 if(boardtype.reg_type == ni_reg_611x )
1772                         max_count -= num_adc_stages_611x;
1773                 if(cmd->stop_arg > max_count){
1774                         cmd->stop_arg = max_count;
1775                         err++;
1776                 }
1777                 if(cmd->stop_arg < 1){
1778                         cmd->stop_arg = 1;
1779                         err++;
1780                 }
1781         }else{
1782                 /* TRIG_NONE */
1783                 if(cmd->stop_arg!=0){
1784                         cmd->stop_arg=0;
1785                         err++;
1786                 }
1787         }
1788
1789         if(err)return 3;
1790
1791         /* step 4: fix up any arguments */
1792
1793         if(cmd->scan_begin_src==TRIG_TIMER){
1794                 tmp=cmd->scan_begin_arg;
1795                 ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
1796                 if(tmp!=cmd->scan_begin_arg)err++;
1797         }
1798         if(cmd->convert_src==TRIG_TIMER){
1799                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1800                         tmp=cmd->convert_arg;
1801                         ni_ns_to_timer(dev, &cmd->convert_arg, cmd->flags&TRIG_ROUND_MASK);
1802                         if(tmp!=cmd->convert_arg)err++;
1803                         if(cmd->scan_begin_src==TRIG_TIMER &&
1804                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1805                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1806                                 err++;
1807                         }
1808                 }
1809         }
1810
1811         if(err)return 4;
1812
1813         return 0;
1814 }
1815
1816 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1817 {
1818         comedi_cmd *cmd=&s->async->cmd;
1819         int timer;
1820         int mode1=0; /* mode1 is needed for both stop and convert */
1821         int mode2=0;
1822         int start_stop_select=0;
1823         unsigned int stop_count;
1824         int interrupt_a_enable=0;
1825
1826         MDPRINTK("ni_ai_cmd\n");
1827         if(dev->irq == 0)
1828         {
1829                 comedi_error(dev, "cannot run command without an irq");
1830                 return -EIO;
1831         }
1832         ni_flush_ai_fifo(dev);
1833
1834         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1835
1836         /* start configuration */
1837         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1838
1839         /* disable analog triggering for now, since it
1840          * interferes with the use of pfi0 */
1841         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1842         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1843
1844         switch(cmd->start_src){
1845                 case TRIG_INT:
1846                 case TRIG_NOW:
1847                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1848                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1849                                 AI_Trigger_Select_Register);
1850                         break;
1851                 case TRIG_EXT:
1852                 {
1853                         int chan = CR_CHAN(cmd->start_arg);
1854                         unsigned int bits = AI_START2_Select(0)|
1855                                 AI_START1_Sync |
1856                                 AI_START1_Select(chan + 1);
1857
1858                         if(cmd->start_arg & CR_INVERT)
1859                                 bits |= AI_START1_Polarity;
1860                         if(cmd->start_arg & CR_EDGE)
1861                                 bits |= AI_START1_Edge;
1862                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1863                         break;
1864                 }
1865         }
1866
1867         mode2 &= ~AI_Pre_Trigger;
1868         mode2 &= ~AI_SC_Initial_Load_Source;
1869         mode2 &= ~AI_SC_Reload_Mode;
1870         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1871
1872         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1873                 start_stop_select |= AI_STOP_Polarity;
1874                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1875                 start_stop_select |= AI_STOP_Sync;
1876         }else
1877         {
1878                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
1879         }
1880         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1881
1882         devpriv->ai_cmd2 = 0;
1883         switch(cmd->stop_src){
1884         case TRIG_COUNT:
1885                 stop_count = cmd->stop_arg - 1;
1886
1887                 if(boardtype.reg_type == ni_reg_611x){
1888                         // have to take 3 stage adc pipeline into account
1889                         stop_count += num_adc_stages_611x;
1890                 }
1891                 /* stage number of scans */
1892                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
1893
1894                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1895                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1896                 /* load SC (Scan Count) */
1897                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1898
1899                 devpriv->ai_continuous = 0;
1900                 if( stop_count == 0 ){
1901                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1902                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1903                         // this is required to get the last sample for chanlist_len > 1, not sure why
1904                         if(cmd->chanlist_len > 1)
1905                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
1906                 }
1907                 break;
1908         case TRIG_NONE:
1909                 /* stage number of scans */
1910                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
1911
1912                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1913                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1914
1915                 /* load SC (Scan Count) */
1916                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1917
1918                 devpriv->ai_continuous = 1;
1919
1920                 break;
1921         }
1922
1923         switch(cmd->scan_begin_src){
1924         case TRIG_TIMER:
1925                 /*
1926                         stop bits for non 611x boards
1927                         AI_SI_Special_Trigger_Delay=0
1928                         AI_Pre_Trigger=0
1929                         AI_START_STOP_Select_Register:
1930                         AI_START_Polarity=0 (?) rising edge
1931                         AI_START_Edge=1         edge triggered
1932                         AI_START_Sync=1 (?)
1933                         AI_START_Select=0               SI_TC
1934                         AI_STOP_Polarity=0              rising edge
1935                         AI_STOP_Edge=0          level
1936                         AI_STOP_Sync=1
1937                         AI_STOP_Select=19               external pin (configuration mem)
1938                  */
1939                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1940                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1941
1942                 mode2 |= AI_SI_Reload_Mode(0);
1943                 /* AI_SI_Initial_Load_Source=A */
1944                 mode2 &= ~AI_SI_Initial_Load_Source;
1945                 //mode2 |= AI_SC_Reload_Mode;
1946                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1947
1948                 /* load SI */
1949                 timer = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
1950                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
1951                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
1952                 break;
1953         case TRIG_EXT:
1954                 if( cmd->scan_begin_arg & CR_EDGE )
1955                         start_stop_select |= AI_START_Edge;
1956                 /* AI_START_Polarity==1 is falling edge */
1957                 if( cmd->scan_begin_arg & CR_INVERT )
1958                         start_stop_select |= AI_START_Polarity;
1959                 if( cmd->scan_begin_src != cmd->convert_src ||
1960                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1961                         start_stop_select |= AI_START_Sync;
1962                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
1963                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1964                 break;
1965         }
1966
1967         switch(cmd->convert_src){
1968         case TRIG_TIMER:
1969         case TRIG_NOW:
1970                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
1971                         timer = 1;
1972                 else
1973                         timer = ni_ns_to_timer(dev, &cmd->convert_arg, TRIG_ROUND_NEAREST);
1974                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
1975                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
1976
1977                 /* AI_SI2_Reload_Mode = alternate */
1978                 /* AI_SI2_Initial_Load_Source = A */
1979                 mode2 &= ~AI_SI2_Initial_Load_Source;
1980                 mode2 |= AI_SI2_Reload_Mode;
1981                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
1982
1983                 /* AI_SI2_Load */
1984                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
1985
1986                 mode2 |= AI_SI2_Reload_Mode; // alternate
1987                 mode2 |= AI_SI2_Initial_Load_Source; // B
1988
1989                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
1990                 break;
1991         case TRIG_EXT:
1992                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
1993                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
1994                         mode1 |= AI_CONVERT_Source_Polarity;
1995                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1996
1997                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
1998                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1999
2000                 break;
2001         }
2002
2003         if(dev->irq){
2004
2005                 /* interrupt on FIFO, errors, SC_TC */
2006                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2007                         AI_SC_TC_Interrupt_Enable;
2008
2009 #ifndef PCIDMA
2010                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2011 #endif
2012
2013                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2014                         /* wake on end-of-scan */
2015                         devpriv->aimode=AIMODE_SCAN;
2016                 }else{
2017                         devpriv->aimode=AIMODE_HALF_FULL;
2018                 }
2019
2020                 switch(devpriv->aimode){
2021                 case AIMODE_HALF_FULL:
2022                         /*generate FIFO interrupts and DMA requests on half-full */
2023 #ifdef PCIDMA
2024                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2025 #else
2026                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2027 #endif
2028                         break;
2029                 case AIMODE_SAMPLE:
2030                         /*generate FIFO interrupts on non-empty */
2031                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2032                         break;
2033                 case AIMODE_SCAN:
2034 #ifdef PCIDMA
2035                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2036 #else
2037                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2038 #endif
2039                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2040                         break;
2041                 default:
2042                         break;
2043                 }
2044
2045                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2046
2047                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2048
2049                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2050         }else{
2051                 /* interrupt on nothing */
2052                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2053
2054                 /* XXX start polling if necessary */
2055                 MDPRINTK("interrupting on nothing\n");
2056         }
2057
2058         /* end configuration */
2059         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2060
2061         switch(cmd->scan_begin_src){
2062         case TRIG_TIMER:
2063                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2064                         AI_Command_1_Register);
2065                 break;
2066         case TRIG_EXT:
2067                 /* XXX AI_SI_Arm? */
2068                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2069                         AI_Command_1_Register);
2070                 break;
2071         }
2072
2073 #ifdef PCIDMA
2074         ni_ai_setup_MITE_dma(dev,cmd);
2075         //mite_dump_regs(devpriv->mite);
2076 #endif
2077
2078         switch(cmd->start_src){
2079         case TRIG_NOW:
2080                 /* AI_START1_Pulse */
2081                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2082                 s->async->inttrig=NULL;
2083                 break;
2084         case TRIG_EXT:
2085                 s->async->inttrig=NULL;
2086                 break;
2087         case TRIG_INT:
2088                 s->async->inttrig=ni_ai_inttrig;
2089                 break;
2090         }
2091
2092         MDPRINTK("exit ni_ai_cmd\n");
2093
2094         return 0;
2095 }
2096
2097 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2098         unsigned int trignum)
2099 {
2100         if(trignum!=0)return -EINVAL;
2101
2102         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2103         s->async->inttrig=NULL;
2104
2105         return 1;
2106 }
2107
2108 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2109         comedi_insn *insn, lsampl_t *data);
2110
2111 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2112         comedi_insn *insn, lsampl_t *data)
2113 {
2114         if(insn->n<1)return -EINVAL;
2115
2116         switch(data[0]){
2117         case INSN_CONFIG_ANALOG_TRIG:
2118                 return ni_ai_config_analog_trig(dev,s,insn,data);
2119         case INSN_CONFIG_ALT_SOURCE:
2120                 if(boardtype.reg_type == ni_reg_m_series)
2121                 {
2122                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2123                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2124                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2125                         {
2126                                 return -EINVAL;
2127                         }
2128                         devpriv->ai_calib_source = data[1];
2129                 } else if(boardtype.reg_type == ni_reg_6143)
2130                 {
2131                         unsigned int calib_source;
2132
2133                         calib_source = data[1] & 0xf;
2134
2135
2136                         if(calib_source > 0xF)
2137                                 return -EINVAL;
2138
2139                         devpriv->ai_calib_source = calib_source;
2140                         ni_writew(calib_source, Calibration_Channel_6143);
2141                 }else
2142                 {
2143                         unsigned int calib_source;
2144                         unsigned int calib_source_adjust;
2145
2146                         calib_source = data[1] & 0xf;
2147                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2148
2149                         if(calib_source >= 8)
2150                                 return -EINVAL;
2151                         devpriv->ai_calib_source = calib_source;
2152                         if(boardtype.reg_type == ni_reg_611x){
2153                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2154                         }
2155                 }
2156                 return 2;
2157         default:
2158                 break;
2159         }
2160
2161         return -EINVAL;
2162 }
2163
2164 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2165         comedi_insn *insn, lsampl_t *data)
2166 {
2167         unsigned int a,b,modebits;
2168         int err=0;
2169
2170         /* data[1] is flags
2171          * data[2] is analog line
2172          * data[3] is set level
2173          * data[4] is reset level */
2174         if(!boardtype.has_analog_trig)return -EINVAL;
2175         if(insn->n!=5)return -EINVAL;
2176         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2177                 data[1]&=~(COMEDI_EV_SCAN_BEGIN&0xffff);
2178                 err++;
2179         }
2180         if(data[2]>=boardtype.n_adchan){
2181                 data[2]=boardtype.n_adchan-1;
2182                 err++;
2183         }
2184         if(data[3]>255){ /* a */
2185                 data[3]=255;
2186                 err++;
2187         }
2188         if(data[4]>255){ /* b */
2189                 data[4]=255;
2190                 err++;
2191         }
2192         /*
2193          * 00 ignore
2194          * 01 set
2195          * 10 reset
2196          *
2197          * modes:
2198          *   1 level:                    +b-   +a-
2199          *     high mode                00 00 01 10
2200          *     low mode                 00 00 10 01
2201          *   2 level: (a<b)
2202          *     hysteresis low mode      10 00 00 01
2203          *     hysteresis high mode     01 00 00 10
2204          *     middle mode              10 01 01 10
2205          */
2206
2207         a=data[3];
2208         b=data[4];
2209         modebits=data[1]&0xff;
2210         if(modebits&0xf0){
2211                 /* two level mode */
2212                 if(b<a){
2213                         /* swap order */
2214                         a=data[4];
2215                         b=data[3];
2216                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2217                 }
2218                 devpriv->atrig_low = a;
2219                 devpriv->atrig_high = b;
2220                 switch(modebits){
2221                 case 0x81:      /* low hysteresis mode */
2222                         devpriv->atrig_mode = 6;
2223                         break;
2224                 case 0x42:      /* high hysteresis mode */
2225                         devpriv->atrig_mode = 3;
2226                         break;
2227                 case 0x96:      /* middle window mode */
2228                         devpriv->atrig_mode = 2;
2229                         break;
2230                 default:
2231                         data[1]&=~0xff;
2232                         err++;
2233                 }
2234         }else{
2235                 /* one level mode */
2236                 if(b!=0){
2237                         data[4]=0;
2238                         err++;
2239                 }
2240                 switch(modebits){
2241                 case 0x06:      /* high window mode */
2242                         devpriv->atrig_high = a;
2243                         devpriv->atrig_mode = 0;
2244                         break;
2245                 case 0x09:      /* low window mode */
2246                         devpriv->atrig_low = a;
2247                         devpriv->atrig_mode = 1;
2248                         break;
2249                 default:
2250                         data[1]&=~0xff;
2251                         err++;
2252                 }
2253         }
2254         if(err)return -EAGAIN;
2255         return 5;
2256 }
2257
2258 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2259 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2260         void *data, unsigned int num_bytes, unsigned int chan_index )
2261 {
2262         comedi_async *async = s->async;
2263         unsigned int range;
2264         unsigned int i;
2265         unsigned int offset;
2266         unsigned int length = num_bytes / sizeof( sampl_t );
2267         sampl_t *array = data;
2268
2269         offset = 1 << (boardtype.aobits - 1);
2270         for(i = 0; i < length; i++)
2271         {
2272                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2273                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2274                         array[i] -= offset;
2275 #ifdef PCIDMA
2276                 array[i] = cpu_to_le16( array[i] );
2277 #endif
2278                 chan_index++;
2279                 chan_index %= async->cmd.chanlist_len;
2280         }
2281 }
2282
2283 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2284         unsigned int chanspec[], unsigned int n_chans)
2285 {
2286         unsigned int range;
2287         unsigned int chan;
2288         unsigned int conf;
2289         int i;
2290         int invert = 0;
2291
2292         for(i=0;i<n_chans;i++){
2293                 chan = CR_CHAN(chanspec[i]);
2294                 range = CR_RANGE(chanspec[i]);
2295                 if(boardtype.reg_type == ni_reg_m_series)
2296                 {
2297                         comedi_krange *krange = s->range_table->range + range;
2298                         invert = 0;
2299                         conf = 0;
2300                         switch(krange->max - krange->min)
2301                         {
2302                         case 20000000:
2303                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2304                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2305                                 break;
2306                         case 10000000:
2307                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2308                                 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2309                                 break;
2310                         case 4000000:
2311                                 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2312                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2313                                 break;
2314                         case 2000000:
2315                                 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2316                                 ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2317                                 break;
2318                         default:
2319                                 rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2320                                 break;
2321                         }
2322                         switch(krange->max + krange->min)
2323                         {
2324                         case 0:
2325                                 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2326                                 break;
2327                         case 10000000:
2328                                 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2329                                 break;
2330                         default:
2331                                 rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2332                                 break;
2333                         }
2334                         ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2335                 }else
2336                 {
2337                         conf = AO_Channel(chan);
2338
2339                         if(boardtype.ao_unipolar){
2340                                 if((range&1) == 0){
2341                                         conf |= AO_Bipolar;
2342                                         invert = (1<<(boardtype.aobits-1));
2343                                 }else{
2344                                         invert = 0;
2345                                 }
2346                                 if(range&2)
2347                                         conf |= AO_Ext_Ref;
2348                         }else{
2349                                 conf |= AO_Bipolar;
2350                                 invert = (1<<(boardtype.aobits-1));
2351                         }
2352
2353                         /* not all boards can deglitch, but this shouldn't hurt */
2354                         if(chanspec[i] & CR_DEGLITCH)
2355                                 conf |= AO_Deglitch;
2356
2357                         /* analog reference */
2358                         /* AREF_OTHER connects AO ground to AI ground, i think */
2359                         conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2360
2361                         ni_writew(conf,AO_Configuration);
2362                 }
2363                 devpriv->ao_conf[chan] = conf;
2364         }
2365         return invert;
2366 }
2367
2368 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2369         comedi_insn *insn,lsampl_t *data)
2370 {
2371         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2372
2373         return 1;
2374 }
2375
2376 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2377         comedi_insn *insn,lsampl_t *data)
2378 {
2379         unsigned int chan = CR_CHAN(insn->chanspec);
2380         unsigned int invert;
2381
2382         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2383
2384         devpriv->ao[chan] = data[0];
2385
2386         if(boardtype.reg_type == ni_reg_m_series)
2387         {
2388                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2389         }
2390         else
2391                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2392
2393         return 1;
2394 }
2395
2396 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2397         comedi_insn *insn,lsampl_t *data)
2398 {
2399         unsigned int chan = CR_CHAN(insn->chanspec);
2400         unsigned int invert;
2401
2402         ao_win_out(1 << chan, AO_Immediate_671x);
2403         invert = 1 << (boardtype.aobits - 1);
2404
2405         ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2406
2407         devpriv->ao[chan] = data[0];
2408         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2409
2410         return 1;
2411 }
2412
2413 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2414         unsigned int trignum)
2415 {
2416         int ret;
2417         int interrupt_b_bits;
2418         int i;
2419         static const int timeout = 1000;
2420
2421         if(trignum!=0)return -EINVAL;
2422
2423         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2424         interrupt_b_bits = AO_Error_Interrupt_Enable;
2425 #ifdef PCIDMA
2426         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2427         if(boardtype.reg_type & ni_reg_6xxx_mask)
2428                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2429         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2430         ret = ni_ao_wait_for_dma_load(dev);
2431         if(ret < 0) return ret;
2432
2433 #else
2434         ret = ni_ao_prep_fifo(dev,s);
2435         if(ret==0)return -EPIPE;
2436
2437         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2438 #endif
2439
2440         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2441         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2442         /* wait for DACs to be loaded */
2443         for(i = 0; i < timeout; i++)
2444         {
2445                 comedi_udelay(10);
2446                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2447                         break;
2448         }
2449         if(i == timeout)
2450         {
2451                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2452                 return -EIO;
2453         }
2454         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2455         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2456
2457         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2458
2459         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2460                 AO_Command_1_Register);
2461
2462         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2463
2464         s->async->inttrig=NULL;
2465
2466         return 0;
2467 }
2468
2469 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2470 {
2471         comedi_cmd *cmd = &s->async->cmd;
2472         int trigvar;
2473         int bits;
2474         int i;
2475
2476         if(dev->irq == 0)
2477         {
2478                 comedi_error(dev, "cannot run command without an irq");
2479                 return -EIO;
2480         }
2481         trigvar = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2482
2483         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2484
2485         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2486
2487         if(boardtype.reg_type & ni_reg_6xxx_mask)
2488         {
2489                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2490
2491                 bits = 0;
2492                 for(i = 0; i < cmd->chanlist_len; i++)
2493                 {
2494                         int chan;
2495
2496                         chan = CR_CHAN(cmd->chanlist[i]);
2497                         bits |= 1 << chan;
2498                         ao_win_out(chan, AO_Waveform_Generation_611x);
2499                 }
2500                 ao_win_out(bits, AO_Timed_611x);
2501         }
2502
2503         ni_ao_config_chanlist(dev,s,cmd->chanlist,cmd->chanlist_len);
2504
2505         if(cmd->stop_src==TRIG_NONE){
2506                 devpriv->ao_mode1|=AO_Continuous;
2507                 devpriv->ao_mode1&=~AO_Trigger_Once;
2508         }else{
2509                 devpriv->ao_mode1&=~AO_Continuous;
2510                 devpriv->ao_mode1|=AO_Trigger_Once;
2511         }
2512         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2513         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2514         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2515         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2516         devpriv->ao_mode3&=~AO_Trigger_Length;
2517         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2518
2519         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2520         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2521         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2522         if(cmd->stop_src==TRIG_NONE){
2523                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2524         }else{
2525                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2526         }
2527         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2528         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2529         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2530         switch(cmd->stop_src){
2531         case TRIG_COUNT:
2532                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2533                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2534                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2535                 break;
2536         case TRIG_NONE:
2537                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2538                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2539                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2540                 break;
2541         default:
2542                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2543                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2544                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2545         }
2546
2547         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2548         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2549         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2550         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2551         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2552         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2553         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2554         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2555         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2556
2557         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2558                 if(cmd->scan_end_arg>1){
2559                         devpriv->ao_mode1|=AO_Multiple_Channels;
2560                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2561                                 AO_UPDATE_Output_Select(1),
2562                                 AO_Output_Control_Register);
2563                 }else{
2564                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2565                         devpriv->stc_writew(dev, AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]))|
2566                                 AO_UPDATE_Output_Select(1),
2567                                 AO_Output_Control_Register);
2568                 }
2569                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2570         }
2571
2572         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2573
2574         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2575         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2576
2577         devpriv->ao_mode2 &= AO_FIFO_Mode_Mask;
2578 #ifdef PCIDMA
2579         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2580 #else
2581         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2582 #endif
2583         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2584         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2585
2586         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2587                 AO_TMRDACWR_Pulse_Width;
2588         if( boardtype.ao_fifo_depth )
2589                 bits |= AO_FIFO_Enable;
2590         else
2591                 bits |= AO_DMA_PIO_Control;
2592         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2593         // enable sending of ao dma requests
2594         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2595
2596         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2597
2598         if(cmd->stop_src==TRIG_COUNT) {
2599                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2600                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2601                         AO_BC_TC_Interrupt_Enable, 1);
2602         }
2603
2604         s->async->inttrig=ni_ao_inttrig;
2605
2606         return 0;
2607 }
2608
2609 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2610 {
2611         int err=0;
2612         int tmp;
2613
2614         /* step 1: make sure trigger sources are trivially valid */
2615
2616         tmp=cmd->start_src;
2617         cmd->start_src &= TRIG_INT;
2618         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2619
2620         tmp=cmd->scan_begin_src;
2621         cmd->scan_begin_src &= TRIG_TIMER;
2622         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2623
2624         tmp=cmd->convert_src;
2625         cmd->convert_src &= TRIG_NOW;
2626         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2627
2628         tmp=cmd->scan_end_src;
2629         cmd->scan_end_src &= TRIG_COUNT;
2630         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2631
2632         tmp=cmd->stop_src;
2633         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2634         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2635
2636         if(err)return 1;
2637
2638         /* step 2: make sure trigger sources are unique and mutually compatible */
2639
2640         if(cmd->stop_src!=TRIG_COUNT &&
2641            cmd->stop_src!=TRIG_NONE)err++;
2642
2643         if(err)return 2;
2644
2645         /* step 3: make sure arguments are trivially compatible */
2646
2647         if(cmd->start_arg!=0){
2648                 cmd->start_arg=0;
2649                 err++;
2650         }
2651 #if 0
2652         /* XXX need ao_speed */
2653         if(cmd->scan_begin_arg<boardtype.ao_speed){
2654                 cmd->scan_begin_arg=boardtype.ao_speed;
2655                 err++;
2656         }
2657 #endif
2658         if(cmd->scan_begin_arg>devpriv->clock_ns*0xffffff){ /* XXX check */
2659                 cmd->scan_begin_arg=devpriv->clock_ns*0xffffff;
2660                 err++;
2661         }
2662         if(cmd->convert_arg!=0){
2663                 cmd->convert_arg=0;
2664                 err++;
2665         }
2666         if(cmd->scan_end_arg!=cmd->chanlist_len){
2667                 cmd->scan_end_arg=cmd->chanlist_len;
2668                 err++;
2669         }
2670         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2671                 if(cmd->stop_arg>0x00ffffff){
2672                         cmd->stop_arg=0x00ffffff;
2673                         err++;
2674                 }
2675         }else{
2676                 /* TRIG_NONE */
2677                 if(cmd->stop_arg!=0){
2678                         cmd->stop_arg=0;
2679                         err++;
2680                 }
2681         }
2682
2683         if(err)return 3;
2684
2685         /* step 4: fix up any arguments */
2686
2687         tmp = cmd->scan_begin_arg;
2688         ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
2689         if(tmp!=cmd->scan_begin_arg)err++;
2690
2691         if(err)return 4;
2692
2693         /* step 5: fix up chanlist */
2694
2695         if(err)return 5;
2696
2697         return 0;
2698 }
2699
2700
2701 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2702 {
2703         //devpriv->ao0p=0x0000;
2704         //ni_writew(devpriv->ao0p,AO_Configuration);
2705
2706         //devpriv->ao1p=AO_Channel(1);
2707         //ni_writew(devpriv->ao1p,AO_Configuration);
2708
2709 #ifdef PCIDMA
2710         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2711         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
2712 #endif
2713
2714         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2715         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2716         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2717         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2718         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2719         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2720                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2721         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2722         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2723         devpriv->ao_cmd1=0;
2724         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2725         devpriv->ao_cmd2=0;
2726         devpriv->ao_mode1=0;
2727         devpriv->ao_mode2=0;
2728         if(boardtype.reg_type == ni_reg_m_series)
2729                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2730         else
2731                 devpriv->ao_mode3 = 0;
2732         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2733         devpriv->ao_trigger_select=0;
2734         if(boardtype.reg_type & ni_reg_6xxx_mask){
2735                 ao_win_out(0x3, AO_Immediate_671x);
2736                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2737         }
2738         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2739
2740         return 0;
2741 }
2742
2743 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2744         comedi_insn *insn,lsampl_t *data)
2745 {
2746 #ifdef DEBUG_DIO
2747         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2748                 CR_CHAN(insn->chanspec),data[0]);
2749 #endif
2750         switch(data[0]){
2751         case INSN_CONFIG_DIO_OUTPUT:
2752                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2753                 break;
2754         case INSN_CONFIG_DIO_INPUT:
2755                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2756                 break;
2757         case INSN_CONFIG_DIO_QUERY:
2758                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2759                 return insn->n;
2760                 break;
2761         default:
2762                 return -EINVAL;
2763         }
2764
2765         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2766         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2767         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2768
2769         return 1;
2770 }
2771
2772 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2773         comedi_insn *insn,lsampl_t *data)
2774 {
2775 #ifdef DEBUG_DIO
2776         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2777 #endif
2778         if(insn->n!=2)return -EINVAL;
2779         if(data[0]){
2780                 /* Perform check to make sure we're not using the
2781                    serial part of the dio */
2782                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2783                         return -EBUSY;
2784
2785                 s->state &= ~data[0];
2786                 s->state |= (data[0]&data[1]);
2787                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2788                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2789                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2790         }
2791         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2792
2793         return 2;
2794 }
2795
2796 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2797         comedi_insn *insn, lsampl_t *data)
2798 {
2799 #ifdef DEBUG_DIO
2800         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
2801                 CR_CHAN(insn->chanspec), data[0]);
2802 #endif
2803         switch(data[0])
2804         {
2805         case INSN_CONFIG_DIO_OUTPUT:
2806                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2807                 break;
2808         case INSN_CONFIG_DIO_INPUT:
2809                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2810                 break;
2811         case INSN_CONFIG_DIO_QUERY:
2812                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2813                 return insn->n;
2814                 break;
2815         default:
2816                 return -EINVAL;
2817         }
2818
2819         ni_writel(s->io_bits, M_Offset_DIO_Direction);
2820
2821         return 1;
2822 }
2823
2824 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2825         comedi_insn *insn, lsampl_t *data)
2826 {
2827 #ifdef DEBUG_DIO
2828         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2829 #endif
2830         if(insn->n!=2)return -EINVAL;
2831         if(data[0]){
2832                 s->state &= ~data[0];
2833                 s->state |= (data[0] & data[1]);
2834                 ni_writel(s->state, M_Offset_Static_Digital_Output);
2835         }
2836         data[1] = ni_readl(M_Offset_Static_Digital_Input);
2837
2838         return 2;
2839 }
2840
2841 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2842                                  comedi_insn *insn,lsampl_t *data)
2843 {
2844         int err = insn->n;
2845         unsigned char byte_out, byte_in;
2846
2847         if(insn->n!=2)return -EINVAL;
2848
2849         switch(data[0]) {
2850         case INSN_CONFIG_SERIAL_CLOCK:
2851
2852 #ifdef DEBUG_DIO
2853                 rt_printk("SPI serial clock Config cd\n", data[1]);
2854 #endif
2855                 devpriv->serial_hw_mode = 1;
2856                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2857
2858                 if(data[1] == SERIAL_DISABLED) {
2859                         devpriv->serial_hw_mode = 0;
2860                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2861                                                   DIO_Software_Serial_Control);
2862                         data[1] = SERIAL_DISABLED;
2863                         devpriv->serial_interval_ns = data[1];
2864                 }
2865                 else if(data[1] <= SERIAL_600NS) {
2866                         /* Warning: this clock speed is too fast to reliably
2867                         control SCXI. */
2868                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2869                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2870                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2871                         data[1] = SERIAL_600NS;
2872                         devpriv->serial_interval_ns = data[1];
2873                 }
2874                 else if(data[1] <= SERIAL_1_2US) {
2875                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2876                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2877                                 DIO_Serial_Out_Divide_By_2;
2878                         data[1] = SERIAL_1_2US;
2879                         devpriv->serial_interval_ns = data[1];
2880                 }
2881                 else if(data[1] <= SERIAL_10US) {
2882                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2883                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2884                                 DIO_Serial_Out_Divide_By_2;
2885                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2886                         600ns/1.2us. If you turn divide_by_2 off with the
2887                         slow clock, you will still get 10us, except then
2888                         all your delays are wrong. */
2889                         data[1] = SERIAL_10US;
2890                         devpriv->serial_interval_ns = data[1];
2891                 }
2892                 else {
2893                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2894                                                   DIO_Software_Serial_Control);
2895                         devpriv->serial_hw_mode = 0;
2896                         data[1] = (data[1] / 1000) * 1000;
2897                         devpriv->serial_interval_ns = data[1];
2898                 }
2899
2900                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2901                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
2902                 return 1;
2903
2904         break;
2905
2906         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2907
2908                 if(devpriv->serial_interval_ns == 0) {
2909                         return -EINVAL;
2910                 }
2911
2912                 byte_out = data[1] & 0xFF;
2913
2914                 if(devpriv->serial_hw_mode) {
2915                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2916                 } else if(devpriv->serial_interval_ns > 0) {
2917                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2918                 } else {
2919                         rt_printk("ni_serial_insn_config: serial disabled!\n");
2920                         return -EINVAL;
2921                 }
2922                 if(err < 0) return err;
2923                 data[1] = byte_in & 0xFF;
2924                 return insn->n;
2925
2926         break;
2927         default:
2928                 return -EINVAL;
2929         }
2930
2931 }
2932
2933 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2934                                    unsigned char data_out,
2935                                    unsigned char *data_in)
2936 {
2937         unsigned int status1;
2938         int err = 0, count = 20;
2939
2940 #ifdef DEBUG_DIO
2941         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
2942 #endif
2943
2944         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
2945         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
2946         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2947
2948         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
2949         if(status1 & DIO_Serial_IO_In_Progress_St) {
2950                 err = -EBUSY;
2951                 goto Error;
2952         }
2953
2954         devpriv->dio_control |= DIO_HW_Serial_Start;
2955         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2956         devpriv->dio_control &= ~DIO_HW_Serial_Start;
2957
2958         /* Wait until STC says we're done, but don't loop infinitely. */
2959         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
2960                 /* Delay one bit per loop */
2961                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2962                 if(--count < 0) {
2963                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
2964                         err = -ETIME;
2965                         goto Error;
2966                 }
2967         }
2968
2969         /* Delay for last bit. This delay is absolutely necessary, because
2970            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
2971         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2972
2973         if(data_in != NULL) {
2974                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
2975 #ifdef DEBUG_DIO
2976                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
2977 #endif
2978         }
2979
2980  Error:
2981         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2982
2983         return err;
2984 }
2985
2986 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2987                                    unsigned char data_out,
2988                                    unsigned char *data_in)
2989 {
2990         unsigned char mask, input = 0;
2991
2992 #ifdef DEBUG_DIO
2993         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
2994 #endif
2995
2996         /* Wait for one bit before transfer */
2997         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2998
2999         for(mask = 0x80; mask; mask >>= 1) {
3000                 /* Output current bit; note that we cannot touch s->state
3001            because it is a per-subdevice field, and serial is
3002                    a separate subdevice from DIO. */
3003                 devpriv->dio_output &= ~DIO_SDOUT;
3004                 if(data_out & mask) {
3005                         devpriv->dio_output |= DIO_SDOUT;
3006                 }
3007                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3008
3009                 /* Assert SDCLK (active low, inverted), wait for half of
3010                    the delay, deassert SDCLK, and wait for the other half. */
3011                 devpriv->dio_control |= DIO_Software_Serial_Control;
3012                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3013
3014                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3015
3016                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3017                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3018
3019                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3020
3021                 /* Input current bit */
3022                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3023 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3024                         input |= mask;
3025                 }
3026         }
3027 #ifdef DEBUG_DIO
3028         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3029 #endif
3030         if(data_in) *data_in = input;
3031
3032         return 0;
3033 }
3034
3035 static void mio_common_detach(comedi_device *dev)
3036 {
3037         if(dev->subdevices && boardtype.has_8255)
3038                 subdev_8255_cleanup(dev,dev->subdevices+3);
3039 }
3040
3041 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3042 {
3043         int i;
3044
3045         for(i = 0; i < s->n_chan; i++)
3046                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3047 }
3048
3049 static int ni_alloc_private(comedi_device *dev)
3050 {
3051         int ret;
3052
3053         ret = alloc_private(dev, sizeof(ni_private));
3054         if(ret < 0) return ret;
3055
3056         spin_lock_init(&devpriv->window_lock);
3057
3058         return 0;
3059 };
3060
3061 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3062 {
3063         comedi_subdevice *s;
3064         int bits;
3065
3066         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3067         {
3068                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3069                 return -EINVAL;
3070         }
3071
3072         if(alloc_subdevices(dev, 11) < 0)
3073                 return -ENOMEM;
3074
3075         /* analog input subdevice */
3076
3077         s=dev->subdevices+0;
3078         dev->read_subdev=s;
3079         if(boardtype.n_adchan){
3080                 s->type=COMEDI_SUBD_AI;
3081                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER;
3082                 if(boardtype.reg_type != ni_reg_611x)
3083                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3084                 if(boardtype.adbits > 16)
3085                         s->subdev_flags |= SDF_LSAMPL;
3086                 if(boardtype.reg_type == ni_reg_m_series)
3087                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3088                 s->n_chan=boardtype.n_adchan;
3089                 s->len_chanlist=512;
3090                 s->maxdata=(1<<boardtype.adbits)-1;
3091                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3092                 s->insn_read=ni_ai_insn_read;
3093                 s->insn_config=ni_ai_insn_config;
3094                 s->do_cmdtest=ni_ai_cmdtest;
3095                 s->do_cmd=ni_ai_cmd;
3096                 s->cancel=ni_ai_reset;
3097                 s->poll=ni_ai_poll;
3098                 s->munge=ni_ai_munge;
3099         }else{
3100                 s->type=COMEDI_SUBD_UNUSED;
3101         }
3102
3103         /* analog output subdevice */
3104
3105         s=dev->subdevices+1;
3106         if(boardtype.n_aochan){
3107                 dev->write_subdev=s;
3108                 s->type=COMEDI_SUBD_AO;
3109                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
3110                 if(boardtype.reg_type == ni_reg_m_series)
3111                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3112                 s->n_chan=boardtype.n_aochan;
3113                 s->maxdata=(1<<boardtype.aobits)-1;
3114                 s->range_table = boardtype.ao_range_table;
3115                 s->insn_read=ni_ao_insn_read;
3116                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3117                         s->insn_write=ni_ao_insn_write_671x;
3118                 }else{
3119                         s->insn_write=ni_ao_insn_write;
3120                 }
3121 #ifdef PCIDMA
3122                 if(boardtype.n_aochan){
3123 #else
3124                 if(boardtype.ao_fifo_depth){
3125 #endif
3126                         s->do_cmd=ni_ao_cmd;
3127                         s->do_cmdtest=ni_ao_cmdtest;
3128                         s->len_chanlist = boardtype.n_aochan;
3129                         if(boardtype.reg_type != ni_reg_m_series)
3130                                 s->munge=ni_ao_munge;
3131                 }
3132                 s->cancel=ni_ao_reset;
3133         }else{
3134                 s->type=COMEDI_SUBD_UNUSED;
3135         }
3136         if((boardtype.reg_type & ni_reg_67xx_mask))
3137                 init_ao_67xx(dev, s);
3138
3139         /* digital i/o subdevice */
3140
3141         s=dev->subdevices+2;
3142         s->type=COMEDI_SUBD_DIO;
3143         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3144         s->maxdata=1;
3145         s->io_bits=0;           /* all bits input */
3146         s->range_table=&range_digital;
3147         if(boardtype.reg_type == ni_reg_m_series)
3148         {
3149                 s->n_chan = 32;
3150                 s->insn_bits = ni_m_series_dio_insn_bits;
3151                 s->insn_config=ni_m_series_dio_insn_config;
3152                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3153         }else
3154         {
3155                 s->n_chan=8;
3156                 s->insn_bits=ni_dio_insn_bits;
3157                 s->insn_config=ni_dio_insn_config;
3158                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3159                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3160         }
3161
3162         /* 8255 device */
3163         s=dev->subdevices+3;
3164         if(boardtype.has_8255){
3165                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3166         }else{
3167                 s->type=COMEDI_SUBD_UNUSED;
3168         }
3169
3170         /* general purpose counter/timer device */
3171         s=dev->subdevices+4;
3172         s->type=COMEDI_SUBD_COUNTER;
3173         s->subdev_flags=SDF_READABLE|SDF_WRITABLE;
3174         s->insn_read=  ni_gpct_insn_read;
3175         s->insn_write= ni_gpct_insn_write;
3176         s->insn_config=ni_gpct_insn_config;
3177         s->n_chan=2;
3178         s->maxdata=1;
3179         devpriv->an_trig_etc_reg = 0;
3180         GPCT_Reset(dev,0);
3181         GPCT_Reset(dev,1);
3182
3183         /* calibration subdevice -- ai and ao */
3184         s=dev->subdevices+5;
3185         s->type=COMEDI_SUBD_CALIB;
3186         if(boardtype.reg_type == ni_reg_m_series)
3187         {
3188                 // internal PWM analog output used for AI nonlinearity calibration
3189                 s->subdev_flags = SDF_INTERNAL;
3190                 s->insn_config = &ni_m_series_pwm_config;
3191                 s->n_chan = 1;
3192                 s->maxdata = 0;
3193                 ni_writel(0x0, M_Offset_Cal_PWM);
3194         } else if(boardtype.reg_type == ni_reg_6143)
3195         {
3196                 // internal PWM analog output used for AI nonlinearity calibration
3197                 s->subdev_flags = SDF_INTERNAL;
3198                 s->insn_config = &ni_6143_pwm_config;
3199                 s->n_chan = 1;
3200                 s->maxdata = 0;
3201         }else
3202         {
3203                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3204                 s->insn_read = &ni_calib_insn_read;
3205                 s->insn_write = &ni_calib_insn_write;
3206                 caldac_setup(dev, s);
3207         }
3208
3209         /* EEPROM */
3210         s=dev->subdevices+6;
3211         s->type=COMEDI_SUBD_MEMORY;
3212         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3213         s->maxdata=0xff;
3214         if(boardtype.reg_type == ni_reg_m_series)
3215         {
3216                 s->n_chan = M_SERIES_EEPROM_SIZE;
3217                 s->insn_read = &ni_m_series_eeprom_insn_read;
3218         }else
3219         {
3220                 s->n_chan = 512;
3221                 s->insn_read = &ni_eeprom_insn_read;
3222         }
3223         /* PFI */
3224         s=dev->subdevices + 7;
3225         s->type = COMEDI_SUBD_DIO;
3226         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3227         if(boardtype.reg_type == ni_reg_m_series)
3228         {
3229                 s->n_chan = 16;
3230         }else
3231         {
3232                 s->n_chan = 10;
3233         }
3234         s->maxdata = 1;
3235         s->insn_bits = ni_pfi_insn_bits;
3236         s->insn_config = ni_pfi_insn_config;
3237         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3238         unsigned i;
3239         for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3240         {
3241                 ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3242         }
3243         /* cs5529 calibration adc */
3244         s = dev->subdevices + 8;
3245         if(boardtype.reg_type & ni_reg_67xx_mask)
3246         {
3247                 s->type = COMEDI_SUBD_AI;
3248                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3249                 // one channel for each analog output channel
3250                 s->n_chan = boardtype.n_aochan;
3251                 s->maxdata = (1 << 16) - 1;
3252                 s->range_table = &range_unknown; /* XXX */
3253                 s->insn_read=cs5529_ai_insn_read;
3254                 s->insn_config=NULL;
3255                 init_cs5529(dev);
3256         }else
3257         {
3258                 s->type=COMEDI_SUBD_UNUSED;
3259         }
3260
3261         /* Serial */
3262         s=dev->subdevices+9;
3263         s->type=COMEDI_SUBD_SERIAL;
3264         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3265         s->n_chan=1;
3266         s->maxdata=0xff;
3267         s->insn_config = ni_serial_insn_config;
3268         devpriv->serial_interval_ns = 0;
3269         devpriv->serial_hw_mode = 0;
3270
3271         /* RTSI */
3272         s=dev->subdevices + 10;
3273         s->type = COMEDI_SUBD_DIO;
3274         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3275         s->n_chan = 8;
3276         s->maxdata = 1;
3277         s->insn_bits = ni_rtsi_insn_bits;
3278         s->insn_config = ni_rtsi_insn_config;
3279         ni_rtsi_init(dev);
3280
3281         /* ai configuration */
3282         ni_ai_reset(dev,dev->subdevices+0);
3283         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3284                 // BEAM is this needed for PCI-6143 ??
3285                 devpriv->clock_and_fout =
3286                         Slow_Internal_Time_Divide_By_2 |
3287                         Slow_Internal_Timebase |
3288                         Clock_To_Board_Divide_By_2 |
3289                         Clock_To_Board |
3290                         AI_Output_Divide_By_2 |
3291                         AO_Output_Divide_By_2;
3292         }else{
3293                 devpriv->clock_and_fout =
3294                         Slow_Internal_Time_Divide_By_2 |
3295                         Slow_Internal_Timebase |
3296                         Clock_To_Board_Divide_By_2 |
3297                         Clock_To_Board;
3298         }
3299         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3300
3301         /* analog output configuration */
3302         ni_ao_reset(dev,dev->subdevices + 1);
3303
3304         if(dev->irq){
3305                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3306                         (Interrupt_Output_On_3_Pins&0) |
3307                         Interrupt_A_Enable |
3308                         Interrupt_B_Enable |
3309                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3310                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3311                         Interrupt_Control_Register
3312                 );
3313         }
3314
3315         /* DMA setup */
3316         /* tell the STC which dma channels to use for AI and AO */
3317         bits = 1 << ( AI_DMA_CHAN );
3318         bits |= 1 << ( AO_DMA_CHAN + 4 );
3319         ni_writeb( bits, AI_AO_Select);
3320         /* tell the STC which dma channels to use for
3321          * General purpose counters 0 and 1 */
3322         bits = 1 << ( GPC0_DMA_CHAN );
3323         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
3324         ni_writeb( bits, G0_G1_Select);
3325
3326         if(boardtype.reg_type & ni_reg_6xxx_mask)
3327         {
3328                 ni_writeb( 0, Magic_611x );
3329         }else if(boardtype.reg_type == ni_reg_m_series)
3330         {
3331                 int channel;
3332                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3333                 {
3334                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3335                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3336                 }
3337                 ni_writeb(0x0, M_Offset_AO_Calibration);
3338         }
3339
3340         printk("\n");
3341         return 0;
3342 }
3343
3344
3345
3346 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3347 {
3348         comedi_device *dev=(comedi_device *)arg;
3349
3350         if(dir){
3351                 ni_writeb(data,Port_A+2*port);
3352                 return 0;
3353         }else{
3354                 return ni_readb(Port_A+2*port);
3355         }
3356 }
3357
3358 /*
3359         presents the EEPROM as a subdevice
3360 */
3361
3362 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3363         comedi_insn *insn,lsampl_t *data)
3364 {
3365         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3366
3367         return 1;
3368 }
3369
3370 /*
3371         reads bytes out of eeprom
3372 */
3373
3374 static int ni_read_eeprom(comedi_device *dev,int addr)
3375 {
3376         int bit;
3377         int bitstring;
3378
3379         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3380         ni_writeb(0x04,Serial_Command);
3381         for(bit=0x8000;bit;bit>>=1){
3382                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3383                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3384         }
3385         bitstring=0;
3386         for(bit=0x80;bit;bit>>=1){
3387                 ni_writeb(0x04,Serial_Command);
3388                 ni_writeb(0x05,Serial_Command);
3389                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3390         }
3391         ni_writeb(0x00,Serial_Command);
3392
3393         return bitstring;
3394 }
3395
3396 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3397         comedi_insn *insn,lsampl_t *data)
3398 {
3399         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3400
3401         return 1;
3402 }
3403
3404 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3405 {
3406         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3407         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3408         return 3;
3409 }
3410
3411 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3412         comedi_insn *insn, lsampl_t *data)
3413 {
3414         unsigned up_count, down_count;
3415         switch(data[0])
3416         {
3417         case INSN_CONFIG_PWM_OUTPUT:
3418                 switch(data[1])
3419                 {
3420                 case TRIG_ROUND_NEAREST:
3421                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3422                         break;
3423                 case TRIG_ROUND_DOWN:
3424                         up_count = data[2] / devpriv->clock_ns;
3425                         break;
3426                 case TRIG_ROUND_UP:
3427                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3428                         break;
3429                 default:
3430                         return -EINVAL;
3431                         break;
3432                 }
3433                 switch(data[3])
3434                 {
3435                 case TRIG_ROUND_NEAREST:
3436                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3437                         break;
3438                 case TRIG_ROUND_DOWN:
3439                         down_count = data[4] / devpriv->clock_ns;
3440                         break;
3441                 case TRIG_ROUND_UP:
3442                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3443                         break;
3444                 default:
3445                         return -EINVAL;
3446                         break;
3447                 }
3448                 if(up_count * devpriv->clock_ns != data[2] ||
3449                         down_count * devpriv->clock_ns != data[4])
3450                 {
3451                         data[2] = up_count * devpriv->clock_ns;
3452                         data[4] = down_count * devpriv->clock_ns;
3453                         return -EAGAIN;
3454                 }
3455                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3456                 devpriv->pwm_up_count = up_count;
3457                 devpriv->pwm_down_count = down_count;
3458                 return 5;
3459                 break;
3460         case INSN_CONFIG_GET_PWM_OUTPUT:
3461                 return ni_get_pwm_config(dev, data);
3462                 break;
3463         default:
3464                 return -EINVAL;
3465                 break;
3466         }
3467         return 0;
3468 }
3469
3470 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3471         comedi_insn *insn, lsampl_t *data)
3472 {
3473         unsigned up_count, down_count;
3474         switch(data[0])
3475         {
3476         case INSN_CONFIG_PWM_OUTPUT:
3477                 switch(data[1])
3478                 {
3479                 case TRIG_ROUND_NEAREST:
3480                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3481                         break;
3482                 case TRIG_ROUND_DOWN:
3483                         up_count = data[2] / devpriv->clock_ns;
3484                         break;
3485                 case TRIG_ROUND_UP:
3486                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3487                         break;
3488                 default:
3489                         return -EINVAL;
3490                         break;
3491                 }
3492                 switch(data[3])
3493                 {
3494                 case TRIG_ROUND_NEAREST:
3495                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3496                         break;
3497                 case TRIG_ROUND_DOWN:
3498                         down_count = data[4] / devpriv->clock_ns;
3499                         break;
3500                 case TRIG_ROUND_UP:
3501                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3502                         break;
3503                 default:
3504                         return -EINVAL;
3505                         break;
3506                 }
3507                 if(up_count * devpriv->clock_ns != data[2] ||
3508                         down_count * devpriv->clock_ns != data[4])
3509                 {
3510                         data[2] = up_count * devpriv->clock_ns;
3511                         data[4] = down_count * devpriv->clock_ns;
3512                         return -EAGAIN;
3513                 }
3514                 ni_writel(up_count, Calibration_HighTime_6143);
3515                 devpriv->pwm_up_count = up_count;
3516                 ni_writel(down_count, Calibration_LowTime_6143);
3517                 devpriv->pwm_down_count = down_count;
3518                 return 5;
3519                 break;
3520         case INSN_CONFIG_GET_PWM_OUTPUT:
3521                 return ni_get_pwm_config(dev, data);
3522         default:
3523                 return -EINVAL;
3524                 break;
3525         }
3526         return 0;
3527 }
3528
3529 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3530 /*
3531         calibration subdevice
3532 */
3533 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3534         comedi_insn *insn,lsampl_t *data)
3535 {
3536         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3537
3538         return 1;
3539 }
3540
3541 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3542         comedi_insn *insn,lsampl_t *data)
3543 {
3544         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3545
3546         return 1;
3547 }
3548
3549 static int pack_mb88341(int addr,int val,int *bitstring);
3550 static int pack_dac8800(int addr,int val,int *bitstring);
3551 static int pack_dac8043(int addr,int val,int *bitstring);
3552 static int pack_ad8522(int addr,int val,int *bitstring);
3553 static int pack_ad8804(int addr,int val,int *bitstring);
3554 static int pack_ad8842(int addr,int val,int *bitstring);
3555
3556 struct caldac_struct{
3557         int n_chans;
3558         int n_bits;
3559         int (*packbits)(int,int,int *);
3560 };
3561
3562 static struct caldac_struct caldacs[] = {
3563         [mb88341] = { 12, 8, pack_mb88341 },
3564         [dac8800] = { 8, 8, pack_dac8800 },
3565         [dac8043] = { 1, 12, pack_dac8043 },
3566         [ad8522]  = { 2, 12, pack_ad8522 },
3567         [ad8804] = { 12, 8, pack_ad8804 },
3568         [ad8842] = { 8, 8, pack_ad8842 },
3569         [ad8804_debug] = { 16, 8, pack_ad8804 },
3570 };
3571
3572 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3573 {
3574         int i,j;
3575         int n_dacs;
3576         int n_chans=0;
3577         int n_bits;
3578         int diffbits=0;
3579         int type;
3580         int chan;
3581
3582         type = boardtype.caldac[0];
3583         if(type==caldac_none)return;
3584         n_bits=caldacs[type].n_bits;
3585         for(i=0;i<3;i++){
3586                 type = boardtype.caldac[i];
3587                 if(type==caldac_none)break;
3588                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3589                 n_chans+=caldacs[type].n_chans;
3590         }
3591         n_dacs=i;
3592         s->n_chan=n_chans;
3593
3594         if(diffbits){
3595
3596                 if(n_chans>MAX_N_CALDACS){
3597                         printk("BUG! MAX_N_CALDACS too small\n");
3598                 }
3599                 s->maxdata_list=devpriv->caldac_maxdata_list;
3600                 chan=0;
3601                 for(i=0;i<n_dacs;i++){
3602                         type = boardtype.caldac[i];
3603                         for(j=0;j<caldacs[type].n_chans;j++){
3604                                 s->maxdata_list[chan]=
3605                                         (1<<caldacs[type].n_bits)-1;
3606                                 chan++;
3607                         }
3608                 }
3609
3610                 for( chan = 0; chan < s->n_chan; chan++ )
3611                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3612         }else{
3613                 type = boardtype.caldac[0];
3614                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3615
3616                 for( chan = 0; chan < s->n_chan; chan++ )
3617                         ni_write_caldac( dev, i, s->maxdata / 2 );
3618         }
3619 }
3620
3621 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3622 {
3623         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3624         int i;
3625         int type;
3626
3627         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3628         if( devpriv->caldacs[ addr ] == val ) return;
3629         devpriv->caldacs[ addr ] = val;
3630
3631         for(i=0;i<3;i++){
3632                 type = boardtype.caldac[i];
3633                 if(type==caldac_none)break;
3634                 if(addr<caldacs[type].n_chans){
3635                         bits=caldacs[type].packbits(addr,val,&bitstring);
3636                         loadbit=SerDacLd(i);
3637                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3638                         break;
3639                 }
3640                 addr-=caldacs[type].n_chans;
3641         }
3642
3643         for(bit=1<<(bits-1);bit;bit>>=1){
3644                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3645                 comedi_udelay(1);
3646                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3647                 comedi_udelay(1);
3648         }
3649         ni_writeb(loadbit,Serial_Command);
3650         comedi_udelay(1);
3651         ni_writeb(0,Serial_Command);
3652 }
3653
3654
3655
3656 static int pack_mb88341(int addr,int val,int *bitstring)
3657 {
3658         /*
3659            Fujitsu MB 88341
3660            Note that address bits are reversed.  Thanks to
3661            Ingo Keen for noticing this.
3662
3663            Note also that the 88341 expects address values from
3664            1-12, whereas we use channel numbers 0-11.  The NI
3665            docs use 1-12, also, so be careful here.
3666         */
3667         addr++;
3668         *bitstring=((addr&0x1)<<11) |
3669                   ((addr&0x2)<<9)  |
3670                   ((addr&0x4)<<7)  |
3671                   ((addr&0x8)<<5)  |
3672                   (val&0xff);
3673         return 12;
3674 }
3675
3676 static int pack_dac8800(int addr,int val,int *bitstring)
3677 {
3678         *bitstring=((addr&0x7)<<8)|(val&0xff);
3679         return 11;
3680 }
3681
3682 static int pack_dac8043(int addr,int val,int *bitstring)
3683 {
3684         *bitstring=val&0xfff;
3685         return 12;
3686 }
3687
3688 static int pack_ad8522(int addr,int val,int *bitstring)
3689 {
3690         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3691         return 16;
3692 }
3693
3694 static int pack_ad8804(int addr,int val,int *bitstring)
3695 {
3696         *bitstring=((addr&0xf)<<8) | (val&0xff);
3697         return 12;
3698 }
3699
3700 static int pack_ad8842(int addr,int val,int *bitstring)
3701 {
3702         *bitstring=((addr+1)<<8) | (val&0xff);
3703         return 12;
3704 }
3705
3706
3707
3708
3709
3710 /*
3711  *
3712  *  General Purpose Counter/Timer section
3713  *
3714  */
3715
3716 /*
3717  * Low level stuff...Each STC counter has two 24 bit load registers
3718  * (A&B).  Just make it easier to access them.
3719  *
3720  * These are inlined _only_ because they are used once in subsequent
3721  * code.  Otherwise they should not be inlined.
3722  */
3723 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3724 {
3725         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_A_Register(chan));
3726 }
3727
3728 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3729 {
3730         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_B_Register(chan));
3731 }
3732
3733 /*  Load a value into the counter, using register A as the intermediate step.
3734 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3735 *  reset its value.
3736 */
3737 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3738 {
3739         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3740         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3741         GPCT_Load_A(dev,chan,value);
3742         devpriv->stc_writew(dev,  devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3743 }
3744
3745 /*
3746  *      Read the GPCTs current value.
3747  */
3748 static int GPCT_G_Watch(comedi_device *dev, int chan)
3749 {
3750         unsigned int hi1,hi2,lo;
3751
3752         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3753         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3754
3755         devpriv->gpct_command[chan] |= G_Save_Trace;
3756         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
3757
3758         /* This procedure is used because the two registers cannot
3759          * be read atomically. */
3760         do{
3761                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3762                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
3763                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3764         }while(hi1!=hi2);
3765
3766         return (hi1<<16)|lo;
3767 }
3768
3769
3770 static int GPCT_Disarm(comedi_device *dev, int chan)
3771 {
3772         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3773         return 0;
3774 }
3775
3776
3777 static int GPCT_Arm(comedi_device *dev, int chan)
3778 {
3779         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3780         /* If the counter is doing pulse width measurement, then make
3781          sure that the counter did not start counting right away.  This would
3782          indicate that we started acquiring the pulse after it had already
3783          started and our measurement would be inaccurate */
3784         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3785                 int g_status;
3786
3787                 g_status=devpriv->stc_readw(dev, G_Status_Register);
3788
3789                 if(chan == 0){
3790                         //TIM 5/2/01 possible error with very short pulses
3791                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3792                                 //error: we missed the beginning of the pulse
3793                                 return -EINVAL; //there is probably a more accurate error code...
3794                         }
3795                 }else{
3796                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3797                                 //error: we missed the beginning of the pulse
3798                                 return -EINVAL;
3799                         }
3800                 }
3801         }
3802         return 0;
3803 }
3804
3805 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3806 {
3807         //printk("GPCT_Set_Source...");
3808         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3809         switch(source) {
3810                 case GPCT_INT_CLOCK:
3811                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3812                 break;
3813         case GPCT_EXT_PIN:
3814                 if(chan==0)
3815                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3816                 else
3817                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3818                 break;
3819         default:
3820                 return -EINVAL;
3821         }
3822         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3823         //printk("exit GPCT_Set_Source\n");
3824         return 0;
3825 }
3826
3827 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3828 {
3829         //printk("GPCT_Set_Gate...");
3830         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3831         switch(gate) {
3832         case GPCT_NO_GATE:
3833                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3834                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3835                 break;
3836         case GPCT_EXT_PIN:
3837                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3838                 if(chan==0){
3839                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3840                 }else{
3841                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3842                 }
3843                 break;
3844         default:
3845                 return -EINVAL;
3846         }
3847         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3848         devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3849         //printk("exit GPCT_Set_Gate\n");
3850         return 0;
3851 }
3852
3853 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3854 {
3855         //printk("GPCT_Set_Direction...");
3856
3857         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3858         switch (direction) {
3859                 case GPCT_UP:
3860                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3861                         break;
3862                 case GPCT_DOWN:
3863                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3864                         break;
3865                 case GPCT_HWUD:
3866                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3867                         break;
3868                 default:
3869                         rt_printk("Error direction=0x%08x..",direction);
3870                         return -EINVAL;
3871         }
3872         devpriv->stc_writew(dev, devpriv->gpct_command[chan], G_Command_Register(chan));
3873         //TIM 4/23/01 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3874         //printk("exit GPCT_Set_Direction\n");
3875         return 0;
3876 }
3877
3878 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3879 {
3880
3881         //NOTE: possible residual bits from multibit masks can corrupt
3882         //If you config for several measurements between Resets, watch out!
3883
3884         //printk("GPCT_Event_Counting...");
3885
3886         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3887
3888         // Gating_Mode = 1
3889         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3890         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3891
3892         // Trigger_Mode_For_Edge_Gate = 1
3893         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3894         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3895
3896         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3897         //printk("exit GPCT_Event_Counting\n");
3898 }
3899
3900 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3901 {
3902         //printk("GPCT_Period_Meas...");
3903
3904         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3905
3906
3907         //NOTE: possible residual bits from multibit masks can corrupt
3908         //If you config for several measurements between Resets, watch out!
3909         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3910         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3911
3912         // Output_Mode = 3
3913         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3914         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3915
3916
3917         //Gating Mode=2
3918         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3919         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
3920
3921         // Trigger_Mode_For_Edge_Gate=0
3922         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3923         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
3924
3925         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3926         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3927         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3928         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3929
3930         // Stop_Mode = 2
3931         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3932         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3933
3934         // Counting_Once = 2
3935         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3936         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3937
3938         // Up_Down = 1
3939         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3940         devpriv->gpct_command[chan] |= G_Up_Down(1);
3941
3942         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3943         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3944         //printk("exit GPCT_Period_Meas\n");
3945 }
3946
3947 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
3948 {
3949         //printk("GPCT_Pulse_Width_Meas...");
3950
3951         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
3952
3953         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3954         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3955
3956         // Output_Mode = 3
3957         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3958         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3959
3960         //Gating Mode=1
3961         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3962         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
3963
3964         // Trigger_Mode_For_Edge_Gate=2
3965         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3966         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
3967
3968
3969         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
3970         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
3971
3972         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3973         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3974
3975         // Stop_Mode = 0
3976         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3977         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3978
3979         // Counting_Once = 2
3980         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3981         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3982
3983         // Up_Down = 1
3984         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3985         devpriv->gpct_command[chan] |= G_Up_Down(1);
3986
3987         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3988         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3989
3990         //printk("exit GPCT_Pulse_Width_Meas\n");
3991 }
3992
3993 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
3994 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
3995 be modified to send a pulse in response to a trigger event at its gate.*/
3996 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
3997 {
3998         //printk("GPCT_Gen_Cont...");
3999
4000         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
4001
4002         // Set length of the pulse
4003         GPCT_Load_B(dev,chan, length-1);
4004
4005         //Load next time using B, This is reset by GPCT_Load_Using_A()
4006         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4007
4008         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4009         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4010
4011         // Output_Mode = 3
4012         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4013         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4014
4015         //Gating Mode=0 for untriggered single pulse
4016         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4017         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
4018
4019         // Trigger_Mode_For_Edge_Gate=0
4020         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4021         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4022
4023
4024         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4025         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4026         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
4027         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4028
4029         // Stop_Mode = 2
4030         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4031         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
4032
4033         // Counting_Once = 2
4034         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4035         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
4036
4037         // Up_Down = 1
4038         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4039         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
4040
4041         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4042         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4043
4044         //printk("exit GPCT_Gen_Cont\n");
4045 }
4046
4047 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
4048 {
4049         //printk("GPCT_Gen_Cont...");
4050
4051         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
4052
4053         // Set length of the pulse
4054         GPCT_Load_B(dev,chan, length-1);
4055
4056         //Load next time using B, This is reset by GPCT_Load_Using_A()
4057         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4058
4059         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4060         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4061
4062         // Output_Mode = 3
4063         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4064         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4065
4066         //Gating Mode=0 for untriggered single pulse
4067         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4068         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
4069
4070         // Trigger_Mode_For_Edge_Gate=0
4071         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4072         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4073
4074
4075         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4076         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4077         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
4078         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4079
4080         // Stop_Mode = 2
4081         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4082         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
4083
4084         // Counting_Once = 2
4085         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4086         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
4087
4088         // Up_Down = 1
4089         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4090         devpriv->gpct_command[chan] |= G_Up_Down(0);
4091
4092         //TIM 4/26/01
4093         //This seems pretty unsafe since I don't think it is cleared anywhere.
4094         //I don't think this is working
4095         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
4096         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
4097
4098
4099         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4100         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4101
4102         //printk("exit GPCT_Gen_Cont\n");
4103 }
4104
4105 static void GPCT_Reset(comedi_device *dev, int chan)
4106 {
4107         int temp_ack_reg=0;
4108
4109         //printk("GPCT_Reset...");
4110         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4111
4112         switch (chan) {
4113                 case 0:
4114                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4115                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4116                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4117                         temp_ack_reg |= G0_Gate_Error_Confirm;
4118                         temp_ack_reg |= G0_TC_Error_Confirm;
4119                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4120                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4121                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4122
4123                         //problem...this interferes with the other ctr...
4124                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4125                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4126                         break;
4127                 case 1:
4128                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4129                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4130                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4131                         temp_ack_reg |= G1_Gate_Error_Confirm;
4132                         temp_ack_reg |= G1_TC_Error_Confirm;
4133                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4134                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4135                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4136
4137                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4138                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4139                         break;
4140         };
4141
4142         devpriv->gpct_mode[chan] = 0;
4143         devpriv->gpct_input_select[chan] = 0;
4144         devpriv->gpct_command[chan] = 0;
4145
4146         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4147
4148         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4149         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4150         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4151
4152         //printk("exit GPCT_Reset\n");
4153 }
4154
4155 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
4156         comedi_insn *insn,lsampl_t *data)
4157 {
4158         int retval=0;
4159         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4160         switch(data[0]){
4161         case GPCT_RESET:
4162                 if(insn->n!=1)return -EINVAL;
4163                 GPCT_Reset(dev,insn->chanspec);
4164                 break;
4165         case GPCT_SET_SOURCE:
4166                 if(insn->n!=2)return -EINVAL;
4167                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
4168                 break;
4169         case GPCT_SET_GATE:
4170                 if(insn->n!=2)return -EINVAL;
4171                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
4172                 break;
4173         case GPCT_SET_DIRECTION:
4174                 if(insn->n!=2) return -EINVAL;
4175                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
4176                 break;
4177         case GPCT_GET_INT_CLK_FRQ:
4178                 if(insn->n!=2) return -EINVAL;
4179                 //There are actually 2 internal clocks on the STC, we always
4180                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
4181                 //NOTE: This is not the final interface, ideally the user
4182                 //will never need to know the int. clk. freq.
4183                 data[1]=50;//50ns = 20MHz = internal timebase of STC
4184                 break;
4185         case GPCT_SET_OPERATION:
4186                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
4187                 switch(data[1]){
4188                         case GPCT_SIMPLE_EVENT:
4189                                 GPCT_Event_Counting(dev,insn->chanspec);
4190                                 break;
4191                         case GPCT_SINGLE_PERIOD:
4192                                 GPCT_Period_Meas(dev,insn->chanspec);
4193                                 break;
4194                         case GPCT_SINGLE_PW:
4195                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
4196                                 break;
4197                         case GPCT_SINGLE_PULSE_OUT:
4198                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
4199                                 break;
4200                         case GPCT_CONT_PULSE_OUT:
4201                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
4202                                 break;
4203                         default:
4204                                 rt_printk("unsupported GPCT operation!\n");
4205                                 return -EINVAL;
4206                 }
4207                 break;
4208         case GPCT_ARM:
4209                 if(insn->n!=1)return -EINVAL;
4210                 retval=GPCT_Arm(dev,insn->chanspec);
4211                 break;
4212         case GPCT_DISARM:
4213                 if(insn->n!=1)return -EINVAL;
4214                 retval=GPCT_Disarm(dev,insn->chanspec);
4215                 break;
4216         default:
4217                 return -EINVAL;
4218         }
4219
4220         //catch any errors from return values
4221         if(retval==0){
4222                 return insn->n;
4223         }else{
4224                 if(data[0]!=GPCT_ARM){
4225                         rt_printk("error: retval was %d\n",retval);
4226                         rt_printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4227                 }
4228
4229                 return retval;
4230         }
4231 }
4232
4233 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
4234         comedi_insn *insn,lsampl_t *data) {
4235
4236         int chan=insn->chanspec;
4237         int cur_op = devpriv->gpct_cur_operation[chan];
4238
4239         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
4240         if(insn->n!=1)return -EINVAL;
4241
4242         data[0] = GPCT_G_Watch(dev,insn->chanspec);
4243
4244         /* for certain modes (period and pulse width measurment), the value
4245         in the counter is not valid until the counter stops.  If the value is
4246         invalid, return a 0 */
4247         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
4248                 /* is the counter still running? */
4249                 if(devpriv->stc_readw(dev, G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
4250                         data[0]=0;
4251         }
4252         return 1;
4253 }
4254
4255 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
4256         comedi_insn *insn,lsampl_t *data) {
4257
4258         //printk("in ni_gpct_insn_write");
4259         if(insn->n!=1)return -EINVAL;
4260         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
4261         return 1;
4262 }
4263
4264
4265 /*
4266  *
4267  *  Programmable Function Inputs
4268  *
4269  */
4270
4271 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4272 {
4273         if((source & 0x1f) != source) return -EINVAL;
4274         const unsigned pfi_reg_index = 1 + chan / 3;
4275         const unsigned array_offset = pfi_reg_index - 1;
4276         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4277         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4278         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4279         return 2;
4280 }
4281
4282 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4283 {
4284         // pre-m-series boards have fixed signals on pfi pins
4285         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4286         return 2;
4287 }
4288
4289 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4290 {
4291         if(boardtype.reg_type == ni_reg_m_series)
4292                 return ni_m_series_set_pfi_routing(dev, chan, source);
4293         else
4294                 return ni_old_set_pfi_routing(dev, chan, source);
4295 }
4296
4297 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4298 {
4299         const unsigned array_offset = chan / 3;
4300         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4301 }
4302
4303 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4304 {
4305         // pre-m-series boards have fixed signals on pfi pins
4306         switch(chan)
4307         {
4308         case 0:
4309                 return NI_PFI_OUTPUT_AI_START1;
4310                 break;
4311         case 1:
4312                 return NI_PFI_OUTPUT_AI_START2;
4313                 break;
4314         case 2:
4315                 return NI_PFI_OUTPUT_AI_CONVERT;
4316                 break;
4317         case 3:
4318                 return NI_PFI_OUTPUT_G_SRC1;
4319                 break;
4320         case 4:
4321                 return NI_PFI_OUTPUT_G_GATE1;
4322                 break;
4323         case 5:
4324                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4325                 break;
4326         case 6:
4327                 return NI_PFI_OUTPUT_AO_START1;
4328                 break;
4329         case 7:
4330                 return NI_PFI_OUTPUT_AI_START_PULSE;
4331                 break;
4332         case 8:
4333                 return NI_PFI_OUTPUT_G_SRC0;
4334                 break;
4335         case 9:
4336                 return NI_PFI_OUTPUT_G_GATE0;
4337                 break;
4338         default:
4339                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4340                 break;
4341         }
4342         return 0;
4343 }
4344
4345 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4346 {
4347         if(boardtype.reg_type == ni_reg_m_series)
4348                 return ni_m_series_get_pfi_routing(dev, chan);
4349         else
4350                 return ni_old_get_pfi_routing(dev, chan);
4351 }
4352
4353 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4354         comedi_insn *insn,lsampl_t *data)
4355 {
4356         if(boardtype.reg_type != ni_reg_m_series)
4357         {
4358                 data[1] = 0;
4359                 return 2;
4360         }
4361         if(data[0])
4362         {
4363                 s->state &= ~data[0];
4364                 s->state |= (data[0] & data[1]);
4365                 ni_writew(s->state, M_Offset_PFI_DO);
4366         }
4367         data[1] = ni_readw(M_Offset_PFI_DI);
4368         return 2;
4369 }
4370
4371 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4372         comedi_insn *insn,lsampl_t *data)
4373 {
4374         unsigned int chan;
4375
4376         if(insn->n < 1)return -EINVAL;
4377
4378         chan = CR_CHAN(insn->chanspec);
4379
4380         switch(data[0]){
4381         case COMEDI_OUTPUT:
4382                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4383                 break;
4384         case COMEDI_INPUT:
4385                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4386                 break;
4387         case INSN_CONFIG_DIO_QUERY:
4388                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4389                 return insn->n;
4390                 break;
4391         case INSN_CONFIG_SET_ROUTING:
4392                 return ni_set_pfi_routing(dev, chan, data[1]);
4393                 break;
4394         case INSN_CONFIG_GET_ROUTING:
4395                 data[1] = ni_get_pfi_routing(dev, chan);
4396                 return 2;
4397                 break;
4398         default:
4399                 return -EINVAL;
4400         }
4401
4402         return 1;
4403 }
4404
4405 /*
4406  *
4407  *  NI RTSI Bus Functions
4408  *
4409  */
4410 static void ni_rtsi_init(comedi_device *dev)
4411 {
4412         // Initialises the RTSI bus signal switch to a default state
4413
4414         // Set clock mode to internal
4415         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4416         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4417         {
4418                 rt_printk("ni_set_master_clock failed, bug?");
4419         }
4420         // default internal lines routing to RTSI bus lines
4421         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4422                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4423                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4424                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4425         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4426                 RTSI_Trig_A_Output_Register);
4427         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4428                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4429                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4430         if(boardtype.reg_type == ni_reg_m_series)
4431                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4432         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4433                 RTSI_Trig_B_Output_Register);
4434
4435         // Sets the source and direction of the 4 on board lines
4436 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4437 }
4438
4439 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4440         comedi_insn *insn,lsampl_t *data)
4441 {
4442         if(insn->n != 2) return -EINVAL;
4443
4444         data[1] = 0;
4445
4446         return 2;
4447 }
4448
4449 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4450  * given an arbitrary frequency input clock */
4451 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4452         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4453 {
4454         unsigned div;
4455         unsigned best_div = 1;
4456         static const unsigned max_div = 0x10;
4457         unsigned mult;
4458         unsigned best_mult = 1;
4459         static const unsigned max_mult = 0x100;
4460         static const unsigned pico_per_nano = 1000;
4461
4462         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4463         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4464          * 20 MHz for most timing clocks */
4465         static const unsigned target_picosec = 12500;
4466         int best_period_picosec = 0;
4467         for(div = 1; div <= max_div; ++div)
4468         {
4469                 for(mult = 1; mult <= max_mult; ++mult)
4470                 {
4471                         unsigned new_period_ps = (reference_picosec * div) / mult;
4472                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4473                         {
4474                                 best_period_picosec = new_period_ps;
4475                                 best_div = div;
4476                                 best_mult = mult;
4477                         }
4478                 }
4479         }
4480         if(best_period_picosec == 0)
4481         {
4482                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4483                 return -EIO;
4484         }
4485         *freq_divider = best_div;
4486         *freq_multiplier = best_mult;
4487         static const unsigned fudge_factor_80_to_20Mhz = 4;
4488         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4489         return 0;
4490 }
4491
4492 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4493 {
4494         if(boardtype.reg_type == ni_reg_m_series) return 8;
4495         else return 7;
4496 }
4497
4498 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4499 {
4500         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4501         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4502         static const unsigned min_period_ns = 50;
4503         static const unsigned max_period_ns = 1000;
4504         if(period_ns < min_period_ns || period_ns > max_period_ns)
4505         {
4506                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4507                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4508                 return -EINVAL;
4509         }
4510         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4511         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4512         unsigned pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4513         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit;
4514         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4515         int retval;
4516         unsigned freq_divider;
4517         unsigned freq_multiplier;
4518         switch(source)
4519         {
4520         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4521                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4522                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4523                         &freq_multiplier, &devpriv->clock_ns);
4524                 if(retval < 0) return retval;
4525                 break;
4526         case NI_MIO_PLL_PXI10_CLOCK:
4527                 /* pxi clock is 10MHz */
4528                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4529                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4530                         &freq_multiplier, &devpriv->clock_ns);
4531                 if(retval < 0) return retval;
4532                 break;
4533         default:
4534                 {
4535                         unsigned rtsi_channel;
4536                         static const unsigned max_rtsi_channel = 7;
4537                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4538                         {
4539                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4540                                 {
4541                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4542                                         break;
4543                                 }
4544                         }
4545                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4546                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4547                                 &freq_multiplier, &devpriv->clock_ns);
4548                         if(retval < 0) return retval;
4549                 }
4550                 break;
4551         }
4552         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4553         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4554 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4555 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4556         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4557         devpriv->clock_source = source;
4558         unsigned i;
4559         static const unsigned timeout = 1000;
4560         /* it seems to typically take a few hundred microseconds for PLL to lock */
4561         for(i = 0; i < timeout; ++i)
4562         {
4563                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4564                 {
4565                         break;
4566                 }
4567                 udelay(1);
4568         }
4569         if(i == timeout)
4570         {
4571                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4572                         __FUNCTION__, source, period_ns);
4573                 return -ETIMEDOUT;
4574         }
4575         return 3;
4576 }
4577
4578 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4579 {
4580         if(source == NI_MIO_INTERNAL_CLOCK)
4581         {
4582                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4583                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4584                 devpriv->clock_ns = 50;
4585                 if(boardtype.reg_type == ni_reg_m_series)
4586                 {
4587                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4588                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4589                         ni_writew(0, M_Offset_PLL_Control);
4590                 }
4591                 devpriv->clock_source = source;
4592         }else
4593         {
4594                 if(boardtype.reg_type == ni_reg_m_series)
4595                 {
4596                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4597                 }else
4598                 {
4599                         if(source == NI_MIO_RTSI_CLOCK)
4600                         {
4601                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4602                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4603                                 if(devpriv->clock_ns == 0)
4604                                 {
4605                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4606                                                 __FUNCTION__);
4607                                         return -EINVAL;
4608                                 }else
4609                                 {
4610                                         devpriv->clock_ns = period_ns;
4611                                 }
4612                                 devpriv->clock_source = source;
4613                         }else
4614                                 return -EINVAL;
4615                 }
4616         }
4617         return 3;
4618 }
4619
4620 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4621 {
4622         if(chan >= num_configurable_rtsi_channels(dev))
4623         {
4624                 if(chan == old_RTSI_clock_channel)
4625                 {
4626                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4627                         else
4628                         {
4629                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4630                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4631                                 return 0;
4632                         }
4633                 }
4634                 return 0;
4635         }
4636         switch(source)
4637         {
4638         case NI_RTSI_OUTPUT_ADR_START1:
4639         case NI_RTSI_OUTPUT_ADR_START2:
4640         case NI_RTSI_OUTPUT_SCLKG:
4641         case NI_RTSI_OUTPUT_DACUPDN:
4642         case NI_RTSI_OUTPUT_DA_START1:
4643         case NI_RTSI_OUTPUT_G_SRC0:
4644         case NI_RTSI_OUTPUT_G_GATE0:
4645         case NI_RTSI_OUTPUT_RGOUT0:
4646         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4647                 return 1;
4648                 break;
4649         case NI_RTSI_OUTPUT_RTSI_OSC:
4650                 if(boardtype.reg_type == ni_reg_m_series)
4651                         return 1;
4652                 else return 0;
4653                 break;
4654         default:
4655                 return 0;
4656                 break;
4657         }
4658 }
4659
4660 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4661 {
4662         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4663         if(chan < 4)
4664         {
4665                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4666                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4667                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4668                         RTSI_Trig_A_Output_Register);
4669         }else if(chan < 8)
4670         {
4671                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4672                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4673                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4674                         RTSI_Trig_B_Output_Register);
4675         }
4676         return 2;
4677 }
4678
4679 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4680 {
4681         if(chan < 4)
4682         {
4683                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4684         }else if(chan < num_configurable_rtsi_channels(dev))
4685         {
4686                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4687         }else
4688         {
4689                 if(chan == old_RTSI_clock_channel)
4690                         return NI_RTSI_OUTPUT_RTSI_OSC;
4691                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4692                 return 0;
4693         }
4694 }
4695
4696 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4697         comedi_insn *insn,lsampl_t *data)
4698 {
4699         unsigned int chan = CR_CHAN(insn->chanspec);
4700         switch(data[0]){
4701         case INSN_CONFIG_DIO_OUTPUT:
4702                 if(chan < num_configurable_rtsi_channels(dev))
4703                 {
4704                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4705                 }else if(chan == old_RTSI_clock_channel)
4706                 {
4707                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4708                 }
4709                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4710                 break;
4711         case INSN_CONFIG_DIO_INPUT:
4712                 if(chan < num_configurable_rtsi_channels(dev))
4713                 {
4714                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4715                 }else if(chan == old_RTSI_clock_channel)
4716                 {
4717                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4718                 }
4719                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4720                 break;
4721         case INSN_CONFIG_DIO_QUERY:
4722                 if(chan < num_configurable_rtsi_channels(dev))
4723                 {
4724                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series)) ?
4725                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4726                 }else if(chan == old_RTSI_clock_channel)
4727                 {
4728                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4729                 }
4730                 return 2;
4731                 break;
4732         case INSN_CONFIG_SET_CLOCK_SRC:
4733                 return ni_set_master_clock(dev, data[1], data[2]);
4734                 break;
4735         case INSN_CONFIG_GET_CLOCK_SRC:
4736                 data[1] = devpriv->clock_source;
4737                 data[2] = devpriv->clock_ns;
4738                 return 3;
4739                 break;
4740         case INSN_CONFIG_SET_ROUTING:
4741                 return ni_set_rtsi_routing(dev, chan, data[1]);
4742                 break;
4743         case INSN_CONFIG_GET_ROUTING:
4744                 data[1] = ni_get_rtsi_routing(dev, chan);
4745                 return 2;
4746                 break;
4747         default:
4748                 return -EINVAL;
4749                 break;
4750         }
4751         return 1;
4752 }
4753
4754 static int cs5529_wait_for_idle(comedi_device *dev)
4755 {
4756         unsigned short status;
4757         const int timeout = HZ;
4758         int i;
4759
4760         for(i = 0; i < timeout; i++)
4761         {
4762                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4763                 if((status & CSS_ADC_BUSY) == 0)
4764                 {
4765                         break;
4766                 }
4767                 set_current_state(TASK_INTERRUPTIBLE);
4768                 if(schedule_timeout(1))
4769                 {
4770                         return -EIO;
4771                 }
4772         }
4773 //printk("looped %i times waiting for idle\n", i);
4774         if(i == timeout)
4775         {
4776                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4777                 return -ETIME;
4778         }
4779         return 0;
4780 }
4781
4782 static void cs5529_command(comedi_device *dev, unsigned short value)
4783 {
4784         static const int timeout = 100;
4785         int i;
4786
4787         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4788         /* give time for command to start being serially clocked into cs5529.
4789          * this insures that the CSS_ADC_BUSY bit will get properly
4790          * set before we exit this function.
4791         */
4792         for(i = 0; i < timeout; i++)
4793         {
4794                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4795                         break;
4796                 comedi_udelay(1);
4797         }
4798 //printk("looped %i times writing command to cs5529\n", i);
4799         if(i == timeout)
4800         {
4801                 comedi_error(dev, "possible problem - never saw adc go busy?");
4802         }
4803 }
4804
4805 /* write to cs5529 register */
4806 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4807 {
4808         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4809         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4810         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4811         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4812         if(cs5529_wait_for_idle(dev))
4813                 comedi_error(dev, "time or signal in cs5529_config_write()");
4814 }
4815
4816 /* read from cs5529 register */
4817 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4818 {
4819         unsigned int value;
4820
4821         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4822         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4823         if(cs5529_wait_for_idle(dev))
4824                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4825         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4826         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4827         return value;
4828 }
4829
4830 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4831 {
4832         int retval;
4833         unsigned short status;
4834
4835         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4836         retval = cs5529_wait_for_idle(dev);
4837         if(retval)
4838         {
4839                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4840                 return -ETIME;
4841         }
4842         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4843         if(status & CSS_OSC_DETECT)
4844         {
4845                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4846                 return -EIO;
4847         }
4848         if(status & CSS_OVERRANGE)
4849         {
4850                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4851         }
4852         if(data)
4853         {
4854                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4855                 /* cs5529 returns 16 bit signed data in bipolar mode */
4856                 *data ^= (1 << 15);
4857         }
4858         return 0;
4859 }
4860
4861 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4862 {
4863         int n, retval;
4864         unsigned short sample;
4865         unsigned int channel_select;
4866         const unsigned int INTERNAL_REF = 0x1000;
4867
4868         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4869          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4870          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4871         if(insn->chanspec & CR_ALT_SOURCE)
4872                 channel_select = INTERNAL_REF;
4873         else
4874                 channel_select = CR_CHAN(insn->chanspec);
4875         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4876
4877         for(n = 0; n < insn->n; n++)
4878         {
4879                 retval = cs5529_do_conversion(dev, &sample);
4880                 if(retval < 0) return retval;
4881                 data[n] = sample;
4882         }
4883         return insn->n;
4884 }
4885
4886 static int init_cs5529(comedi_device *dev)
4887 {
4888         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4889
4890 #if 1
4891         /* do self-calibration */
4892         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4893         /* need to force a conversion for calibration to run */
4894         cs5529_do_conversion(dev, NULL);
4895 #else
4896         /* force gain calibration to 1 */
4897         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4898         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4899         if(cs5529_wait_for_idle(dev))
4900                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4901 #endif
4902         if(0)
4903         {
4904                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4905                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4906                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4907         }
4908         return 0;
4909 }
4910
4911