comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55          - many printk's need to be changed to rt_printk()
  56 */
  57
  58 //#define DEBUG_INTERRUPT
  59 //#define DEBUG_STATUS_A
  60 //#define DEBUG_STATUS_B
  61
  62 #include "8255.h"
  63 #include "mite.h"
  64 #include "comedi_fc.h"
  65
  66 #ifndef MDPRINTK
  67 #define MDPRINTK(format,args...)
  68 #endif
  69
  70 /* A timeout count */
  71
  72 #define NI_TIMEOUT 1000
  73
  74 /* Note: this table must match the ai_gain_* definitions */
  75 static short ni_gainlkup[][16]={
  76         /* ai_gain_16 */
  77         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  78                 0x106, 0x107 },
  79         /* ai_gain_8 */
  80         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  81         /* ai_gain_14 */
  82         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  83                 0x107 },
  84         /* ai_gain_4 */
  85         { 0, 1, 4, 7 },
  86         /* ai_gain_611x */
  87         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 }
  88 };
  89
  90 static comedi_lrange range_ni_E_ai={    16, {
  91         RANGE( -10,     10      ),
  92         RANGE( -5,      5       ),
  93         RANGE( -2.5,    2.5     ),
  94         RANGE( -1,      1       ),
  95         RANGE( -0.5,    0.5     ),
  96         RANGE( -0.25,   0.25    ),
  97         RANGE( -0.1,    0.1     ),
  98         RANGE( -0.05,   0.05    ),
  99         RANGE( 0,       20      ),
 100         RANGE( 0,       10      ),
 101         RANGE( 0,       5       ),
 102         RANGE( 0,       2       ),
 103         RANGE( 0,       1       ),
 104         RANGE( 0,       0.5     ),
 105         RANGE( 0,       0.2     ),
 106         RANGE( 0,       0.1     ),
 107 }};
 108 static comedi_lrange range_ni_E_ai_limited={    8, {
 109         RANGE( -10,     10      ),
 110         RANGE( -5,      5       ),
 111         RANGE( -1,      1       ),
 112         RANGE( -0.1,    0.1     ),
 113         RANGE( 0,       10      ),
 114         RANGE( 0,       5       ),
 115         RANGE( 0,       1       ),
 116         RANGE( 0,       0.1     ),
 117 }};
 118 static comedi_lrange range_ni_E_ai_limited14={  14, {
 119         RANGE( -10,     10      ),
 120         RANGE( -5,      5       ),
 121         RANGE( -2,      2       ),
 122         RANGE( -1,      1       ),
 123         RANGE( -0.5,    0.5     ),
 124         RANGE( -0.2,    0.2     ),
 125         RANGE( -0.1,    0.1     ),
 126         RANGE( 0,       10      ),
 127         RANGE( 0,       5       ),
 128         RANGE( 0,       2       ),
 129         RANGE( 0,       1       ),
 130         RANGE( 0,       0.5     ),
 131         RANGE( 0,       0.2     ),
 132         RANGE( 0,       0.1     ),
 133 }};
 134 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 135         RANGE( -10,     10      ),
 136         RANGE( -5,      5       ),
 137         RANGE( -0.5,    0.5     ),
 138         RANGE( -0.05,   0.05    ),
 139 }};
 140 static comedi_lrange range_ni_E_ai_611x={ 8, {
 141         RANGE( -50,     50      ),
 142         RANGE( -20,     20      ),
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -2,      2       ),
 146         RANGE( -1,      1       ),
 147         RANGE( -0.5,    0.5     ),
 148         RANGE( -0.2,    0.2     ),
 149 }};
 150 static comedi_lrange range_ni_E_ao_ext = { 4, {
 151         RANGE( -10,     10      ),
 152         RANGE( 0,       10      ),
 153         RANGE_ext( -1,  1       ),
 154         RANGE_ext( 0,   1       ),
 155 }};
 156
 157 static comedi_lrange *ni_range_lkup[]={
 158         &range_ni_E_ai,
 159         &range_ni_E_ai_limited,
 160         &range_ni_E_ai_limited14,
 161         &range_ni_E_ai_bipolar4,
 162         &range_ni_E_ai_611x,
 163 };
 164
 165
 166
 167 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 168         comedi_insn *insn,lsampl_t *data);
 169 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 170         comedi_insn *insn,lsampl_t *data);
 171
 172 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 173         comedi_insn *insn,lsampl_t *data);
 174 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 175         unsigned char data_out, unsigned char *data_in);
 176 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 177         unsigned char data_out, unsigned char *data_in);
 178
 179 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 180         comedi_insn *insn,lsampl_t *data);
 181 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 182         comedi_insn *insn,lsampl_t *data);
 183
 184 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 185         comedi_insn *insn,lsampl_t *data);
 186
 187 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 188         comedi_insn *insn,lsampl_t *data);
 189 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 190         comedi_insn *insn,lsampl_t *data);
 191
 192 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 193 static int ni_read_eeprom(comedi_device *dev,int addr);
 194
 195 #ifdef DEBUG_STATUS_A
 196 static void ni_mio_print_status_a(int status);
 197 #else
 198 #define ni_mio_print_status_a(a)
 199 #endif
 200 #ifdef DEBUG_STATUS_B
 201 static void ni_mio_print_status_b(int status);
 202 #else
 203 #define ni_mio_print_status_b(a)
 204 #endif
 205
 206 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 207 #ifndef PCIDMA
 208 static void ni_handle_fifo_half_full(comedi_device *dev);
 209 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 210 #endif
 211 static void ni_handle_fifo_dregs(comedi_device *dev);
 212 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 213         unsigned int trignum);
 214 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 215         unsigned int *list);
 216
 217 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 218         unsigned int trignum);
 219
 220 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 221
 222 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 223
 224 static int ni_ns_to_timer(int *nanosec,int round_mode);
 225
 226
 227 /*GPCT function def's*/
 228 static int GPCT_G_Watch(comedi_device *dev, int chan);
 229
 230 static void GPCT_Reset(comedi_device *dev, int chan);
 231 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 232 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 233 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 234 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 235 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 236 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 237 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 238 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 239
 240 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 241         comedi_insn *insn,lsampl_t *data);
 242 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 243         comedi_insn *insn,lsampl_t *data);
 244 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 245         comedi_insn *insn,lsampl_t *data);
 246
 247 static int init_cs5529(comedi_device *dev);
 248 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 249 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 250 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 251 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 252
 253 enum aimodes
 254 {
 255         AIMODE_NONE = 0,
 256         AIMODE_HALF_FULL = 1,
 257         AIMODE_SCAN = 2,
 258         AIMODE_SAMPLE = 3,
 259 };
 260
 261 #define SERIAL_DISABLED         0
 262 #define SERIAL_600NS            600
 263 #define SERIAL_1_2US            1200
 264 #define SERIAL_10US                     10000
 265
 266 static const int num_adc_stages_611x = 3;
 267
 268 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 269         unsigned int m_status);
 270 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 271         unsigned int m_status);
 272 static void get_last_sample_611x( comedi_device *dev );
 273 #ifdef PCIDMA
 274 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 275 static int ni_ai_drain_dma(comedi_device *dev );
 276 #endif
 277
 278 #define win_out2(data,addr) do{ \
 279         win_out((data)>>16, (addr)); \
 280         win_out((data)&0xffff, (addr)+1); \
 281 }while(0)
 282
 283
 284 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 285 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 286 {
 287         unsigned long flags;
 288
 289         comedi_spin_lock_irqsave(&dev->spinlock,flags);
 290         ni_writew(addr,AO_Window_Address_611x);
 291         ni_writew(data,AO_Window_Data_611x);
 292         comedi_spin_unlock_irqrestore(&dev->spinlock,flags);
 293 }
 294
 295 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 296 {
 297         unsigned long flags;
 298
 299         comedi_spin_lock_irqsave(&dev->spinlock,flags);
 300         ni_writew(addr,AO_Window_Address_611x);
 301         ni_writel(data,AO_Window_Data_611x);
 302         comedi_spin_unlock_irqrestore(&dev->spinlock,flags);
 303 }
 304
 305 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 306 {
 307         unsigned long flags;
 308         unsigned short data;
 309
 310         comedi_spin_lock_irqsave(&dev->spinlock,flags);
 311         ni_writew(addr, AO_Window_Address_611x);
 312         data = ni_readw(AO_Window_Data_611x);
 313         comedi_spin_unlock_irqrestore(&dev->spinlock,flags);
 314         return data;
 315 }
 316
 317 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 318 * share registers (such as Interrupt_A_Register) without interfering with
 319 * each other.
 320 *
 321 * NOTE: the switch/case statements are optimized out for a constant argument
 322 * so this is actually quite fast---  If you must wrap another function around this
 323 * make it inline to avoid a large speed penalty.
 324 *
 325 * value should only be 1 or 0.
 326 */
 327 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 328 {
 329         unsigned long flags;
 330
 331         comedi_spin_lock_irqsave( &dev->spinlock, flags );
 332         switch (reg){
 333                 case Interrupt_A_Enable_Register:
 334                         if(value)
 335                                 devpriv->int_a_enable_reg |= bits;
 336                         else
 337                                 devpriv->int_a_enable_reg &= ~bits;
 338                         comedi_spin_unlock_irqrestore( &dev->spinlock, flags );
 339                         win_out(devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 340                         break;
 341                 case Interrupt_B_Enable_Register:
 342                         if(value)
 343                                 devpriv->int_b_enable_reg |= bits;
 344                         else
 345                                 devpriv->int_b_enable_reg &= ~bits;
 346                         comedi_spin_unlock_irqrestore( &dev->spinlock, flags );
 347                         win_out(devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 348                         break;
 349                 case IO_Bidirection_Pin_Register:
 350                         if(value)
 351                                 devpriv->io_bidirection_pin_reg |= bits;
 352                         else
 353                                 devpriv->io_bidirection_pin_reg &= ~bits;
 354                         comedi_spin_unlock_irqrestore( &dev->spinlock, flags );
 355                         win_out(devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 356                         break;
 357                 default:
 358                         printk("Warning ni_set_bits() called with invalid arguments\n");
 359                         printk("reg is %d\n",reg);
 360                         comedi_spin_unlock_irqrestore( &dev->spinlock, flags );
 361                         break;
 362         }
 363 }
 364
 365
 366 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 367 {
 368         comedi_device *dev=d;
 369         unsigned short a_status;
 370         unsigned short b_status;
 371         unsigned int m0_status;
 372         unsigned int m1_status;
 373 #ifdef PCIDMA
 374         struct mite_struct *mite = devpriv->mite;
 375 #endif
 376
 377         a_status=win_in(AI_Status_1_Register);
 378         b_status=win_in(AO_Status_1_Register);
 379 #ifdef PCIDMA
 380         m0_status=readl(mite->mite_io_addr+MITE_CHSR+CHAN_OFFSET(AI_DMA_CHAN));
 381         m1_status=readl(mite->mite_io_addr+MITE_CHSR+CHAN_OFFSET(AO_DMA_CHAN));
 382 #else
 383         m0_status = 0;
 384         m1_status = 0;
 385 #endif
 386
 387         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 388                 handle_a_interrupt(dev, a_status, m0_status);
 389         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 390                 handle_b_interrupt(dev, b_status, m1_status);
 391         return IRQ_HANDLED;
 392 }
 393
 394 #ifdef PCIDMA
 395 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 396 {
 397         int count;
 398         comedi_subdevice *s = dev->subdevices + 0;
 399         comedi_async *async = s->async;
 400         unsigned int nbytes, old_alloc_count;
 401         unsigned int bytes_per_scan = 2 * async->cmd.chanlist_len;
 402
 403         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR + CHAN_OFFSET(AI_DMA_CHAN));
 404
 405         old_alloc_count = async->buf_write_alloc_count;
 406         // write alloc as much as we can
 407         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 408
 409         nbytes = mite_bytes_transferred(mite, AI_DMA_CHAN);
 410         if( (int)(nbytes - old_alloc_count) > 0 ){
 411                 printk("ni_mio_common: DMA overwrite of free area\n");
 412                 ni_ai_reset(dev,s);
 413                 async->events |= COMEDI_CB_OVERFLOW;
 414                 return;
 415         }
 416
 417         count = nbytes - async->buf_write_count;
 418         if( count < 0 ){
 419                 rt_printk("ni_mio_common: BUG: negative ai count\n");
 420                 count = 0;
 421         }
 422
 423         comedi_buf_write_free(async, count);
 424
 425         async->scan_progress += count;
 426         if( async->scan_progress >= bytes_per_scan )
 427         {
 428                 async->scan_progress %= bytes_per_scan;
 429                 async->events |= COMEDI_CB_EOS;
 430         }
 431         async->events |= COMEDI_CB_BLOCK;
 432 }
 433
 434 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 435 {
 436         int count;
 437         comedi_subdevice *s = dev->subdevices + 1;
 438         comedi_async *async = s->async;
 439         unsigned int nbytes, new_write_count;
 440
 441         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR + CHAN_OFFSET(AO_DMA_CHAN));
 442
 443         new_write_count = async->buf_write_count;
 444
 445         nbytes = mite_bytes_read(mite, AO_DMA_CHAN);
 446         if( async->cmd.stop_src == TRIG_COUNT &&
 447                 (int) (nbytes - async->cmd.stop_arg * sizeof( sampl_t ) ) > 0 )
 448                 nbytes = async->cmd.stop_arg * sizeof( sampl_t );
 449         if( (int)(nbytes - devpriv->last_buf_write_count) > 0 ){
 450                 rt_printk("ni_mio_common: DMA underrun\n");
 451                 ni_ao_reset(dev,s);
 452                 async->events |= COMEDI_CB_OVERFLOW;
 453                 return;
 454         }
 455
 456         devpriv->last_buf_write_count = new_write_count;
 457
 458         count = nbytes - async->buf_read_count;
 459         if( count < 0 ){
 460                 rt_printk("ni_mio_common: BUG: negative ao count\n");
 461                 count = 0;
 462         }
 463         comedi_buf_read_free(async, count);
 464
 465         async->events |= COMEDI_CB_BLOCK;
 466 }
 467
 468 #if 0
 469 static void mite_handle_interrupt(comedi_device *dev,unsigned int m_status)
 470 {
 471         int len;
 472         comedi_subdevice *s = dev->subdevices+0;
 473         comedi_async *async = s->async;
 474         struct mite_struct *mite = devpriv->mite;
 475
 476         async->events |= COMEDI_CB_BLOCK;
 477
 478         MDPRINTK("mite_handle_interrupt: m_status=%08x\n",m_status);
 479         if(m_status & CHSR_DONE){
 480                 writel(CHOR_CLRDONE, mite->mite_io_addr + MITE_CHOR +
 481                         CHAN_OFFSET(0));
 482         }
 483
 484 #if 0
 485         len = sizeof(sampl_t)*async->cmd.stop_arg*async->cmd.scan_end_arg;
 486         if((devpriv->mite->DMA_CheckNearEnd) &&
 487                         (s->async->buf_int_count > (len - s->async->prealloc_bufsz))) {
 488                 long offset;
 489                 int i;
 490
 491                 offset = len % async->prealloc_bufsz;
 492                 if(offset < mite->ring[0].count) {
 493                         mite->ring[0].count = offset;
 494                         mite->ring[1].count = 0;
 495                 }else{
 496                         offset -= mite->ring[0].count;
 497                         i = offset >> PAGE_SHIFT;
 498                         mite->ring[i].count = offset & ~PAGE_MASK;
 499                         mite->ring[(i+1)%mite->n_links].count = 0;
 500                 }
 501                 mite->DMA_CheckNearEnd = 0;
 502         }
 503 #endif
 504
 505 #if  0
 506         MDPRINTK("CHSR is 0x%08x, count is %d\n",m_status,async->buf_int_count);
 507         if(m_status&CHSR_DONE){
 508                 writel(CHOR_CLRDONE, mite->mite_io_addr+MITE_CHOR+CHAN_OFFSET(mite->chan));
 509                 //printk("buf_int_count is %d, buf_int_ptr is %d\n",
 510                 //              s->async->buf_int_count,s->async->buf_int_ptr);
 511                 ni_handle_block_dma(dev);
 512         }
 513         MDPRINTK("exit mite_handle_interrupt\n");
 514 #endif
 515
 516         //comedi_event(dev,s,async->events);
 517 }
 518 #endif
 519
 520 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 521 {
 522         static const int timeout = 10000;
 523         int i;
 524
 525         for(i = 0; i < timeout; i++)
 526         {
 527                 unsigned short b_status;
 528
 529                 b_status = win_in( AO_Status_1_Register );
 530                 if( b_status & AO_FIFO_Half_Full_St )
 531                         break;
 532                 comedi_udelay(10);
 533         }
 534         if( i == timeout )
 535         {
 536                 comedi_error(dev, "timed out waiting for dma load");
 537                 return -EPIPE;
 538         }
 539         return 0;
 540 }
 541
 542 #endif //PCIDMA
 543
 544 static void shutdown_ai_command( comedi_device *dev )
 545 {
 546         comedi_subdevice *s = dev->subdevices + 0;
 547
 548 #ifdef PCIDMA
 549         ni_ai_drain_dma( dev );
 550         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 551 #endif
 552         ni_handle_fifo_dregs(dev);
 553         get_last_sample_611x(dev);
 554
 555         ni_set_bits(dev, Interrupt_A_Enable_Register,
 556                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 557                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 558                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 559                 AI_FIFO_Interrupt_Enable,0);
 560
 561         s->async->events |= COMEDI_CB_EOA;
 562 }
 563
 564 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 565         unsigned int m_status)
 566 {
 567         comedi_subdevice *s=dev->subdevices+0;
 568         //comedi_async *async = s->async;
 569         unsigned short ack=0;
 570
 571         s->async->events = 0;
 572
 573 #ifdef DEBUG_INTERRUPT
 574         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 575                 status, m_status);
 576         ni_mio_print_status_a(status);
 577 #endif
 578
 579
 580 #ifdef PCIDMA
 581         /* Currently, mite.c requires us to handle LINKC and DONE */
 582         if(m_status & CHSR_LINKC){
 583                 ni_sync_ai_dma(devpriv->mite, dev);
 584         }
 585
 586         if(m_status & CHSR_DONE){
 587                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR +
 588                         CHAN_OFFSET(AI_DMA_CHAN));
 589         }
 590
 591         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 592                 printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 593                 //mite_print_chsr(m_status);
 594                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 595                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR +
 596                         CHAN_OFFSET(AI_DMA_CHAN));
 597                 //disable_irq(dev->irq);
 598         }
 599 #endif
 600
 601         /* test for all uncommon interrupt events at the same time */
 602         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 603                 if(status==0xffff){
 604                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 605                         /* we probably aren't even running a command now,
 606                          * so it's a good idea to be careful. */
 607                         if(s->subdev_flags&SDF_RUNNING){
 608                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 609                                 //comedi_event(dev,s,s->async->events);
 610                         }
 611                         return;
 612                 }
 613                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 614                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 615                                 status);
 616                         ni_mio_print_status_a(status);
 617
 618                         ni_ai_reset(dev,dev->subdevices);
 619
 620                         win_out(AI_Error_Interrupt_Ack, Interrupt_A_Ack_Register);
 621
 622                         shutdown_ai_command( dev );
 623
 624                         s->async->events |= COMEDI_CB_ERROR;
 625                         comedi_event(dev,s,s->async->events);
 626
 627                         return;
 628                 }
 629                 if(status&AI_SC_TC_St){
 630 #ifdef DEBUG_INTERRUPT
 631                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 632 #endif
 633                         if(!devpriv->ai_continuous){
 634                                 shutdown_ai_command( dev );
 635                         }
 636                         ack|=AI_SC_TC_Interrupt_Ack;
 637                 }
 638                 if(status&AI_START1_St){
 639                         ack|=AI_START1_Interrupt_Ack;
 640                 }
 641         }
 642 #ifndef PCIDMA
 643         if(status&AI_FIFO_Half_Full_St){
 644                 ni_handle_fifo_half_full(dev);
 645         }
 646 #endif // !PCIDMA
 647
 648         if( (status & AI_STOP_St) ){
 649                 if(devpriv->aimode==AIMODE_SCAN){
 650 #ifdef PCIDMA
 651                         ni_sync_ai_dma(devpriv->mite, dev);
 652 #else
 653                         ni_handle_fifo_dregs(dev);
 654                         s->async->events |= COMEDI_CB_EOS;
 655 #endif
 656                 }
 657                 /* handle special case of single scan using AI_End_On_End_Of_Scan */
 658                 if( ( devpriv->ai_cmd2 & AI_End_On_End_Of_Scan ) ){
 659                         shutdown_ai_command( dev );
 660                 }
 661
 662                 /* we need to ack the START, also */
 663                 ack|=AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 664         }
 665         if(devpriv->aimode==AIMODE_SAMPLE){
 666                 ni_handle_fifo_dregs(dev);
 667
 668                 //s->async->events |= COMEDI_CB_SAMPLE;
 669         }
 670
 671         if(ack) win_out(ack,Interrupt_A_Ack_Register);
 672
 673         comedi_event(dev,s,s->async->events);
 674
 675 #ifdef DEBUG_INTERRUPT
 676         status=win_in(AI_Status_1_Register);
 677         if(status&Interrupt_A_St){
 678                 printk("handle_a_interrupt: BUG, didn't clear interrupt. disabling.\n");
 679                 win_out(0,Interrupt_Control_Register);
 680         }
 681 #endif
 682 }
 683
 684 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 685 {
 686         comedi_subdevice *s=dev->subdevices+1;
 687         //unsigned short ack=0;
 688 #ifdef DEBUG_INTERRUPT
 689         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 690                 b_status,m_status);
 691         ni_mio_print_status_b(b_status);
 692 #endif
 693
 694
 695 #ifdef PCIDMA
 696         /* Currently, mite.c requires us to handle LINKC and DONE */
 697         if(m_status & CHSR_LINKC){
 698                 mite_handle_b_linkc(devpriv->mite, dev);
 699         }
 700
 701         if(m_status & CHSR_DONE){
 702                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR +
 703                         CHAN_OFFSET(AO_DMA_CHAN));
 704         }
 705
 706         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 707                 printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 708                 //mite_print_chsr(m_status);
 709                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 710                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR +
 711                         CHAN_OFFSET(AO_DMA_CHAN));
 712        }
 713 #endif
 714
 715         if(b_status==0xffff)return;
 716         if(b_status&AO_Overrun_St){
 717                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,win_in(AO_Status_2_Register));
 718                 ni_ao_reset(dev,s);
 719                 s->async->events |= COMEDI_CB_OVERFLOW;
 720         }
 721
 722         if(b_status&AO_BC_TC_St){
 723                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,win_in(AO_Status_2_Register));
 724                 ni_ao_reset(dev,s);
 725                 s->async->events |= COMEDI_CB_EOA;
 726         }
 727
 728 #ifndef PCIDMA
 729         if(b_status&AO_FIFO_Request_St){
 730                 int ret;
 731
 732                 ret = ni_ao_fifo_half_empty(dev,s);
 733                 if(!ret){
 734                         rt_printk("ni_mio_common: AO buffer underrun\n");
 735                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 736                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 737                         s->async->events |= COMEDI_CB_OVERFLOW;
 738                 }
 739         }
 740 #endif
 741
 742         b_status=win_in(AO_Status_1_Register);
 743         if(b_status&Interrupt_B_St){
 744                 if(b_status&AO_FIFO_Request_St){
 745                         rt_printk("ni_mio_common: AO buffer underrun\n");
 746                 }
 747                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 748                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 749                 ni_ao_reset(dev,s);
 750                 s->async->events |= COMEDI_CB_OVERFLOW;
 751         }
 752
 753         comedi_event(dev,s,s->async->events);
 754 }
 755
 756 #ifdef DEBUG_STATUS_A
 757 static char *status_a_strings[]={
 758         "passthru0","fifo","G0_gate","G0_TC",
 759         "stop","start","sc_tc","start1",
 760         "start2","sc_tc_error","overflow","overrun",
 761         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 762 };
 763
 764 static void ni_mio_print_status_a(int status)
 765 {
 766         int i;
 767
 768         rt_printk("A status:");
 769         for(i=15;i>=0;i--){
 770                 if(status&(1<<i)){
 771                         rt_printk(" %s",status_a_strings[i]);
 772                 }
 773         }
 774         rt_printk("\n");
 775 }
 776 #endif
 777
 778 #ifdef DEBUG_STATUS_B
 779 static char *status_b_strings[]={
 780         "passthru1","fifo","G1_gate","G1_TC",
 781         "UI2_TC","UPDATE","UC_TC","BC_TC",
 782         "start1","overrun","start","bc_tc_error",
 783         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 784 };
 785
 786 static void ni_mio_print_status_b(int status)
 787 {
 788         int i;
 789
 790         rt_printk("B status:");
 791         for(i=15;i>=0;i--){
 792                 if(status&(1<<i)){
 793                         rt_printk(" %s",status_b_strings[i]);
 794                 }
 795         }
 796         rt_printk("\n");
 797 }
 798 #endif
 799
 800 #ifndef PCIDMA
 801
 802 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 803 {
 804         comedi_async *async = s->async;
 805         comedi_cmd *cmd = &async->cmd;
 806         int chan;
 807         int i;
 808         sampl_t d;
 809         u32 packed_data;
 810         int range;
 811         int err = 1;
 812
 813         chan = async->cur_chan;
 814         for(i=0;i<n;i++){
 815                 err &= comedi_buf_get(async, &d);
 816                 if(err == 0) break;
 817
 818                 range = CR_RANGE(cmd->chanlist[chan]);
 819
 820                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 821                 {
 822                         packed_data = d & 0xffff;
 823                         /* 6711 only has 16 bit wide ao fifo */
 824                         if(boardtype.reg_type != ni_reg_6711)
 825                         {
 826                                 err &= comedi_buf_get(async, &d);
 827                                 if(err == 0) break;
 828                                 chan++;
 829                                 i++;
 830                                 packed_data |= ( d << 16 ) & 0xffff0000;
 831                         }
 832                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 833                 }else{
 834                         ni_writew(d, DAC_FIFO_Data);
 835                 }
 836                 chan++;
 837                 chan %= cmd->chanlist_len;
 838         }
 839         async->cur_chan = chan;
 840         if(err==0){
 841                 async->events |= COMEDI_CB_OVERFLOW;
 842         }
 843 }
 844
 845 /*
 846  *  There's a small problem if the FIFO gets really low and we
 847  *  don't have the data to fill it.  Basically, if after we fill
 848  *  the FIFO with all the data available, the FIFO is _still_
 849  *  less than half full, we never clear the interrupt.  If the
 850  *  IRQ is in edge mode, we never get another interrupt, because
 851  *  this one wasn't cleared.  If in level mode, we get flooded
 852  *  with interrupts that we can't fulfill, because nothing ever
 853  *  gets put into the buffer.
 854  *
 855  *  This kind of situation is recoverable, but it is easier to
 856  *  just pretend we had a FIFO underrun, since there is a good
 857  *  chance it will happen anyway.  This is _not_ the case for
 858  *  RT code, as RT code might purposely be running close to the
 859  *  metal.  Needs to be fixed eventually.
 860  */
 861 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 862 {
 863         int n;
 864
 865         n = comedi_buf_read_n_available(s);
 866         if(n==0){
 867                 s->async->events |= COMEDI_CB_OVERFLOW;
 868                 return 0;
 869         }
 870
 871         n /= sizeof(sampl_t);
 872         if(n > boardtype.ao_fifo_depth / 2)
 873                 n = boardtype.ao_fifo_depth / 2;
 874
 875         ni_ao_fifo_load(dev,s,n);
 876
 877         s->async->events |= COMEDI_CB_BLOCK;
 878
 879         return 1;
 880 }
 881
 882 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 883 {
 884         int n;
 885
 886         /* reset fifo */
 887         win_out(0,DAC_FIFO_Clear);
 888         ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 889
 890         /* load some data */
 891         n = comedi_buf_read_n_available(s);
 892         if(n==0)return 0;
 893
 894         n /= sizeof(sampl_t);
 895         if(n > boardtype.ao_fifo_depth)
 896                 n = boardtype.ao_fifo_depth;
 897
 898         ni_ao_fifo_load(dev,s,n);
 899
 900         return n;
 901 }
 902
 903 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 904         int n)
 905 {
 906         comedi_async *async = s->async;
 907         int i;
 908         u32 dl;
 909         sampl_t data;
 910         unsigned int mask;
 911         int no_err = 1;
 912
 913         mask=(1<<boardtype.adbits)-1;
 914         if(boardtype.reg_type == ni_reg_611x){
 915                 for( i = 0; i < n / 2; i++ ){
 916                         dl=ni_readl(ADC_FIFO_Data_611x);
 917
 918                         /* This may get the hi/lo data in the wrong order */
 919                         data = (dl>>16) & 0xffff;
 920                         no_err &= comedi_buf_put(s->async, data);
 921                         data = dl & 0xffff;
 922                         no_err &= comedi_buf_put(s->async, data);
 923                 }
 924
 925                 /* Check if there's a single sample stuck in the FIFO */
 926                 if( n % 2){
 927                         dl=ni_readl(ADC_FIFO_Data_611x);
 928                         data = dl & 0xffff;
 929                         no_err &= comedi_buf_put(s->async, data);
 930                 }
 931                 if(no_err==0){
 932                         async->events |= COMEDI_CB_OVERFLOW;
 933                 }
 934         }else{
 935                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
 936                 {
 937                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
 938                         async->events |= COMEDI_CB_ERROR;
 939                         return;
 940                 }
 941                 for(i=0;i<n;i++){
 942                         devpriv->ai_fifo_buffer[ n ] = ni_readw(ADC_FIFO_Data_Register);
 943                 }
 944                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
 945                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
 946         }
 947 }
 948
 949 static void ni_handle_fifo_half_full(comedi_device *dev)
 950 {
 951         int n;
 952         comedi_subdevice *s=dev->subdevices+0;
 953         /*
 954            if we got a fifo_half_full interrupt, we can transfer fifo/2
 955            samples without checking the empty flag.  It doesn't matter if
 956            we transfer the rest of the samples, the performance trade-off
 957            is minimal (checking empty flag for a few samples vs. having
 958            1% more interrupts.)  At really high speeds, it's better to
 959            ignore them.
 960
 961         */
 962
 963         n=boardtype.ai_fifo_depth/2;
 964
 965         ni_ai_fifo_read(dev,s,n);
 966 }
 967 #endif
 968
 969 #ifdef PCIDMA
 970 static int ni_ai_drain_dma(comedi_device *dev )
 971 {
 972         struct mite_struct *mite = devpriv->mite;
 973         int i;
 974         static const int timeout = 10000;
 975
 976         for( i = 0; i < timeout; i++ )
 977         {
 978                 if( ( win_in( AI_Status_1_Register ) & AI_FIFO_Empty_St ) &&
 979                         mite_bytes_in_transit( mite, AI_DMA_CHAN ) == 0 )
 980                         break;
 981                 comedi_udelay( 1 );
 982         }
 983         if( i == timeout )
 984         {
 985                 rt_printk( "ni_mio_common: wait for dma drain timed out\n" );
 986                 return -1;
 987         }
 988
 989         ni_sync_ai_dma( mite, dev );
 990
 991         return 0;
 992 }
 993 #endif
 994 /*
 995    Empties the AI fifo
 996 */
 997 static void ni_handle_fifo_dregs(comedi_device *dev)
 998 {
 999         comedi_subdevice *s=dev->subdevices+0;
1000         comedi_async *async = s->async;
1001         sampl_t data;
1002         u32 dl;
1003         int err = 1;
1004
1005         if(boardtype.reg_type == ni_reg_611x){
1006                 while((win_in(AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1007                         dl=ni_readl(ADC_FIFO_Data_611x);
1008
1009                         /* This may get the hi/lo data in the wrong order */
1010                         data = (dl>>16);
1011                         err &= comedi_buf_put(s->async, data);
1012                         data = (dl&0xffff);
1013                         err &= comedi_buf_put(s->async, data);
1014                 }
1015         }else{
1016                 while((win_in(AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1017                         data=ni_readw(ADC_FIFO_Data_Register);
1018                         err &= comedi_buf_put(s->async, data);
1019                 }
1020         }
1021         if(err==0){
1022                 async->events |= COMEDI_CB_OVERFLOW;
1023         }
1024 }
1025
1026 static void get_last_sample_611x( comedi_device *dev )
1027 {
1028         comedi_subdevice *s=dev->subdevices+0;
1029         comedi_async *async = s->async;
1030         sampl_t data;
1031         u32 dl;
1032         int err = 1;
1033
1034         if(boardtype.reg_type != ni_reg_611x) return;
1035
1036         /* Check if there's a single sample stuck in the FIFO */
1037         if(ni_readb(XXX_Status)&0x80){
1038                 dl=ni_readl(ADC_FIFO_Data_611x);
1039                 data = (dl&0xffff);
1040                 err &= comedi_buf_put(s->async, data);
1041         }
1042         if(err==0){
1043                 async->events |= COMEDI_CB_OVERFLOW;
1044         }
1045 }
1046
1047 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1048         void *data, unsigned int num_bytes, unsigned int chan_index )
1049 {
1050         comedi_async *async = s->async;
1051         unsigned int i;
1052         unsigned int length = num_bytes / sizeof( sampl_t );
1053         sampl_t *array = data;
1054
1055         for(i = 0; i < length; i++)
1056         {
1057 #ifdef PCIDMA
1058                 array[i] = le16_to_cpu(array[i]);
1059 #endif
1060                 array[i] += devpriv->ai_offset[ chan_index ];
1061                 chan_index++;
1062                 chan_index %= async->cmd.chanlist_len;
1063         }
1064 }
1065
1066 #ifdef PCIDMA
1067
1068 #if 0
1069 static void ni_handle_block_dma(comedi_device *dev)
1070 {
1071         comedi_subdevice *s = dev->subdevices + 0;
1072
1073         MDPRINTK("ni_handle_block_dma\n");
1074         mite_dma_disarm(devpriv->mite);
1075         ni_set_bits(dev, Interrupt_A_Enable_Register,
1076                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1077                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1078                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
1079                 AI_FIFO_Interrupt_Enable,0);
1080
1081         ni_ai_reset(dev,dev->subdevices);
1082         s->async->events |= COMEDI_CB_EOA;
1083         MDPRINTK("exit ni_handle_block_dma\n");
1084 }
1085 #endif
1086
1087 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1088 {
1089         struct mite_struct *mite = devpriv->mite;
1090         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1091         comedi_subdevice *s = dev->subdevices + 0;
1092
1093         /* write alloc the entire buffer */
1094         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1095
1096         mite_chan->current_link = 0;
1097         mite_chan->dir = COMEDI_INPUT;
1098         if(boardtype.reg_type == ni_reg_611x)
1099                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1100         else
1101                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1102
1103         /*start the MITE*/
1104         mite_dma_arm(mite, AI_DMA_CHAN);
1105 }
1106
1107 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1108 {
1109         struct mite_struct *mite = devpriv->mite;
1110         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1111         comedi_subdevice *s = dev->subdevices + 1;
1112
1113         devpriv->last_buf_write_count = s->async->buf_write_count;
1114
1115         mite_chan->current_link = 0;
1116         mite_chan->dir = COMEDI_OUTPUT;
1117         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1118                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1119         else
1120                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1121
1122         /*start the MITE*/
1123         mite_dma_arm(mite, AO_DMA_CHAN);
1124 }
1125
1126 #endif // PCIDMA
1127
1128 /*
1129    used for both cancel ioctl and board initialization
1130
1131    this is pretty harsh for a cancel, but it works...
1132  */
1133
1134 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1135 {
1136 #ifdef PCIDMA
1137         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1138 #endif
1139         /* ai configuration */
1140         win_out( AI_Configuration_Start | AI_Reset, Joint_Reset_Register );
1141
1142         ni_set_bits(dev, Interrupt_A_Enable_Register,
1143                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1144                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1145                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1146                 AI_FIFO_Interrupt_Enable,0);
1147
1148         win_out(1,ADC_FIFO_Clear);
1149
1150         ni_writeb(0, Misc_Command);
1151
1152         win_out(AI_Disarm, AI_Command_1_Register); /* reset pulses */
1153         win_out(AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1154                 AI_Mode_1_Register);
1155         win_out(0x0000,AI_Mode_2_Register);
1156 #if 0
1157         /* generate FIFO interrupts on half full */
1158         win_out((1<<6)|0x0000,AI_Mode_3_Register);
1159 #else
1160         /* generate FIFO interrupts on non-empty */
1161         win_out((0<<6)|0x0000,AI_Mode_3_Register);
1162 #endif
1163         if(boardtype.reg_type == ni_reg_normal){
1164                 win_out(AI_SHIFTIN_Pulse_Width |
1165                         AI_SOC_Polarity |
1166                         AI_CONVERT_Pulse_Width |
1167                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1168                 win_out(AI_SCAN_IN_PROG_Output_Select(3) |
1169                         AI_EXTMUX_CLK_Output_Select(0) |
1170                         AI_LOCALMUX_CLK_Output_Select(2) |
1171                         AI_SC_TC_Output_Select(3) |
1172                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1173         }else{/* 611x boards */
1174                 win_out(AI_SHIFTIN_Pulse_Width |
1175                         AI_SOC_Polarity |
1176                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1177                 win_out(AI_SCAN_IN_PROG_Output_Select(3) |
1178                         AI_EXTMUX_CLK_Output_Select(0) |
1179                         AI_LOCALMUX_CLK_Output_Select(2) |
1180                         AI_SC_TC_Output_Select(3) |
1181                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1182         }
1183
1184         /* the following registers should not be changed, because there
1185          * are no backup registers in devpriv.  If you want to change
1186          * any of these, add a backup register and other appropriate code:
1187          *      AI_Mode_1_Register
1188          *      AI_Mode_3_Register
1189          *      AI_Personal_Register
1190          *      AI_Output_Control_Register
1191         */
1192         win_out(0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
1193
1194         win_out(AI_Configuration_End,Joint_Reset_Register);
1195
1196         return 0;
1197 }
1198
1199 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1200 {
1201 #ifndef PCIDMA
1202         ni_handle_fifo_dregs(dev);
1203
1204         //comedi_event(dev,s,s->async->events);
1205
1206         return s->async->buf_write_count - s->async->buf_read_count;
1207 #else
1208         /* XXX we don't support this yet. */
1209         return -EINVAL;
1210 #endif
1211 }
1212
1213
1214 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1215 {
1216         int i,n;
1217         unsigned int mask;
1218         unsigned short signbits;
1219         unsigned short d;
1220
1221         ni_load_channelgain_list(dev,1,&insn->chanspec);
1222
1223         win_out(1,ADC_FIFO_Clear);
1224
1225         mask=(1<<boardtype.adbits)-1;
1226         signbits=devpriv->ai_offset[0];
1227         if(boardtype.reg_type == ni_reg_611x){
1228                 for(n=0; n < num_adc_stages_611x; n++){
1229                         win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
1230                         comedi_udelay(1);
1231                 }
1232                 for(n=0; n<insn->n; n++){
1233                         win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
1234                         /* The 611x has screwy 32-bit FIFOs. */
1235                         d = 0;
1236                         for(i=0; i<NI_TIMEOUT; i++){
1237                                 if(ni_readb(XXX_Status)&0x80)
1238                                 {
1239                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1240                                         break;
1241                                 }
1242                                 if(!(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St))
1243                                 {
1244                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1245                                         break;
1246                                 }
1247                         }
1248                         if(i==NI_TIMEOUT){
1249                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1250                                 return -ETIME;
1251                         }
1252                         d += signbits; /* subtle: needs to be short addition */
1253                         data[ n ] = d;
1254                 }
1255         }else{
1256                 for(n=0;n<insn->n;n++){
1257                         win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
1258                         for(i=0;i<NI_TIMEOUT;i++){
1259                                 if(!(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St))
1260                                         break;
1261                         }
1262                         if(i==NI_TIMEOUT){
1263                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1264                                 return -ETIME;
1265                         }
1266                         d = ni_readw(ADC_FIFO_Data_Register);
1267                         d += signbits; /* subtle: needs to be short addition */
1268                         data[n] = d;
1269                 }
1270         }
1271         return insn->n;
1272 }
1273
1274 /*
1275  * Notes on the 6110 and 6111:
1276  * These boards a slightly different than the rest of the series, since
1277  * they have multiple A/D converters.
1278  * From the driver side, the configuration memory is a
1279  * little different.
1280  * Configuration Memory Low:
1281  *   bits 15-9: same
1282  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1283  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1284  *       1001 gain=0.1 (+/- 50)
1285  *       1010 0.2
1286  *       1011 0.1
1287  *       0001 1
1288  *       0010 2
1289  *       0011 5
1290  *       0100 10
1291  *       0101 20
1292  *       0110 50
1293  * Configuration Memory High:
1294  *   bits 12-14: Channel Type
1295  *       001 for differential
1296  *       000 for calibration
1297  *   bit 11: coupling  (this is not currently handled)
1298  *       1 AC coupling
1299  *       0 DC coupling
1300  *   bits 0-2: channel
1301  *       valid channels are 0-3
1302  */
1303 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1304         unsigned int *list)
1305 {
1306         unsigned int chan,range,aref;
1307         unsigned int i;
1308         unsigned int hi,lo;
1309         unsigned short offset;
1310         unsigned int dither;
1311
1312         if(n_chan == 1 && boardtype.reg_type == ni_reg_normal){
1313                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1314                         // ready to go.
1315                         return;
1316                 }
1317                 devpriv->changain_state=1;
1318                 devpriv->changain_spec=list[0];
1319         }else{
1320                 devpriv->changain_state=0;
1321         }
1322
1323         win_out(1,Configuration_Memory_Clear);
1324
1325         offset=1<<(boardtype.adbits-1);
1326         for(i=0;i<n_chan;i++){
1327                 if(list[i]&CR_ALT_SOURCE){
1328                         chan=devpriv->ai_calib_source;
1329                 }else{
1330                         chan=CR_CHAN(list[i]);
1331                 }
1332                 aref=CR_AREF(list[i]);
1333                 range=CR_RANGE(list[i]);
1334                 dither=((list[i]&CR_ALT_FILTER)!=0);
1335
1336                 /* fix the external/internal range differences */
1337                 range = ni_gainlkup[boardtype.gainlkup][range];
1338                 if(boardtype.reg_type == ni_reg_611x)
1339                         devpriv->ai_offset[i] = offset;
1340                 else
1341                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1342
1343                 hi = 0;
1344                 if( ( list[i] & CR_ALT_SOURCE ) )
1345                 {
1346                         if(boardtype.reg_type == ni_reg_611x)
1347                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1348                 }else
1349                 {
1350                         if(boardtype.reg_type == ni_reg_611x)
1351                                 aref = AREF_DIFF;
1352                         switch( aref )
1353                         {
1354                                 case AREF_DIFF:
1355                                         hi |= AI_DIFFERENTIAL;
1356                                         break;
1357                                 case AREF_COMMON:
1358                                         hi |= AI_COMMON;
1359                                         break;
1360                                 case AREF_GROUND:
1361                                         hi |= AI_GROUND;
1362                                         break;
1363                                 case AREF_OTHER:
1364                                         break;
1365                         }
1366                 }
1367                 hi |= AI_CONFIG_CHANNEL( chan );
1368
1369                 ni_writew(hi,Configuration_Memory_High);
1370
1371                 lo = range;
1372                 if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1373                 if( dither ) lo |= AI_DITHER;
1374
1375                 ni_writew(lo,Configuration_Memory_Low);
1376         }
1377
1378         /* prime the channel/gain list */
1379         if(boardtype.reg_type == ni_reg_normal){
1380                 win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
1381                 for(i=0;i<NI_TIMEOUT;i++){
1382                         if(!(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St)){
1383                                 win_out(1,ADC_FIFO_Clear);
1384                                 return;
1385                         }
1386                         comedi_udelay(1);
1387                 }
1388                 rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1389         }
1390 }
1391
1392 #define TIMER_BASE 50 /* 20 Mhz base */
1393
1394 static int ni_ns_to_timer(int *nanosec,int round_mode)
1395 {
1396         int divider,base;
1397
1398         base=TIMER_BASE;
1399
1400         switch(round_mode){
1401         case TRIG_ROUND_NEAREST:
1402         default:
1403                 divider=(*nanosec+base/2)/base;
1404                 break;
1405         case TRIG_ROUND_DOWN:
1406                 divider=(*nanosec)/base;
1407                 break;
1408         case TRIG_ROUND_UP:
1409                 divider=(*nanosec+base-1)/base;
1410                 break;
1411         }
1412
1413         *nanosec=base*divider;
1414         return divider-1;
1415 }
1416
1417 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1418 {
1419         int err=0;
1420         int tmp;
1421         int sources;
1422
1423         /* step 1: make sure trigger sources are trivially valid */
1424
1425         tmp=cmd->start_src;
1426         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1427         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1428
1429         tmp=cmd->scan_begin_src;
1430         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1431         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1432
1433         tmp=cmd->convert_src;
1434         sources = TRIG_TIMER | TRIG_EXT;
1435         if(boardtype.reg_type == ni_reg_611x) sources |= TRIG_NOW;
1436         cmd->convert_src &= sources;
1437         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1438
1439         tmp=cmd->scan_end_src;
1440         cmd->scan_end_src &= TRIG_COUNT;
1441         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1442
1443         tmp=cmd->stop_src;
1444         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1445         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1446
1447         if(err)return 1;
1448
1449         /* step 2: make sure trigger sources are unique and mutually compatible */
1450
1451         /* note that mutual compatiblity is not an issue here */
1452         if(cmd->start_src!=TRIG_NOW &&
1453            cmd->start_src!=TRIG_INT &&
1454            cmd->start_src!=TRIG_EXT)err++;
1455         if(cmd->scan_begin_src!=TRIG_TIMER &&
1456            cmd->scan_begin_src!=TRIG_EXT &&
1457            cmd->scan_begin_src!=TRIG_OTHER)err++;
1458         if(cmd->convert_src!=TRIG_TIMER &&
1459            cmd->convert_src!=TRIG_EXT &&
1460            cmd->convert_src!=TRIG_NOW)err++;
1461         if(cmd->stop_src!=TRIG_COUNT &&
1462            cmd->stop_src!=TRIG_NONE)err++;
1463
1464         if(err)return 2;
1465
1466         /* step 3: make sure arguments are trivially compatible */
1467
1468         if(cmd->start_src==TRIG_EXT){
1469                 /* external trigger */
1470                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1471
1472                 if(tmp>9)tmp=9;
1473                 /* XXX for now, use the top bit to invert the signal */
1474                 tmp |= (cmd->start_arg&0x80000000);
1475                 if(cmd->start_arg!=tmp){
1476                         cmd->start_arg = tmp;
1477                         err++;
1478                 }
1479         }else{
1480                 if(cmd->start_arg!=0){
1481                         /* true for both TRIG_NOW and TRIG_INT */
1482                         cmd->start_arg=0;
1483                         err++;
1484                 }
1485         }
1486         if(cmd->scan_begin_src==TRIG_TIMER){
1487                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1488                         cmd->scan_begin_arg=boardtype.ai_speed;
1489                         err++;
1490                 }
1491                 if(cmd->scan_begin_arg>TIMER_BASE*0xffffff){
1492                         cmd->scan_begin_arg=TIMER_BASE*0xffffff;
1493                         err++;
1494                 }
1495         }else if(cmd->scan_begin_src==TRIG_EXT){
1496                 /* external trigger */
1497                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1498
1499                 if(tmp>9)tmp=9;
1500                 /* XXX for now, use the top bit to invert the signal */
1501                 tmp |= (cmd->scan_begin_arg&0x80000000);
1502                 if(cmd->scan_begin_arg!=tmp){
1503                         cmd->scan_begin_arg = tmp;
1504                         err++;
1505                 }
1506         }else{ /* TRIG_OTHER */
1507                 if(cmd->scan_begin_arg){
1508                         cmd->scan_begin_arg=0;
1509                         err++;
1510                 }
1511         }
1512         if(cmd->convert_src==TRIG_TIMER){
1513                 if(boardtype.reg_type == ni_reg_611x){
1514                         if(cmd->convert_arg != 0){
1515                                 cmd->convert_arg = 0;
1516                                 err++;
1517                         }
1518                 }else{
1519                         if(cmd->convert_arg<boardtype.ai_speed){
1520                                 cmd->convert_arg=boardtype.ai_speed;
1521                                 err++;
1522                         }
1523                         if(cmd->convert_arg>TIMER_BASE*0xffff){
1524                                 cmd->convert_arg=TIMER_BASE*0xffff;
1525                                 err++;
1526                         }
1527                 }
1528         }else if(cmd->convert_src == TRIG_EXT){
1529                 /* external trigger */
1530                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1531
1532                 if(tmp>9)tmp=9;
1533                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1534                 if(cmd->convert_arg!=tmp){
1535                         cmd->convert_arg = tmp;
1536                         err++;
1537                 }
1538         }else if(cmd->convert_src == TRIG_NOW){
1539                 if(cmd->convert_arg != 0){
1540                         cmd->convert_arg = 0;
1541                         err++;
1542                 }
1543         }
1544
1545         if(cmd->scan_end_arg!=cmd->chanlist_len){
1546                 cmd->scan_end_arg=cmd->chanlist_len;
1547                 err++;
1548         }
1549         if(cmd->stop_src==TRIG_COUNT){
1550                 unsigned int max_count = 0x01000000;
1551
1552                 if(boardtype.reg_type == ni_reg_611x )
1553                         max_count -= num_adc_stages_611x;
1554                 if(cmd->stop_arg > max_count){
1555                         cmd->stop_arg = max_count;
1556                         err++;
1557                 }
1558         }else{
1559                 /* TRIG_NONE */
1560                 if(cmd->stop_arg!=0){
1561                         cmd->stop_arg=0;
1562                         err++;
1563                 }
1564         }
1565
1566         if(err)return 3;
1567
1568         /* step 4: fix up any arguments */
1569
1570         if(cmd->scan_begin_src==TRIG_TIMER){
1571                 tmp=cmd->scan_begin_arg;
1572                 ni_ns_to_timer(&cmd->scan_begin_arg,cmd->flags&TRIG_ROUND_MASK);
1573                 if(tmp!=cmd->scan_begin_arg)err++;
1574         }
1575         if(cmd->convert_src==TRIG_TIMER){
1576                 if(boardtype.reg_type == ni_reg_normal){
1577                         tmp=cmd->convert_arg;
1578                         ni_ns_to_timer(&cmd->convert_arg,cmd->flags&TRIG_ROUND_MASK);
1579                         if(tmp!=cmd->convert_arg)err++;
1580                         if(cmd->scan_begin_src==TRIG_TIMER &&
1581                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1582                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1583                                 err++;
1584                         }
1585                 }
1586         }
1587
1588         if(err)return 4;
1589
1590         return 0;
1591 }
1592
1593 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1594 {
1595         comedi_cmd *cmd=&s->async->cmd;
1596         int timer;
1597         int mode1=0; /* mode1 is needed for both stop and convert */
1598         int mode2=0;
1599         int start_stop_select=0;
1600         unsigned int stop_count;
1601         int interrupt_a_enable=0;
1602
1603         MDPRINTK("ni_ai_cmd\n");
1604
1605         win_out(1,ADC_FIFO_Clear);
1606
1607         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1608
1609         /* start configuration */
1610         win_out(AI_Configuration_Start,Joint_Reset_Register);
1611
1612         /* disable analog triggering for now, since it
1613          * interferes with the use of pfi0 */
1614         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1615         win_out(devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1616
1617         switch(cmd->start_src){
1618         case TRIG_INT:
1619         case TRIG_NOW:
1620                 win_out(AI_START2_Select(0)|
1621                         AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1622                         AI_Trigger_Select_Register);
1623                 break;
1624         case TRIG_EXT:
1625         {
1626                 int chan = CR_CHAN(cmd->start_arg);
1627
1628                 win_out(AI_START2_Select(0)|
1629                         AI_START1_Sync | AI_START1_Edge |
1630                         AI_START1_Select(chan + 1),
1631                         AI_Trigger_Select_Register);
1632                 break;
1633         }
1634         }
1635
1636         mode2 &= ~AI_Pre_Trigger;
1637         mode2 &= ~AI_SC_Initial_Load_Source;
1638         mode2 &= ~AI_SC_Reload_Mode;
1639         win_out(mode2, AI_Mode_2_Register);
1640
1641         start_stop_select |= AI_STOP_Sync;
1642         if(boardtype.reg_type == ni_reg_611x){
1643                 start_stop_select |= AI_STOP_Polarity;
1644                 start_stop_select |= AI_STOP_Select( 31 );
1645         }else{
1646                 start_stop_select |= AI_STOP_Select( 19 );
1647         }
1648         win_out(start_stop_select, AI_START_STOP_Select_Register);
1649
1650         devpriv->ai_cmd2 = 0;
1651         switch(cmd->stop_src){
1652         case TRIG_COUNT:
1653                 stop_count = cmd->stop_arg - 1;
1654
1655                 if(boardtype.reg_type == ni_reg_611x){
1656                         // have to take 3 stage adc pipeline into account
1657                         stop_count += num_adc_stages_611x;
1658                 }
1659                 /* stage number of scans */
1660                 win_out2( stop_count, AI_SC_Load_A_Registers);
1661
1662                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1663                 win_out(mode1,AI_Mode_1_Register);
1664                 /* load SC (Scan Count) */
1665                 win_out(AI_SC_Load,AI_Command_1_Register);
1666
1667                 devpriv->ai_continuous = 0;
1668                 if( stop_count == 0 ){
1669                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1670                         interrupt_a_enable|=AI_STOP_Interrupt_Enable;
1671                 }
1672                 break;
1673         case TRIG_NONE:
1674                 /* stage number of scans */
1675                 win_out(0,AI_SC_Load_A_Registers);
1676                 win_out(0,AI_SC_Load_A_Registers+1);
1677
1678                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1679                 win_out(mode1,AI_Mode_1_Register);
1680
1681                 /* load SC (Scan Count) */
1682                 win_out(AI_SC_Load,AI_Command_1_Register);
1683
1684                 devpriv->ai_continuous = 1;
1685
1686                 break;
1687         }
1688
1689         switch(cmd->scan_begin_src){
1690         case TRIG_TIMER:
1691                 /*
1692                         stop bits for non 611x boards
1693                         AI_SI_Special_Trigger_Delay=0
1694                         AI_Pre_Trigger=0
1695                         AI_START_STOP_Select_Register:
1696                         AI_START_Polarity=0 (?) rising edge
1697                         AI_START_Edge=1         edge triggered
1698                         AI_START_Sync=1 (?)
1699                         AI_START_Select=0               SI_TC
1700                         AI_STOP_Polarity=0              rising edge
1701                         AI_STOP_Edge=0          level
1702                         AI_STOP_Sync=1
1703                         AI_STOP_Select=19               external pin (configuration mem)
1704                  */
1705                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1706                 win_out(start_stop_select, AI_START_STOP_Select_Register);
1707
1708                 mode2 |= AI_SI_Reload_Mode(0);
1709                 /* AI_SI_Initial_Load_Source=A */
1710                 mode2 &= ~AI_SI_Initial_Load_Source;
1711                 //mode2 |= AI_SC_Reload_Mode;
1712                 win_out(mode2, AI_Mode_2_Register);
1713
1714                 /* load SI */
1715                 timer=ni_ns_to_timer(&cmd->scan_begin_arg,TRIG_ROUND_NEAREST);
1716                 win_out2(timer,AI_SI_Load_A_Registers);
1717                 win_out(AI_SI_Load,AI_Command_1_Register);
1718                 break;
1719         case TRIG_EXT:
1720
1721 /* Level trigger usually doesn't work, making it the default
1722  * doesn't make sense.  Disabling it. */
1723 /*              if( cmd->scan_begin_arg & CR_EDGE ) */
1724                 start_stop_select |= AI_START_Edge;
1725                 /* AI_START_Polarity==1 is falling edge */
1726                 if( cmd->scan_begin_arg & CR_INVERT )
1727                         start_stop_select |= AI_START_Polarity;
1728                 if( cmd->scan_begin_src != cmd->convert_src ||
1729                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1730                         start_stop_select |= AI_START_Sync;
1731                 start_stop_select |= AI_START_Select(1+(cmd->scan_begin_arg&0xf));
1732                 win_out(start_stop_select, AI_START_STOP_Select_Register);
1733                 break;
1734         }
1735
1736         switch(cmd->convert_src){
1737         case TRIG_TIMER:
1738         case TRIG_NOW:
1739                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
1740                         timer = 1;
1741                 else
1742                         timer=ni_ns_to_timer(&cmd->convert_arg, TRIG_ROUND_NEAREST);
1743                 win_out(1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
1744                 win_out(timer,AI_SI2_Load_B_Register);
1745
1746                 /* AI_SI2_Reload_Mode = alternate */
1747                 /* AI_SI2_Initial_Load_Source = A */
1748                 mode2 &= ~AI_SI2_Initial_Load_Source;
1749                 mode2 |= AI_SI2_Reload_Mode;
1750                 win_out( mode2, AI_Mode_2_Register);
1751
1752                 /* AI_SI2_Load */
1753                 win_out(AI_SI2_Load,AI_Command_1_Register);
1754
1755                 mode2 |= AI_SI2_Reload_Mode; // alternate
1756                 mode2 |= AI_SI2_Initial_Load_Source; // B
1757
1758                 win_out(mode2,AI_Mode_2_Register);
1759                 break;
1760         case TRIG_EXT:
1761                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
1762                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
1763                         mode1 |= AI_CONVERT_Source_Polarity;
1764                 win_out(mode1,AI_Mode_1_Register);
1765
1766                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
1767                 win_out(mode2, AI_Mode_2_Register);
1768
1769                 break;
1770         }
1771
1772         if(dev->irq){
1773
1774                 /* interrupt on FIFO, errors, SC_TC */
1775                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
1776                         AI_SC_TC_Interrupt_Enable;
1777
1778 #ifndef PCIDMA
1779                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
1780 #endif
1781
1782                 if(s->async->cb_mask&COMEDI_CB_EOS){
1783                         /* wake on end-of-scan */
1784                         devpriv->aimode=AIMODE_SCAN;
1785                 }else{
1786                         devpriv->aimode=AIMODE_HALF_FULL;
1787                 }
1788
1789                 switch(devpriv->aimode){
1790                 case AIMODE_HALF_FULL:
1791                         /*generate FIFO interrupts and DMA requests on half-full */
1792 #ifdef PCIDMA
1793                         win_out(AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
1794 #else
1795                         win_out(AI_FIFO_Mode_HF, AI_Mode_3_Register);
1796 #endif
1797                         break;
1798                 case AIMODE_SAMPLE:
1799                         /*generate FIFO interrupts on non-empty */
1800                         win_out(AI_FIFO_Mode_NE, AI_Mode_3_Register);
1801                         break;
1802                 case AIMODE_SCAN:
1803 #ifdef PCIDMA
1804                         win_out(AI_FIFO_Mode_NE, AI_Mode_3_Register);
1805 #else
1806                         win_out(AI_FIFO_Mode_HF, AI_Mode_3_Register);
1807 #endif
1808                         interrupt_a_enable|=AI_STOP_Interrupt_Enable;
1809                         break;
1810                 default:
1811                         break;
1812                 }
1813
1814                 win_out(0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
1815
1816                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
1817
1818                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
1819         }else{
1820                 /* interrupt on nothing */
1821                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
1822
1823                 /* XXX start polling if necessary */
1824                 MDPRINTK("interrupting on nothing\n");
1825         }
1826
1827         /* end configuration */
1828         win_out(AI_Configuration_End,Joint_Reset_Register);
1829
1830         switch(cmd->scan_begin_src){
1831         case TRIG_TIMER:
1832                 win_out(AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
1833                         AI_Command_1_Register);
1834                 break;
1835         case TRIG_EXT:
1836                 /* XXX AI_SI_Arm? */
1837                 win_out(AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
1838                         AI_Command_1_Register);
1839                 break;
1840         }
1841
1842 #ifdef PCIDMA
1843         ni_ai_setup_MITE_dma(dev,cmd);
1844         //mite_dump_regs(devpriv->mite);
1845 #endif
1846
1847         switch(cmd->start_src){
1848         case TRIG_NOW:
1849                 /* AI_START1_Pulse */
1850                 win_out( AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
1851                 s->async->inttrig=NULL;
1852                 break;
1853         case TRIG_EXT:
1854                 s->async->inttrig=NULL;
1855                 break;
1856         case TRIG_INT:
1857                 s->async->inttrig=ni_ai_inttrig;
1858                 break;
1859         }
1860
1861         MDPRINTK("exit ni_ai_cmd\n");
1862
1863         return 0;
1864 }
1865
1866 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
1867         unsigned int trignum)
1868 {
1869         if(trignum!=0)return -EINVAL;
1870
1871         win_out( AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
1872         s->async->inttrig=NULL;
1873
1874         return 1;
1875 }
1876
1877 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
1878         comedi_insn *insn, lsampl_t *data);
1879
1880 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
1881         comedi_insn *insn, lsampl_t *data)
1882 {
1883         if(insn->n<1)return -EINVAL;
1884
1885         switch(data[0]){
1886         case INSN_CONFIG_ANALOG_TRIG:
1887                 return ni_ai_config_analog_trig(dev,s,insn,data);
1888         case INSN_CONFIG_ALT_SOURCE:
1889                 {
1890                 unsigned int calib_source;
1891                 unsigned int calib_source_adjust;
1892
1893                 calib_source = data[1] & 0xf;
1894                 calib_source_adjust = ( data[1] >> 4 ) & 0xff;
1895
1896                 if(calib_source >= 8)
1897                         return -EINVAL;
1898                 devpriv->ai_calib_source = calib_source;
1899                 if(boardtype.reg_type == ni_reg_611x){
1900                         ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
1901                 }
1902                 return 2;
1903                 }
1904         default:
1905                 break;
1906         }
1907
1908         return -EINVAL;
1909 }
1910
1911 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
1912         comedi_insn *insn, lsampl_t *data)
1913 {
1914         unsigned int a,b,modebits;
1915         int err=0;
1916
1917         /* data[1] is flags
1918          * data[2] is analog line
1919          * data[3] is set level
1920          * data[4] is reset level */
1921         if(!boardtype.has_analog_trig)return -EINVAL;
1922         if(insn->n!=5)return -EINVAL;
1923         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
1924                 data[1]&=~(COMEDI_EV_SCAN_BEGIN&0xffff);
1925                 err++;
1926         }
1927         if(data[2]>=boardtype.n_adchan){
1928                 data[2]=boardtype.n_adchan-1;
1929                 err++;
1930         }
1931         if(data[3]>255){ /* a */
1932                 data[3]=255;
1933                 err++;
1934         }
1935         if(data[4]>255){ /* b */
1936                 data[4]=255;
1937                 err++;
1938         }
1939         /*
1940          * 00 ignore
1941          * 01 set
1942          * 10 reset
1943          *
1944          * modes:
1945          *   1 level:                    +b-   +a-
1946          *     high mode                00 00 01 10
1947          *     low mode                 00 00 10 01
1948          *   2 level: (a<b)
1949          *     hysteresis low mode      10 00 00 01
1950          *     hysteresis high mode     01 00 00 10
1951          *     middle mode              10 01 01 10
1952          */
1953
1954         a=data[3];
1955         b=data[4];
1956         modebits=data[1]&0xff;
1957         if(modebits&0xf0){
1958                 /* two level mode */
1959                 if(b<a){
1960                         /* swap order */
1961                         a=data[4];
1962                         b=data[3];
1963                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
1964                 }
1965                 devpriv->atrig_low = a;
1966                 devpriv->atrig_high = b;
1967                 switch(modebits){
1968                 case 0x81:      /* low hysteresis mode */
1969                         devpriv->atrig_mode = 6;
1970                         break;
1971                 case 0x42:      /* high hysteresis mode */
1972                         devpriv->atrig_mode = 3;
1973                         break;
1974                 case 0x96:      /* middle window mode */
1975                         devpriv->atrig_mode = 2;
1976                         break;
1977                 default:
1978                         data[1]&=~0xff;
1979                         err++;
1980                 }
1981         }else{
1982                 /* one level mode */
1983                 if(b!=0){
1984                         data[4]=0;
1985                         err++;
1986                 }
1987                 switch(modebits){
1988                 case 0x06:      /* high window mode */
1989                         devpriv->atrig_high = a;
1990                         devpriv->atrig_mode = 0;
1991                         break;
1992                 case 0x09:      /* low window mode */
1993                         devpriv->atrig_low = a;
1994                         devpriv->atrig_mode = 1;
1995                         break;
1996                 default:
1997                         data[1]&=~0xff;
1998                         err++;
1999                 }
2000         }
2001         if(err)return -EAGAIN;
2002         return 5;
2003 }
2004
2005 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2006 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2007         void *data, unsigned int num_bytes, unsigned int chan_index )
2008 {
2009         comedi_async *async = s->async;
2010         unsigned int range;
2011         unsigned int i;
2012         unsigned int offset;
2013         unsigned int length = num_bytes / sizeof( sampl_t );
2014         sampl_t *array = data;
2015
2016         offset = 1 << (boardtype.aobits - 1);
2017         for(i = 0; i < length; i++)
2018         {
2019                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2020                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2021                         array[i] -= offset;
2022 #ifdef PCIDMA
2023                 array[i] = cpu_to_le16( array[i] );
2024 #endif
2025                 chan_index++;
2026                 chan_index %= async->cmd.chanlist_len;
2027         }
2028 }
2029
2030 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2031         unsigned int chanspec[], unsigned int n_chans)
2032 {
2033         unsigned int range;
2034         unsigned int chan;
2035         unsigned int conf;
2036         int i;
2037         int invert = 0;
2038
2039         for(i=0;i<n_chans;i++){
2040                 chan = CR_CHAN(chanspec[i]);
2041                 range = CR_RANGE(chanspec[i]);
2042
2043                 conf = AO_Channel(chan);
2044
2045                 if(boardtype.ao_unipolar){
2046                         if((range&1) == 0){
2047                                 conf |= AO_Bipolar;
2048                                 invert = (1<<(boardtype.aobits-1));
2049                         }else{
2050                                 invert = 0;
2051                         }
2052                         if(range&2)
2053                                 conf |= AO_Ext_Ref;
2054                 }else{
2055                         conf |= AO_Bipolar;
2056                         invert = (1<<(boardtype.aobits-1));
2057                 }
2058
2059                 /* not all boards can deglitch, but this shouldn't hurt */
2060                 if(chanspec[i] & CR_DEGLITCH)
2061                         conf |= AO_Deglitch;
2062
2063                 /* analog reference */
2064                 /* AREF_OTHER connects AO ground to AI ground, i think */
2065                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2066
2067                 devpriv->ao_conf[chan] = conf;
2068
2069                 ni_writew(conf,AO_Configuration);
2070         }
2071         return invert;
2072 }
2073
2074 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2075         comedi_insn *insn,lsampl_t *data)
2076 {
2077         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2078
2079         return 1;
2080 }
2081
2082 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2083         comedi_insn *insn,lsampl_t *data)
2084 {
2085         unsigned int chan = CR_CHAN(insn->chanspec);
2086         unsigned int invert;
2087
2088         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2089
2090         devpriv->ao[chan] = data[0];
2091
2092         ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2093
2094         return 1;
2095 }
2096
2097 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2098         comedi_insn *insn,lsampl_t *data)
2099 {
2100         unsigned int chan = CR_CHAN(insn->chanspec);
2101         unsigned int invert;
2102
2103         ao_win_out(1 << chan, AO_Immediate_671x);
2104         invert = 1 << (boardtype.aobits - 1);
2105
2106         ni_ao_config_chanlist(dev,s,&insn->chanspec,1);
2107
2108         devpriv->ao[chan] = data[0];
2109         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2110
2111         return 1;
2112 }
2113
2114 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2115         unsigned int trignum)
2116 {
2117         int ret;
2118         int bits;
2119
2120         if(trignum!=0)return -EINVAL;
2121
2122         win_out(devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2123         win_out(devpriv->ao_mode3,AO_Mode_3_Register);
2124
2125         /* wait for DACs to be loaded */
2126         comedi_udelay(100);
2127
2128         win_out(devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2129                 AO_Command_1_Register);
2130
2131         bits = AO_Error_Interrupt_Enable;
2132 #ifdef PCIDMA
2133         win_out(0, DAC_FIFO_Clear);
2134         ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2135         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2136         ret = ni_ao_wait_for_dma_load(dev);
2137         if(ret < 0) return ret;
2138
2139         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable, 0);
2140 #else
2141         ret = ni_ao_prep_fifo(dev,s);
2142         if(ret==0)return -EPIPE;
2143
2144         bits |= AO_FIFO_Interrupt_Enable;
2145 #endif
2146         ni_set_bits(dev, Interrupt_B_Enable_Register, bits, 1);
2147
2148         win_out(devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2149
2150         s->async->inttrig=NULL;
2151
2152         return 0;
2153 }
2154
2155 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2156 {
2157         comedi_cmd *cmd = &s->async->cmd;
2158         int trigvar;
2159         int bits;
2160         int i;
2161
2162         trigvar = ni_ns_to_timer(&cmd->scan_begin_arg,TRIG_ROUND_NEAREST);
2163
2164         win_out(AO_Configuration_Start,Joint_Reset_Register);
2165
2166         win_out(AO_Disarm,AO_Command_1_Register);
2167
2168         if(boardtype.reg_type & ni_reg_6xxx_mask)
2169         {
2170                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2171
2172                 bits = 0;
2173                 for(i = 0; i < cmd->chanlist_len; i++)
2174                 {
2175                         int chan;
2176
2177                         chan = CR_CHAN(cmd->chanlist[i]);
2178                         bits |= 1 << chan;
2179                         ao_win_out(chan, AO_Waveform_Generation_611x);
2180                 }
2181                 ao_win_out(bits, AO_Timed_611x);
2182         }
2183
2184         ni_ao_config_chanlist(dev,s,cmd->chanlist,cmd->chanlist_len);
2185
2186         if(cmd->stop_src==TRIG_NONE){
2187                 devpriv->ao_mode1|=AO_Continuous;
2188                 devpriv->ao_mode1&=~AO_Trigger_Once;
2189         }else{
2190                 devpriv->ao_mode1&=~AO_Continuous;
2191                 devpriv->ao_mode1|=AO_Trigger_Once;
2192         }
2193         win_out(devpriv->ao_mode1,AO_Mode_1_Register);
2194         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2195         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2196         win_out(devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2197         devpriv->ao_mode3&=~AO_Trigger_Length;
2198         win_out(devpriv->ao_mode3,AO_Mode_3_Register);
2199
2200         win_out(devpriv->ao_mode1,AO_Mode_1_Register);
2201         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2202         win_out(devpriv->ao_mode2,AO_Mode_2_Register);
2203         if(cmd->stop_src==TRIG_NONE){
2204                 win_out2(0xffffff,AO_BC_Load_A_Register);
2205         }else{
2206                 win_out2(0,AO_BC_Load_A_Register);
2207         }
2208         win_out(AO_BC_Load,AO_Command_1_Register);
2209         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2210         win_out(devpriv->ao_mode2,AO_Mode_2_Register);
2211         switch(cmd->stop_src){
2212         case TRIG_COUNT:
2213                 win_out2(cmd->stop_arg,AO_UC_Load_A_Register);
2214                 win_out(AO_UC_Load,AO_Command_1_Register);
2215                 win_out2(cmd->stop_arg - 1,AO_UC_Load_A_Register);
2216                 break;
2217         case TRIG_NONE:
2218                 win_out2(0xffffff,AO_UC_Load_A_Register);
2219                 win_out(AO_UC_Load,AO_Command_1_Register);
2220                 win_out2(0xffffff,AO_UC_Load_A_Register);
2221                 break;
2222         default:
2223                 win_out2(0,AO_UC_Load_A_Register);
2224                 win_out(AO_UC_Load,AO_Command_1_Register);
2225                 win_out2(cmd->stop_arg,AO_UC_Load_A_Register);
2226         }
2227
2228         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2229         win_out(devpriv->ao_cmd2,AO_Command_2_Register);
2230         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2231         win_out(devpriv->ao_mode1,AO_Mode_1_Register);
2232         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2233         win_out(devpriv->ao_mode2,AO_Mode_2_Register);
2234         win_out2(1,AO_UI_Load_A_Register);
2235         win_out(AO_UI_Load,AO_Command_1_Register);
2236         win_out2(trigvar,AO_UI_Load_A_Register);
2237
2238         if(boardtype.reg_type == ni_reg_normal){
2239                 if(cmd->scan_end_arg>1){
2240                         devpriv->ao_mode1|=AO_Multiple_Channels;
2241                         win_out(AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2242                                 AO_UPDATE_Output_Select(1),
2243                                 AO_Output_Control_Register);
2244                 }else{
2245                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2246                         win_out(AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]))|
2247                                 AO_UPDATE_Output_Select(1),
2248                                 AO_Output_Control_Register);
2249                 }
2250                 win_out(devpriv->ao_mode1,AO_Mode_1_Register);
2251         }
2252
2253         win_out(AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2254
2255         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2256         win_out(devpriv->ao_mode3,AO_Mode_3_Register);
2257
2258         devpriv->ao_mode2 &= AO_FIFO_Mode_Mask;
2259 #ifdef PCIDMA
2260         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2261 #else
2262         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2263 #endif
2264         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2265         win_out(devpriv->ao_mode2,AO_Mode_2_Register);
2266
2267         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2268                 AO_TMRDACWR_Pulse_Width;
2269         if( boardtype.ao_fifo_depth )
2270                 bits |= AO_FIFO_Enable;
2271         win_out(bits, AO_Personal_Register);
2272         // enable sending of ao dma requests
2273         win_out(AO_AOFREQ_Enable, AO_Start_Select_Register);
2274
2275         win_out(AO_Configuration_End,Joint_Reset_Register);
2276
2277         if(cmd->stop_src==TRIG_COUNT) {
2278                 win_out(AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2279                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2280                         AO_BC_TC_Interrupt_Enable, 1);
2281         }
2282
2283         s->async->inttrig=ni_ao_inttrig;
2284
2285         return 0;
2286 }
2287
2288 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2289 {
2290         int err=0;
2291         int tmp;
2292
2293         /* step 1: make sure trigger sources are trivially valid */
2294
2295         tmp=cmd->start_src;
2296         cmd->start_src &= TRIG_INT;
2297         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2298
2299         tmp=cmd->scan_begin_src;
2300         cmd->scan_begin_src &= TRIG_TIMER;
2301         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2302
2303         tmp=cmd->convert_src;
2304         cmd->convert_src &= TRIG_NOW;
2305         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2306
2307         tmp=cmd->scan_end_src;
2308         cmd->scan_end_src &= TRIG_COUNT;
2309         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2310
2311         tmp=cmd->stop_src;
2312         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2313         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2314
2315         if(err)return 1;
2316
2317         /* step 2: make sure trigger sources are unique and mutually compatible */
2318
2319         if(cmd->stop_src!=TRIG_COUNT &&
2320            cmd->stop_src!=TRIG_NONE)err++;
2321
2322         if(err)return 2;
2323
2324         /* step 3: make sure arguments are trivially compatible */
2325
2326         if(cmd->start_arg!=0){
2327                 cmd->start_arg=0;
2328                 err++;
2329         }
2330 #if 0
2331         /* XXX need ao_speed */
2332         if(cmd->scan_begin_arg<boardtype.ao_speed){
2333                 cmd->scan_begin_arg=boardtype.ao_speed;
2334                 err++;
2335         }
2336 #endif
2337         if(cmd->scan_begin_arg>TIMER_BASE*0xffffff){ /* XXX check */
2338                 cmd->scan_begin_arg=TIMER_BASE*0xffffff;
2339                 err++;
2340         }
2341         if(cmd->convert_arg!=0){
2342                 cmd->convert_arg=0;
2343                 err++;
2344         }
2345         if(cmd->scan_end_arg!=cmd->chanlist_len){
2346                 cmd->scan_end_arg=cmd->chanlist_len;
2347                 err++;
2348         }
2349         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2350                 if(cmd->stop_arg>0x00ffffff){
2351                         cmd->stop_arg=0x00ffffff;
2352                         err++;
2353                 }
2354         }else{
2355                 /* TRIG_NONE */
2356                 if(cmd->stop_arg!=0){
2357                         cmd->stop_arg=0;
2358                         err++;
2359                 }
2360         }
2361
2362         if(err)return 3;
2363
2364         /* step 4: fix up any arguments */
2365
2366         tmp = cmd->scan_begin_arg;
2367         ni_ns_to_timer(&cmd->scan_begin_arg,cmd->flags&TRIG_ROUND_MASK);
2368         if(tmp!=cmd->scan_begin_arg)err++;
2369
2370         if(err)return 4;
2371
2372         /* step 5: fix up chanlist */
2373
2374         if(cmd->chanlist_len != cmd->scan_end_arg){
2375                 cmd->chanlist_len = cmd->scan_end_arg;
2376                 err++;
2377         }
2378
2379         if(err)return 5;
2380
2381         return 0;
2382 }
2383
2384
2385 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2386 {
2387         //devpriv->ao0p=0x0000;
2388         //ni_writew(devpriv->ao0p,AO_Configuration);
2389
2390         //devpriv->ao1p=AO_Channel(1);
2391         //ni_writew(devpriv->ao1p,AO_Configuration);
2392
2393 #ifdef PCIDMA
2394         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2395         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR +
2396                 CHAN_OFFSET(AO_DMA_CHAN));
2397 #endif
2398
2399         win_out(AO_Configuration_Start,Joint_Reset_Register);
2400         win_out(AO_Disarm,AO_Command_1_Register);
2401         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2402         win_out(0x0010,AO_Personal_Register);
2403         win_out(0x3f98,Interrupt_B_Ack_Register);
2404         win_out(AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2405                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2406         win_out(0,AO_Output_Control_Register);
2407         win_out(0,AO_Start_Select_Register);
2408         devpriv->ao_cmd1=0;
2409         win_out(devpriv->ao_cmd1,AO_Command_1_Register);
2410         devpriv->ao_cmd2=0;
2411         devpriv->ao_mode1=0;
2412         devpriv->ao_mode2=0;
2413         devpriv->ao_mode3=0;
2414         devpriv->ao_trigger_select=0;
2415         if(boardtype.reg_type & ni_reg_6xxx_mask){
2416                 ao_win_out(0x3, AO_Immediate_671x);
2417                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2418         }
2419
2420         return 0;
2421 }
2422
2423 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2424         comedi_insn *insn,lsampl_t *data)
2425 {
2426 #ifdef DEBUG_DIO
2427         printk("ni_dio_insn_config() chan=%d io=%d\n",
2428                 CR_CHAN(insn->chanspec),data[0]);
2429 #endif
2430         if(insn->n!=1)return -EINVAL;
2431         switch(data[0]){
2432         case COMEDI_OUTPUT:
2433                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2434                 break;
2435         case COMEDI_INPUT:
2436                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2437                 break;
2438         default:
2439                 return -EINVAL;
2440         }
2441
2442         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2443         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2444         win_out(devpriv->dio_control,DIO_Control_Register);
2445
2446         return 1;
2447 }
2448
2449 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2450         comedi_insn *insn,lsampl_t *data)
2451 {
2452 #ifdef DEBUG_DIO
2453         printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2454 #endif
2455         if(insn->n!=2)return -EINVAL;
2456         if(data[0]){
2457                 /* Perform check to make sure we're not using the
2458                    serial part of the dio */
2459                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2460                         return -EBUSY;
2461
2462                 s->state &= ~data[0];
2463                 s->state |= (data[0]&data[1]);
2464                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2465                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2466                 win_out(devpriv->dio_output,DIO_Output_Register);
2467         }
2468         data[1] = win_in(DIO_Parallel_Input_Register);
2469
2470         return 2;
2471 }
2472
2473 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2474                                  comedi_insn *insn,lsampl_t *data)
2475 {
2476         int err = insn->n;
2477         unsigned char byte_out, byte_in;
2478
2479         if(insn->n!=2)return -EINVAL;
2480
2481         switch(data[0]) {
2482         case INSN_CONFIG_SERIAL_CLOCK:
2483
2484 #ifdef DEBUG_DIO
2485                 printk("SPI serial clock Config cd\n", data[1]);
2486 #endif
2487                 devpriv->serial_hw_mode = 1;
2488                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2489
2490                 if(data[1] == SERIAL_DISABLED) {
2491                         devpriv->serial_hw_mode = 0;
2492                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2493                                                   DIO_Software_Serial_Control);
2494                         data[1] = SERIAL_DISABLED;
2495                         devpriv->serial_interval_ns = data[1];
2496                 }
2497                 else if(data[1] <= SERIAL_600NS) {
2498                         /* Warning: this clock speed is too fast to reliably
2499                         control SCXI. */
2500                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2501                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2502                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2503                         data[1] = SERIAL_600NS;
2504                         devpriv->serial_interval_ns = data[1];
2505                 }
2506                 else if(data[1] <= SERIAL_1_2US) {
2507                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2508                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2509                                 DIO_Serial_Out_Divide_By_2;
2510                         data[1] = SERIAL_1_2US;
2511                         devpriv->serial_interval_ns = data[1];
2512                 }
2513                 else if(data[1] <= SERIAL_10US) {
2514                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2515                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2516                                 DIO_Serial_Out_Divide_By_2;
2517                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2518                         600ns/1.2us. If you turn divide_by_2 off with the
2519                         slow clock, you will still get 10us, except then
2520                         all your delays are wrong. */
2521                         data[1] = SERIAL_10US;
2522                         devpriv->serial_interval_ns = data[1];
2523                 }
2524                 else {
2525                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2526                                                   DIO_Software_Serial_Control);
2527                         devpriv->serial_hw_mode = 0;
2528                         data[1] = (data[1] / 1000) * 1000;
2529                         devpriv->serial_interval_ns = data[1];
2530                 }
2531
2532                 win_out(devpriv->dio_control,DIO_Control_Register);
2533                 win_out(devpriv->clock_and_fout,Clock_and_FOUT_Register);
2534                 return 1;
2535
2536         break;
2537
2538         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2539
2540                 if(devpriv->serial_interval_ns == 0) {
2541                         return -EINVAL;
2542                 }
2543
2544                 byte_out = data[1] & 0xFF;
2545
2546                 if(devpriv->serial_hw_mode) {
2547                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2548                 } else if(devpriv->serial_interval_ns > 0) {
2549                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2550                 } else {
2551                         printk("ni_serial_insn_config: serial disabled!\n");
2552                         return -EINVAL;
2553                 }
2554                 if(err < 0) return err;
2555                 data[1] = byte_in & 0xFF;
2556                 return insn->n;
2557
2558         break;
2559         default:
2560                 return -EINVAL;
2561         }
2562
2563 }
2564
2565 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2566                                    unsigned char data_out,
2567                                    unsigned char *data_in)
2568 {
2569         unsigned int status1;
2570         int err = 0, count = 20;
2571
2572 #ifdef DEBUG_DIO
2573         printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
2574 #endif
2575
2576         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
2577         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
2578         win_out(devpriv->dio_output,DIO_Output_Register);
2579
2580         status1 = win_in(Joint_Status_1_Register);
2581         if(status1 & DIO_Serial_IO_In_Progress_St) {
2582                 err = -EBUSY;
2583                 goto Error;
2584         }
2585
2586         devpriv->dio_control |= DIO_HW_Serial_Start;
2587         win_out(devpriv->dio_control,DIO_Control_Register);
2588         devpriv->dio_control &= ~DIO_HW_Serial_Start;
2589
2590         /* Wait until STC says we're done, but don't loop infinitely. Also,
2591            we don't have to keep updating the window address for this. */
2592
2593         while((status1 = win_in(Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
2594                 /* Delay one bit per loop */
2595                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2596                 if(--count < 0) {
2597                         printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
2598                         err = -ETIME;
2599                         goto Error;
2600                 }
2601         }
2602
2603         /* Delay for last bit. This delay is absolutely necessary, because
2604            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
2605         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2606
2607         if(data_in != NULL) {
2608                 *data_in = win_in(DIO_Serial_Input_Register);
2609 #ifdef DEBUG_DIO
2610                 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
2611 #endif
2612         }
2613
2614  Error:
2615         win_out(devpriv->dio_control,DIO_Control_Register);
2616
2617         return err;
2618 }
2619
2620 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2621                                    unsigned char data_out,
2622                                    unsigned char *data_in)
2623 {
2624         unsigned char mask, input = 0;
2625
2626 #ifdef DEBUG_DIO
2627         printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
2628 #endif
2629
2630         /* Wait for one bit before transfer */
2631         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
2632
2633         for(mask = 0x80; mask; mask >>= 1) {
2634                 /* Output current bit; note that we cannot touch s->state
2635            because it is a per-subdevice field, and serial is
2636                    a separate subdevice from DIO. */
2637                 devpriv->dio_output &= ~DIO_SDOUT;
2638                 if(data_out & mask) {
2639                         devpriv->dio_output |= DIO_SDOUT;
2640                 }
2641                 win_out(devpriv->dio_output,DIO_Output_Register);
2642
2643                 /* Assert SDCLK (active low, inverted), wait for half of
2644                    the delay, deassert SDCLK, and wait for the other half. */
2645                 devpriv->dio_control |= DIO_Software_Serial_Control;
2646                 win_out(devpriv->dio_control,DIO_Control_Register);
2647
2648                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
2649
2650                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
2651                 win_out(devpriv->dio_control,DIO_Control_Register);
2652
2653                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
2654
2655                 /* Input current bit */
2656                 if(win_in(DIO_Parallel_Input_Register) & DIO_SDIN) {
2657 /*                      printk("DIO_P_I_R: 0x%x\n", win_in(DIO_Parallel_Input_Register)); */
2658                         input |= mask;
2659                 }
2660         }
2661 #ifdef DEBUG_DIO
2662         printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
2663 #endif
2664         if(data_in) *data_in = input;
2665
2666         return 0;
2667 }
2668
2669 static void mio_common_detach(comedi_device *dev)
2670 {
2671         if(dev->subdevices && boardtype.has_8255)
2672                 subdev_8255_cleanup(dev,dev->subdevices+3);
2673 }
2674
2675 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
2676 {
2677         int i;
2678
2679         for(i = 0; i < s->n_chan; i++)
2680                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
2681 }
2682
2683 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
2684 {
2685         comedi_subdevice *s;
2686         int bits;
2687
2688         if(alloc_subdevices(dev, 10) < 0)
2689                 return -ENOMEM;
2690
2691         /* analog input subdevice */
2692
2693         s=dev->subdevices+0;
2694         dev->read_subdev=s;
2695         if(boardtype.n_adchan){
2696                 s->type=COMEDI_SUBD_AI;
2697                 s->subdev_flags=SDF_READABLE|SDF_DIFF;
2698                 if(boardtype.reg_type == ni_reg_normal)
2699                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
2700                 s->subdev_flags|=SDF_DITHER;
2701                 s->n_chan=boardtype.n_adchan;
2702                 s->len_chanlist=512;
2703                 s->maxdata=(1<<boardtype.adbits)-1;
2704                 s->range_table=ni_range_lkup[boardtype.gainlkup];
2705                 s->insn_read=ni_ai_insn_read;
2706                 s->insn_config=ni_ai_insn_config;
2707                 s->do_cmdtest=ni_ai_cmdtest;
2708                 s->do_cmd=ni_ai_cmd;
2709                 s->cancel=ni_ai_reset;
2710                 s->poll=ni_ai_poll;
2711                 s->munge=ni_ai_munge;
2712         }else{
2713                 s->type=COMEDI_SUBD_UNUSED;
2714         }
2715
2716         /* analog output subdevice */
2717
2718         s=dev->subdevices+1;
2719         if(boardtype.n_aochan){
2720                 dev->write_subdev=s;
2721                 s->type=COMEDI_SUBD_AO;
2722                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
2723                 s->n_chan=boardtype.n_aochan;
2724                 s->maxdata=(1<<boardtype.aobits)-1;
2725                 if(boardtype.ao_unipolar){
2726                         s->range_table=&range_ni_E_ao_ext;      /* XXX wrong for some boards */
2727                 }else{
2728                         s->range_table=&range_bipolar10;
2729                 }
2730                 s->insn_read=ni_ao_insn_read;
2731                 if(boardtype.reg_type & ni_reg_6xxx_mask){
2732                         s->insn_write=ni_ao_insn_write_671x;
2733                 }else{
2734                         s->insn_write=ni_ao_insn_write;
2735                 }
2736                 if(boardtype.ao_fifo_depth){
2737                         s->do_cmd=ni_ao_cmd;
2738                         s->do_cmdtest=ni_ao_cmdtest;
2739                         s->len_chanlist = 2;
2740                         s->munge=ni_ao_munge;
2741                 }
2742                 s->cancel=ni_ao_reset;
2743         }else{
2744                 s->type=COMEDI_SUBD_UNUSED;
2745         }
2746         if((boardtype.reg_type & ni_reg_67xx_mask))
2747                 init_ao_67xx(dev, s);
2748
2749         /* digital i/o subdevice */
2750
2751         s=dev->subdevices+2;
2752         s->type=COMEDI_SUBD_DIO;
2753         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
2754         s->n_chan=8;
2755         s->maxdata=1;
2756         s->range_table=&range_digital;
2757         s->io_bits=0;           /* all bits input */
2758         s->insn_bits=ni_dio_insn_bits;
2759         s->insn_config=ni_dio_insn_config;
2760
2761         /* dio setup */
2762         devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
2763         win_out(devpriv->dio_control,DIO_Control_Register);
2764
2765         /* 8255 device */
2766         s=dev->subdevices+3;
2767         if(boardtype.has_8255){
2768                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
2769         }else{
2770                 s->type=COMEDI_SUBD_UNUSED;
2771         }
2772
2773         /* general purpose counter/timer device */
2774         s=dev->subdevices+4;
2775         s->type=COMEDI_SUBD_COUNTER;
2776         s->subdev_flags=SDF_READABLE|SDF_WRITABLE;
2777         s->insn_read=  ni_gpct_insn_read;
2778         s->insn_write= ni_gpct_insn_write;
2779         s->insn_config=ni_gpct_insn_config;
2780         s->n_chan=2;
2781         s->maxdata=1;
2782         devpriv->an_trig_etc_reg = 0;
2783         GPCT_Reset(dev,0);
2784         GPCT_Reset(dev,1);
2785
2786         /* calibration subdevice -- ai and ao */
2787         s=dev->subdevices+5;
2788         s->type=COMEDI_SUBD_CALIB;
2789         s->subdev_flags=SDF_WRITABLE|SDF_INTERNAL;
2790         s->insn_read=ni_calib_insn_read;
2791         s->insn_write=ni_calib_insn_write;
2792         caldac_setup(dev,s);
2793
2794         /* EEPROM */
2795         s=dev->subdevices+6;
2796         s->type=COMEDI_SUBD_MEMORY;
2797         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
2798         s->n_chan=512;
2799         s->maxdata=0xff;
2800         s->insn_read=ni_eeprom_insn_read;
2801
2802         /* PFI */
2803         s=dev->subdevices+7;
2804         s->type=COMEDI_SUBD_DIO;
2805         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
2806         s->n_chan=10;
2807         s->maxdata=1;
2808         s->insn_bits = ni_pfi_insn_bits;
2809         s->insn_config = ni_pfi_insn_config;
2810         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
2811
2812         /* cs5529 calibration adc */
2813         s = dev->subdevices + 8;
2814         if(boardtype.reg_type & ni_reg_67xx_mask)
2815         {
2816                 s->type = COMEDI_SUBD_AI;
2817                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
2818                 // one channel for each analog output channel
2819                 s->n_chan = boardtype.n_aochan;
2820                 s->maxdata = (1 << 16) - 1;
2821                 s->range_table = &range_unknown; /* XXX */
2822                 s->insn_read=cs5529_ai_insn_read;
2823                 s->insn_config=NULL;
2824                 init_cs5529(dev);
2825         }else
2826         {
2827                 s->type=COMEDI_SUBD_UNUSED;
2828         }
2829
2830         /* Serial */
2831         s=dev->subdevices+9;
2832         s->type=COMEDI_SUBD_SERIAL;
2833         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
2834         s->n_chan=1;
2835         s->maxdata=0xff;
2836         s->insn_config = ni_serial_insn_config;
2837         devpriv->serial_interval_ns = 0;
2838         devpriv->serial_hw_mode = 0;
2839
2840         /* ai configuration */
2841         ni_ai_reset(dev,dev->subdevices+0);
2842         if(boardtype.reg_type == ni_reg_normal){
2843                 devpriv->clock_and_fout =
2844                         Slow_Internal_Time_Divide_By_2 |
2845                         Slow_Internal_Timebase |
2846                         Clock_To_Board_Divide_By_2 |
2847                         Clock_To_Board |
2848                         AI_Output_Divide_By_2 |
2849                         AO_Output_Divide_By_2;
2850         }else{
2851                 devpriv->clock_and_fout =
2852                         Slow_Internal_Time_Divide_By_2 |
2853                         Slow_Internal_Timebase |
2854                         Clock_To_Board_Divide_By_2 |
2855                         Clock_To_Board;
2856         }
2857         win_out(devpriv->clock_and_fout, Clock_and_FOUT_Register);
2858
2859         /* analog output configuration */
2860         ni_ao_reset(dev,dev->subdevices + 1);
2861
2862         if(dev->irq){
2863                 win_out((IRQ_POLARITY?Interrupt_Output_Polarity:0) |
2864                         (Interrupt_Output_On_3_Pins&0) |
2865                         Interrupt_A_Enable |
2866                         Interrupt_B_Enable |
2867                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
2868                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
2869                         Interrupt_Control_Register
2870                 );
2871         }
2872
2873         /* DMA setup */
2874         /* tell the STC which dma channels to use for AI and AO */
2875         bits = 1 << ( AI_DMA_CHAN );
2876         bits |= 1 << ( AO_DMA_CHAN + 4 );
2877         ni_writeb( bits, AI_AO_Select);
2878         /* tell the STC which dma channels to use for
2879          * General purpose counters 0 and 1 */
2880         bits = 1 << ( GPC0_DMA_CHAN );
2881         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
2882         ni_writeb( bits, G0_G1_Select);
2883
2884         /* 611x init */
2885         if(boardtype.reg_type != ni_reg_normal)
2886         {
2887                 ni_writeb( 0, Magic_611x );
2888         }
2889
2890         printk("\n");
2891
2892         return 0;
2893 }
2894
2895
2896
2897 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
2898 {
2899         comedi_device *dev=(comedi_device *)arg;
2900
2901         if(dir){
2902                 ni_writeb(data,Port_A+2*port);
2903                 return 0;
2904         }else{
2905                 return ni_readb(Port_A+2*port);
2906         }
2907 }
2908
2909 /*
2910         presents the EEPROM as a subdevice
2911 */
2912
2913 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
2914         comedi_insn *insn,lsampl_t *data)
2915 {
2916         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
2917
2918         return 1;
2919 }
2920
2921 /*
2922         reads bytes out of eeprom
2923 */
2924
2925 static int ni_read_eeprom(comedi_device *dev,int addr)
2926 {
2927         int bit;
2928         int bitstring;
2929
2930         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
2931         ni_writeb(0x04,Serial_Command);
2932         for(bit=0x8000;bit;bit>>=1){
2933                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
2934                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
2935         }
2936         bitstring=0;
2937         for(bit=0x80;bit;bit>>=1){
2938                 ni_writeb(0x04,Serial_Command);
2939                 ni_writeb(0x05,Serial_Command);
2940                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
2941         }
2942         ni_writeb(0x00,Serial_Command);
2943
2944         return bitstring;
2945 }
2946
2947 static void ni_write_caldac(comedi_device *dev,int addr,int val);
2948 /*
2949         calibration subdevice
2950 */
2951 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
2952         comedi_insn *insn,lsampl_t *data)
2953 {
2954         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
2955
2956         return 1;
2957 }
2958
2959 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
2960         comedi_insn *insn,lsampl_t *data)
2961 {
2962         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
2963
2964         return 1;
2965 }
2966
2967 static int pack_mb88341(int addr,int val,int *bitstring);
2968 static int pack_dac8800(int addr,int val,int *bitstring);
2969 static int pack_dac8043(int addr,int val,int *bitstring);
2970 static int pack_ad8522(int addr,int val,int *bitstring);
2971 static int pack_ad8804(int addr,int val,int *bitstring);
2972 static int pack_ad8842(int addr,int val,int *bitstring);
2973
2974 struct caldac_struct{
2975         int n_chans;
2976         int n_bits;
2977         int (*packbits)(int,int,int *);
2978 };
2979
2980 static struct caldac_struct caldacs[] = {
2981         [mb88341] = { 12, 8, pack_mb88341 },
2982         [dac8800] = { 8, 8, pack_dac8800 },
2983         [dac8043] = { 1, 12, pack_dac8043 },
2984         [ad8522]  = { 2, 12, pack_ad8522 },
2985         [ad8804] = { 12, 8, pack_ad8804 },
2986         [ad8842] = { 8, 8, pack_ad8842 },
2987         [ad8804_debug] = { 16, 8, pack_ad8804 },
2988 };
2989
2990 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
2991 {
2992         int i,j;
2993         int n_dacs;
2994         int n_chans=0;
2995         int n_bits;
2996         int diffbits=0;
2997         int type;
2998         int chan;
2999
3000         type = boardtype.caldac[0];
3001         if(type==caldac_none)return;
3002         n_bits=caldacs[type].n_bits;
3003         for(i=0;i<3;i++){
3004                 type = boardtype.caldac[i];
3005                 if(type==caldac_none)break;
3006                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3007                 n_chans+=caldacs[type].n_chans;
3008         }
3009         n_dacs=i;
3010         s->n_chan=n_chans;
3011
3012         if(diffbits){
3013
3014                 if(n_chans>MAX_N_CALDACS){
3015                         printk("BUG! MAX_N_CALDACS too small\n");
3016                 }
3017                 s->maxdata_list=devpriv->caldac_maxdata_list;
3018                 chan=0;
3019                 for(i=0;i<n_dacs;i++){
3020                         type = boardtype.caldac[i];
3021                         for(j=0;j<caldacs[type].n_chans;j++){
3022                                 s->maxdata_list[chan]=
3023                                         (1<<caldacs[type].n_bits)-1;
3024                                 chan++;
3025                         }
3026                 }
3027
3028                 for( chan = 0; chan < s->n_chan; chan++ )
3029                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3030         }else{
3031                 type = boardtype.caldac[0];
3032                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3033
3034                 for( chan = 0; chan < s->n_chan; chan++ )
3035                         ni_write_caldac( dev, i, s->maxdata / 2 );
3036         }
3037 }
3038
3039 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3040 {
3041         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3042         int i;
3043         int type;
3044
3045         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3046         if( devpriv->caldacs[ addr ] == val ) return;
3047         devpriv->caldacs[ addr ] = val;
3048
3049         for(i=0;i<3;i++){
3050                 type = boardtype.caldac[i];
3051                 if(type==caldac_none)break;
3052                 if(addr<caldacs[type].n_chans){
3053                         bits=caldacs[type].packbits(addr,val,&bitstring);
3054                         loadbit=SerDacLd(i);
3055                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3056                         break;
3057                 }
3058                 addr-=caldacs[type].n_chans;
3059         }
3060
3061         for(bit=1<<(bits-1);bit;bit>>=1){
3062                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3063                 comedi_udelay(1);
3064                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3065                 comedi_udelay(1);
3066         }
3067         ni_writeb(loadbit,Serial_Command);
3068         comedi_udelay(1);
3069         ni_writeb(0,Serial_Command);
3070 }
3071
3072
3073
3074 static int pack_mb88341(int addr,int val,int *bitstring)
3075 {
3076         /*
3077            Fujitsu MB 88341
3078            Note that address bits are reversed.  Thanks to
3079            Ingo Keen for noticing this.
3080
3081            Note also that the 88341 expects address values from
3082            1-12, whereas we use channel numbers 0-11.  The NI
3083            docs use 1-12, also, so be careful here.
3084         */
3085         addr++;
3086         *bitstring=((addr&0x1)<<11) |
3087                   ((addr&0x2)<<9)  |
3088                   ((addr&0x4)<<7)  |
3089                   ((addr&0x8)<<5)  |
3090                   (val&0xff);
3091         return 12;
3092 }
3093
3094 static int pack_dac8800(int addr,int val,int *bitstring)
3095 {
3096         *bitstring=((addr&0x7)<<8)|(val&0xff);
3097         return 11;
3098 }
3099
3100 static int pack_dac8043(int addr,int val,int *bitstring)
3101 {
3102         *bitstring=val&0xfff;
3103         return 12;
3104 }
3105
3106 static int pack_ad8522(int addr,int val,int *bitstring)
3107 {
3108         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3109         return 16;
3110 }
3111
3112 static int pack_ad8804(int addr,int val,int *bitstring)
3113 {
3114         *bitstring=((addr&0xf)<<8) | (val&0xff);
3115         return 12;
3116 }
3117
3118 static int pack_ad8842(int addr,int val,int *bitstring)
3119 {
3120         *bitstring=((addr+1)<<8) | (val&0xff);
3121         return 12;
3122 }
3123
3124
3125
3126
3127
3128 /*
3129  *
3130  *  General Purpose Counter/Timer section
3131  *
3132  */
3133
3134 /*
3135  * Low level stuff...Each STC counter has two 24 bit load registers
3136  * (A&B).  Just make it easier to access them.
3137  *
3138  * These are inlined _only_ because they are used once in subsequent
3139  * code.  Otherwise they should not be inlined.
3140  */
3141 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3142 {
3143         win_out2( value & 0x00ffffff, G_Load_A_Register(chan));
3144 }
3145
3146 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3147 {
3148         win_out2( value & 0x00ffffff, G_Load_B_Register(chan));
3149 }
3150
3151 /*  Load a value into the counter, using register A as the intermediate step.
3152 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3153 *  reset its value.
3154 */
3155 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3156 {
3157         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3158         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3159         GPCT_Load_A(dev,chan,value);
3160         win_out( devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3161 }
3162
3163 /*
3164  *      Read the GPCTs current value.
3165  */
3166 static int GPCT_G_Watch(comedi_device *dev, int chan)
3167 {
3168         unsigned int hi1,hi2,lo;
3169
3170         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3171         win_out( devpriv->gpct_command[chan],G_Command_Register(chan));
3172
3173         devpriv->gpct_command[chan] |= G_Save_Trace;
3174         win_out( devpriv->gpct_command[chan], G_Command_Register(chan));
3175
3176         /* This procedure is used because the two registers cannot
3177          * be read atomically. */
3178         do{
3179                 hi1 = win_in( G_Save_Register_High(chan));
3180                 lo = win_in(G_Save_Register_Low(chan));
3181                 hi2 = win_in( G_Save_Register_High(chan));
3182         }while(hi1!=hi2);
3183
3184         return (hi1<<16)|lo;
3185 }
3186
3187
3188 static int GPCT_Disarm(comedi_device *dev, int chan)
3189 {
3190         win_out( devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3191         return 0;
3192 }
3193
3194
3195 static int GPCT_Arm(comedi_device *dev, int chan)
3196 {
3197         win_out( devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3198         /* If the counter is doing pulse width measurement, then make
3199          sure that the counter did not start counting right away.  This would
3200          indicate that we started acquiring the pulse after it had already
3201          started and our measurement would be inaccurate */
3202         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3203                 int g_status;
3204
3205                 g_status=win_in(G_Status_Register);
3206
3207                 if(chan == 0){
3208                         //TIM 5/2/01 possible error with very short pulses
3209                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3210                                 //error: we missed the beginning of the pulse
3211                                 return -EINVAL; //there is probably a more accurate error code...
3212                         }
3213                 }else{
3214                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3215                                 //error: we missed the beginning of the pulse
3216                                 return -EINVAL;
3217                         }
3218                 }
3219         }
3220         return 0;
3221 }
3222
3223 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3224 {
3225         //printk("GPCT_Set_Source...");
3226         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3227         switch(source) {
3228                 case GPCT_INT_CLOCK:
3229                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3230                 break;
3231         case GPCT_EXT_PIN:
3232                 if(chan==0)
3233                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3234                 else
3235                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3236                 break;
3237         default:
3238                 return -EINVAL;
3239         }
3240         win_out(devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3241         //printk("exit GPCT_Set_Source\n");
3242         return 0;
3243 }
3244
3245 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3246 {
3247         //printk("GPCT_Set_Gate...");
3248         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3249         switch(gate) {
3250         case GPCT_NO_GATE:
3251                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3252                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3253                 break;
3254         case GPCT_EXT_PIN:
3255                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3256                 if(chan==0){
3257                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3258                 }else{
3259                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3260                 }
3261                 break;
3262         default:
3263                 return -EINVAL;
3264         }
3265         win_out(devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3266         win_out(devpriv->gpct_mode[chan], G_Mode_Register(chan));
3267         //printk("exit GPCT_Set_Gate\n");
3268         return 0;
3269 }
3270
3271 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3272 {
3273         //printk("GPCT_Set_Direction...");
3274
3275         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3276         switch (direction) {
3277                 case GPCT_UP:
3278                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3279                         break;
3280                 case GPCT_DOWN:
3281                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3282                         break;
3283                 case GPCT_HWUD:
3284                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3285                         break;
3286                 default:
3287                         printk("Error direction=0x%08x..",direction);
3288                         return -EINVAL;
3289         }
3290         win_out(devpriv->gpct_command[chan], G_Command_Register(chan));
3291         //TIM 4/23/01 win_out(devpriv->gpct_mode[chan], G_Mode_Register(chan));
3292         //printk("exit GPCT_Set_Direction\n");
3293         return 0;
3294 }
3295
3296 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3297 {
3298
3299         //NOTE: possible residual bits from multibit masks can corrupt
3300         //If you config for several measurements between Resets, watch out!
3301
3302         //printk("GPCT_Event_Counting...");
3303
3304         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3305
3306         // Gating_Mode = 1
3307         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3308         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3309
3310         // Trigger_Mode_For_Edge_Gate = 1
3311         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3312         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3313
3314         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3315         //printk("exit GPCT_Event_Counting\n");
3316 }
3317
3318 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3319 {
3320         //printk("GPCT_Period_Meas...");
3321
3322         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3323
3324
3325         //NOTE: possible residual bits from multibit masks can corrupt
3326         //If you config for several measurements between Resets, watch out!
3327         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3328         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3329
3330         // Output_Mode = 3
3331         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3332         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3333
3334
3335         //Gating Mode=2
3336         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3337         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
3338
3339         // Trigger_Mode_For_Edge_Gate=0
3340         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3341         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
3342
3343         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3344         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3345         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3346         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3347
3348         // Stop_Mode = 2
3349         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3350         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3351
3352         // Counting_Once = 2
3353         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3354         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3355
3356         // Up_Down = 1
3357         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3358         devpriv->gpct_command[chan] |= G_Up_Down(1);
3359
3360         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3361         win_out( devpriv->gpct_command[chan],G_Command_Register(chan));
3362         //printk("exit GPCT_Period_Meas\n");
3363 }
3364
3365 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
3366 {
3367         //printk("GPCT_Pulse_Width_Meas...");
3368
3369         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
3370
3371         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3372         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3373
3374         // Output_Mode = 3
3375         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3376         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3377
3378         //Gating Mode=1
3379         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3380         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
3381
3382         // Trigger_Mode_For_Edge_Gate=2
3383         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3384         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
3385
3386
3387         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
3388         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
3389
3390         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3391         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3392
3393         // Stop_Mode = 0
3394         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3395         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3396
3397         // Counting_Once = 2
3398         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3399         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3400
3401         // Up_Down = 1
3402         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3403         devpriv->gpct_command[chan] |= G_Up_Down(1);
3404
3405         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3406         win_out( devpriv->gpct_command[chan],G_Command_Register(chan));
3407
3408         //printk("exit GPCT_Pulse_Width_Meas\n");
3409 }
3410
3411 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
3412 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
3413 be modified to send a pulse in response to a trigger event at its gate.*/
3414 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
3415 {
3416         //printk("GPCT_Gen_Cont...");
3417
3418         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
3419
3420         // Set length of the pulse
3421         GPCT_Load_B(dev,chan, length-1);
3422
3423         //Load next time using B, This is reset by GPCT_Load_Using_A()
3424         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
3425
3426         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3427         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3428
3429         // Output_Mode = 3
3430         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3431         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
3432
3433         //Gating Mode=0 for untriggered single pulse
3434         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3435         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
3436
3437         // Trigger_Mode_For_Edge_Gate=0
3438         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3439         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3440
3441
3442         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3443         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3444         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
3445         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3446
3447         // Stop_Mode = 2
3448         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3449         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
3450
3451         // Counting_Once = 2
3452         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3453         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
3454
3455         // Up_Down = 1
3456         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3457         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
3458
3459         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3460         win_out( devpriv->gpct_command[chan],G_Command_Register(chan));
3461
3462         //printk("exit GPCT_Gen_Cont\n");
3463 }
3464
3465 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
3466 {
3467         //printk("GPCT_Gen_Cont...");
3468
3469         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
3470
3471         // Set length of the pulse
3472         GPCT_Load_B(dev,chan, length-1);
3473
3474         //Load next time using B, This is reset by GPCT_Load_Using_A()
3475         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
3476
3477         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3478         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3479
3480         // Output_Mode = 3
3481         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3482         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
3483
3484         //Gating Mode=0 for untriggered single pulse
3485         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3486         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
3487
3488         // Trigger_Mode_For_Edge_Gate=0
3489         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3490         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3491
3492
3493         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3494         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3495         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
3496         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3497
3498         // Stop_Mode = 2
3499         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3500         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
3501
3502         // Counting_Once = 2
3503         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3504         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
3505
3506         // Up_Down = 1
3507         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3508         devpriv->gpct_command[chan] |= G_Up_Down(0);
3509
3510         //TIM 4/26/01
3511         //This seems pretty unsafe since I don't think it is cleared anywhere.
3512         //I don't think this is working
3513         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
3514         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
3515
3516
3517         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3518         win_out( devpriv->gpct_command[chan],G_Command_Register(chan));
3519
3520         //printk("exit GPCT_Gen_Cont\n");
3521 }
3522
3523 static void GPCT_Reset(comedi_device *dev, int chan)
3524 {
3525         int temp_ack_reg=0;
3526
3527         //printk("GPCT_Reset...");
3528         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
3529
3530         switch (chan) {
3531                 case 0:
3532                         win_out(G0_Reset,Joint_Reset_Register);
3533                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
3534                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
3535                         temp_ack_reg |= G0_Gate_Error_Confirm;
3536                         temp_ack_reg |= G0_TC_Error_Confirm;
3537                         temp_ack_reg |= G0_TC_Interrupt_Ack;
3538                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
3539                         win_out(temp_ack_reg,Interrupt_A_Ack_Register);
3540
3541                         //problem...this interferes with the other ctr...
3542                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
3543                         win_out(devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
3544                         break;
3545                 case 1:
3546                         win_out(G1_Reset,Joint_Reset_Register);
3547                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
3548                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
3549                         temp_ack_reg |= G1_Gate_Error_Confirm;
3550                         temp_ack_reg |= G1_TC_Error_Confirm;
3551                         temp_ack_reg |= G1_TC_Interrupt_Ack;
3552                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
3553                         win_out(temp_ack_reg,Interrupt_B_Ack_Register);
3554
3555                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
3556                         win_out(devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
3557                         break;
3558         };
3559
3560         devpriv->gpct_mode[chan] = 0;
3561         devpriv->gpct_input_select[chan] = 0;
3562         devpriv->gpct_command[chan] = 0;
3563
3564         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
3565
3566         win_out( devpriv->gpct_mode[chan],G_Mode_Register(chan));
3567         win_out( devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
3568         win_out( 0,G_Autoincrement_Register(chan));
3569
3570         //printk("exit GPCT_Reset\n");
3571 }
3572
3573 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
3574         comedi_insn *insn,lsampl_t *data)
3575 {
3576         int retval=0;
3577         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
3578         switch(data[0]){
3579         case GPCT_RESET:
3580                 if(insn->n!=1)return -EINVAL;
3581                 GPCT_Reset(dev,insn->chanspec);
3582                 break;
3583         case GPCT_SET_SOURCE:
3584                 if(insn->n!=2)return -EINVAL;
3585                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
3586                 break;
3587         case GPCT_SET_GATE:
3588                 if(insn->n!=2)return -EINVAL;
3589                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
3590                 break;
3591         case GPCT_SET_DIRECTION:
3592                 if(insn->n!=2) return -EINVAL;
3593                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
3594                 break;
3595         case GPCT_GET_INT_CLK_FRQ:
3596                 if(insn->n!=2) return -EINVAL;
3597                 //There are actually 2 internal clocks on the STC, we always
3598                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
3599                 //NOTE: This is not the final interface, ideally the user
3600                 //will never need to know the int. clk. freq.
3601                 data[1]=50;//50ns = 20MHz = internal timebase of STC
3602                 break;
3603         case GPCT_SET_OPERATION:
3604                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
3605                 switch(data[1]){
3606                         case GPCT_SIMPLE_EVENT:
3607                                 GPCT_Event_Counting(dev,insn->chanspec);
3608                                 break;
3609                         case GPCT_SINGLE_PERIOD:
3610                                 GPCT_Period_Meas(dev,insn->chanspec);
3611                                 break;
3612                         case GPCT_SINGLE_PW:
3613                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
3614                                 break;
3615                         case GPCT_SINGLE_PULSE_OUT:
3616                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
3617                                 break;
3618                         case GPCT_CONT_PULSE_OUT:
3619                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
3620                                 break;
3621                         default:
3622                                 printk("unsupported GPCT operation!\n");
3623                                 return -EINVAL;
3624                 }
3625                 break;
3626         case GPCT_ARM:
3627                 if(insn->n!=1)return -EINVAL;
3628                 retval=GPCT_Arm(dev,insn->chanspec);
3629                 break;
3630         case GPCT_DISARM:
3631                 if(insn->n!=1)return -EINVAL;
3632                 retval=GPCT_Disarm(dev,insn->chanspec);
3633                 break;
3634         default:
3635                 return -EINVAL;
3636         }
3637
3638         //catch any errors from return values
3639         if(retval==0){
3640                 return insn->n;
3641         }else{
3642                 if(data[0]!=GPCT_ARM){
3643                         printk("error: retval was %d\n",retval);
3644                         printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
3645                 }
3646
3647                 return retval;
3648         }
3649 }
3650
3651 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
3652         comedi_insn *insn,lsampl_t *data) {
3653
3654         int chan=insn->chanspec;
3655         int cur_op = devpriv->gpct_cur_operation[chan];
3656
3657         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
3658         if(insn->n!=1)return -EINVAL;
3659
3660         data[0] = GPCT_G_Watch(dev,insn->chanspec);
3661
3662         /* for certain modes (period and pulse width measurment), the value
3663         in the counter is not valid until the counter stops.  If the value is
3664         invalid, return a 0 */
3665         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
3666                 /* is the counter still running? */
3667                 if(win_in(G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
3668                         data[0]=0;
3669         }
3670         return 1;
3671 }
3672
3673 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
3674         comedi_insn *insn,lsampl_t *data) {
3675
3676         //printk("in ni_gpct_insn_write");
3677         if(insn->n!=1)return -EINVAL;
3678         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
3679         return 1;
3680 }
3681
3682
3683 /*
3684  *
3685  *  Programmable Function Inputs
3686  *
3687  */
3688
3689 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
3690         comedi_insn *insn,lsampl_t *data)
3691 {
3692         if(insn->n!=2)return -EINVAL;
3693
3694         data[1] = 0;
3695
3696         return 2;
3697 }
3698
3699 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
3700         comedi_insn *insn,lsampl_t *data)
3701 {
3702         unsigned int chan;
3703
3704         if(insn->n!=1)return -EINVAL;
3705
3706         chan = CR_CHAN(insn->chanspec);
3707         if(chan>10)return -EINVAL;
3708
3709         switch(data[0]){
3710         case COMEDI_OUTPUT:
3711                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
3712                 break;
3713         case COMEDI_INPUT:
3714                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
3715                 break;
3716         default:
3717                 return -EINVAL;
3718         }
3719
3720         return 1;
3721 }
3722
3723 static void cs5529_command(comedi_device *dev, unsigned short value)
3724 {
3725         static const int timeout = 100;
3726         int i;
3727
3728         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
3729         /* give time for command to start being serially clocked into cs5529.
3730          * this insures that the CSS_ADC_BUSY bit will get properly
3731          * set before we exit this function.
3732         */
3733         for(i = 0; i < timeout; i++)
3734         {
3735                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
3736                         break;
3737                 comedi_udelay(1);
3738         }
3739         if(i == timeout)
3740         {
3741 //              comedi_error(dev, "possible problem - never saw adc go busy?");
3742         }
3743 }
3744
3745 /* write to cs5529 register */
3746 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
3747 {
3748         int i;
3749         unsigned short status;
3750         int timeout = HZ;
3751
3752         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
3753         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
3754         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
3755         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
3756         for(i = 0; i < timeout; i++)
3757         {
3758                         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
3759                         if((status & CSS_ADC_BUSY) == 0)
3760                                 break;
3761                         set_current_state(TASK_INTERRUPTIBLE);
3762                         if(schedule_timeout(1))
3763                         {
3764                                 comedi_error(dev, "interrupted in cs5529_config_write()");
3765                                 return;
3766                         }
3767         }
3768         if(i == timeout)
3769                 comedi_error(dev, "timed out in cs5529_config_write()");
3770 //printk("looped %i times writing to cs5529\n", i);
3771 }
3772
3773 /* read from cs5529 register */
3774 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
3775 {
3776         int i;
3777         unsigned short status;
3778         unsigned int value;
3779         int timeout = HZ;
3780
3781         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
3782         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
3783         for(i = 0; i < timeout; i++)
3784         {
3785                         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
3786                         if((status & CSS_ADC_BUSY) == 0)
3787                                 break;
3788                         set_current_state(TASK_INTERRUPTIBLE);
3789                         if(schedule_timeout(1))
3790                         {
3791                                 comedi_error(dev, "interrupted in cs5529_config_read()");
3792                                 return 0;
3793                         }
3794         }
3795         if(i == timeout)
3796                 comedi_error(dev, "timed out in cs5529_config_read()");
3797 //printk("looped %i times reading from cs5529\n", i);
3798         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
3799         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
3800         return value;
3801 }
3802
3803 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
3804 {
3805         int i;
3806         int timeout = HZ;
3807         unsigned int status;
3808
3809         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
3810         for(i = 0; i < timeout; i++)
3811         {
3812                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
3813                 if((status & CSS_ADC_BUSY) == 0)
3814                 {
3815                         break;
3816                 }
3817                 set_current_state(TASK_INTERRUPTIBLE);
3818                 if(schedule_timeout(1))
3819                 {
3820                         return -EIO;
3821                 }
3822         }
3823         if(i == timeout)
3824         {
3825                 rt_printk("ni_mio_common: timeout in cs5529_do_conversion()\n");
3826                 return -ETIME;
3827         }
3828         if(status & (CSS_OSC_DETECT | CSS_OVERRANGE))
3829         {
3830                 rt_printk("ni_mio_common: cs5529 conversion error, status 0x%x\n", status);
3831                 return -EIO;
3832         }
3833 //rt_printk("looped %i times waiting for data\n", i);
3834         if(data)
3835         {
3836                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
3837                 /* cs5529 returns 16 bit signed data in bipolar mode */
3838                 *data ^= (1 << 15);
3839         }
3840         return 0;
3841 }
3842
3843 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
3844 {
3845         int n, retval;
3846         unsigned short sample;
3847         unsigned int channel;
3848
3849         channel = CR_CHAN(insn->chanspec);
3850         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
3851          * do nothing. */
3852         ni_ao_win_outw(dev, 0x100 | channel, AO_Calibration_Channel_Select_67xx);
3853
3854         for(n = 0; n < insn->n; n++)
3855         {
3856                 retval = cs5529_do_conversion(dev, &sample);
3857                 if(retval < 0) return retval;
3858                 data[n] = sample;
3859         }
3860         return insn->n;
3861 }
3862
3863 static int init_cs5529(comedi_device *dev)
3864 {
3865         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
3866
3867         /* force gain calibration to 1 */
3868         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
3869         /* do self-calibration */
3870 //      cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
3871         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
3872         /* need to force a conversion for calibration to run */
3873         cs5529_do_conversion(dev, NULL);
3874
3875         if(0)
3876         {
3877                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
3878                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
3879                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
3880         }
3881         return 0;
3882 }
3883
3884