comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode);
 264
 265
 266 /*GPCT function def's*/
 267 static int GPCT_G_Watch(comedi_device *dev, int chan);
 268
 269 static void GPCT_Reset(comedi_device *dev, int chan);
 270 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 271 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 272 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 273 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 274 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 275 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 276 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 277 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 278
 279 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 280         comedi_insn *insn,lsampl_t *data);
 281 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 282         comedi_insn *insn,lsampl_t *data);
 283 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 284         comedi_insn *insn,lsampl_t *data);
 285
 286 static int init_cs5529(comedi_device *dev);
 287 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 288 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 289 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 290 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 291
 292 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 293         comedi_insn *insn,lsampl_t *data);
 294 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 295         comedi_insn *insn, lsampl_t *data);
 296
 297 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 298
 299 enum aimodes
 300 {
 301         AIMODE_NONE = 0,
 302         AIMODE_HALF_FULL = 1,
 303         AIMODE_SCAN = 2,
 304         AIMODE_SAMPLE = 3,
 305 };
 306
 307 #define SERIAL_DISABLED         0
 308 #define SERIAL_600NS            600
 309 #define SERIAL_1_2US            1200
 310 #define SERIAL_10US                     10000
 311
 312 static const int num_adc_stages_611x = 3;
 313
 314 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 315         unsigned int m_status);
 316 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 317         unsigned int m_status);
 318 static void get_last_sample_611x( comedi_device *dev );
 319 static void get_last_sample_6143( comedi_device *dev );
 320 #ifdef PCIDMA
 321 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 322 static int ni_ai_drain_dma(comedi_device *dev );
 323 #endif
 324
 325 static void ni_flush_ai_fifo(comedi_device *dev){
 326         if(boardtype.reg_type == ni_reg_6143){
 327                 // Flush the 6143 data FIFO
 328                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 329                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 330                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 331         }
 332         else {
 333                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 334         }
 335 }
 336
 337 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 338 {
 339         devpriv->stc_writew(dev, data >> 16, reg);
 340         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 341 }
 342
 343 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 344 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 345 {
 346         unsigned long flags;
 347
 348         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 349         ni_writew(addr,AO_Window_Address_611x);
 350         ni_writew(data,AO_Window_Data_611x);
 351         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 352 }
 353
 354 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 355 {
 356         unsigned long flags;
 357
 358         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 359         ni_writew(addr,AO_Window_Address_611x);
 360         ni_writel(data,AO_Window_Data_611x);
 361         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 362 }
 363
 364 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 365 {
 366         unsigned long flags;
 367         unsigned short data;
 368
 369         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 370         ni_writew(addr, AO_Window_Address_611x);
 371         data = ni_readw(AO_Window_Data_611x);
 372         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 373         return data;
 374 }
 375
 376 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 377 * share registers (such as Interrupt_A_Register) without interfering with
 378 * each other.
 379 *
 380 * NOTE: the switch/case statements are optimized out for a constant argument
 381 * so this is actually quite fast---  If you must wrap another function around this
 382 * make it inline to avoid a large speed penalty.
 383 *
 384 * value should only be 1 or 0.
 385 */
 386 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 387 {
 388         unsigned long flags;
 389
 390         comedi_spin_lock_irqsave( &devpriv->window_lock, flags );
 391         switch (reg){
 392                 case Interrupt_A_Enable_Register:
 393                         if(value)
 394                                 devpriv->int_a_enable_reg |= bits;
 395                         else
 396                                 devpriv->int_a_enable_reg &= ~bits;
 397                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 398                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 399                         break;
 400                 case Interrupt_B_Enable_Register:
 401                         if(value)
 402                                 devpriv->int_b_enable_reg |= bits;
 403                         else
 404                                 devpriv->int_b_enable_reg &= ~bits;
 405                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 406                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 407                         break;
 408                 case IO_Bidirection_Pin_Register:
 409                         if(value)
 410                                 devpriv->io_bidirection_pin_reg |= bits;
 411                         else
 412                                 devpriv->io_bidirection_pin_reg &= ~bits;
 413                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 414                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 415                         break;
 416                 default:
 417                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 418                         rt_printk("reg is %d\n",reg);
 419                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 420                         break;
 421         }
 422 }
 423
 424
 425 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 426 {
 427         comedi_device *dev=d;
 428         unsigned short a_status;
 429         unsigned short b_status;
 430         unsigned int m0_status;
 431         unsigned int m1_status;
 432         unsigned long flags;
 433 #ifdef PCIDMA
 434         struct mite_struct *mite = devpriv->mite;
 435 #endif
 436
 437         if(dev->attached == 0) return IRQ_NONE;
 438         // lock to avoid race with comedi_poll
 439         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 440         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 441         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 442 #ifdef PCIDMA
 443         m0_status=readl(mite->mite_io_addr + MITE_CHSR(AI_DMA_CHAN));
 444         m1_status=readl(mite->mite_io_addr + MITE_CHSR(AO_DMA_CHAN));
 445 #else
 446         m0_status = 0;
 447         m1_status = 0;
 448 #endif
 449
 450         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 451                 handle_a_interrupt(dev, a_status, m0_status);
 452         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 453                 handle_b_interrupt(dev, b_status, m1_status);
 454         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 455         return IRQ_HANDLED;
 456 }
 457
 458 #ifdef PCIDMA
 459 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 460 {
 461         int count;
 462         comedi_subdevice *s = dev->subdevices + 0;
 463         comedi_async *async = s->async;
 464         unsigned int nbytes, old_alloc_count;
 465         unsigned int bytes_per_scan = bytes_per_sample(s) * async->cmd.chanlist_len;
 466
 467         old_alloc_count = async->buf_write_alloc_count;
 468         // write alloc as much as we can
 469         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 470
 471         nbytes = mite_bytes_written_to_memory_lb(mite, AI_DMA_CHAN);
 472         rmb();
 473         if( (int)(mite_bytes_written_to_memory_ub(mite, AI_DMA_CHAN) - old_alloc_count) > 0 ){
 474                 rt_printk("ni_mio_common: DMA overwrite of free area\n");
 475                 ni_ai_reset(dev,s);
 476                 async->events |= COMEDI_CB_OVERFLOW;
 477                 return;
 478         }
 479
 480         count = nbytes - async->buf_write_count;
 481         if( count <= 0 ){
 482                 /* it's possible count will be negative due to
 483                  * conservative value returned by mite_bytes_transferred */
 484                 return;
 485         }
 486         comedi_buf_write_free(async, count);
 487
 488         async->scan_progress += count;
 489         if( async->scan_progress >= bytes_per_scan )
 490         {
 491                 async->scan_progress %= bytes_per_scan;
 492                 async->events |= COMEDI_CB_EOS;
 493         }
 494         async->events |= COMEDI_CB_BLOCK;
 495 }
 496
 497 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 498 {
 499         int count;
 500         comedi_subdevice *s = dev->subdevices + 1;
 501         comedi_async *async = s->async;
 502         u32 nbytes_ub, nbytes_lb;
 503         unsigned int new_write_count;
 504         u32 stop_count = async->cmd.stop_arg * sizeof(sampl_t);
 505
 506         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 507
 508         new_write_count = async->buf_write_count;
 509         mb();
 510         nbytes_lb = mite_bytes_read_from_memory_lb(mite, AO_DMA_CHAN);
 511         if(async->cmd.stop_src == TRIG_COUNT &&
 512                 (int) (nbytes_lb - stop_count) > 0)
 513                 nbytes_lb = stop_count;
 514         mb();
 515         nbytes_ub = mite_bytes_read_from_memory_ub(mite, AO_DMA_CHAN);
 516         if(async->cmd.stop_src == TRIG_COUNT &&
 517                 (int) (nbytes_ub - stop_count) > 0)
 518                 nbytes_ub = stop_count;
 519         if((int)(nbytes_ub - devpriv->last_buf_write_count) > 0){
 520                 rt_printk("ni_mio_common: DMA underrun\n");
 521                 ni_ao_reset(dev,s);
 522                 async->events |= COMEDI_CB_OVERFLOW;
 523                 return;
 524         }
 525         mb();
 526         devpriv->last_buf_write_count = new_write_count;
 527
 528         count = nbytes_lb - async->buf_read_count;
 529         if(count < 0){
 530                 return;
 531         }
 532         comedi_buf_read_free(async, count);
 533
 534         async->events |= COMEDI_CB_BLOCK;
 535 }
 536 // #define DEBUG_DMA_TIMING
 537 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 538 {
 539         static const int timeout = 10000;
 540         int i;
 541 #ifdef DEBUG_DMA_TIMING
 542         struct timeval start;
 543         do_gettimeofday(&start);
 544 #endif
 545         for(i = 0; i < timeout; i++)
 546         {
 547                 unsigned short b_status;
 548
 549                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 550                 if( b_status & AO_FIFO_Half_Full_St )
 551                         break;
 552                 /* if we poll too often, the pci bus activity seems
 553                  to slow the dma transfer down */
 554                 comedi_udelay(10);
 555         }
 556 #ifdef DEBUG_DMA_TIMING
 557         rt_printk("looped %i times waiting for ao fifo load.\n", i);
 558         struct timeval now;
 559         do_gettimeofday(&now);
 560         unsigned elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 561         rt_printk("total elapsed usec=%i\n", elapsed_usec);
 562         do_gettimeofday(&start);
 563         unsigned b_status;
 564         for(i = 0; i < 100; ++i)
 565         {
 566 //              devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
 567                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 568         }
 569         do_gettimeofday(&now);
 570         elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 571         rt_printk("usec to do 100 word xfers=%i\n", elapsed_usec);
 572 #endif
 573         if( i == timeout )
 574         {
 575                 comedi_error(dev, "timed out waiting for dma load");
 576                 return -EPIPE;
 577         }
 578         return 0;
 579 }
 580
 581 #endif //PCIDMA
 582 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 583 {
 584         if(devpriv->aimode == AIMODE_SCAN)
 585         {
 586 #ifdef PCIDMA
 587                 static const int timeout = 10;
 588                 int i;
 589
 590                 for(i = 0; i < timeout; i++)
 591                 {
 592                         ni_sync_ai_dma(devpriv->mite, dev);
 593                         if((s->async->events & COMEDI_CB_EOS)) break;
 594                         comedi_udelay(1);
 595                 }
 596 #else
 597                 ni_handle_fifo_dregs(dev);
 598                 s->async->events |= COMEDI_CB_EOS;
 599 #endif
 600         }
 601         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 602         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 603                 shutdown_ai_command( dev );
 604                 ni_ai_reset(dev, s);
 605         }
 606 }
 607
 608 static void shutdown_ai_command( comedi_device *dev )
 609 {
 610         comedi_subdevice *s = dev->subdevices + 0;
 611
 612 #ifdef PCIDMA
 613         ni_ai_drain_dma( dev );
 614         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 615 #endif
 616         ni_handle_fifo_dregs(dev);
 617         get_last_sample_611x(dev);
 618         get_last_sample_6143(dev);
 619
 620         ni_set_bits(dev, Interrupt_A_Enable_Register,
 621                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 622                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 623                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 624                 AI_FIFO_Interrupt_Enable,0);
 625
 626         s->async->events |= COMEDI_CB_EOA;
 627 }
 628
 629 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 630         unsigned int m_status)
 631 {
 632         comedi_subdevice *s=dev->subdevices+0;
 633         unsigned short ack=0;
 634
 635         s->async->events = 0;
 636
 637 #ifdef DEBUG_INTERRUPT
 638         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 639                 status, m_status);
 640         ni_mio_print_status_a(status);
 641 #endif
 642
 643
 644 #ifdef PCIDMA
 645         /* Currently, mite.c requires us to handle LINKC and DONE */
 646         if(m_status & CHSR_LINKC){
 647                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 648                 ni_sync_ai_dma(devpriv->mite, dev);
 649         }
 650
 651         if(m_status & CHSR_DONE){
 652                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 653         }
 654
 655         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 656                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 657                 //mite_print_chsr(m_status);
 658                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 659                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 660                 //disable_irq(dev->irq);
 661         }
 662 #endif
 663
 664         /* test for all uncommon interrupt events at the same time */
 665         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 666                 if(status==0xffff){
 667                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 668                         /* we probably aren't even running a command now,
 669                          * so it's a good idea to be careful. */
 670                         if(s->subdev_flags&SDF_RUNNING){
 671                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 672                                 //comedi_event(dev,s,s->async->events);
 673                         }
 674                         return;
 675                 }
 676                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 677                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 678                                 status);
 679                         ni_mio_print_status_a(status);
 680
 681                         ni_ai_reset(dev,dev->subdevices);
 682
 683
 684                         shutdown_ai_command( dev );
 685
 686                         s->async->events |= COMEDI_CB_ERROR;
 687                         if(status & (AI_Overrun_St | AI_Overflow_St))
 688                                 s->async->events |= COMEDI_CB_OVERFLOW;
 689
 690                         comedi_event(dev,s,s->async->events);
 691
 692                         return;
 693                 }
 694                 if(status&AI_SC_TC_St){
 695 #ifdef DEBUG_INTERRUPT
 696                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 697 #endif
 698                         if(!devpriv->ai_continuous){
 699                                 shutdown_ai_command( dev );
 700                         }
 701                         ack|=AI_SC_TC_Interrupt_Ack;
 702                 }
 703                 if(status&AI_START1_St){
 704                         ack|=AI_START1_Interrupt_Ack;
 705                 }
 706         }
 707 #ifndef PCIDMA
 708         if(status&AI_FIFO_Half_Full_St){
 709                 int i;
 710                 static const int timeout = 10;
 711                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 712                  *fail to get the fifo less than half full, so loop to be sure.*/
 713                 for(i = 0; i < timeout; ++i)
 714                 {
 715                         ni_handle_fifo_half_full(dev);
 716                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 717                                 break;
 718                 }
 719         }
 720 #endif // !PCIDMA
 721
 722         if( (status & AI_STOP_St) ){
 723                 ni_handle_eos(dev, s);
 724                 /* we need to ack the START, also */
 725                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 726         }
 727 #if 0
 728         if(devpriv->aimode==AIMODE_SAMPLE){
 729                 ni_handle_fifo_dregs(dev);
 730
 731                 //s->async->events |= COMEDI_CB_SAMPLE;
 732         }
 733 #endif
 734         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 735
 736         comedi_event(dev,s,s->async->events);
 737
 738 #ifdef DEBUG_INTERRUPT
 739         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 740         if(status&Interrupt_A_St){
 741                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 742         }
 743 #endif
 744 }
 745
 746 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 747 {
 748         comedi_subdevice *s=dev->subdevices+1;
 749         //unsigned short ack=0;
 750 #ifdef DEBUG_INTERRUPT
 751         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 752                 b_status,m_status);
 753         ni_mio_print_status_b(b_status);
 754 #endif
 755
 756
 757 #ifdef PCIDMA
 758         /* Currently, mite.c requires us to handle LINKC and DONE */
 759         if(m_status & CHSR_LINKC){
 760                 mite_handle_b_linkc(devpriv->mite, dev);
 761         }
 762
 763         if(m_status & CHSR_DONE){
 764                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 765         }
 766
 767         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 768                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 769                 //mite_print_chsr(m_status);
 770                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 771                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 772        }
 773 #endif
 774
 775         if(b_status==0xffff)return;
 776         if(b_status&AO_Overrun_St){
 777                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 778                 ni_ao_reset(dev,s);
 779                 s->async->events |= COMEDI_CB_OVERFLOW;
 780         }
 781
 782         if(b_status&AO_BC_TC_St){
 783                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 784                 ni_ao_reset(dev,s);
 785                 s->async->events |= COMEDI_CB_EOA;
 786         }
 787
 788 #ifndef PCIDMA
 789         if(b_status&AO_FIFO_Request_St){
 790                 int ret;
 791
 792                 ret = ni_ao_fifo_half_empty(dev,s);
 793                 if(!ret){
 794                         rt_printk("ni_mio_common: AO buffer underrun\n");
 795                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 796                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 797                         s->async->events |= COMEDI_CB_OVERFLOW;
 798                 }
 799         }
 800 #endif
 801
 802         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 803         if(b_status&Interrupt_B_St){
 804                 if(b_status&AO_FIFO_Request_St){
 805                         rt_printk("ni_mio_common: AO buffer underrun\n");
 806                 }
 807                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 808                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 809                 ni_ao_reset(dev,s);
 810                 s->async->events |= COMEDI_CB_OVERFLOW;
 811         }
 812
 813         comedi_event(dev,s,s->async->events);
 814 }
 815
 816 #ifdef DEBUG_STATUS_A
 817 static char *status_a_strings[]={
 818         "passthru0","fifo","G0_gate","G0_TC",
 819         "stop","start","sc_tc","start1",
 820         "start2","sc_tc_error","overflow","overrun",
 821         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 822 };
 823
 824 static void ni_mio_print_status_a(int status)
 825 {
 826         int i;
 827
 828         rt_printk("A status:");
 829         for(i=15;i>=0;i--){
 830                 if(status&(1<<i)){
 831                         rt_printk(" %s",status_a_strings[i]);
 832                 }
 833         }
 834         rt_printk("\n");
 835 }
 836 #endif
 837
 838 #ifdef DEBUG_STATUS_B
 839 static char *status_b_strings[]={
 840         "passthru1","fifo","G1_gate","G1_TC",
 841         "UI2_TC","UPDATE","UC_TC","BC_TC",
 842         "start1","overrun","start","bc_tc_error",
 843         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 844 };
 845
 846 static void ni_mio_print_status_b(int status)
 847 {
 848         int i;
 849
 850         rt_printk("B status:");
 851         for(i=15;i>=0;i--){
 852                 if(status&(1<<i)){
 853                         rt_printk(" %s",status_b_strings[i]);
 854                 }
 855         }
 856         rt_printk("\n");
 857 }
 858 #endif
 859
 860 #ifndef PCIDMA
 861
 862 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 863 {
 864         comedi_async *async = s->async;
 865         comedi_cmd *cmd = &async->cmd;
 866         int chan;
 867         int i;
 868         sampl_t d;
 869         u32 packed_data;
 870         int range;
 871         int err = 1;
 872
 873         chan = async->cur_chan;
 874         for(i=0;i<n;i++){
 875                 err &= comedi_buf_get(async, &d);
 876                 if(err == 0) break;
 877
 878                 range = CR_RANGE(cmd->chanlist[chan]);
 879
 880                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 881                 {
 882                         packed_data = d & 0xffff;
 883                         /* 6711 only has 16 bit wide ao fifo */
 884                         if(boardtype.reg_type != ni_reg_6711)
 885                         {
 886                                 err &= comedi_buf_get(async, &d);
 887                                 if(err == 0) break;
 888                                 chan++;
 889                                 i++;
 890                                 packed_data |= ( d << 16 ) & 0xffff0000;
 891                         }
 892                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 893                 }else{
 894                         ni_writew(d, DAC_FIFO_Data);
 895                 }
 896                 chan++;
 897                 chan %= cmd->chanlist_len;
 898         }
 899         async->cur_chan = chan;
 900         if(err==0){
 901                 async->events |= COMEDI_CB_OVERFLOW;
 902         }
 903 }
 904
 905 /*
 906  *  There's a small problem if the FIFO gets really low and we
 907  *  don't have the data to fill it.  Basically, if after we fill
 908  *  the FIFO with all the data available, the FIFO is _still_
 909  *  less than half full, we never clear the interrupt.  If the
 910  *  IRQ is in edge mode, we never get another interrupt, because
 911  *  this one wasn't cleared.  If in level mode, we get flooded
 912  *  with interrupts that we can't fulfill, because nothing ever
 913  *  gets put into the buffer.
 914  *
 915  *  This kind of situation is recoverable, but it is easier to
 916  *  just pretend we had a FIFO underrun, since there is a good
 917  *  chance it will happen anyway.  This is _not_ the case for
 918  *  RT code, as RT code might purposely be running close to the
 919  *  metal.  Needs to be fixed eventually.
 920  */
 921 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 922 {
 923         int n;
 924
 925         n = comedi_buf_read_n_available(s);
 926         if(n==0){
 927                 s->async->events |= COMEDI_CB_OVERFLOW;
 928                 return 0;
 929         }
 930
 931         n /= sizeof(sampl_t);
 932         if(n > boardtype.ao_fifo_depth / 2)
 933                 n = boardtype.ao_fifo_depth / 2;
 934
 935         ni_ao_fifo_load(dev,s,n);
 936
 937         s->async->events |= COMEDI_CB_BLOCK;
 938
 939         return 1;
 940 }
 941
 942 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 943 {
 944         int n;
 945
 946         /* reset fifo */
 947         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
 948         if(boardtype.reg_type & ni_reg_6xxx_mask)
 949                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 950
 951         /* load some data */
 952         n = comedi_buf_read_n_available(s);
 953         if(n==0)return 0;
 954
 955         n /= sizeof(sampl_t);
 956         if(n > boardtype.ao_fifo_depth)
 957                 n = boardtype.ao_fifo_depth;
 958
 959         ni_ao_fifo_load(dev,s,n);
 960
 961         return n;
 962 }
 963
 964 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 965         int n)
 966 {
 967         comedi_async *async = s->async;
 968         int i;
 969
 970         if(boardtype.reg_type == ni_reg_611x){
 971                 sampl_t data[2];
 972                 u32 dl;
 973
 974                 for( i = 0; i < n / 2; i++ ){
 975                         dl=ni_readl(ADC_FIFO_Data_611x);
 976                         /* This may get the hi/lo data in the wrong order */
 977                         data[0] = (dl>>16) & 0xffff;
 978                         data[1] = dl & 0xffff;
 979                         cfc_write_array_to_buffer(s, data, sizeof(data));
 980                 }
 981                 /* Check if there's a single sample stuck in the FIFO */
 982                 if( n % 2){
 983                         dl=ni_readl(ADC_FIFO_Data_611x);
 984                         data[0] = dl & 0xffff;
 985                         cfc_write_to_buffer(s, data[0]);
 986                 }
 987         } else if(boardtype.reg_type == ni_reg_6143){
 988                 sampl_t data[2];
 989                 u32     dl;
 990
 991                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
 992                 for(i = 0; i < n / 2; i++){
 993                         dl = ni_readl(AIFIFO_Data_6143);
 994
 995                         data[0] = (dl >> 16) & 0xffff;
 996                         data[1] = dl & 0xffff;
 997                         cfc_write_array_to_buffer(s, data, sizeof(data));
 998                 }
 999                 if(n % 2){
1000                         /* Assume there is a single sample stuck in the FIFO */
1001                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1002                         dl = ni_readl(AIFIFO_Data_6143);
1003                         data[0] = (dl >> 16) & 0xffff;
1004                         cfc_write_to_buffer(s, data[0]);
1005                 }
1006         } else{
1007                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1008                 {
1009                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1010                         async->events |= COMEDI_CB_ERROR;
1011                         return;
1012                 }
1013                 for(i = 0; i < n; i++){
1014                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1015                 }
1016                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1017                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1018         }
1019 }
1020
1021 static void ni_handle_fifo_half_full(comedi_device *dev)
1022 {
1023         int n;
1024         comedi_subdevice *s=dev->subdevices+0;
1025
1026         n=boardtype.ai_fifo_depth/2;
1027
1028         ni_ai_fifo_read(dev,s,n);
1029 }
1030 #endif
1031
1032 #ifdef PCIDMA
1033 static int ni_ai_drain_dma(comedi_device *dev )
1034 {
1035         struct mite_struct *mite = devpriv->mite;
1036         int i;
1037         static const int timeout = 10000;
1038
1039         for( i = 0; i < timeout; i++ )
1040         {
1041                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1042                         mite_bytes_in_transit(mite, AI_DMA_CHAN) == 0)
1043                         break;
1044                 comedi_udelay(2);
1045         }
1046         if(i == timeout)
1047         {
1048                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1049                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1050                         mite_bytes_in_transit(mite, AI_DMA_CHAN), devpriv->stc_readw(dev, AI_Status_1_Register));
1051                 return -1;
1052         }
1053
1054         ni_sync_ai_dma( mite, dev );
1055
1056         return 0;
1057 }
1058 #endif
1059 /*
1060    Empties the AI fifo
1061 */
1062 static void ni_handle_fifo_dregs(comedi_device *dev)
1063 {
1064         comedi_subdevice *s=dev->subdevices+0;
1065         sampl_t data[2];
1066         u32 dl;
1067         short fifo_empty;
1068         int i;
1069
1070         if(boardtype.reg_type == ni_reg_611x){
1071                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1072                         dl=ni_readl(ADC_FIFO_Data_611x);
1073
1074                         /* This may get the hi/lo data in the wrong order */
1075                         data[0] = (dl>>16);
1076                         data[1] = (dl&0xffff);
1077                         cfc_write_array_to_buffer(s, data, sizeof(data));
1078                 }
1079         }else if(boardtype.reg_type == ni_reg_6143){
1080                 i = 0;
1081                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1082                         dl = ni_readl(AIFIFO_Data_6143);
1083
1084                         /* This may get the hi/lo data in the wrong order */
1085                         data[0] = (dl >> 16);
1086                         data[1] = (dl & 0xffff);
1087                         cfc_write_array_to_buffer(s, data, sizeof(data));
1088                         i += 2;
1089                 }
1090                 // Check if stranded sample is present
1091                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1092                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1093                         dl = ni_readl(AIFIFO_Data_6143);
1094                         data[0] = (dl >> 16) & 0xffff;
1095                         cfc_write_to_buffer(s, data[0]);
1096                 }
1097
1098         }else{
1099                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1100                 while(fifo_empty == 0)
1101                 {
1102                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1103                         {
1104                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1105                                 if(fifo_empty) break;
1106                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1107                         }
1108                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1109                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1110                 }
1111         }
1112 }
1113
1114 static void get_last_sample_611x( comedi_device *dev )
1115 {
1116         comedi_subdevice *s=dev->subdevices+0;
1117         sampl_t data;
1118         u32 dl;
1119
1120         if(boardtype.reg_type != ni_reg_611x) return;
1121
1122         /* Check if there's a single sample stuck in the FIFO */
1123         if(ni_readb(XXX_Status)&0x80){
1124                 dl=ni_readl(ADC_FIFO_Data_611x);
1125                 data = (dl&0xffff);
1126                 cfc_write_to_buffer(s, data);
1127         }
1128 }
1129
1130 static void get_last_sample_6143(comedi_device* dev)
1131 {
1132         comedi_subdevice*       s = dev->subdevices + 0;
1133         sampl_t                 data;
1134         u32                     dl;
1135
1136         if(boardtype.reg_type != ni_reg_6143) return;
1137
1138         /* Check if there's a single sample stuck in the FIFO */
1139         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1140                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1141                 dl = ni_readl(AIFIFO_Data_6143);
1142
1143                 /* This may get the hi/lo data in the wrong order */
1144                 data = (dl >> 16) & 0xffff;
1145                 cfc_write_to_buffer(s, data);
1146         }
1147 }
1148
1149 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1150         void *data, unsigned int num_bytes, unsigned int chan_index )
1151 {
1152         comedi_async *async = s->async;
1153         unsigned int i;
1154         unsigned int length = num_bytes / bytes_per_sample(s);
1155         sampl_t *array = data;
1156         lsampl_t *larray = data;
1157         for(i = 0; i < length; i++)
1158         {
1159 #ifdef PCIDMA
1160                 if(s->subdev_flags & SDF_LSAMPL)
1161                         larray[i] = le32_to_cpu(larray[i]);
1162                 else
1163                         array[i] = le16_to_cpu(array[i]);
1164 #endif
1165                 if(s->subdev_flags & SDF_LSAMPL)
1166                         larray[i] += devpriv->ai_offset[chan_index];
1167                 else
1168                         array[i] += devpriv->ai_offset[chan_index];
1169                 chan_index++;
1170                 chan_index %= async->cmd.chanlist_len;
1171         }
1172 }
1173
1174 #ifdef PCIDMA
1175
1176 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1177 {
1178         struct mite_struct *mite = devpriv->mite;
1179         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1180         comedi_subdevice *s = dev->subdevices + 0;
1181
1182         /* write alloc the entire buffer */
1183         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1184
1185         mite_chan->current_link = 0;
1186         mite_chan->dir = COMEDI_INPUT;
1187         switch(boardtype.reg_type)
1188         {
1189         case ni_reg_611x:
1190         case ni_reg_6143:
1191                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1192                 break;
1193         case ni_reg_m_series:
1194                 if(boardtype.adbits > 16)
1195                         mite_prep_dma(mite, AI_DMA_CHAN, 32, 32);
1196                 else
1197                         mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);       //guess
1198                 break;
1199         default:
1200                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1201                 break;
1202         };
1203         /*start the MITE*/
1204         mite_dma_arm(mite, AI_DMA_CHAN);
1205 }
1206
1207 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1208 {
1209         struct mite_struct *mite = devpriv->mite;
1210         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1211         comedi_subdevice *s = dev->subdevices + 1;
1212
1213         devpriv->last_buf_write_count = s->async->buf_write_count;
1214
1215         mite_chan->current_link = 0;
1216         mite_chan->dir = COMEDI_OUTPUT;
1217         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1218                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1219         else
1220                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1221
1222         /*start the MITE*/
1223         mite_dma_arm(mite, AO_DMA_CHAN);
1224 }
1225
1226 #endif // PCIDMA
1227
1228 /*
1229    used for both cancel ioctl and board initialization
1230
1231    this is pretty harsh for a cancel, but it works...
1232  */
1233
1234 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1235 {
1236 #ifdef PCIDMA
1237         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1238 #endif
1239         /* ai configuration */
1240         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1241
1242         ni_set_bits(dev, Interrupt_A_Enable_Register,
1243                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1244                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1245                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1246                 AI_FIFO_Interrupt_Enable,0);
1247
1248         ni_flush_ai_fifo(dev);
1249
1250         if(boardtype.reg_type != ni_reg_6143)
1251                 ni_writeb(0, Misc_Command);
1252
1253         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1254         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1255                 AI_Mode_1_Register);
1256         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1257         /* generate FIFO interrupts on non-empty */
1258         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1259         if(boardtype.reg_type == ni_reg_611x){
1260                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1261                         AI_SOC_Polarity |
1262                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1263                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1264                         AI_EXTMUX_CLK_Output_Select(0) |
1265                         AI_LOCALMUX_CLK_Output_Select(2) |
1266                         AI_SC_TC_Output_Select(3) |
1267                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1268         }else if(boardtype.reg_type == ni_reg_6143){
1269                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1270                         AI_SOC_Polarity |
1271                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1272                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1273                         AI_EXTMUX_CLK_Output_Select(0) |
1274                         AI_LOCALMUX_CLK_Output_Select(2) |
1275                         AI_SC_TC_Output_Select(3) |
1276                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1277         }else{
1278                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1279                         AI_SOC_Polarity |
1280                         AI_CONVERT_Pulse_Width |
1281                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1282                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1283                         AI_EXTMUX_CLK_Output_Select(0) |
1284                         AI_LOCALMUX_CLK_Output_Select(2) |
1285                         AI_SC_TC_Output_Select(3) |
1286                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1287         }
1288         /* the following registers should not be changed, because there
1289          * are no backup registers in devpriv.  If you want to change
1290          * any of these, add a backup register and other appropriate code:
1291          *      AI_Mode_1_Register
1292          *      AI_Mode_3_Register
1293          *      AI_Personal_Register
1294          *      AI_Output_Control_Register
1295         */
1296         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1297                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1298                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1299                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1300
1301         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1302
1303         return 0;
1304 }
1305
1306 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1307 {
1308         unsigned long flags = 0;
1309         int count;
1310
1311         // lock to avoid race with interrupt handler
1312         if(in_interrupt() == 0)
1313                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1314 #ifndef PCIDMA
1315         ni_handle_fifo_dregs(dev);
1316 #else
1317         ni_sync_ai_dma(devpriv->mite, dev);
1318 #endif
1319         count = s->async->buf_write_count - s->async->buf_read_count;
1320         if(in_interrupt() == 0)
1321                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1322
1323         return count;
1324 }
1325
1326
1327 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1328 {
1329         int i,n;
1330         const unsigned int mask = (1 << boardtype.adbits) - 1;
1331         unsigned signbits;
1332         unsigned short d;
1333         unsigned long dl;
1334
1335         ni_load_channelgain_list(dev,1,&insn->chanspec);
1336
1337         ni_flush_ai_fifo(dev);
1338
1339         signbits=devpriv->ai_offset[0];
1340         if(boardtype.reg_type == ni_reg_611x){
1341                 for(n=0; n < num_adc_stages_611x; n++){
1342                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1343                         comedi_udelay(1);
1344                 }
1345                 for(n=0; n<insn->n; n++){
1346                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1347                         /* The 611x has screwy 32-bit FIFOs. */
1348                         d = 0;
1349                         for(i=0; i<NI_TIMEOUT; i++){
1350                                 if(ni_readb(XXX_Status)&0x80)
1351                                 {
1352                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1353                                         break;
1354                                 }
1355                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1356                                 {
1357                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1358                                         break;
1359                                 }
1360                         }
1361                         if(i==NI_TIMEOUT){
1362                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1363                                 return -ETIME;
1364                         }
1365                         d += signbits;
1366                         data[ n ] = d;
1367                 }
1368         }else if(boardtype.reg_type == ni_reg_6143){
1369                 for(n = 0; n < insn->n; n++){
1370                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1371
1372                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1373                         dl = 0;
1374                         for(i = 0; i < NI_TIMEOUT; i++){
1375                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1376                                 {
1377                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1378                                         dl = ni_readl(AIFIFO_Data_6143);
1379                                         break;
1380                                 }
1381                         }
1382                         if(i == NI_TIMEOUT){
1383                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1384                                 return -ETIME;
1385                         }
1386                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1387                 }
1388         }else{
1389                 for(n=0;n<insn->n;n++){
1390                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1391                         for(i=0;i<NI_TIMEOUT;i++){
1392                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1393                                         break;
1394                         }
1395                         if(i==NI_TIMEOUT){
1396                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1397                                 return -ETIME;
1398                         }
1399                         if(boardtype.reg_type == ni_reg_m_series)
1400                         {
1401                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1402                         }else
1403                         {
1404                                 d = ni_readw(ADC_FIFO_Data_Register);
1405                                 d += signbits; /* subtle: needs to be short addition */
1406                                 data[n] = d;
1407                         }
1408                 }
1409         }
1410         return insn->n;
1411 }
1412
1413 void ni_prime_channelgain_list(comedi_device *dev)
1414 {
1415         int i;
1416         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1417         for(i = 0; i < NI_TIMEOUT; ++i)
1418         {
1419                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1420                 {
1421                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1422                         return;
1423                 }
1424                 comedi_udelay(1);
1425         }
1426         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1427 }
1428
1429 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1430         unsigned int *list)
1431 {
1432         unsigned int chan, range, aref;
1433         unsigned int i;
1434         unsigned config_bits = 0;
1435         unsigned offset;
1436         unsigned int dither;
1437         unsigned range_code;
1438
1439         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1440
1441 //      offset = 1 << (boardtype.adbits - 1);
1442         if((list[0] & CR_ALT_SOURCE))
1443         {
1444                 chan = CR_CHAN(list[0]);
1445                 range = CR_RANGE(list[0]);
1446                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1447                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1448                 unsigned bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1449                 bypass_bits |= chan;
1450                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1451                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1452                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1453                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1454                 if(dither)
1455                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1456                 // don't use 2's complement encoding
1457                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1458                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1459         }else
1460         {
1461                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1462         }
1463         offset = 0;
1464         for(i = 0; i < n_chan; i++)
1465         {
1466                 chan = CR_CHAN(list[i]);
1467                 aref = CR_AREF(list[i]);
1468                 range = CR_RANGE(list[i]);
1469                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1470
1471                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1472                 devpriv->ai_offset[i] = offset;
1473
1474                 switch( aref )
1475                 {
1476                         case AREF_DIFF:
1477                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1478                                 break;
1479                         case AREF_COMMON:
1480                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1481                                 break;
1482                         case AREF_GROUND:
1483                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1484                                 break;
1485                         case AREF_OTHER:
1486                                 break;
1487                 }
1488                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1489                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1490                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1491                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1492                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1493                 // don't use 2's complement encoding
1494                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1495                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1496         }
1497         ni_prime_channelgain_list(dev);
1498 }
1499
1500 /*
1501  * Notes on the 6110 and 6111:
1502  * These boards a slightly different than the rest of the series, since
1503  * they have multiple A/D converters.
1504  * From the driver side, the configuration memory is a
1505  * little different.
1506  * Configuration Memory Low:
1507  *   bits 15-9: same
1508  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1509  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1510  *       1001 gain=0.1 (+/- 50)
1511  *       1010 0.2
1512  *       1011 0.1
1513  *       0001 1
1514  *       0010 2
1515  *       0011 5
1516  *       0100 10
1517  *       0101 20
1518  *       0110 50
1519  * Configuration Memory High:
1520  *   bits 12-14: Channel Type
1521  *       001 for differential
1522  *       000 for calibration
1523  *   bit 11: coupling  (this is not currently handled)
1524  *       1 AC coupling
1525  *       0 DC coupling
1526  *   bits 0-2: channel
1527  *       valid channels are 0-3
1528  */
1529 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1530         unsigned int *list)
1531 {
1532         unsigned int chan,range,aref;
1533         unsigned int i;
1534         unsigned int hi,lo;
1535         unsigned offset;
1536         unsigned int dither;
1537
1538         if(boardtype.reg_type == ni_reg_m_series)
1539         {
1540                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1541                 return;
1542         }
1543         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1544                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1545                         // ready to go.
1546                         return;
1547                 }
1548                 devpriv->changain_state=1;
1549                 devpriv->changain_spec=list[0];
1550         }else{
1551                 devpriv->changain_state=0;
1552         }
1553
1554         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1555
1556         // Set up Calibration mode if required
1557         if(boardtype.reg_type == ni_reg_6143){
1558                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1559                         // Strobe Relay enable bit
1560                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1561                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1562                         devpriv->ai_calib_source_enabled = 1;
1563                         msleep_interruptible(100);      // Allow relays to change
1564                 }
1565                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1566                         // Strobe Relay disable bit
1567                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1568                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1569                         devpriv->ai_calib_source_enabled = 0;
1570                         msleep_interruptible(100);      // Allow relays to change
1571                 }
1572         }
1573
1574         offset=1<<(boardtype.adbits-1);
1575         for(i=0;i<n_chan;i++){
1576                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1577                         chan=devpriv->ai_calib_source;
1578                 }else{
1579                         chan=CR_CHAN(list[i]);
1580                 }
1581                 aref=CR_AREF(list[i]);
1582                 range=CR_RANGE(list[i]);
1583                 dither=((list[i]&CR_ALT_FILTER)!=0);
1584
1585                 /* fix the external/internal range differences */
1586                 range = ni_gainlkup[boardtype.gainlkup][range];
1587                 if(boardtype.reg_type == ni_reg_611x)
1588                         devpriv->ai_offset[i] = offset;
1589                 else
1590                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1591
1592                 hi = 0;
1593                 if( ( list[i] & CR_ALT_SOURCE ) )
1594                 {
1595                         if(boardtype.reg_type == ni_reg_611x)
1596                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1597                 }else
1598                 {
1599                         if(boardtype.reg_type == ni_reg_611x)
1600                                 aref = AREF_DIFF;
1601                         else if(boardtype.reg_type == ni_reg_6143)
1602                                 aref = AREF_OTHER;
1603                         switch( aref )
1604                         {
1605                                 case AREF_DIFF:
1606                                         hi |= AI_DIFFERENTIAL;
1607                                         break;
1608                                 case AREF_COMMON:
1609                                         hi |= AI_COMMON;
1610                                         break;
1611                                 case AREF_GROUND:
1612                                         hi |= AI_GROUND;
1613                                         break;
1614                                 case AREF_OTHER:
1615                                         break;
1616                         }
1617                 }
1618                 hi |= AI_CONFIG_CHANNEL( chan );
1619
1620                 ni_writew(hi,Configuration_Memory_High);
1621
1622                 if(boardtype.reg_type != ni_reg_6143){
1623                         lo = range;
1624                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1625                         if( dither ) lo |= AI_DITHER;
1626
1627                         ni_writew(lo,Configuration_Memory_Low);
1628                 }
1629         }
1630
1631         /* prime the channel/gain list */
1632         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1633                 ni_prime_channelgain_list(dev);
1634         }
1635 }
1636
1637 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode)
1638 {
1639         int divider;
1640         switch(round_mode)
1641         {
1642         case TRIG_ROUND_NEAREST:
1643         default:
1644                 divider = (*nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1645                 break;
1646         case TRIG_ROUND_DOWN:
1647                 divider = (*nanosec) / devpriv->clock_ns;
1648                 break;
1649         case TRIG_ROUND_UP:
1650                 divider=(*nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1651                 break;
1652         }
1653
1654         *nanosec = devpriv->clock_ns * divider;
1655         return divider - 1;
1656 }
1657
1658 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1659 {
1660         int err=0;
1661         int tmp;
1662         int sources;
1663
1664         /* step 1: make sure trigger sources are trivially valid */
1665
1666         tmp=cmd->start_src;
1667         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1668         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1669
1670         tmp=cmd->scan_begin_src;
1671         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1672         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1673
1674         tmp=cmd->convert_src;
1675         sources = TRIG_TIMER | TRIG_EXT;
1676         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1677         cmd->convert_src &= sources;
1678         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1679
1680         tmp=cmd->scan_end_src;
1681         cmd->scan_end_src &= TRIG_COUNT;
1682         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1683
1684         tmp=cmd->stop_src;
1685         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1686         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1687
1688         if(err)return 1;
1689
1690         /* step 2: make sure trigger sources are unique and mutually compatible */
1691
1692         /* note that mutual compatiblity is not an issue here */
1693         if(cmd->start_src!=TRIG_NOW &&
1694            cmd->start_src!=TRIG_INT &&
1695            cmd->start_src!=TRIG_EXT)err++;
1696         if(cmd->scan_begin_src!=TRIG_TIMER &&
1697            cmd->scan_begin_src!=TRIG_EXT &&
1698            cmd->scan_begin_src!=TRIG_OTHER)err++;
1699         if(cmd->convert_src!=TRIG_TIMER &&
1700            cmd->convert_src!=TRIG_EXT &&
1701            cmd->convert_src!=TRIG_NOW)err++;
1702         if(cmd->stop_src!=TRIG_COUNT &&
1703            cmd->stop_src!=TRIG_NONE)err++;
1704
1705         if(err)return 2;
1706
1707         /* step 3: make sure arguments are trivially compatible */
1708
1709         if(cmd->start_src==TRIG_EXT){
1710                 /* external trigger */
1711                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1712
1713                 if(tmp > 16) tmp = 16;
1714                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1715                 if(cmd->start_arg != tmp){
1716                         cmd->start_arg = tmp;
1717                         err++;
1718                 }
1719         }else{
1720                 if(cmd->start_arg!=0){
1721                         /* true for both TRIG_NOW and TRIG_INT */
1722                         cmd->start_arg=0;
1723                         err++;
1724                 }
1725         }
1726         if(cmd->scan_begin_src==TRIG_TIMER){
1727                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1728                         cmd->scan_begin_arg=boardtype.ai_speed;
1729                         err++;
1730                 }
1731                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1732                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1733                         err++;
1734                 }
1735         }else if(cmd->scan_begin_src==TRIG_EXT){
1736                 /* external trigger */
1737                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1738
1739                 if(tmp>16)tmp=16;
1740                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1741                 if(cmd->scan_begin_arg!=tmp){
1742                         cmd->scan_begin_arg = tmp;
1743                         err++;
1744                 }
1745         }else{ /* TRIG_OTHER */
1746                 if(cmd->scan_begin_arg){
1747                         cmd->scan_begin_arg=0;
1748                         err++;
1749                 }
1750         }
1751         if(cmd->convert_src==TRIG_TIMER){
1752                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1753                         if(cmd->convert_arg != 0){
1754                                 cmd->convert_arg = 0;
1755                                 err++;
1756                         }
1757                 }else{
1758                         if(cmd->convert_arg<boardtype.ai_speed){
1759                                 cmd->convert_arg=boardtype.ai_speed;
1760                                 err++;
1761                         }
1762                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1763                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1764                                 err++;
1765                         }
1766                 }
1767         }else if(cmd->convert_src == TRIG_EXT){
1768                 /* external trigger */
1769                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1770
1771                 if(tmp>16)tmp=16;
1772                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1773                 if(cmd->convert_arg!=tmp){
1774                         cmd->convert_arg = tmp;
1775                         err++;
1776                 }
1777         }else if(cmd->convert_src == TRIG_NOW){
1778                 if(cmd->convert_arg != 0){
1779                         cmd->convert_arg = 0;
1780                         err++;
1781                 }
1782         }
1783
1784         if(cmd->scan_end_arg!=cmd->chanlist_len){
1785                 cmd->scan_end_arg=cmd->chanlist_len;
1786                 err++;
1787         }
1788         if(cmd->stop_src==TRIG_COUNT){
1789                 unsigned int max_count = 0x01000000;
1790
1791                 if(boardtype.reg_type == ni_reg_611x )
1792                         max_count -= num_adc_stages_611x;
1793                 if(cmd->stop_arg > max_count){
1794                         cmd->stop_arg = max_count;
1795                         err++;
1796                 }
1797                 if(cmd->stop_arg < 1){
1798                         cmd->stop_arg = 1;
1799                         err++;
1800                 }
1801         }else{
1802                 /* TRIG_NONE */
1803                 if(cmd->stop_arg!=0){
1804                         cmd->stop_arg=0;
1805                         err++;
1806                 }
1807         }
1808
1809         if(err)return 3;
1810
1811         /* step 4: fix up any arguments */
1812
1813         if(cmd->scan_begin_src==TRIG_TIMER){
1814                 tmp=cmd->scan_begin_arg;
1815                 ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
1816                 if(tmp!=cmd->scan_begin_arg)err++;
1817         }
1818         if(cmd->convert_src==TRIG_TIMER){
1819                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1820                         tmp=cmd->convert_arg;
1821                         ni_ns_to_timer(dev, &cmd->convert_arg, cmd->flags&TRIG_ROUND_MASK);
1822                         if(tmp!=cmd->convert_arg)err++;
1823                         if(cmd->scan_begin_src==TRIG_TIMER &&
1824                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1825                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1826                                 err++;
1827                         }
1828                 }
1829         }
1830
1831         if(err)return 4;
1832
1833         return 0;
1834 }
1835
1836 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1837 {
1838         comedi_cmd *cmd=&s->async->cmd;
1839         int timer;
1840         int mode1=0; /* mode1 is needed for both stop and convert */
1841         int mode2=0;
1842         int start_stop_select=0;
1843         unsigned int stop_count;
1844         int interrupt_a_enable=0;
1845
1846         MDPRINTK("ni_ai_cmd\n");
1847         if(dev->irq == 0)
1848         {
1849                 comedi_error(dev, "cannot run command without an irq");
1850                 return -EIO;
1851         }
1852         ni_flush_ai_fifo(dev);
1853
1854         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1855
1856         /* start configuration */
1857         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1858
1859         /* disable analog triggering for now, since it
1860          * interferes with the use of pfi0 */
1861         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1862         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1863
1864         switch(cmd->start_src){
1865                 case TRIG_INT:
1866                 case TRIG_NOW:
1867                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1868                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1869                                 AI_Trigger_Select_Register);
1870                         break;
1871                 case TRIG_EXT:
1872                 {
1873                         int chan = CR_CHAN(cmd->start_arg);
1874                         unsigned int bits = AI_START2_Select(0)|
1875                                 AI_START1_Sync |
1876                                 AI_START1_Select(chan + 1);
1877
1878                         if(cmd->start_arg & CR_INVERT)
1879                                 bits |= AI_START1_Polarity;
1880                         if(cmd->start_arg & CR_EDGE)
1881                                 bits |= AI_START1_Edge;
1882                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1883                         break;
1884                 }
1885         }
1886
1887         mode2 &= ~AI_Pre_Trigger;
1888         mode2 &= ~AI_SC_Initial_Load_Source;
1889         mode2 &= ~AI_SC_Reload_Mode;
1890         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1891
1892         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1893                 start_stop_select |= AI_STOP_Polarity;
1894                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1895                 start_stop_select |= AI_STOP_Sync;
1896         }else
1897         {
1898                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
1899         }
1900         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1901
1902         devpriv->ai_cmd2 = 0;
1903         switch(cmd->stop_src){
1904         case TRIG_COUNT:
1905                 stop_count = cmd->stop_arg - 1;
1906
1907                 if(boardtype.reg_type == ni_reg_611x){
1908                         // have to take 3 stage adc pipeline into account
1909                         stop_count += num_adc_stages_611x;
1910                 }
1911                 /* stage number of scans */
1912                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
1913
1914                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1915                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1916                 /* load SC (Scan Count) */
1917                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1918
1919                 devpriv->ai_continuous = 0;
1920                 if( stop_count == 0 ){
1921                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1922                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1923                         // this is required to get the last sample for chanlist_len > 1, not sure why
1924                         if(cmd->chanlist_len > 1)
1925                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
1926                 }
1927                 break;
1928         case TRIG_NONE:
1929                 /* stage number of scans */
1930                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
1931
1932                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1933                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1934
1935                 /* load SC (Scan Count) */
1936                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1937
1938                 devpriv->ai_continuous = 1;
1939
1940                 break;
1941         }
1942
1943         switch(cmd->scan_begin_src){
1944         case TRIG_TIMER:
1945                 /*
1946                         stop bits for non 611x boards
1947                         AI_SI_Special_Trigger_Delay=0
1948                         AI_Pre_Trigger=0
1949                         AI_START_STOP_Select_Register:
1950                         AI_START_Polarity=0 (?) rising edge
1951                         AI_START_Edge=1         edge triggered
1952                         AI_START_Sync=1 (?)
1953                         AI_START_Select=0               SI_TC
1954                         AI_STOP_Polarity=0              rising edge
1955                         AI_STOP_Edge=0          level
1956                         AI_STOP_Sync=1
1957                         AI_STOP_Select=19               external pin (configuration mem)
1958                  */
1959                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1960                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1961
1962                 mode2 |= AI_SI_Reload_Mode(0);
1963                 /* AI_SI_Initial_Load_Source=A */
1964                 mode2 &= ~AI_SI_Initial_Load_Source;
1965                 //mode2 |= AI_SC_Reload_Mode;
1966                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1967
1968                 /* load SI */
1969                 timer = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
1970                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
1971                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
1972                 break;
1973         case TRIG_EXT:
1974                 if( cmd->scan_begin_arg & CR_EDGE )
1975                         start_stop_select |= AI_START_Edge;
1976                 /* AI_START_Polarity==1 is falling edge */
1977                 if( cmd->scan_begin_arg & CR_INVERT )
1978                         start_stop_select |= AI_START_Polarity;
1979                 if( cmd->scan_begin_src != cmd->convert_src ||
1980                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1981                         start_stop_select |= AI_START_Sync;
1982                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
1983                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1984                 break;
1985         }
1986
1987         switch(cmd->convert_src){
1988         case TRIG_TIMER:
1989         case TRIG_NOW:
1990                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
1991                         timer = 1;
1992                 else
1993                         timer = ni_ns_to_timer(dev, &cmd->convert_arg, TRIG_ROUND_NEAREST);
1994                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
1995                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
1996
1997                 /* AI_SI2_Reload_Mode = alternate */
1998                 /* AI_SI2_Initial_Load_Source = A */
1999                 mode2 &= ~AI_SI2_Initial_Load_Source;
2000                 mode2 |= AI_SI2_Reload_Mode;
2001                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2002
2003                 /* AI_SI2_Load */
2004                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2005
2006                 mode2 |= AI_SI2_Reload_Mode; // alternate
2007                 mode2 |= AI_SI2_Initial_Load_Source; // B
2008
2009                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2010                 break;
2011         case TRIG_EXT:
2012                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2013                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2014                         mode1 |= AI_CONVERT_Source_Polarity;
2015                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2016
2017                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2018                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2019
2020                 break;
2021         }
2022
2023         if(dev->irq){
2024
2025                 /* interrupt on FIFO, errors, SC_TC */
2026                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2027                         AI_SC_TC_Interrupt_Enable;
2028
2029 #ifndef PCIDMA
2030                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2031 #endif
2032
2033                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2034                         /* wake on end-of-scan */
2035                         devpriv->aimode=AIMODE_SCAN;
2036                 }else{
2037                         devpriv->aimode=AIMODE_HALF_FULL;
2038                 }
2039
2040                 switch(devpriv->aimode){
2041                 case AIMODE_HALF_FULL:
2042                         /*generate FIFO interrupts and DMA requests on half-full */
2043 #ifdef PCIDMA
2044                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2045 #else
2046                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2047 #endif
2048                         break;
2049                 case AIMODE_SAMPLE:
2050                         /*generate FIFO interrupts on non-empty */
2051                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2052                         break;
2053                 case AIMODE_SCAN:
2054 #ifdef PCIDMA
2055                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2056 #else
2057                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2058 #endif
2059                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2060                         break;
2061                 default:
2062                         break;
2063                 }
2064
2065                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2066
2067                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2068
2069                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2070         }else{
2071                 /* interrupt on nothing */
2072                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2073
2074                 /* XXX start polling if necessary */
2075                 MDPRINTK("interrupting on nothing\n");
2076         }
2077
2078         /* end configuration */
2079         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2080
2081         switch(cmd->scan_begin_src){
2082         case TRIG_TIMER:
2083                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2084                         AI_Command_1_Register);
2085                 break;
2086         case TRIG_EXT:
2087                 /* XXX AI_SI_Arm? */
2088                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2089                         AI_Command_1_Register);
2090                 break;
2091         }
2092
2093 #ifdef PCIDMA
2094         ni_ai_setup_MITE_dma(dev,cmd);
2095         //mite_dump_regs(devpriv->mite);
2096 #endif
2097
2098         switch(cmd->start_src){
2099         case TRIG_NOW:
2100                 /* AI_START1_Pulse */
2101                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2102                 s->async->inttrig=NULL;
2103                 break;
2104         case TRIG_EXT:
2105                 s->async->inttrig=NULL;
2106                 break;
2107         case TRIG_INT:
2108                 s->async->inttrig=ni_ai_inttrig;
2109                 break;
2110         }
2111
2112         MDPRINTK("exit ni_ai_cmd\n");
2113
2114         return 0;
2115 }
2116
2117 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2118         unsigned int trignum)
2119 {
2120         if(trignum!=0)return -EINVAL;
2121
2122         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2123         s->async->inttrig=NULL;
2124
2125         return 1;
2126 }
2127
2128 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2129         comedi_insn *insn, lsampl_t *data);
2130
2131 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2132         comedi_insn *insn, lsampl_t *data)
2133 {
2134         if(insn->n<1)return -EINVAL;
2135
2136         switch(data[0]){
2137         case INSN_CONFIG_ANALOG_TRIG:
2138                 return ni_ai_config_analog_trig(dev,s,insn,data);
2139         case INSN_CONFIG_ALT_SOURCE:
2140                 if(boardtype.reg_type == ni_reg_m_series)
2141                 {
2142                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2143                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2144                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2145                         {
2146                                 return -EINVAL;
2147                         }
2148                         devpriv->ai_calib_source = data[1];
2149                 } else if(boardtype.reg_type == ni_reg_6143)
2150                 {
2151                         unsigned int calib_source;
2152
2153                         calib_source = data[1] & 0xf;
2154
2155
2156                         if(calib_source > 0xF)
2157                                 return -EINVAL;
2158
2159                         devpriv->ai_calib_source = calib_source;
2160                         ni_writew(calib_source, Calibration_Channel_6143);
2161                 }else
2162                 {
2163                         unsigned int calib_source;
2164                         unsigned int calib_source_adjust;
2165
2166                         calib_source = data[1] & 0xf;
2167                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2168
2169                         if(calib_source >= 8)
2170                                 return -EINVAL;
2171                         devpriv->ai_calib_source = calib_source;
2172                         if(boardtype.reg_type == ni_reg_611x){
2173                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2174                         }
2175                 }
2176                 return 2;
2177         default:
2178                 break;
2179         }
2180
2181         return -EINVAL;
2182 }
2183
2184 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2185         comedi_insn *insn, lsampl_t *data)
2186 {
2187         unsigned int a,b,modebits;
2188         int err=0;
2189
2190         /* data[1] is flags
2191          * data[2] is analog line
2192          * data[3] is set level
2193          * data[4] is reset level */
2194         if(!boardtype.has_analog_trig)return -EINVAL;
2195         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2196                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2197                 err++;
2198         }
2199         if(data[2]>=boardtype.n_adchan){
2200                 data[2]=boardtype.n_adchan-1;
2201                 err++;
2202         }
2203         if(data[3]>255){ /* a */
2204                 data[3]=255;
2205                 err++;
2206         }
2207         if(data[4]>255){ /* b */
2208                 data[4]=255;
2209                 err++;
2210         }
2211         /*
2212          * 00 ignore
2213          * 01 set
2214          * 10 reset
2215          *
2216          * modes:
2217          *   1 level:                    +b-   +a-
2218          *     high mode                00 00 01 10
2219          *     low mode                 00 00 10 01
2220          *   2 level: (a<b)
2221          *     hysteresis low mode      10 00 00 01
2222          *     hysteresis high mode     01 00 00 10
2223          *     middle mode              10 01 01 10
2224          */
2225
2226         a=data[3];
2227         b=data[4];
2228         modebits=data[1]&0xff;
2229         if(modebits&0xf0){
2230                 /* two level mode */
2231                 if(b<a){
2232                         /* swap order */
2233                         a=data[4];
2234                         b=data[3];
2235                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2236                 }
2237                 devpriv->atrig_low = a;
2238                 devpriv->atrig_high = b;
2239                 switch(modebits){
2240                 case 0x81:      /* low hysteresis mode */
2241                         devpriv->atrig_mode = 6;
2242                         break;
2243                 case 0x42:      /* high hysteresis mode */
2244                         devpriv->atrig_mode = 3;
2245                         break;
2246                 case 0x96:      /* middle window mode */
2247                         devpriv->atrig_mode = 2;
2248                         break;
2249                 default:
2250                         data[1]&=~0xff;
2251                         err++;
2252                 }
2253         }else{
2254                 /* one level mode */
2255                 if(b!=0){
2256                         data[4]=0;
2257                         err++;
2258                 }
2259                 switch(modebits){
2260                 case 0x06:      /* high window mode */
2261                         devpriv->atrig_high = a;
2262                         devpriv->atrig_mode = 0;
2263                         break;
2264                 case 0x09:      /* low window mode */
2265                         devpriv->atrig_low = a;
2266                         devpriv->atrig_mode = 1;
2267                         break;
2268                 default:
2269                         data[1]&=~0xff;
2270                         err++;
2271                 }
2272         }
2273         if(err)return -EAGAIN;
2274         return 5;
2275 }
2276
2277 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2278 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2279         void *data, unsigned int num_bytes, unsigned int chan_index )
2280 {
2281         comedi_async *async = s->async;
2282         unsigned int range;
2283         unsigned int i;
2284         unsigned int offset;
2285         unsigned int length = num_bytes / sizeof( sampl_t );
2286         sampl_t *array = data;
2287
2288         offset = 1 << (boardtype.aobits - 1);
2289         for(i = 0; i < length; i++)
2290         {
2291                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2292                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2293                         array[i] -= offset;
2294 #ifdef PCIDMA
2295                 array[i] = cpu_to_le16( array[i] );
2296 #endif
2297                 chan_index++;
2298                 chan_index %= async->cmd.chanlist_len;
2299         }
2300 }
2301
2302 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2303         unsigned int chanspec[], unsigned int n_chans, int timed)
2304 {
2305         unsigned int range;
2306         unsigned int chan;
2307         unsigned int conf;
2308         int i;
2309         int invert = 0;
2310
2311         for(i = 0; i < boardtype.n_aochan; ++i)
2312         {
2313                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2314         }
2315         for(i=0;i<n_chans;i++)
2316         {
2317                 chan = CR_CHAN(chanspec[i]);
2318                 range = CR_RANGE(chanspec[i]);
2319                 comedi_krange *krange = s->range_table->range + range;
2320                 invert = 0;
2321                 conf = 0;
2322                 switch(krange->max - krange->min)
2323                 {
2324                 case 20000000:
2325                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2326                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2327                         break;
2328                 case 10000000:
2329                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2330                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2331                         break;
2332                 case 4000000:
2333                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2334                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2335                         break;
2336                 case 2000000:
2337                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2338                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2339                         break;
2340                 default:
2341                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2342                         break;
2343                 }
2344                 switch(krange->max + krange->min)
2345                 {
2346                 case 0:
2347                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2348                         break;
2349                 case 10000000:
2350                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2351                         break;
2352                 default:
2353                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2354                         break;
2355                 }
2356                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2357                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2358                 devpriv->ao_conf[chan] = conf;
2359                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2360         }
2361         return invert;
2362 }
2363
2364 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2365         unsigned int chanspec[], unsigned int n_chans)
2366 {
2367         unsigned int range;
2368         unsigned int chan;
2369         unsigned int conf;
2370         int i;
2371         int invert = 0;
2372
2373         for(i=0;i<n_chans;i++)
2374         {
2375                 chan = CR_CHAN(chanspec[i]);
2376                 range = CR_RANGE(chanspec[i]);
2377                 conf = AO_Channel(chan);
2378
2379                 if(boardtype.ao_unipolar){
2380                         if((range&1) == 0){
2381                                 conf |= AO_Bipolar;
2382                                 invert = (1<<(boardtype.aobits-1));
2383                         }else{
2384                                 invert = 0;
2385                         }
2386                         if(range&2)
2387                                 conf |= AO_Ext_Ref;
2388                 }else{
2389                         conf |= AO_Bipolar;
2390                         invert = (1<<(boardtype.aobits-1));
2391                 }
2392
2393                 /* not all boards can deglitch, but this shouldn't hurt */
2394                 if(chanspec[i] & CR_DEGLITCH)
2395                         conf |= AO_Deglitch;
2396
2397                 /* analog reference */
2398                 /* AREF_OTHER connects AO ground to AI ground, i think */
2399                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2400
2401                 ni_writew(conf,AO_Configuration);
2402                 devpriv->ao_conf[chan] = conf;
2403         }
2404         return invert;
2405 }
2406
2407 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2408         unsigned int chanspec[], unsigned int n_chans, int timed)
2409 {
2410         if(boardtype.reg_type == ni_reg_m_series)
2411                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2412         else
2413                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2414 }
2415 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2416         comedi_insn *insn,lsampl_t *data)
2417 {
2418         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2419
2420         return 1;
2421 }
2422
2423 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2424         comedi_insn *insn,lsampl_t *data)
2425 {
2426         unsigned int chan = CR_CHAN(insn->chanspec);
2427         unsigned int invert;
2428
2429         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2430
2431         devpriv->ao[chan] = data[0];
2432
2433         if(boardtype.reg_type == ni_reg_m_series)
2434         {
2435                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2436         }
2437         else
2438                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2439
2440         return 1;
2441 }
2442
2443 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2444         comedi_insn *insn,lsampl_t *data)
2445 {
2446         unsigned int chan = CR_CHAN(insn->chanspec);
2447         unsigned int invert;
2448
2449         ao_win_out(1 << chan, AO_Immediate_671x);
2450         invert = 1 << (boardtype.aobits - 1);
2451
2452         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2453
2454         devpriv->ao[chan] = data[0];
2455         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2456
2457         return 1;
2458 }
2459
2460 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2461         unsigned int trignum)
2462 {
2463         int ret;
2464         int interrupt_b_bits;
2465         int i;
2466         static const int timeout = 1000;
2467
2468         if(trignum!=0)return -EINVAL;
2469
2470         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2471         interrupt_b_bits = AO_Error_Interrupt_Enable;
2472 #ifdef PCIDMA
2473         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2474         if(boardtype.reg_type & ni_reg_6xxx_mask)
2475                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2476         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2477         ret = ni_ao_wait_for_dma_load(dev);
2478         if(ret < 0) return ret;
2479
2480 #else
2481         ret = ni_ao_prep_fifo(dev,s);
2482         if(ret==0)return -EPIPE;
2483
2484         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2485 #endif
2486
2487         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2488         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2489         /* wait for DACs to be loaded */
2490         for(i = 0; i < timeout; i++)
2491         {
2492                 comedi_udelay(1);
2493                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2494                         break;
2495         }
2496         if(i == timeout)
2497         {
2498                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2499                 return -EIO;
2500         }
2501         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2502         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2503
2504         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2505
2506         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2507                 AO_Command_1_Register);
2508
2509         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2510
2511         s->async->inttrig=NULL;
2512
2513         return 0;
2514 }
2515
2516 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2517 {
2518         comedi_cmd *cmd = &s->async->cmd;
2519         int trigvar;
2520         int bits;
2521         int i;
2522
2523         if(dev->irq == 0)
2524         {
2525                 comedi_error(dev, "cannot run command without an irq");
2526                 return -EIO;
2527         }
2528         trigvar = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2529
2530         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2531
2532         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2533
2534         if(boardtype.reg_type & ni_reg_6xxx_mask)
2535         {
2536                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2537
2538                 bits = 0;
2539                 for(i = 0; i < cmd->chanlist_len; i++)
2540                 {
2541                         int chan;
2542
2543                         chan = CR_CHAN(cmd->chanlist[i]);
2544                         bits |= 1 << chan;
2545                         ao_win_out(chan, AO_Waveform_Generation_611x);
2546                 }
2547                 ao_win_out(bits, AO_Timed_611x);
2548         }
2549
2550         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2551
2552         if(cmd->stop_src==TRIG_NONE){
2553                 devpriv->ao_mode1|=AO_Continuous;
2554                 devpriv->ao_mode1&=~AO_Trigger_Once;
2555         }else{
2556                 devpriv->ao_mode1&=~AO_Continuous;
2557                 devpriv->ao_mode1|=AO_Trigger_Once;
2558         }
2559         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2560         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2561         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2562         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2563         devpriv->ao_mode3&=~AO_Trigger_Length;
2564         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2565
2566         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2567         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2568         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2569         if(cmd->stop_src==TRIG_NONE){
2570                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2571         }else{
2572                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2573         }
2574         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2575         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2576         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2577         switch(cmd->stop_src){
2578         case TRIG_COUNT:
2579                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2580                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2581                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2582                 break;
2583         case TRIG_NONE:
2584                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2585                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2586                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2587                 break;
2588         default:
2589                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2590                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2591                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2592         }
2593
2594         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2595         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2596         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2597         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2598         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2599         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2600         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2601         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2602         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2603
2604         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2605                 if(cmd->scan_end_arg>1){
2606                         devpriv->ao_mode1|=AO_Multiple_Channels;
2607                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2608                                 AO_UPDATE_Output_Select(1),
2609                                 AO_Output_Control_Register);
2610                 }else{
2611                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2612                         unsigned bits = AO_UPDATE_Output_Select(1);
2613                         if(boardtype.reg_type == ni_reg_m_series)
2614                                 bits |= AO_Number_Of_Channels(0);
2615                         else
2616                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2617                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2618                 }
2619                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2620         }
2621
2622         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2623
2624         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2625         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2626
2627         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
2628 #ifdef PCIDMA
2629         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2630 #else
2631         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2632 #endif
2633         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2634         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2635
2636         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2637                 AO_TMRDACWR_Pulse_Width;
2638         if( boardtype.ao_fifo_depth )
2639                 bits |= AO_FIFO_Enable;
2640         else
2641                 bits |= AO_DMA_PIO_Control;
2642         if(boardtype.reg_type == ni_reg_m_series)
2643                 bits |= AO_Number_Of_DAC_Packages/* | AO_Multiple_DACS_Per_Package*/;
2644         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2645         // enable sending of ao dma requests
2646         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2647
2648         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2649
2650         if(cmd->stop_src==TRIG_COUNT) {
2651                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2652                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2653                         AO_BC_TC_Interrupt_Enable, 1);
2654         }
2655
2656         s->async->inttrig=ni_ao_inttrig;
2657
2658         return 0;
2659 }
2660
2661 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2662 {
2663         int err=0;
2664         int tmp;
2665
2666         /* step 1: make sure trigger sources are trivially valid */
2667
2668         tmp=cmd->start_src;
2669         cmd->start_src &= TRIG_INT;
2670         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2671
2672         tmp=cmd->scan_begin_src;
2673         cmd->scan_begin_src &= TRIG_TIMER;
2674         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2675
2676         tmp=cmd->convert_src;
2677         cmd->convert_src &= TRIG_NOW;
2678         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2679
2680         tmp=cmd->scan_end_src;
2681         cmd->scan_end_src &= TRIG_COUNT;
2682         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2683
2684         tmp=cmd->stop_src;
2685         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2686         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2687
2688         if(err)return 1;
2689
2690         /* step 2: make sure trigger sources are unique and mutually compatible */
2691
2692         if(cmd->stop_src!=TRIG_COUNT &&
2693            cmd->stop_src!=TRIG_NONE)err++;
2694
2695         if(err)return 2;
2696
2697         /* step 3: make sure arguments are trivially compatible */
2698
2699         if(cmd->start_arg!=0){
2700                 cmd->start_arg=0;
2701                 err++;
2702         }
2703 #if 0
2704         /* XXX need ao_speed */
2705         if(cmd->scan_begin_arg<boardtype.ao_speed){
2706                 cmd->scan_begin_arg=boardtype.ao_speed;
2707                 err++;
2708         }
2709 #endif
2710         if(cmd->scan_begin_arg>devpriv->clock_ns*0xffffff){ /* XXX check */
2711                 cmd->scan_begin_arg=devpriv->clock_ns*0xffffff;
2712                 err++;
2713         }
2714         if(cmd->convert_arg!=0){
2715                 cmd->convert_arg=0;
2716                 err++;
2717         }
2718         if(cmd->scan_end_arg!=cmd->chanlist_len){
2719                 cmd->scan_end_arg=cmd->chanlist_len;
2720                 err++;
2721         }
2722         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2723                 if(cmd->stop_arg>0x00ffffff){
2724                         cmd->stop_arg=0x00ffffff;
2725                         err++;
2726                 }
2727         }else{
2728                 /* TRIG_NONE */
2729                 if(cmd->stop_arg!=0){
2730                         cmd->stop_arg=0;
2731                         err++;
2732                 }
2733         }
2734
2735         if(err)return 3;
2736
2737         /* step 4: fix up any arguments */
2738
2739         tmp = cmd->scan_begin_arg;
2740         ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
2741         if(tmp!=cmd->scan_begin_arg)err++;
2742
2743         if(err)return 4;
2744
2745         /* step 5: fix up chanlist */
2746
2747         if(err)return 5;
2748
2749         return 0;
2750 }
2751
2752
2753 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2754 {
2755         //devpriv->ao0p=0x0000;
2756         //ni_writew(devpriv->ao0p,AO_Configuration);
2757
2758         //devpriv->ao1p=AO_Channel(1);
2759         //ni_writew(devpriv->ao1p,AO_Configuration);
2760
2761 #ifdef PCIDMA
2762         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2763         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
2764 #endif
2765
2766         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2767         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2768         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2769         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2770         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2771         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2772                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2773         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2774         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2775         devpriv->ao_cmd1=0;
2776         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2777         devpriv->ao_cmd2=0;
2778         devpriv->ao_mode1=0;
2779         devpriv->ao_mode2=0;
2780         if(boardtype.reg_type == ni_reg_m_series)
2781                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2782         else
2783                 devpriv->ao_mode3 = 0;
2784         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2785         devpriv->ao_trigger_select=0;
2786         if(boardtype.reg_type & ni_reg_6xxx_mask){
2787                 ao_win_out(0x3, AO_Immediate_671x);
2788                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2789         }
2790         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2791
2792         return 0;
2793 }
2794
2795 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2796         comedi_insn *insn,lsampl_t *data)
2797 {
2798 #ifdef DEBUG_DIO
2799         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2800                 CR_CHAN(insn->chanspec),data[0]);
2801 #endif
2802         switch(data[0]){
2803         case INSN_CONFIG_DIO_OUTPUT:
2804                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2805                 break;
2806         case INSN_CONFIG_DIO_INPUT:
2807                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2808                 break;
2809         case INSN_CONFIG_DIO_QUERY:
2810                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2811                 return insn->n;
2812                 break;
2813         default:
2814                 return -EINVAL;
2815         }
2816
2817         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2818         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2819         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2820
2821         return 1;
2822 }
2823
2824 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2825         comedi_insn *insn,lsampl_t *data)
2826 {
2827 #ifdef DEBUG_DIO
2828         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2829 #endif
2830         if(insn->n!=2)return -EINVAL;
2831         if(data[0]){
2832                 /* Perform check to make sure we're not using the
2833                    serial part of the dio */
2834                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2835                         return -EBUSY;
2836
2837                 s->state &= ~data[0];
2838                 s->state |= (data[0]&data[1]);
2839                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2840                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2841                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2842         }
2843         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2844
2845         return 2;
2846 }
2847
2848 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2849         comedi_insn *insn, lsampl_t *data)
2850 {
2851 #ifdef DEBUG_DIO
2852         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
2853                 CR_CHAN(insn->chanspec), data[0]);
2854 #endif
2855         switch(data[0])
2856         {
2857         case INSN_CONFIG_DIO_OUTPUT:
2858                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2859                 break;
2860         case INSN_CONFIG_DIO_INPUT:
2861                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2862                 break;
2863         case INSN_CONFIG_DIO_QUERY:
2864                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2865                 return insn->n;
2866                 break;
2867         default:
2868                 return -EINVAL;
2869         }
2870
2871         ni_writel(s->io_bits, M_Offset_DIO_Direction);
2872
2873         return 1;
2874 }
2875
2876 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2877         comedi_insn *insn, lsampl_t *data)
2878 {
2879 #ifdef DEBUG_DIO
2880         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2881 #endif
2882         if(insn->n!=2)return -EINVAL;
2883         if(data[0]){
2884                 s->state &= ~data[0];
2885                 s->state |= (data[0] & data[1]);
2886                 ni_writel(s->state, M_Offset_Static_Digital_Output);
2887         }
2888         data[1] = ni_readl(M_Offset_Static_Digital_Input);
2889
2890         return 2;
2891 }
2892
2893 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2894                                  comedi_insn *insn,lsampl_t *data)
2895 {
2896         int err = insn->n;
2897         unsigned char byte_out, byte_in;
2898
2899         if(insn->n!=2)return -EINVAL;
2900
2901         switch(data[0]) {
2902         case INSN_CONFIG_SERIAL_CLOCK:
2903
2904 #ifdef DEBUG_DIO
2905                 rt_printk("SPI serial clock Config cd\n", data[1]);
2906 #endif
2907                 devpriv->serial_hw_mode = 1;
2908                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2909
2910                 if(data[1] == SERIAL_DISABLED) {
2911                         devpriv->serial_hw_mode = 0;
2912                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2913                                                   DIO_Software_Serial_Control);
2914                         data[1] = SERIAL_DISABLED;
2915                         devpriv->serial_interval_ns = data[1];
2916                 }
2917                 else if(data[1] <= SERIAL_600NS) {
2918                         /* Warning: this clock speed is too fast to reliably
2919                         control SCXI. */
2920                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2921                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2922                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2923                         data[1] = SERIAL_600NS;
2924                         devpriv->serial_interval_ns = data[1];
2925                 }
2926                 else if(data[1] <= SERIAL_1_2US) {
2927                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2928                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2929                                 DIO_Serial_Out_Divide_By_2;
2930                         data[1] = SERIAL_1_2US;
2931                         devpriv->serial_interval_ns = data[1];
2932                 }
2933                 else if(data[1] <= SERIAL_10US) {
2934                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2935                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2936                                 DIO_Serial_Out_Divide_By_2;
2937                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2938                         600ns/1.2us. If you turn divide_by_2 off with the
2939                         slow clock, you will still get 10us, except then
2940                         all your delays are wrong. */
2941                         data[1] = SERIAL_10US;
2942                         devpriv->serial_interval_ns = data[1];
2943                 }
2944                 else {
2945                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2946                                                   DIO_Software_Serial_Control);
2947                         devpriv->serial_hw_mode = 0;
2948                         data[1] = (data[1] / 1000) * 1000;
2949                         devpriv->serial_interval_ns = data[1];
2950                 }
2951
2952                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2953                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
2954                 return 1;
2955
2956         break;
2957
2958         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2959
2960                 if(devpriv->serial_interval_ns == 0) {
2961                         return -EINVAL;
2962                 }
2963
2964                 byte_out = data[1] & 0xFF;
2965
2966                 if(devpriv->serial_hw_mode) {
2967                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2968                 } else if(devpriv->serial_interval_ns > 0) {
2969                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2970                 } else {
2971                         rt_printk("ni_serial_insn_config: serial disabled!\n");
2972                         return -EINVAL;
2973                 }
2974                 if(err < 0) return err;
2975                 data[1] = byte_in & 0xFF;
2976                 return insn->n;
2977
2978         break;
2979         default:
2980                 return -EINVAL;
2981         }
2982
2983 }
2984
2985 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
2986                                    unsigned char data_out,
2987                                    unsigned char *data_in)
2988 {
2989         unsigned int status1;
2990         int err = 0, count = 20;
2991
2992 #ifdef DEBUG_DIO
2993         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
2994 #endif
2995
2996         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
2997         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
2998         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2999
3000         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3001         if(status1 & DIO_Serial_IO_In_Progress_St) {
3002                 err = -EBUSY;
3003                 goto Error;
3004         }
3005
3006         devpriv->dio_control |= DIO_HW_Serial_Start;
3007         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3008         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3009
3010         /* Wait until STC says we're done, but don't loop infinitely. */
3011         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3012                 /* Delay one bit per loop */
3013                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3014                 if(--count < 0) {
3015                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3016                         err = -ETIME;
3017                         goto Error;
3018                 }
3019         }
3020
3021         /* Delay for last bit. This delay is absolutely necessary, because
3022            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3023         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3024
3025         if(data_in != NULL) {
3026                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3027 #ifdef DEBUG_DIO
3028                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3029 #endif
3030         }
3031
3032  Error:
3033         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3034
3035         return err;
3036 }
3037
3038 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3039                                    unsigned char data_out,
3040                                    unsigned char *data_in)
3041 {
3042         unsigned char mask, input = 0;
3043
3044 #ifdef DEBUG_DIO
3045         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3046 #endif
3047
3048         /* Wait for one bit before transfer */
3049         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3050
3051         for(mask = 0x80; mask; mask >>= 1) {
3052                 /* Output current bit; note that we cannot touch s->state
3053            because it is a per-subdevice field, and serial is
3054                    a separate subdevice from DIO. */
3055                 devpriv->dio_output &= ~DIO_SDOUT;
3056                 if(data_out & mask) {
3057                         devpriv->dio_output |= DIO_SDOUT;
3058                 }
3059                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3060
3061                 /* Assert SDCLK (active low, inverted), wait for half of
3062                    the delay, deassert SDCLK, and wait for the other half. */
3063                 devpriv->dio_control |= DIO_Software_Serial_Control;
3064                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3065
3066                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3067
3068                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3069                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3070
3071                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3072
3073                 /* Input current bit */
3074                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3075 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3076                         input |= mask;
3077                 }
3078         }
3079 #ifdef DEBUG_DIO
3080         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3081 #endif
3082         if(data_in) *data_in = input;
3083
3084         return 0;
3085 }
3086
3087 static void mio_common_detach(comedi_device *dev)
3088 {
3089         if(dev->subdevices && boardtype.has_8255)
3090                 subdev_8255_cleanup(dev,dev->subdevices+3);
3091 }
3092
3093 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3094 {
3095         int i;
3096
3097         for(i = 0; i < s->n_chan; i++)
3098                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3099 }
3100
3101 static int ni_alloc_private(comedi_device *dev)
3102 {
3103         int ret;
3104
3105         ret = alloc_private(dev, sizeof(ni_private));
3106         if(ret < 0) return ret;
3107
3108         spin_lock_init(&devpriv->window_lock);
3109
3110         return 0;
3111 };
3112
3113 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3114 {
3115         comedi_subdevice *s;
3116         int bits;
3117
3118         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3119         {
3120                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3121                 return -EINVAL;
3122         }
3123
3124         if(alloc_subdevices(dev, 11) < 0)
3125                 return -ENOMEM;
3126
3127         /* analog input subdevice */
3128
3129         s=dev->subdevices+0;
3130         dev->read_subdev=s;
3131         if(boardtype.n_adchan){
3132                 s->type=COMEDI_SUBD_AI;
3133                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER;
3134                 if(boardtype.reg_type != ni_reg_611x)
3135                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3136                 if(boardtype.adbits > 16)
3137                         s->subdev_flags |= SDF_LSAMPL;
3138                 if(boardtype.reg_type == ni_reg_m_series)
3139                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3140                 s->n_chan=boardtype.n_adchan;
3141                 s->len_chanlist=512;
3142                 s->maxdata=(1<<boardtype.adbits)-1;
3143                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3144                 s->insn_read=ni_ai_insn_read;
3145                 s->insn_config=ni_ai_insn_config;
3146                 s->do_cmdtest=ni_ai_cmdtest;
3147                 s->do_cmd=ni_ai_cmd;
3148                 s->cancel=ni_ai_reset;
3149                 s->poll=ni_ai_poll;
3150                 s->munge=ni_ai_munge;
3151         }else{
3152                 s->type=COMEDI_SUBD_UNUSED;
3153         }
3154
3155         /* analog output subdevice */
3156
3157         s=dev->subdevices+1;
3158         if(boardtype.n_aochan){
3159                 dev->write_subdev=s;
3160                 s->type=COMEDI_SUBD_AO;
3161                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
3162                 if(boardtype.reg_type == ni_reg_m_series)
3163                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3164                 s->n_chan=boardtype.n_aochan;
3165                 s->maxdata=(1<<boardtype.aobits)-1;
3166                 s->range_table = boardtype.ao_range_table;
3167                 s->insn_read=ni_ao_insn_read;
3168                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3169                         s->insn_write=ni_ao_insn_write_671x;
3170                 }else{
3171                         s->insn_write=ni_ao_insn_write;
3172                 }
3173 #ifdef PCIDMA
3174                 if(boardtype.n_aochan){
3175 #else
3176                 if(boardtype.ao_fifo_depth){
3177 #endif
3178                         s->do_cmd=ni_ao_cmd;
3179                         s->do_cmdtest=ni_ao_cmdtest;
3180                         s->len_chanlist = boardtype.n_aochan;
3181                         if(boardtype.reg_type != ni_reg_m_series)
3182                                 s->munge=ni_ao_munge;
3183                 }
3184                 s->cancel=ni_ao_reset;
3185         }else{
3186                 s->type=COMEDI_SUBD_UNUSED;
3187         }
3188         if((boardtype.reg_type & ni_reg_67xx_mask))
3189                 init_ao_67xx(dev, s);
3190
3191         /* digital i/o subdevice */
3192
3193         s=dev->subdevices+2;
3194         s->type=COMEDI_SUBD_DIO;
3195         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3196         s->maxdata=1;
3197         s->io_bits=0;           /* all bits input */
3198         s->range_table=&range_digital;
3199         if(boardtype.reg_type == ni_reg_m_series)
3200         {
3201                 s->n_chan = 32;
3202                 s->insn_bits = ni_m_series_dio_insn_bits;
3203                 s->insn_config=ni_m_series_dio_insn_config;
3204                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3205         }else
3206         {
3207                 s->n_chan=8;
3208                 s->insn_bits=ni_dio_insn_bits;
3209                 s->insn_config=ni_dio_insn_config;
3210                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3211                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3212         }
3213
3214         /* 8255 device */
3215         s=dev->subdevices+3;
3216         if(boardtype.has_8255){
3217                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3218         }else{
3219                 s->type=COMEDI_SUBD_UNUSED;
3220         }
3221
3222         /* general purpose counter/timer device */
3223         s=dev->subdevices+4;
3224         s->type=COMEDI_SUBD_COUNTER;
3225         s->subdev_flags=SDF_READABLE|SDF_WRITABLE;
3226         s->insn_read=  ni_gpct_insn_read;
3227         s->insn_write= ni_gpct_insn_write;
3228         s->insn_config=ni_gpct_insn_config;
3229         s->n_chan=2;
3230         s->maxdata=1;
3231         devpriv->an_trig_etc_reg = 0;
3232         GPCT_Reset(dev,0);
3233         GPCT_Reset(dev,1);
3234
3235         /* calibration subdevice -- ai and ao */
3236         s=dev->subdevices+5;
3237         s->type=COMEDI_SUBD_CALIB;
3238         if(boardtype.reg_type == ni_reg_m_series)
3239         {
3240                 // internal PWM analog output used for AI nonlinearity calibration
3241                 s->subdev_flags = SDF_INTERNAL;
3242                 s->insn_config = &ni_m_series_pwm_config;
3243                 s->n_chan = 1;
3244                 s->maxdata = 0;
3245                 ni_writel(0x0, M_Offset_Cal_PWM);
3246         } else if(boardtype.reg_type == ni_reg_6143)
3247         {
3248                 // internal PWM analog output used for AI nonlinearity calibration
3249                 s->subdev_flags = SDF_INTERNAL;
3250                 s->insn_config = &ni_6143_pwm_config;
3251                 s->n_chan = 1;
3252                 s->maxdata = 0;
3253         }else
3254         {
3255                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3256                 s->insn_read = &ni_calib_insn_read;
3257                 s->insn_write = &ni_calib_insn_write;
3258                 caldac_setup(dev, s);
3259         }
3260
3261         /* EEPROM */
3262         s=dev->subdevices+6;
3263         s->type=COMEDI_SUBD_MEMORY;
3264         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3265         s->maxdata=0xff;
3266         if(boardtype.reg_type == ni_reg_m_series)
3267         {
3268                 s->n_chan = M_SERIES_EEPROM_SIZE;
3269                 s->insn_read = &ni_m_series_eeprom_insn_read;
3270         }else
3271         {
3272                 s->n_chan = 512;
3273                 s->insn_read = &ni_eeprom_insn_read;
3274         }
3275         /* PFI */
3276         s=dev->subdevices + 7;
3277         s->type = COMEDI_SUBD_DIO;
3278         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3279         if(boardtype.reg_type == ni_reg_m_series)
3280         {
3281                 s->n_chan = 16;
3282                 ni_writew(s->state, M_Offset_PFI_DO);
3283                 unsigned i;
3284                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3285                 {
3286                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3287                 }
3288         }else
3289         {
3290                 s->n_chan = 10;
3291         }
3292         s->maxdata = 1;
3293         s->insn_bits = ni_pfi_insn_bits;
3294         s->insn_config = ni_pfi_insn_config;
3295         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3296
3297         /* cs5529 calibration adc */
3298         s = dev->subdevices + 8;
3299         if(boardtype.reg_type & ni_reg_67xx_mask)
3300         {
3301                 s->type = COMEDI_SUBD_AI;
3302                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3303                 // one channel for each analog output channel
3304                 s->n_chan = boardtype.n_aochan;
3305                 s->maxdata = (1 << 16) - 1;
3306                 s->range_table = &range_unknown; /* XXX */
3307                 s->insn_read=cs5529_ai_insn_read;
3308                 s->insn_config=NULL;
3309                 init_cs5529(dev);
3310         }else
3311         {
3312                 s->type=COMEDI_SUBD_UNUSED;
3313         }
3314
3315         /* Serial */
3316         s=dev->subdevices+9;
3317         s->type=COMEDI_SUBD_SERIAL;
3318         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3319         s->n_chan=1;
3320         s->maxdata=0xff;
3321         s->insn_config = ni_serial_insn_config;
3322         devpriv->serial_interval_ns = 0;
3323         devpriv->serial_hw_mode = 0;
3324
3325         /* RTSI */
3326         s=dev->subdevices + 10;
3327         s->type = COMEDI_SUBD_DIO;
3328         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3329         s->n_chan = 8;
3330         s->maxdata = 1;
3331         s->insn_bits = ni_rtsi_insn_bits;
3332         s->insn_config = ni_rtsi_insn_config;
3333         ni_rtsi_init(dev);
3334
3335         /* ai configuration */
3336         ni_ai_reset(dev,dev->subdevices+0);
3337         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3338                 // BEAM is this needed for PCI-6143 ??
3339                 devpriv->clock_and_fout =
3340                         Slow_Internal_Time_Divide_By_2 |
3341                         Slow_Internal_Timebase |
3342                         Clock_To_Board_Divide_By_2 |
3343                         Clock_To_Board |
3344                         AI_Output_Divide_By_2 |
3345                         AO_Output_Divide_By_2;
3346         }else{
3347                 devpriv->clock_and_fout =
3348                         Slow_Internal_Time_Divide_By_2 |
3349                         Slow_Internal_Timebase |
3350                         Clock_To_Board_Divide_By_2 |
3351                         Clock_To_Board;
3352         }
3353         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3354
3355         /* analog output configuration */
3356         ni_ao_reset(dev,dev->subdevices + 1);
3357
3358         if(dev->irq){
3359                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3360                         (Interrupt_Output_On_3_Pins&0) |
3361                         Interrupt_A_Enable |
3362                         Interrupt_B_Enable |
3363                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3364                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3365                         Interrupt_Control_Register
3366                 );
3367         }
3368
3369         /* DMA setup */
3370         /* tell the STC which dma channels to use for AI and AO */
3371         bits = 1 << ( AI_DMA_CHAN );
3372         bits |= 1 << ( AO_DMA_CHAN + 4 );
3373         ni_writeb( bits, AI_AO_Select);
3374         /* tell the STC which dma channels to use for
3375          * General purpose counters 0 and 1 */
3376         bits = 1 << ( GPC0_DMA_CHAN );
3377         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
3378         ni_writeb( bits, G0_G1_Select);
3379
3380         if(boardtype.reg_type & ni_reg_6xxx_mask)
3381         {
3382                 ni_writeb( 0, Magic_611x );
3383         }else if(boardtype.reg_type == ni_reg_m_series)
3384         {
3385                 int channel;
3386                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3387                 {
3388                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3389                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3390                 }
3391                 ni_writeb(0x0, M_Offset_AO_Calibration);
3392         }
3393
3394         printk("\n");
3395         return 0;
3396 }
3397
3398
3399
3400 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3401 {
3402         comedi_device *dev=(comedi_device *)arg;
3403
3404         if(dir){
3405                 ni_writeb(data,Port_A+2*port);
3406                 return 0;
3407         }else{
3408                 return ni_readb(Port_A+2*port);
3409         }
3410 }
3411
3412 /*
3413         presents the EEPROM as a subdevice
3414 */
3415
3416 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3417         comedi_insn *insn,lsampl_t *data)
3418 {
3419         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3420
3421         return 1;
3422 }
3423
3424 /*
3425         reads bytes out of eeprom
3426 */
3427
3428 static int ni_read_eeprom(comedi_device *dev,int addr)
3429 {
3430         int bit;
3431         int bitstring;
3432
3433         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3434         ni_writeb(0x04,Serial_Command);
3435         for(bit=0x8000;bit;bit>>=1){
3436                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3437                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3438         }
3439         bitstring=0;
3440         for(bit=0x80;bit;bit>>=1){
3441                 ni_writeb(0x04,Serial_Command);
3442                 ni_writeb(0x05,Serial_Command);
3443                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3444         }
3445         ni_writeb(0x00,Serial_Command);
3446
3447         return bitstring;
3448 }
3449
3450 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3451         comedi_insn *insn,lsampl_t *data)
3452 {
3453         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3454
3455         return 1;
3456 }
3457
3458 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3459 {
3460         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3461         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3462         return 3;
3463 }
3464
3465 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3466         comedi_insn *insn, lsampl_t *data)
3467 {
3468         unsigned up_count, down_count;
3469         switch(data[0])
3470         {
3471         case INSN_CONFIG_PWM_OUTPUT:
3472                 switch(data[1])
3473                 {
3474                 case TRIG_ROUND_NEAREST:
3475                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3476                         break;
3477                 case TRIG_ROUND_DOWN:
3478                         up_count = data[2] / devpriv->clock_ns;
3479                         break;
3480                 case TRIG_ROUND_UP:
3481                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3482                         break;
3483                 default:
3484                         return -EINVAL;
3485                         break;
3486                 }
3487                 switch(data[3])
3488                 {
3489                 case TRIG_ROUND_NEAREST:
3490                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3491                         break;
3492                 case TRIG_ROUND_DOWN:
3493                         down_count = data[4] / devpriv->clock_ns;
3494                         break;
3495                 case TRIG_ROUND_UP:
3496                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3497                         break;
3498                 default:
3499                         return -EINVAL;
3500                         break;
3501                 }
3502                 if(up_count * devpriv->clock_ns != data[2] ||
3503                         down_count * devpriv->clock_ns != data[4])
3504                 {
3505                         data[2] = up_count * devpriv->clock_ns;
3506                         data[4] = down_count * devpriv->clock_ns;
3507                         return -EAGAIN;
3508                 }
3509                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3510                 devpriv->pwm_up_count = up_count;
3511                 devpriv->pwm_down_count = down_count;
3512                 return 5;
3513                 break;
3514         case INSN_CONFIG_GET_PWM_OUTPUT:
3515                 return ni_get_pwm_config(dev, data);
3516                 break;
3517         default:
3518                 return -EINVAL;
3519                 break;
3520         }
3521         return 0;
3522 }
3523
3524 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3525         comedi_insn *insn, lsampl_t *data)
3526 {
3527         unsigned up_count, down_count;
3528         switch(data[0])
3529         {
3530         case INSN_CONFIG_PWM_OUTPUT:
3531                 switch(data[1])
3532                 {
3533                 case TRIG_ROUND_NEAREST:
3534                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3535                         break;
3536                 case TRIG_ROUND_DOWN:
3537                         up_count = data[2] / devpriv->clock_ns;
3538                         break;
3539                 case TRIG_ROUND_UP:
3540                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3541                         break;
3542                 default:
3543                         return -EINVAL;
3544                         break;
3545                 }
3546                 switch(data[3])
3547                 {
3548                 case TRIG_ROUND_NEAREST:
3549                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3550                         break;
3551                 case TRIG_ROUND_DOWN:
3552                         down_count = data[4] / devpriv->clock_ns;
3553                         break;
3554                 case TRIG_ROUND_UP:
3555                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3556                         break;
3557                 default:
3558                         return -EINVAL;
3559                         break;
3560                 }
3561                 if(up_count * devpriv->clock_ns != data[2] ||
3562                         down_count * devpriv->clock_ns != data[4])
3563                 {
3564                         data[2] = up_count * devpriv->clock_ns;
3565                         data[4] = down_count * devpriv->clock_ns;
3566                         return -EAGAIN;
3567                 }
3568                 ni_writel(up_count, Calibration_HighTime_6143);
3569                 devpriv->pwm_up_count = up_count;
3570                 ni_writel(down_count, Calibration_LowTime_6143);
3571                 devpriv->pwm_down_count = down_count;
3572                 return 5;
3573                 break;
3574         case INSN_CONFIG_GET_PWM_OUTPUT:
3575                 return ni_get_pwm_config(dev, data);
3576         default:
3577                 return -EINVAL;
3578                 break;
3579         }
3580         return 0;
3581 }
3582
3583 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3584 /*
3585         calibration subdevice
3586 */
3587 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3588         comedi_insn *insn,lsampl_t *data)
3589 {
3590         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3591
3592         return 1;
3593 }
3594
3595 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3596         comedi_insn *insn,lsampl_t *data)
3597 {
3598         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3599
3600         return 1;
3601 }
3602
3603 static int pack_mb88341(int addr,int val,int *bitstring);
3604 static int pack_dac8800(int addr,int val,int *bitstring);
3605 static int pack_dac8043(int addr,int val,int *bitstring);
3606 static int pack_ad8522(int addr,int val,int *bitstring);
3607 static int pack_ad8804(int addr,int val,int *bitstring);
3608 static int pack_ad8842(int addr,int val,int *bitstring);
3609
3610 struct caldac_struct{
3611         int n_chans;
3612         int n_bits;
3613         int (*packbits)(int,int,int *);
3614 };
3615
3616 static struct caldac_struct caldacs[] = {
3617         [mb88341] = { 12, 8, pack_mb88341 },
3618         [dac8800] = { 8, 8, pack_dac8800 },
3619         [dac8043] = { 1, 12, pack_dac8043 },
3620         [ad8522]  = { 2, 12, pack_ad8522 },
3621         [ad8804] = { 12, 8, pack_ad8804 },
3622         [ad8842] = { 8, 8, pack_ad8842 },
3623         [ad8804_debug] = { 16, 8, pack_ad8804 },
3624 };
3625
3626 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3627 {
3628         int i,j;
3629         int n_dacs;
3630         int n_chans=0;
3631         int n_bits;
3632         int diffbits=0;
3633         int type;
3634         int chan;
3635
3636         type = boardtype.caldac[0];
3637         if(type==caldac_none)return;
3638         n_bits=caldacs[type].n_bits;
3639         for(i=0;i<3;i++){
3640                 type = boardtype.caldac[i];
3641                 if(type==caldac_none)break;
3642                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3643                 n_chans+=caldacs[type].n_chans;
3644         }
3645         n_dacs=i;
3646         s->n_chan=n_chans;
3647
3648         if(diffbits){
3649
3650                 if(n_chans>MAX_N_CALDACS){
3651                         printk("BUG! MAX_N_CALDACS too small\n");
3652                 }
3653                 s->maxdata_list=devpriv->caldac_maxdata_list;
3654                 chan=0;
3655                 for(i=0;i<n_dacs;i++){
3656                         type = boardtype.caldac[i];
3657                         for(j=0;j<caldacs[type].n_chans;j++){
3658                                 s->maxdata_list[chan]=
3659                                         (1<<caldacs[type].n_bits)-1;
3660                                 chan++;
3661                         }
3662                 }
3663
3664                 for( chan = 0; chan < s->n_chan; chan++ )
3665                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3666         }else{
3667                 type = boardtype.caldac[0];
3668                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3669
3670                 for( chan = 0; chan < s->n_chan; chan++ )
3671                         ni_write_caldac( dev, i, s->maxdata / 2 );
3672         }
3673 }
3674
3675 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3676 {
3677         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3678         int i;
3679         int type;
3680
3681         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3682         if( devpriv->caldacs[ addr ] == val ) return;
3683         devpriv->caldacs[ addr ] = val;
3684
3685         for(i=0;i<3;i++){
3686                 type = boardtype.caldac[i];
3687                 if(type==caldac_none)break;
3688                 if(addr<caldacs[type].n_chans){
3689                         bits=caldacs[type].packbits(addr,val,&bitstring);
3690                         loadbit=SerDacLd(i);
3691                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3692                         break;
3693                 }
3694                 addr-=caldacs[type].n_chans;
3695         }
3696
3697         for(bit=1<<(bits-1);bit;bit>>=1){
3698                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3699                 comedi_udelay(1);
3700                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3701                 comedi_udelay(1);
3702         }
3703         ni_writeb(loadbit,Serial_Command);
3704         comedi_udelay(1);
3705         ni_writeb(0,Serial_Command);
3706 }
3707
3708
3709
3710 static int pack_mb88341(int addr,int val,int *bitstring)
3711 {
3712         /*
3713            Fujitsu MB 88341
3714            Note that address bits are reversed.  Thanks to
3715            Ingo Keen for noticing this.
3716
3717            Note also that the 88341 expects address values from
3718            1-12, whereas we use channel numbers 0-11.  The NI
3719            docs use 1-12, also, so be careful here.
3720         */
3721         addr++;
3722         *bitstring=((addr&0x1)<<11) |
3723                   ((addr&0x2)<<9)  |
3724                   ((addr&0x4)<<7)  |
3725                   ((addr&0x8)<<5)  |
3726                   (val&0xff);
3727         return 12;
3728 }
3729
3730 static int pack_dac8800(int addr,int val,int *bitstring)
3731 {
3732         *bitstring=((addr&0x7)<<8)|(val&0xff);
3733         return 11;
3734 }
3735
3736 static int pack_dac8043(int addr,int val,int *bitstring)
3737 {
3738         *bitstring=val&0xfff;
3739         return 12;
3740 }
3741
3742 static int pack_ad8522(int addr,int val,int *bitstring)
3743 {
3744         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3745         return 16;
3746 }
3747
3748 static int pack_ad8804(int addr,int val,int *bitstring)
3749 {
3750         *bitstring=((addr&0xf)<<8) | (val&0xff);
3751         return 12;
3752 }
3753
3754 static int pack_ad8842(int addr,int val,int *bitstring)
3755 {
3756         *bitstring=((addr+1)<<8) | (val&0xff);
3757         return 12;
3758 }
3759
3760
3761
3762
3763
3764 /*
3765  *
3766  *  General Purpose Counter/Timer section
3767  *
3768  */
3769
3770 /*
3771  * Low level stuff...Each STC counter has two 24 bit load registers
3772  * (A&B).  Just make it easier to access them.
3773  *
3774  * These are inlined _only_ because they are used once in subsequent
3775  * code.  Otherwise they should not be inlined.
3776  */
3777 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3778 {
3779         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_A_Register(chan));
3780 }
3781
3782 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3783 {
3784         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_B_Register(chan));
3785 }
3786
3787 /*  Load a value into the counter, using register A as the intermediate step.
3788 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3789 *  reset its value.
3790 */
3791 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3792 {
3793         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3794         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3795         GPCT_Load_A(dev,chan,value);
3796         devpriv->stc_writew(dev,  devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3797 }
3798
3799 /*
3800  *      Read the GPCTs current value.
3801  */
3802 static int GPCT_G_Watch(comedi_device *dev, int chan)
3803 {
3804         unsigned int hi1,hi2,lo;
3805
3806         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3807         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3808
3809         devpriv->gpct_command[chan] |= G_Save_Trace;
3810         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
3811
3812         /* This procedure is used because the two registers cannot
3813          * be read atomically. */
3814         do{
3815                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3816                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
3817                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3818         }while(hi1!=hi2);
3819
3820         return (hi1<<16)|lo;
3821 }
3822
3823
3824 static int GPCT_Disarm(comedi_device *dev, int chan)
3825 {
3826         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3827         return 0;
3828 }
3829
3830
3831 static int GPCT_Arm(comedi_device *dev, int chan)
3832 {
3833         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3834         /* If the counter is doing pulse width measurement, then make
3835          sure that the counter did not start counting right away.  This would
3836          indicate that we started acquiring the pulse after it had already
3837          started and our measurement would be inaccurate */
3838         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3839                 int g_status;
3840
3841                 g_status=devpriv->stc_readw(dev, G_Status_Register);
3842
3843                 if(chan == 0){
3844                         //TIM 5/2/01 possible error with very short pulses
3845                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3846                                 //error: we missed the beginning of the pulse
3847                                 return -EINVAL; //there is probably a more accurate error code...
3848                         }
3849                 }else{
3850                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3851                                 //error: we missed the beginning of the pulse
3852                                 return -EINVAL;
3853                         }
3854                 }
3855         }
3856         return 0;
3857 }
3858
3859 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3860 {
3861         //printk("GPCT_Set_Source...");
3862         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3863         switch(source) {
3864                 case GPCT_INT_CLOCK:
3865                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3866                 break;
3867         case GPCT_EXT_PIN:
3868                 if(chan==0)
3869                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3870                 else
3871                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3872                 break;
3873         default:
3874                 return -EINVAL;
3875         }
3876         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3877         //printk("exit GPCT_Set_Source\n");
3878         return 0;
3879 }
3880
3881 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3882 {
3883         //printk("GPCT_Set_Gate...");
3884         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3885         switch(gate) {
3886         case GPCT_NO_GATE:
3887                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3888                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3889                 break;
3890         case GPCT_EXT_PIN:
3891                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3892                 if(chan==0){
3893                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3894                 }else{
3895                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3896                 }
3897                 break;
3898         default:
3899                 return -EINVAL;
3900         }
3901         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3902         devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3903         //printk("exit GPCT_Set_Gate\n");
3904         return 0;
3905 }
3906
3907 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3908 {
3909         //printk("GPCT_Set_Direction...");
3910
3911         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3912         switch (direction) {
3913                 case GPCT_UP:
3914                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3915                         break;
3916                 case GPCT_DOWN:
3917                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3918                         break;
3919                 case GPCT_HWUD:
3920                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3921                         break;
3922                 default:
3923                         rt_printk("Error direction=0x%08x..",direction);
3924                         return -EINVAL;
3925         }
3926         devpriv->stc_writew(dev, devpriv->gpct_command[chan], G_Command_Register(chan));
3927         //TIM 4/23/01 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3928         //printk("exit GPCT_Set_Direction\n");
3929         return 0;
3930 }
3931
3932 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3933 {
3934
3935         //NOTE: possible residual bits from multibit masks can corrupt
3936         //If you config for several measurements between Resets, watch out!
3937
3938         //printk("GPCT_Event_Counting...");
3939
3940         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3941
3942         // Gating_Mode = 1
3943         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3944         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3945
3946         // Trigger_Mode_For_Edge_Gate = 1
3947         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3948         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3949
3950         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3951         //printk("exit GPCT_Event_Counting\n");
3952 }
3953
3954 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3955 {
3956         //printk("GPCT_Period_Meas...");
3957
3958         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3959
3960
3961         //NOTE: possible residual bits from multibit masks can corrupt
3962         //If you config for several measurements between Resets, watch out!
3963         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3964         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3965
3966         // Output_Mode = 3
3967         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
3968         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
3969
3970
3971         //Gating Mode=2
3972         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3973         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
3974
3975         // Trigger_Mode_For_Edge_Gate=0
3976         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3977         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
3978
3979         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
3980         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
3981         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
3982         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
3983
3984         // Stop_Mode = 2
3985         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
3986         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
3987
3988         // Counting_Once = 2
3989         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
3990         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
3991
3992         // Up_Down = 1
3993         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
3994         devpriv->gpct_command[chan] |= G_Up_Down(1);
3995
3996         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3997         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3998         //printk("exit GPCT_Period_Meas\n");
3999 }
4000
4001 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
4002 {
4003         //printk("GPCT_Pulse_Width_Meas...");
4004
4005         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
4006
4007         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4008         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4009
4010         // Output_Mode = 3
4011         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4012         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
4013
4014         //Gating Mode=1
4015         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4016         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
4017
4018         // Trigger_Mode_For_Edge_Gate=2
4019         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4020         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
4021
4022
4023         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
4024         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
4025
4026         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
4027         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4028
4029         // Stop_Mode = 0
4030         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4031         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
4032
4033         // Counting_Once = 2
4034         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4035         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
4036
4037         // Up_Down = 1
4038         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4039         devpriv->gpct_command[chan] |= G_Up_Down(1);
4040
4041         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4042         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4043
4044         //printk("exit GPCT_Pulse_Width_Meas\n");
4045 }
4046
4047 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
4048 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
4049 be modified to send a pulse in response to a trigger event at its gate.*/
4050 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
4051 {
4052         //printk("GPCT_Gen_Cont...");
4053
4054         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
4055
4056         // Set length of the pulse
4057         GPCT_Load_B(dev,chan, length-1);
4058
4059         //Load next time using B, This is reset by GPCT_Load_Using_A()
4060         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4061
4062         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4063         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4064
4065         // Output_Mode = 3
4066         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4067         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4068
4069         //Gating Mode=0 for untriggered single pulse
4070         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4071         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
4072
4073         // Trigger_Mode_For_Edge_Gate=0
4074         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4075         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4076
4077
4078         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4079         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4080         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
4081         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4082
4083         // Stop_Mode = 2
4084         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4085         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
4086
4087         // Counting_Once = 2
4088         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4089         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
4090
4091         // Up_Down = 1
4092         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4093         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
4094
4095         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4096         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4097
4098         //printk("exit GPCT_Gen_Cont\n");
4099 }
4100
4101 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
4102 {
4103         //printk("GPCT_Gen_Cont...");
4104
4105         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
4106
4107         // Set length of the pulse
4108         GPCT_Load_B(dev,chan, length-1);
4109
4110         //Load next time using B, This is reset by GPCT_Load_Using_A()
4111         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4112
4113         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4114         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4115
4116         // Output_Mode = 3
4117         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4118         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4119
4120         //Gating Mode=0 for untriggered single pulse
4121         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4122         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
4123
4124         // Trigger_Mode_For_Edge_Gate=0
4125         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4126         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4127
4128
4129         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4130         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4131         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
4132         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4133
4134         // Stop_Mode = 2
4135         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4136         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
4137
4138         // Counting_Once = 2
4139         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4140         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
4141
4142         // Up_Down = 1
4143         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4144         devpriv->gpct_command[chan] |= G_Up_Down(0);
4145
4146         //TIM 4/26/01
4147         //This seems pretty unsafe since I don't think it is cleared anywhere.
4148         //I don't think this is working
4149         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
4150         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
4151
4152
4153         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4154         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4155
4156         //printk("exit GPCT_Gen_Cont\n");
4157 }
4158
4159 static void GPCT_Reset(comedi_device *dev, int chan)
4160 {
4161         int temp_ack_reg=0;
4162
4163         //printk("GPCT_Reset...");
4164         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4165
4166         switch (chan) {
4167                 case 0:
4168                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4169                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4170                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4171                         temp_ack_reg |= G0_Gate_Error_Confirm;
4172                         temp_ack_reg |= G0_TC_Error_Confirm;
4173                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4174                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4175                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4176
4177                         //problem...this interferes with the other ctr...
4178                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4179                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4180                         break;
4181                 case 1:
4182                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4183                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4184                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4185                         temp_ack_reg |= G1_Gate_Error_Confirm;
4186                         temp_ack_reg |= G1_TC_Error_Confirm;
4187                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4188                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4189                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4190
4191                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4192                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4193                         break;
4194         };
4195
4196         devpriv->gpct_mode[chan] = 0;
4197         devpriv->gpct_input_select[chan] = 0;
4198         devpriv->gpct_command[chan] = 0;
4199
4200         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4201
4202         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4203         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4204         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4205
4206         //printk("exit GPCT_Reset\n");
4207 }
4208
4209 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
4210         comedi_insn *insn,lsampl_t *data)
4211 {
4212         int retval=0;
4213         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4214         switch(data[0]){
4215         case GPCT_RESET:
4216                 if(insn->n!=1)return -EINVAL;
4217                 GPCT_Reset(dev,insn->chanspec);
4218                 break;
4219         case GPCT_SET_SOURCE:
4220                 if(insn->n!=2)return -EINVAL;
4221                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
4222                 break;
4223         case GPCT_SET_GATE:
4224                 if(insn->n!=2)return -EINVAL;
4225                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
4226                 break;
4227         case GPCT_SET_DIRECTION:
4228                 if(insn->n!=2) return -EINVAL;
4229                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
4230                 break;
4231         case GPCT_GET_INT_CLK_FRQ:
4232                 if(insn->n!=2) return -EINVAL;
4233                 //There are actually 2 internal clocks on the STC, we always
4234                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
4235                 //NOTE: This is not the final interface, ideally the user
4236                 //will never need to know the int. clk. freq.
4237                 data[1]=50;//50ns = 20MHz = internal timebase of STC
4238                 break;
4239         case GPCT_SET_OPERATION:
4240                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
4241                 switch(data[1]){
4242                         case GPCT_SIMPLE_EVENT:
4243                                 GPCT_Event_Counting(dev,insn->chanspec);
4244                                 break;
4245                         case GPCT_SINGLE_PERIOD:
4246                                 GPCT_Period_Meas(dev,insn->chanspec);
4247                                 break;
4248                         case GPCT_SINGLE_PW:
4249                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
4250                                 break;
4251                         case GPCT_SINGLE_PULSE_OUT:
4252                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
4253                                 break;
4254                         case GPCT_CONT_PULSE_OUT:
4255                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
4256                                 break;
4257                         default:
4258                                 rt_printk("unsupported GPCT operation!\n");
4259                                 return -EINVAL;
4260                 }
4261                 break;
4262         case GPCT_ARM:
4263                 if(insn->n!=1)return -EINVAL;
4264                 retval=GPCT_Arm(dev,insn->chanspec);
4265                 break;
4266         case GPCT_DISARM:
4267                 if(insn->n!=1)return -EINVAL;
4268                 retval=GPCT_Disarm(dev,insn->chanspec);
4269                 break;
4270         default:
4271                 return -EINVAL;
4272         }
4273
4274         //catch any errors from return values
4275         if(retval==0){
4276                 return insn->n;
4277         }else{
4278                 if(data[0]!=GPCT_ARM){
4279                         rt_printk("error: retval was %d\n",retval);
4280                         rt_printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4281                 }
4282
4283                 return retval;
4284         }
4285 }
4286
4287 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
4288         comedi_insn *insn,lsampl_t *data) {
4289
4290         int chan=insn->chanspec;
4291         int cur_op = devpriv->gpct_cur_operation[chan];
4292
4293         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
4294         if(insn->n!=1)return -EINVAL;
4295
4296         data[0] = GPCT_G_Watch(dev,insn->chanspec);
4297
4298         /* for certain modes (period and pulse width measurment), the value
4299         in the counter is not valid until the counter stops.  If the value is
4300         invalid, return a 0 */
4301         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
4302                 /* is the counter still running? */
4303                 if(devpriv->stc_readw(dev, G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
4304                         data[0]=0;
4305         }
4306         return 1;
4307 }
4308
4309 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
4310         comedi_insn *insn,lsampl_t *data) {
4311
4312         //printk("in ni_gpct_insn_write");
4313         if(insn->n!=1)return -EINVAL;
4314         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
4315         return 1;
4316 }
4317
4318
4319 /*
4320  *
4321  *  Programmable Function Inputs
4322  *
4323  */
4324
4325 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4326 {
4327         if((source & 0x1f) != source) return -EINVAL;
4328         const unsigned pfi_reg_index = 1 + chan / 3;
4329         const unsigned array_offset = pfi_reg_index - 1;
4330         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4331         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4332         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4333         return 2;
4334 }
4335
4336 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4337 {
4338         // pre-m-series boards have fixed signals on pfi pins
4339         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4340         return 2;
4341 }
4342
4343 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4344 {
4345         if(boardtype.reg_type == ni_reg_m_series)
4346                 return ni_m_series_set_pfi_routing(dev, chan, source);
4347         else
4348                 return ni_old_set_pfi_routing(dev, chan, source);
4349 }
4350
4351 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4352 {
4353         const unsigned array_offset = chan / 3;
4354         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4355 }
4356
4357 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4358 {
4359         // pre-m-series boards have fixed signals on pfi pins
4360         switch(chan)
4361         {
4362         case 0:
4363                 return NI_PFI_OUTPUT_AI_START1;
4364                 break;
4365         case 1:
4366                 return NI_PFI_OUTPUT_AI_START2;
4367                 break;
4368         case 2:
4369                 return NI_PFI_OUTPUT_AI_CONVERT;
4370                 break;
4371         case 3:
4372                 return NI_PFI_OUTPUT_G_SRC1;
4373                 break;
4374         case 4:
4375                 return NI_PFI_OUTPUT_G_GATE1;
4376                 break;
4377         case 5:
4378                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4379                 break;
4380         case 6:
4381                 return NI_PFI_OUTPUT_AO_START1;
4382                 break;
4383         case 7:
4384                 return NI_PFI_OUTPUT_AI_START_PULSE;
4385                 break;
4386         case 8:
4387                 return NI_PFI_OUTPUT_G_SRC0;
4388                 break;
4389         case 9:
4390                 return NI_PFI_OUTPUT_G_GATE0;
4391                 break;
4392         default:
4393                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4394                 break;
4395         }
4396         return 0;
4397 }
4398
4399 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4400 {
4401         if(boardtype.reg_type == ni_reg_m_series)
4402                 return ni_m_series_get_pfi_routing(dev, chan);
4403         else
4404                 return ni_old_get_pfi_routing(dev, chan);
4405 }
4406
4407 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4408         comedi_insn *insn,lsampl_t *data)
4409 {
4410         if(boardtype.reg_type != ni_reg_m_series)
4411         {
4412                 data[1] = 0;
4413                 return 2;
4414         }
4415         if(data[0])
4416         {
4417                 s->state &= ~data[0];
4418                 s->state |= (data[0] & data[1]);
4419                 ni_writew(s->state, M_Offset_PFI_DO);
4420         }
4421         data[1] = ni_readw(M_Offset_PFI_DI);
4422         return 2;
4423 }
4424
4425 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4426         comedi_insn *insn,lsampl_t *data)
4427 {
4428         unsigned int chan;
4429
4430         if(insn->n < 1)return -EINVAL;
4431
4432         chan = CR_CHAN(insn->chanspec);
4433
4434         switch(data[0]){
4435         case COMEDI_OUTPUT:
4436                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4437                 break;
4438         case COMEDI_INPUT:
4439                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4440                 break;
4441         case INSN_CONFIG_DIO_QUERY:
4442                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4443                 return insn->n;
4444                 break;
4445         case INSN_CONFIG_SET_ROUTING:
4446                 return ni_set_pfi_routing(dev, chan, data[1]);
4447                 break;
4448         case INSN_CONFIG_GET_ROUTING:
4449                 data[1] = ni_get_pfi_routing(dev, chan);
4450                 return 2;
4451                 break;
4452         default:
4453                 return -EINVAL;
4454         }
4455
4456         return 1;
4457 }
4458
4459 /*
4460  *
4461  *  NI RTSI Bus Functions
4462  *
4463  */
4464 static void ni_rtsi_init(comedi_device *dev)
4465 {
4466         // Initialises the RTSI bus signal switch to a default state
4467
4468         // Set clock mode to internal
4469         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4470         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4471         {
4472                 rt_printk("ni_set_master_clock failed, bug?");
4473         }
4474         // default internal lines routing to RTSI bus lines
4475         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4476                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4477                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4478                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4479         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4480                 RTSI_Trig_A_Output_Register);
4481         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4482                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4483                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4484         if(boardtype.reg_type == ni_reg_m_series)
4485                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4486         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4487                 RTSI_Trig_B_Output_Register);
4488
4489         // Sets the source and direction of the 4 on board lines
4490 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4491 }
4492
4493 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4494         comedi_insn *insn,lsampl_t *data)
4495 {
4496         if(insn->n != 2) return -EINVAL;
4497
4498         data[1] = 0;
4499
4500         return 2;
4501 }
4502
4503 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4504  * given an arbitrary frequency input clock */
4505 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4506         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4507 {
4508         unsigned div;
4509         unsigned best_div = 1;
4510         static const unsigned max_div = 0x10;
4511         unsigned mult;
4512         unsigned best_mult = 1;
4513         static const unsigned max_mult = 0x100;
4514         static const unsigned pico_per_nano = 1000;
4515
4516         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4517         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4518          * 20 MHz for most timing clocks */
4519         static const unsigned target_picosec = 12500;
4520         int best_period_picosec = 0;
4521         for(div = 1; div <= max_div; ++div)
4522         {
4523                 for(mult = 1; mult <= max_mult; ++mult)
4524                 {
4525                         unsigned new_period_ps = (reference_picosec * div) / mult;
4526                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4527                         {
4528                                 best_period_picosec = new_period_ps;
4529                                 best_div = div;
4530                                 best_mult = mult;
4531                         }
4532                 }
4533         }
4534         if(best_period_picosec == 0)
4535         {
4536                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4537                 return -EIO;
4538         }
4539         *freq_divider = best_div;
4540         *freq_multiplier = best_mult;
4541         static const unsigned fudge_factor_80_to_20Mhz = 4;
4542         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4543         return 0;
4544 }
4545
4546 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4547 {
4548         if(boardtype.reg_type == ni_reg_m_series) return 8;
4549         else return 7;
4550 }
4551
4552 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4553 {
4554         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4555         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4556         static const unsigned min_period_ns = 50;
4557         static const unsigned max_period_ns = 1000;
4558         if(period_ns < min_period_ns || period_ns > max_period_ns)
4559         {
4560                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4561                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4562                 return -EINVAL;
4563         }
4564         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4565         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4566         unsigned pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4567         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit;
4568         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4569         int retval;
4570         unsigned freq_divider;
4571         unsigned freq_multiplier;
4572         switch(source)
4573         {
4574         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4575                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4576                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4577                         &freq_multiplier, &devpriv->clock_ns);
4578                 if(retval < 0) return retval;
4579                 break;
4580         case NI_MIO_PLL_PXI10_CLOCK:
4581                 /* pxi clock is 10MHz */
4582                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4583                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4584                         &freq_multiplier, &devpriv->clock_ns);
4585                 if(retval < 0) return retval;
4586                 break;
4587         default:
4588                 {
4589                         unsigned rtsi_channel;
4590                         static const unsigned max_rtsi_channel = 7;
4591                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4592                         {
4593                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4594                                 {
4595                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4596                                         break;
4597                                 }
4598                         }
4599                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4600                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4601                                 &freq_multiplier, &devpriv->clock_ns);
4602                         if(retval < 0) return retval;
4603                 }
4604                 break;
4605         }
4606         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4607         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4608 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4609 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4610         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4611         devpriv->clock_source = source;
4612         unsigned i;
4613         static const unsigned timeout = 1000;
4614         /* it seems to typically take a few hundred microseconds for PLL to lock */
4615         for(i = 0; i < timeout; ++i)
4616         {
4617                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4618                 {
4619                         break;
4620                 }
4621                 udelay(1);
4622         }
4623         if(i == timeout)
4624         {
4625                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4626                         __FUNCTION__, source, period_ns);
4627                 return -ETIMEDOUT;
4628         }
4629         return 3;
4630 }
4631
4632 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4633 {
4634         if(source == NI_MIO_INTERNAL_CLOCK)
4635         {
4636                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4637                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4638                 devpriv->clock_ns = 50;
4639                 if(boardtype.reg_type == ni_reg_m_series)
4640                 {
4641                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4642                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4643                         ni_writew(0, M_Offset_PLL_Control);
4644                 }
4645                 devpriv->clock_source = source;
4646         }else
4647         {
4648                 if(boardtype.reg_type == ni_reg_m_series)
4649                 {
4650                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4651                 }else
4652                 {
4653                         if(source == NI_MIO_RTSI_CLOCK)
4654                         {
4655                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4656                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4657                                 if(devpriv->clock_ns == 0)
4658                                 {
4659                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4660                                                 __FUNCTION__);
4661                                         return -EINVAL;
4662                                 }else
4663                                 {
4664                                         devpriv->clock_ns = period_ns;
4665                                 }
4666                                 devpriv->clock_source = source;
4667                         }else
4668                                 return -EINVAL;
4669                 }
4670         }
4671         return 3;
4672 }
4673
4674 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4675 {
4676         if(chan >= num_configurable_rtsi_channels(dev))
4677         {
4678                 if(chan == old_RTSI_clock_channel)
4679                 {
4680                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4681                         else
4682                         {
4683                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4684                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4685                                 return 0;
4686                         }
4687                 }
4688                 return 0;
4689         }
4690         switch(source)
4691         {
4692         case NI_RTSI_OUTPUT_ADR_START1:
4693         case NI_RTSI_OUTPUT_ADR_START2:
4694         case NI_RTSI_OUTPUT_SCLKG:
4695         case NI_RTSI_OUTPUT_DACUPDN:
4696         case NI_RTSI_OUTPUT_DA_START1:
4697         case NI_RTSI_OUTPUT_G_SRC0:
4698         case NI_RTSI_OUTPUT_G_GATE0:
4699         case NI_RTSI_OUTPUT_RGOUT0:
4700         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4701                 return 1;
4702                 break;
4703         case NI_RTSI_OUTPUT_RTSI_OSC:
4704                 if(boardtype.reg_type == ni_reg_m_series)
4705                         return 1;
4706                 else return 0;
4707                 break;
4708         default:
4709                 return 0;
4710                 break;
4711         }
4712 }
4713
4714 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4715 {
4716         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4717         if(chan < 4)
4718         {
4719                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4720                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4721                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4722                         RTSI_Trig_A_Output_Register);
4723         }else if(chan < 8)
4724         {
4725                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4726                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4727                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4728                         RTSI_Trig_B_Output_Register);
4729         }
4730         return 2;
4731 }
4732
4733 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4734 {
4735         if(chan < 4)
4736         {
4737                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4738         }else if(chan < num_configurable_rtsi_channels(dev))
4739         {
4740                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4741         }else
4742         {
4743                 if(chan == old_RTSI_clock_channel)
4744                         return NI_RTSI_OUTPUT_RTSI_OSC;
4745                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4746                 return 0;
4747         }
4748 }
4749
4750 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4751         comedi_insn *insn,lsampl_t *data)
4752 {
4753         unsigned int chan = CR_CHAN(insn->chanspec);
4754         switch(data[0]){
4755         case INSN_CONFIG_DIO_OUTPUT:
4756                 if(chan < num_configurable_rtsi_channels(dev))
4757                 {
4758                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4759                 }else if(chan == old_RTSI_clock_channel)
4760                 {
4761                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4762                 }
4763                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4764                 break;
4765         case INSN_CONFIG_DIO_INPUT:
4766                 if(chan < num_configurable_rtsi_channels(dev))
4767                 {
4768                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4769                 }else if(chan == old_RTSI_clock_channel)
4770                 {
4771                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4772                 }
4773                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4774                 break;
4775         case INSN_CONFIG_DIO_QUERY:
4776                 if(chan < num_configurable_rtsi_channels(dev))
4777                 {
4778                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series)) ?
4779                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4780                 }else if(chan == old_RTSI_clock_channel)
4781                 {
4782                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4783                 }
4784                 return 2;
4785                 break;
4786         case INSN_CONFIG_SET_CLOCK_SRC:
4787                 return ni_set_master_clock(dev, data[1], data[2]);
4788                 break;
4789         case INSN_CONFIG_GET_CLOCK_SRC:
4790                 data[1] = devpriv->clock_source;
4791                 data[2] = devpriv->clock_ns;
4792                 return 3;
4793                 break;
4794         case INSN_CONFIG_SET_ROUTING:
4795                 return ni_set_rtsi_routing(dev, chan, data[1]);
4796                 break;
4797         case INSN_CONFIG_GET_ROUTING:
4798                 data[1] = ni_get_rtsi_routing(dev, chan);
4799                 return 2;
4800                 break;
4801         default:
4802                 return -EINVAL;
4803                 break;
4804         }
4805         return 1;
4806 }
4807
4808 static int cs5529_wait_for_idle(comedi_device *dev)
4809 {
4810         unsigned short status;
4811         const int timeout = HZ;
4812         int i;
4813
4814         for(i = 0; i < timeout; i++)
4815         {
4816                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4817                 if((status & CSS_ADC_BUSY) == 0)
4818                 {
4819                         break;
4820                 }
4821                 set_current_state(TASK_INTERRUPTIBLE);
4822                 if(schedule_timeout(1))
4823                 {
4824                         return -EIO;
4825                 }
4826         }
4827 //printk("looped %i times waiting for idle\n", i);
4828         if(i == timeout)
4829         {
4830                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4831                 return -ETIME;
4832         }
4833         return 0;
4834 }
4835
4836 static void cs5529_command(comedi_device *dev, unsigned short value)
4837 {
4838         static const int timeout = 100;
4839         int i;
4840
4841         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4842         /* give time for command to start being serially clocked into cs5529.
4843          * this insures that the CSS_ADC_BUSY bit will get properly
4844          * set before we exit this function.
4845         */
4846         for(i = 0; i < timeout; i++)
4847         {
4848                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4849                         break;
4850                 comedi_udelay(1);
4851         }
4852 //printk("looped %i times writing command to cs5529\n", i);
4853         if(i == timeout)
4854         {
4855                 comedi_error(dev, "possible problem - never saw adc go busy?");
4856         }
4857 }
4858
4859 /* write to cs5529 register */
4860 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4861 {
4862         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4863         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4864         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4865         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4866         if(cs5529_wait_for_idle(dev))
4867                 comedi_error(dev, "time or signal in cs5529_config_write()");
4868 }
4869
4870 /* read from cs5529 register */
4871 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4872 {
4873         unsigned int value;
4874
4875         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4876         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4877         if(cs5529_wait_for_idle(dev))
4878                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4879         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4880         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4881         return value;
4882 }
4883
4884 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4885 {
4886         int retval;
4887         unsigned short status;
4888
4889         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4890         retval = cs5529_wait_for_idle(dev);
4891         if(retval)
4892         {
4893                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4894                 return -ETIME;
4895         }
4896         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4897         if(status & CSS_OSC_DETECT)
4898         {
4899                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4900                 return -EIO;
4901         }
4902         if(status & CSS_OVERRANGE)
4903         {
4904                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4905         }
4906         if(data)
4907         {
4908                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4909                 /* cs5529 returns 16 bit signed data in bipolar mode */
4910                 *data ^= (1 << 15);
4911         }
4912         return 0;
4913 }
4914
4915 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4916 {
4917         int n, retval;
4918         unsigned short sample;
4919         unsigned int channel_select;
4920         const unsigned int INTERNAL_REF = 0x1000;
4921
4922         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4923          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4924          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4925         if(insn->chanspec & CR_ALT_SOURCE)
4926                 channel_select = INTERNAL_REF;
4927         else
4928                 channel_select = CR_CHAN(insn->chanspec);
4929         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4930
4931         for(n = 0; n < insn->n; n++)
4932         {
4933                 retval = cs5529_do_conversion(dev, &sample);
4934                 if(retval < 0) return retval;
4935                 data[n] = sample;
4936         }
4937         return insn->n;
4938 }
4939
4940 static int init_cs5529(comedi_device *dev)
4941 {
4942         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4943
4944 #if 1
4945         /* do self-calibration */
4946         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4947         /* need to force a conversion for calibration to run */
4948         cs5529_do_conversion(dev, NULL);
4949 #else
4950         /* force gain calibration to 1 */
4951         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4952         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4953         if(cs5529_wait_for_idle(dev))
4954                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4955 #endif
4956         if(0)
4957         {
4958                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4959                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4960                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4961         }
4962         return 0;
4963 }
4964
4965