comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode);
 264
 265 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 266         comedi_insn *insn,lsampl_t *data);
 267 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 268         comedi_insn *insn,lsampl_t *data);
 269 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 270         comedi_insn *insn,lsampl_t *data);
 271 static int ni_gpct_cmd(comedi_device *dev,comedi_subdevice *s);
 272 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 273 static int ni_gpct_cancel(comedi_device *dev,comedi_subdevice *s);
 274
 275 static int init_cs5529(comedi_device *dev);
 276 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 277 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 278 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 279 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 280
 281 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 282         comedi_insn *insn,lsampl_t *data);
 283 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 284         comedi_insn *insn, lsampl_t *data);
 285
 286 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 287
 288 enum aimodes
 289 {
 290         AIMODE_NONE = 0,
 291         AIMODE_HALF_FULL = 1,
 292         AIMODE_SCAN = 2,
 293         AIMODE_SAMPLE = 3,
 294 };
 295
 296 #define SERIAL_DISABLED         0
 297 #define SERIAL_600NS            600
 298 #define SERIAL_1_2US            1200
 299 #define SERIAL_10US                     10000
 300
 301 static const int num_adc_stages_611x = 3;
 302
 303 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 304         unsigned int m_status);
 305 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 306         unsigned int m_status);
 307 static void get_last_sample_611x( comedi_device *dev );
 308 static void get_last_sample_6143( comedi_device *dev );
 309 #ifdef PCIDMA
 310 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 311 static int ni_ai_drain_dma(comedi_device *dev );
 312
 313 /* DMA channel setup */
 314
 315 static inline void ni_set_ai_dma_channel(comedi_device *dev, int channel)
 316 {
 317         unsigned long flags;
 318
 319         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 320         devpriv->ai_ao_select_reg &= ~AI_DMA_Select_Mask;
 321         if(channel >= 0)
 322         {
 323                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 324         }
 325         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 326         mmiowb();
 327         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 328 }
 329
 330 static inline void ni_set_ao_dma_channel(comedi_device *dev, int channel)
 331 {
 332         unsigned long flags;
 333
 334         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 335         devpriv->ai_ao_select_reg &= ~AO_DMA_Select_Mask;
 336         if(channel >= 0)
 337         {
 338                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 339         }
 340         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 341         mmiowb();
 342         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 343 }
 344
 345 static int ni_request_ai_mite_channel(comedi_device *dev)
 346 {
 347         unsigned long flags;
 348         static const unsigned max_dma_channel = 5;
 349
 350         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 351         BUG_ON(devpriv->ai_mite_chan);
 352         devpriv->ai_mite_chan = mite_request_channel_in_range(devpriv->mite, devpriv->ai_mite_ring, 0, max_dma_channel);
 353         if(devpriv->ai_mite_chan == NULL)
 354         {
 355                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 356                 comedi_error(dev, "failed to reserve mite dma channel for analog input.");
 357                 return -EBUSY;
 358         }
 359         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 360         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 361         return 0;
 362 }
 363
 364 static int ni_request_ao_mite_channel(comedi_device *dev)
 365 {
 366         unsigned long flags;
 367         static const unsigned max_dma_channel = 5;
 368
 369         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 370         BUG_ON(devpriv->ao_mite_chan);
 371         devpriv->ao_mite_chan = mite_request_channel_in_range(devpriv->mite, devpriv->ao_mite_ring, 0, max_dma_channel);
 372         if(devpriv->ao_mite_chan == NULL)
 373         {
 374                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 375                 comedi_error(dev, "failed to reserve mite dma channel for analog outut.");
 376                 return -EBUSY;
 377         }
 378         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 379         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 380         return 0;
 381 }
 382
 383 #endif  // PCIDMA
 384
 385 static void ni_release_ai_mite_channel(comedi_device *dev)
 386 {
 387 #ifdef PCIDMA
 388         unsigned long flags;
 389
 390         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 391         if(devpriv->ai_mite_chan)
 392         {
 393                 mite_release_channel(devpriv->ai_mite_chan);
 394                 devpriv->ai_mite_chan = NULL;
 395                 ni_set_ai_dma_channel(dev, -1);
 396         }
 397         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 398 #endif  // PCIDMA
 399 }
 400
 401 static void ni_release_ao_mite_channel(comedi_device *dev)
 402 {
 403 #ifdef PCIDMA
 404         unsigned long flags;
 405
 406         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 407         if(devpriv->ao_mite_chan)
 408         {
 409                 mite_release_channel(devpriv->ao_mite_chan);
 410                 devpriv->ao_mite_chan = NULL;
 411                 ni_set_ao_dma_channel(dev, -1);
 412         }
 413         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 414 #endif  // PCIDMA
 415 }
 416
 417 static void ni_clear_ai_fifo(comedi_device *dev){
 418         if(boardtype.reg_type == ni_reg_6143){
 419                 // Flush the 6143 data FIFO
 420                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 421                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 422                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 423         }else {
 424                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 425                 if(boardtype.reg_type == ni_reg_625x)
 426                 {
 427                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 428                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 429 #if 0
 430                 /* the NI example code does 3 convert pulses for 625x boards,
 431                 but that appears to be wrong in practice. */
 432                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 433                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 434                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 435 #endif
 436                 }
 437         }
 438 }
 439
 440 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 441 {
 442         devpriv->stc_writew(dev, data >> 16, reg);
 443         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 444 }
 445
 446 static uint32_t win_in2(comedi_device *dev, int reg)
 447 {
 448         uint32_t bits;
 449         bits = devpriv->stc_readw(dev, reg) << 16;
 450         bits |= devpriv->stc_readw(dev, reg + 1);
 451         return bits;
 452 }
 453
 454 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 455 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 456 {
 457         unsigned long flags;
 458
 459         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 460         ni_writew(addr,AO_Window_Address_611x);
 461         ni_writew(data,AO_Window_Data_611x);
 462         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 463 }
 464
 465 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 466 {
 467         unsigned long flags;
 468
 469         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 470         ni_writew(addr,AO_Window_Address_611x);
 471         ni_writel(data,AO_Window_Data_611x);
 472         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 473 }
 474
 475 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 476 {
 477         unsigned long flags;
 478         unsigned short data;
 479
 480         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 481         ni_writew(addr, AO_Window_Address_611x);
 482         data = ni_readw(AO_Window_Data_611x);
 483         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 484         return data;
 485 }
 486
 487 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 488 * share registers (such as Interrupt_A_Register) without interfering with
 489 * each other.
 490 *
 491 * NOTE: the switch/case statements are optimized out for a constant argument
 492 * so this is actually quite fast---  If you must wrap another function around this
 493 * make it inline to avoid a large speed penalty.
 494 *
 495 * value should only be 1 or 0.
 496 */
 497 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 498 {
 499         unsigned long flags;
 500
 501         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 502         switch (reg){
 503                 case Interrupt_A_Enable_Register:
 504                         if(value)
 505                                 devpriv->int_a_enable_reg |= bits;
 506                         else
 507                                 devpriv->int_a_enable_reg &= ~bits;
 508                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 509                         break;
 510                 case Interrupt_B_Enable_Register:
 511                         if(value)
 512                                 devpriv->int_b_enable_reg |= bits;
 513                         else
 514                                 devpriv->int_b_enable_reg &= ~bits;
 515                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 516                         break;
 517                 case IO_Bidirection_Pin_Register:
 518                         if(value)
 519                                 devpriv->io_bidirection_pin_reg |= bits;
 520                         else
 521                                 devpriv->io_bidirection_pin_reg &= ~bits;
 522                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 523                         break;
 524                 default:
 525                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 526                         rt_printk("reg is %d\n",reg);
 527                         break;
 528         }
 529         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags );
 530 }
 531
 532
 533 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 534 {
 535         comedi_device *dev=d;
 536         unsigned short a_status;
 537         unsigned short b_status;
 538         unsigned int ai_mite_status = 0;
 539         unsigned int ao_mite_status = 0;
 540         unsigned long flags;
 541 #ifdef PCIDMA
 542         struct mite_struct *mite = devpriv->mite;
 543 #endif
 544
 545         if(dev->attached == 0) return IRQ_NONE;
 546         // lock to avoid race with comedi_poll
 547         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 548         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 549         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 550 #ifdef PCIDMA
 551         if(devpriv->ai_mite_chan)
 552                 ai_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ai_mite_chan->channel));
 553         if(devpriv->ao_mite_chan)
 554                 ao_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ao_mite_chan->channel));
 555 #endif
 556
 557         if(a_status & Interrupt_A_St || ai_mite_status & CHSR_INT )
 558                 handle_a_interrupt(dev, a_status, ai_mite_status);
 559         if(b_status & Interrupt_B_St || ao_mite_status & CHSR_INT )
 560                 handle_b_interrupt(dev, b_status, ao_mite_status);
 561         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 562         return IRQ_HANDLED;
 563 }
 564
 565 #ifdef PCIDMA
 566 static void ni_sync_ai_dma(comedi_device *dev)
 567 {
 568         comedi_subdevice *s = dev->subdevices + 0;
 569         int retval;
 570
 571         if(devpriv->ai_mite_chan == NULL) return;
 572         retval = mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 573         if(retval < 0)
 574         {
 575                 ni_ai_reset(dev,s);
 576                 return;
 577         }
 578 }
 579
 580 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 581 {
 582         comedi_subdevice *s = dev->subdevices + 1;
 583
 584         if(devpriv->ao_mite_chan == NULL) return;
 585         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 586
 587         if(mite_sync_output_dma(devpriv->ao_mite_chan, s->async) < 0)
 588         {
 589                 ni_ao_reset(dev, s);
 590                 return;
 591         }
 592 }
 593
 594 // #define DEBUG_DMA_TIMING
 595 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 596 {
 597         static const int timeout = 10000;
 598         int i;
 599 #ifdef DEBUG_DMA_TIMING
 600         struct timeval start;
 601         do_gettimeofday(&start);
 602 #endif
 603         for(i = 0; i < timeout; i++)
 604         {
 605                 unsigned short b_status;
 606
 607                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 608                 if( b_status & AO_FIFO_Half_Full_St )
 609                         break;
 610                 /* if we poll too often, the pci bus activity seems
 611                  to slow the dma transfer down */
 612                 comedi_udelay(10);
 613         }
 614 #ifdef DEBUG_DMA_TIMING
 615         rt_printk("looped %i times waiting for ao fifo load.\n", i);
 616         struct timeval now;
 617         do_gettimeofday(&now);
 618         unsigned elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 619         rt_printk("total elapsed usec=%i\n", elapsed_usec);
 620         do_gettimeofday(&start);
 621         unsigned b_status;
 622         for(i = 0; i < 100; ++i)
 623         {
 624 //              devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
 625                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 626         }
 627         do_gettimeofday(&now);
 628         elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 629         rt_printk("usec to do 100 word xfers=%i\n", elapsed_usec);
 630 #endif
 631         if( i == timeout )
 632         {
 633                 comedi_error(dev, "timed out waiting for dma load");
 634                 return -EPIPE;
 635         }
 636         return 0;
 637 }
 638
 639 #endif //PCIDMA
 640 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 641 {
 642         if(devpriv->aimode == AIMODE_SCAN)
 643         {
 644 #ifdef PCIDMA
 645                 static const int timeout = 10;
 646                 int i;
 647
 648                 for(i = 0; i < timeout; i++)
 649                 {
 650                         ni_sync_ai_dma(dev);
 651                         if((s->async->events & COMEDI_CB_EOS)) break;
 652                         comedi_udelay(1);
 653                 }
 654 #else
 655                 ni_handle_fifo_dregs(dev);
 656                 s->async->events |= COMEDI_CB_EOS;
 657 #endif
 658         }
 659         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 660         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 661                 shutdown_ai_command( dev );
 662                 ni_ai_reset(dev, s);
 663         }
 664 }
 665
 666 static void shutdown_ai_command( comedi_device *dev )
 667 {
 668         comedi_subdevice *s = dev->subdevices + 0;
 669
 670 #ifdef PCIDMA
 671         ni_ai_drain_dma( dev );
 672         if(devpriv->ai_mite_chan)
 673         {
 674                 mite_dma_disarm(devpriv->ai_mite_chan);
 675         }
 676 #endif
 677         ni_handle_fifo_dregs(dev);
 678         get_last_sample_611x(dev);
 679         get_last_sample_6143(dev);
 680
 681         ni_set_bits(dev, Interrupt_A_Enable_Register,
 682                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 683                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 684                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 685                 AI_FIFO_Interrupt_Enable,0);
 686
 687         s->async->events |= COMEDI_CB_EOA;
 688 }
 689
 690 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 691         unsigned int m_status)
 692 {
 693         comedi_subdevice *s=dev->subdevices+0;
 694         unsigned short ack=0;
 695
 696         s->async->events = 0;
 697
 698 #ifdef DEBUG_INTERRUPT
 699         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 700                 status, m_status);
 701         ni_mio_print_status_a(status);
 702 #endif
 703
 704
 705 #ifdef PCIDMA
 706         /* Currently, mite.c requires us to handle LINKC and DONE */
 707         if(m_status & CHSR_LINKC){
 708                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 709                 ni_sync_ai_dma(dev);
 710         }
 711
 712         if(m_status & CHSR_DONE){
 713                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 714         }
 715
 716         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 717                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 718                 //mite_print_chsr(m_status);
 719                 mite_dma_disarm(devpriv->ai_mite_chan);
 720                 mite_dma_reset(devpriv->ai_mite_chan);
 721                 //disable_irq(dev->irq);
 722         }
 723 #endif
 724
 725         /* test for all uncommon interrupt events at the same time */
 726         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 727                 if(status==0xffff){
 728                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 729                         /* we probably aren't even running a command now,
 730                          * so it's a good idea to be careful. */
 731                         if(s->subdev_flags&SDF_RUNNING){
 732                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 733                                 comedi_event(dev,s,s->async->events);
 734                         }
 735                         return;
 736                 }
 737                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 738                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 739                                 status);
 740                         ni_mio_print_status_a(status);
 741
 742                         ni_ai_reset(dev,dev->subdevices);
 743
 744
 745                         shutdown_ai_command( dev );
 746
 747                         s->async->events |= COMEDI_CB_ERROR;
 748                         if(status & (AI_Overrun_St | AI_Overflow_St))
 749                                 s->async->events |= COMEDI_CB_OVERFLOW;
 750
 751                         comedi_event(dev,s,s->async->events);
 752
 753                         return;
 754                 }
 755                 if(status&AI_SC_TC_St){
 756 #ifdef DEBUG_INTERRUPT
 757                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 758 #endif
 759                         if(!devpriv->ai_continuous){
 760                                 shutdown_ai_command( dev );
 761                         }
 762                         ack|=AI_SC_TC_Interrupt_Ack;
 763                 }
 764                 if(status&AI_START1_St){
 765                         ack|=AI_START1_Interrupt_Ack;
 766                 }
 767         }
 768 #ifndef PCIDMA
 769         if(status&AI_FIFO_Half_Full_St){
 770                 int i;
 771                 static const int timeout = 10;
 772                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 773                  *fail to get the fifo less than half full, so loop to be sure.*/
 774                 for(i = 0; i < timeout; ++i)
 775                 {
 776                         ni_handle_fifo_half_full(dev);
 777                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 778                                 break;
 779                 }
 780         }
 781 #endif // !PCIDMA
 782
 783         if( (status & AI_STOP_St) ){
 784                 ni_handle_eos(dev, s);
 785                 /* we need to ack the START, also */
 786                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 787         }
 788 #if 0
 789         if(devpriv->aimode==AIMODE_SAMPLE){
 790                 ni_handle_fifo_dregs(dev);
 791
 792                 //s->async->events |= COMEDI_CB_SAMPLE;
 793         }
 794 #endif
 795         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 796         comedi_event(dev,s,s->async->events);
 797
 798 #ifdef DEBUG_INTERRUPT
 799         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 800         if(status&Interrupt_A_St){
 801                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 802         }
 803 #endif
 804 }
 805
 806 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 807 {
 808         comedi_subdevice *s=dev->subdevices+1;
 809         //unsigned short ack=0;
 810 #ifdef DEBUG_INTERRUPT
 811         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 812                 b_status,m_status);
 813         ni_mio_print_status_b(b_status);
 814 #endif
 815
 816
 817 #ifdef PCIDMA
 818         /* Currently, mite.c requires us to handle LINKC and DONE */
 819         if(m_status & CHSR_LINKC){
 820                 mite_handle_b_linkc(devpriv->mite, dev);
 821         }
 822
 823         if(m_status & CHSR_DONE){
 824                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 825         }
 826
 827         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 828                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 829                 //mite_print_chsr(m_status);
 830                 mite_dma_disarm(devpriv->ao_mite_chan);
 831                 mite_dma_reset(devpriv->ao_mite_chan);
 832         }
 833 #endif
 834
 835         if(b_status==0xffff)return;
 836         if(b_status&AO_Overrun_St){
 837                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 838                 ni_ao_reset(dev,s);
 839                 s->async->events |= COMEDI_CB_OVERFLOW;
 840         }
 841
 842         if(b_status&AO_BC_TC_St){
 843                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 844                 ni_ao_reset(dev,s);
 845                 s->async->events |= COMEDI_CB_EOA;
 846         }
 847
 848 #ifndef PCIDMA
 849         if(b_status&AO_FIFO_Request_St){
 850                 int ret;
 851
 852                 ret = ni_ao_fifo_half_empty(dev,s);
 853                 if(!ret){
 854                         rt_printk("ni_mio_common: AO buffer underrun\n");
 855                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 856                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 857                         s->async->events |= COMEDI_CB_OVERFLOW;
 858                 }
 859         }
 860 #endif
 861
 862         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 863         if(b_status&Interrupt_B_St){
 864                 if(b_status&AO_FIFO_Request_St){
 865                         rt_printk("ni_mio_common: AO buffer underrun\n");
 866                 }
 867                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 868                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 869                 ni_ao_reset(dev,s);
 870                 s->async->events |= COMEDI_CB_OVERFLOW;
 871         }
 872
 873         comedi_event(dev,s,s->async->events);
 874 }
 875
 876 #ifdef DEBUG_STATUS_A
 877 static char *status_a_strings[]={
 878         "passthru0","fifo","G0_gate","G0_TC",
 879         "stop","start","sc_tc","start1",
 880         "start2","sc_tc_error","overflow","overrun",
 881         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 882 };
 883
 884 static void ni_mio_print_status_a(int status)
 885 {
 886         int i;
 887
 888         rt_printk("A status:");
 889         for(i=15;i>=0;i--){
 890                 if(status&(1<<i)){
 891                         rt_printk(" %s",status_a_strings[i]);
 892                 }
 893         }
 894         rt_printk("\n");
 895 }
 896 #endif
 897
 898 #ifdef DEBUG_STATUS_B
 899 static char *status_b_strings[]={
 900         "passthru1","fifo","G1_gate","G1_TC",
 901         "UI2_TC","UPDATE","UC_TC","BC_TC",
 902         "start1","overrun","start","bc_tc_error",
 903         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 904 };
 905
 906 static void ni_mio_print_status_b(int status)
 907 {
 908         int i;
 909
 910         rt_printk("B status:");
 911         for(i=15;i>=0;i--){
 912                 if(status&(1<<i)){
 913                         rt_printk(" %s",status_b_strings[i]);
 914                 }
 915         }
 916         rt_printk("\n");
 917 }
 918 #endif
 919
 920 #ifndef PCIDMA
 921
 922 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 923 {
 924         comedi_async *async = s->async;
 925         comedi_cmd *cmd = &async->cmd;
 926         int chan;
 927         int i;
 928         sampl_t d;
 929         u32 packed_data;
 930         int range;
 931         int err = 1;
 932
 933         chan = async->cur_chan;
 934         for(i=0;i<n;i++){
 935                 err &= comedi_buf_get(async, &d);
 936                 if(err == 0) break;
 937
 938                 range = CR_RANGE(cmd->chanlist[chan]);
 939
 940                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 941                 {
 942                         packed_data = d & 0xffff;
 943                         /* 6711 only has 16 bit wide ao fifo */
 944                         if(boardtype.reg_type != ni_reg_6711)
 945                         {
 946                                 err &= comedi_buf_get(async, &d);
 947                                 if(err == 0) break;
 948                                 chan++;
 949                                 i++;
 950                                 packed_data |= ( d << 16 ) & 0xffff0000;
 951                         }
 952                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 953                 }else{
 954                         ni_writew(d, DAC_FIFO_Data);
 955                 }
 956                 chan++;
 957                 chan %= cmd->chanlist_len;
 958         }
 959         async->cur_chan = chan;
 960         if(err==0){
 961                 async->events |= COMEDI_CB_OVERFLOW;
 962         }
 963 }
 964
 965 /*
 966  *  There's a small problem if the FIFO gets really low and we
 967  *  don't have the data to fill it.  Basically, if after we fill
 968  *  the FIFO with all the data available, the FIFO is _still_
 969  *  less than half full, we never clear the interrupt.  If the
 970  *  IRQ is in edge mode, we never get another interrupt, because
 971  *  this one wasn't cleared.  If in level mode, we get flooded
 972  *  with interrupts that we can't fulfill, because nothing ever
 973  *  gets put into the buffer.
 974  *
 975  *  This kind of situation is recoverable, but it is easier to
 976  *  just pretend we had a FIFO underrun, since there is a good
 977  *  chance it will happen anyway.  This is _not_ the case for
 978  *  RT code, as RT code might purposely be running close to the
 979  *  metal.  Needs to be fixed eventually.
 980  */
 981 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 982 {
 983         int n;
 984
 985         n = comedi_buf_read_n_available(s->async);
 986         if(n==0){
 987                 s->async->events |= COMEDI_CB_OVERFLOW;
 988                 return 0;
 989         }
 990
 991         n /= sizeof(sampl_t);
 992         if(n > boardtype.ao_fifo_depth / 2)
 993                 n = boardtype.ao_fifo_depth / 2;
 994
 995         ni_ao_fifo_load(dev,s,n);
 996
 997         s->async->events |= COMEDI_CB_BLOCK;
 998
 999         return 1;
1000 }
1001
1002 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
1003 {
1004         int n;
1005
1006         /* reset fifo */
1007         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
1008         if(boardtype.reg_type & ni_reg_6xxx_mask)
1009                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1010
1011         /* load some data */
1012         n = comedi_buf_read_n_available(s->async);
1013         if(n==0)return 0;
1014
1015         n /= sizeof(sampl_t);
1016         if(n > boardtype.ao_fifo_depth)
1017                 n = boardtype.ao_fifo_depth;
1018
1019         ni_ao_fifo_load(dev,s,n);
1020
1021         return n;
1022 }
1023
1024 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
1025         int n)
1026 {
1027         comedi_async *async = s->async;
1028         int i;
1029
1030         if(boardtype.reg_type == ni_reg_611x){
1031                 sampl_t data[2];
1032                 u32 dl;
1033
1034                 for( i = 0; i < n / 2; i++ ){
1035                         dl=ni_readl(ADC_FIFO_Data_611x);
1036                         /* This may get the hi/lo data in the wrong order */
1037                         data[0] = (dl>>16) & 0xffff;
1038                         data[1] = dl & 0xffff;
1039                         cfc_write_array_to_buffer(s, data, sizeof(data));
1040                 }
1041                 /* Check if there's a single sample stuck in the FIFO */
1042                 if( n % 2){
1043                         dl=ni_readl(ADC_FIFO_Data_611x);
1044                         data[0] = dl & 0xffff;
1045                         cfc_write_to_buffer(s, data[0]);
1046                 }
1047         } else if(boardtype.reg_type == ni_reg_6143){
1048                 sampl_t data[2];
1049                 u32     dl;
1050
1051                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1052                 for(i = 0; i < n / 2; i++){
1053                         dl = ni_readl(AIFIFO_Data_6143);
1054
1055                         data[0] = (dl >> 16) & 0xffff;
1056                         data[1] = dl & 0xffff;
1057                         cfc_write_array_to_buffer(s, data, sizeof(data));
1058                 }
1059                 if(n % 2){
1060                         /* Assume there is a single sample stuck in the FIFO */
1061                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1062                         dl = ni_readl(AIFIFO_Data_6143);
1063                         data[0] = (dl >> 16) & 0xffff;
1064                         cfc_write_to_buffer(s, data[0]);
1065                 }
1066         } else{
1067                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1068                 {
1069                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1070                         async->events |= COMEDI_CB_ERROR;
1071                         return;
1072                 }
1073                 for(i = 0; i < n; i++){
1074                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1075                 }
1076                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1077                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1078         }
1079 }
1080
1081 static void ni_handle_fifo_half_full(comedi_device *dev)
1082 {
1083         int n;
1084         comedi_subdevice *s=dev->subdevices+0;
1085
1086         n=boardtype.ai_fifo_depth/2;
1087
1088         ni_ai_fifo_read(dev,s,n);
1089 }
1090 #endif
1091
1092 #ifdef PCIDMA
1093 static int ni_ai_drain_dma(comedi_device *dev )
1094 {
1095         int i;
1096         static const int timeout = 10000;
1097
1098         if(devpriv->ai_mite_chan == NULL) return 0;
1099         for( i = 0; i < timeout; i++ )
1100         {
1101                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1102                         mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
1103                         break;
1104                 comedi_udelay(2);
1105         }
1106         if(i == timeout)
1107         {
1108                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1109                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1110                         mite_bytes_in_transit(devpriv->ai_mite_chan), devpriv->stc_readw(dev, AI_Status_1_Register));
1111                 return -1;
1112         }
1113
1114         ni_sync_ai_dma(dev);
1115
1116         return 0;
1117 }
1118 #endif
1119 /*
1120    Empties the AI fifo
1121 */
1122 static void ni_handle_fifo_dregs(comedi_device *dev)
1123 {
1124         comedi_subdevice *s=dev->subdevices+0;
1125         sampl_t data[2];
1126         u32 dl;
1127         short fifo_empty;
1128         int i;
1129
1130         if(boardtype.reg_type == ni_reg_611x){
1131                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1132                         dl=ni_readl(ADC_FIFO_Data_611x);
1133
1134                         /* This may get the hi/lo data in the wrong order */
1135                         data[0] = (dl>>16);
1136                         data[1] = (dl&0xffff);
1137                         cfc_write_array_to_buffer(s, data, sizeof(data));
1138                 }
1139         }else if(boardtype.reg_type == ni_reg_6143){
1140                 i = 0;
1141                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1142                         dl = ni_readl(AIFIFO_Data_6143);
1143
1144                         /* This may get the hi/lo data in the wrong order */
1145                         data[0] = (dl >> 16);
1146                         data[1] = (dl & 0xffff);
1147                         cfc_write_array_to_buffer(s, data, sizeof(data));
1148                         i += 2;
1149                 }
1150                 // Check if stranded sample is present
1151                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1152                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1153                         dl = ni_readl(AIFIFO_Data_6143);
1154                         data[0] = (dl >> 16) & 0xffff;
1155                         cfc_write_to_buffer(s, data[0]);
1156                 }
1157
1158         }else{
1159                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1160                 while(fifo_empty == 0)
1161                 {
1162                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1163                         {
1164                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1165                                 if(fifo_empty) break;
1166                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1167                         }
1168                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1169                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1170                 }
1171         }
1172 }
1173
1174 static void get_last_sample_611x( comedi_device *dev )
1175 {
1176         comedi_subdevice *s=dev->subdevices+0;
1177         sampl_t data;
1178         u32 dl;
1179
1180         if(boardtype.reg_type != ni_reg_611x) return;
1181
1182         /* Check if there's a single sample stuck in the FIFO */
1183         if(ni_readb(XXX_Status)&0x80){
1184                 dl=ni_readl(ADC_FIFO_Data_611x);
1185                 data = (dl&0xffff);
1186                 cfc_write_to_buffer(s, data);
1187         }
1188 }
1189
1190 static void get_last_sample_6143(comedi_device* dev)
1191 {
1192         comedi_subdevice*       s = dev->subdevices + 0;
1193         sampl_t                 data;
1194         u32                     dl;
1195
1196         if(boardtype.reg_type != ni_reg_6143) return;
1197
1198         /* Check if there's a single sample stuck in the FIFO */
1199         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1200                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1201                 dl = ni_readl(AIFIFO_Data_6143);
1202
1203                 /* This may get the hi/lo data in the wrong order */
1204                 data = (dl >> 16) & 0xffff;
1205                 cfc_write_to_buffer(s, data);
1206         }
1207 }
1208
1209 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1210         void *data, unsigned int num_bytes, unsigned int chan_index )
1211 {
1212         comedi_async *async = s->async;
1213         unsigned int i;
1214         unsigned int length = num_bytes / bytes_per_sample(s);
1215         sampl_t *array = data;
1216         lsampl_t *larray = data;
1217         for(i = 0; i < length; i++)
1218         {
1219 #ifdef PCIDMA
1220                 if(s->subdev_flags & SDF_LSAMPL)
1221                         larray[i] = le32_to_cpu(larray[i]);
1222                 else
1223                         array[i] = le16_to_cpu(array[i]);
1224 #endif
1225                 if(s->subdev_flags & SDF_LSAMPL)
1226                         larray[i] += devpriv->ai_offset[chan_index];
1227                 else
1228                         array[i] += devpriv->ai_offset[chan_index];
1229                 chan_index++;
1230                 chan_index %= async->cmd.chanlist_len;
1231         }
1232 }
1233
1234 #ifdef PCIDMA
1235
1236 static int ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1237 {
1238         comedi_subdevice *s = dev->subdevices + 0;
1239         int retval;
1240
1241         retval = ni_request_ai_mite_channel(dev);
1242         if(retval) return retval;
1243 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1244
1245         /* write alloc the entire buffer */
1246         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1247
1248         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
1249         switch(boardtype.reg_type)
1250         {
1251         case ni_reg_611x:
1252         case ni_reg_6143:
1253                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1254                 break;
1255         case ni_reg_628x:
1256                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1257                 break;
1258         default:
1259                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1260                 break;
1261         };
1262         /*start the MITE*/
1263         mite_dma_arm(devpriv->ai_mite_chan);
1264         return 0;
1265 }
1266
1267 static int ni_ao_setup_MITE_dma(comedi_device *dev, comedi_cmd *cmd)
1268 {
1269         comedi_subdevice *s = dev->subdevices + 1;
1270         int retval;
1271
1272         retval = ni_request_ao_mite_channel(dev);
1273         if(retval) return retval;
1274         //rt_printk("comedi_debug: using mite channel %i for ao.\n", devpriv->ao_mite_chan->channel);
1275
1276         /* read alloc the entire buffer */
1277         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1278         /* Barrier is intended to insure comedi_buf_read_alloc
1279         is done touching the async struct before we write
1280         to the mite's registers and arm it.  */
1281         smp_wmb();
1282
1283         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
1284         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1285         {
1286                 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1287         }else
1288         {
1289                 /* doing 32 instead of 16 bit wide transfers from memory
1290                  makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1291                 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1292         }
1293         /*start the MITE*/
1294         mite_dma_arm(devpriv->ao_mite_chan);
1295         return 0;
1296 }
1297
1298 #endif // PCIDMA
1299
1300 /*
1301    used for both cancel ioctl and board initialization
1302
1303    this is pretty harsh for a cancel, but it works...
1304  */
1305
1306 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1307 {
1308 #ifdef PCIDMA
1309         if(devpriv->ai_mite_chan)
1310         {
1311                 mite_dma_disarm(devpriv->ai_mite_chan);
1312         }
1313 #endif
1314         /* ai configuration */
1315         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1316
1317         ni_set_bits(dev, Interrupt_A_Enable_Register,
1318                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1319                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1320                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1321                 AI_FIFO_Interrupt_Enable,0);
1322
1323         ni_clear_ai_fifo(dev);
1324
1325         if(boardtype.reg_type != ni_reg_6143)
1326                 ni_writeb(0, Misc_Command);
1327
1328         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1329         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1330                 AI_Mode_1_Register);
1331         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1332         /* generate FIFO interrupts on non-empty */
1333         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1334         if(boardtype.reg_type == ni_reg_611x){
1335                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1336                         AI_SOC_Polarity |
1337                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1338                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1339                         AI_EXTMUX_CLK_Output_Select(0) |
1340                         AI_LOCALMUX_CLK_Output_Select(2) |
1341                         AI_SC_TC_Output_Select(3) |
1342                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High), AI_Output_Control_Register);
1343         }else if(boardtype.reg_type == ni_reg_6143){
1344                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1345                         AI_SOC_Polarity |
1346                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1347                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1348                         AI_EXTMUX_CLK_Output_Select(0) |
1349                         AI_LOCALMUX_CLK_Output_Select(2) |
1350                         AI_SC_TC_Output_Select(3) |
1351                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),AI_Output_Control_Register);
1352         }else{
1353                 unsigned ai_output_control_bits;
1354                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1355                         AI_SOC_Polarity |
1356                         AI_CONVERT_Pulse_Width |
1357                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1358                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1359                         AI_EXTMUX_CLK_Output_Select(0) |
1360                         AI_LOCALMUX_CLK_Output_Select(2) |
1361                         AI_SC_TC_Output_Select(3);
1362                 if(boardtype.reg_type == ni_reg_622x)
1363                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High);
1364                 else
1365                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low);
1366                 devpriv->stc_writew(dev, ai_output_control_bits, AI_Output_Control_Register);
1367         }
1368         /* the following registers should not be changed, because there
1369          * are no backup registers in devpriv.  If you want to change
1370          * any of these, add a backup register and other appropriate code:
1371          *      AI_Mode_1_Register
1372          *      AI_Mode_3_Register
1373          *      AI_Personal_Register
1374          *      AI_Output_Control_Register
1375         */
1376         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1377                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1378                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1379                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1380
1381         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1382
1383         return 0;
1384 }
1385
1386 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1387 {
1388         unsigned long flags = 0;
1389         int count;
1390
1391         // lock to avoid race with interrupt handler
1392         if(in_interrupt() == 0)
1393                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1394 #ifndef PCIDMA
1395         ni_handle_fifo_dregs(dev);
1396 #else
1397         ni_sync_ai_dma(dev);
1398 #endif
1399         count = s->async->buf_write_count - s->async->buf_read_count;
1400         if(in_interrupt() == 0)
1401                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1402
1403         return count;
1404 }
1405
1406
1407 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1408 {
1409         int i,n;
1410         const unsigned int mask = (1 << boardtype.adbits) - 1;
1411         unsigned signbits;
1412         unsigned short d;
1413         unsigned long dl;
1414
1415         ni_load_channelgain_list(dev,1,&insn->chanspec);
1416
1417         ni_clear_ai_fifo(dev);
1418
1419         signbits=devpriv->ai_offset[0];
1420         if(boardtype.reg_type == ni_reg_611x){
1421                 for(n=0; n < num_adc_stages_611x; n++){
1422                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1423                         comedi_udelay(1);
1424                 }
1425                 for(n=0; n<insn->n; n++){
1426                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1427                         /* The 611x has screwy 32-bit FIFOs. */
1428                         d = 0;
1429                         for(i=0; i<NI_TIMEOUT; i++){
1430                                 if(ni_readb(XXX_Status)&0x80)
1431                                 {
1432                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1433                                         break;
1434                                 }
1435                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1436                                 {
1437                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1438                                         break;
1439                                 }
1440                         }
1441                         if(i==NI_TIMEOUT){
1442                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1443                                 return -ETIME;
1444                         }
1445                         d += signbits;
1446                         data[ n ] = d;
1447                 }
1448         }else if(boardtype.reg_type == ni_reg_6143){
1449                 for(n = 0; n < insn->n; n++){
1450                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1451
1452                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1453                         dl = 0;
1454                         for(i = 0; i < NI_TIMEOUT; i++){
1455                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1456                                 {
1457                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1458                                         dl = ni_readl(AIFIFO_Data_6143);
1459                                         break;
1460                                 }
1461                         }
1462                         if(i == NI_TIMEOUT){
1463                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1464                                 return -ETIME;
1465                         }
1466                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1467                 }
1468         }else{
1469                 for(n = 0; n < insn->n; n++){
1470                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1471                         for(i = 0; i < NI_TIMEOUT; i++){
1472                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1473                                         break;
1474                         }
1475                         if(i == NI_TIMEOUT){
1476                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1477                                 return -ETIME;
1478                         }
1479                         if(boardtype.reg_type & ni_reg_m_series_mask)
1480                         {
1481                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1482                         }else
1483                         {
1484                                 d = ni_readw(ADC_FIFO_Data_Register);
1485                                 d += signbits; /* subtle: needs to be short addition */
1486                                 data[n] = d;
1487                         }
1488                 }
1489         }
1490         return insn->n;
1491 }
1492
1493 void ni_prime_channelgain_list(comedi_device *dev)
1494 {
1495         int i;
1496         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1497         for(i = 0; i < NI_TIMEOUT; ++i)
1498         {
1499                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1500                 {
1501                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1502                         return;
1503                 }
1504                 comedi_udelay(1);
1505         }
1506         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1507 }
1508
1509 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1510         unsigned int *list)
1511 {
1512         unsigned int chan, range, aref;
1513         unsigned int i;
1514         unsigned offset;
1515         unsigned int dither;
1516         unsigned range_code;
1517
1518         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1519
1520 //      offset = 1 << (boardtype.adbits - 1);
1521         if((list[0] & CR_ALT_SOURCE))
1522         {
1523                 unsigned bypass_bits;
1524                 chan = CR_CHAN(list[0]);
1525                 range = CR_RANGE(list[0]);
1526                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1527                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1528                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1529                 bypass_bits |= chan;
1530                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1531                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1532                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1533                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1534                 if(dither)
1535                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1536                 // don't use 2's complement encoding
1537                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1538                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1539         }else
1540         {
1541                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1542         }
1543         offset = 0;
1544         for(i = 0; i < n_chan; i++)
1545         {
1546                 unsigned config_bits = 0;
1547                 chan = CR_CHAN(list[i]);
1548                 aref = CR_AREF(list[i]);
1549                 range = CR_RANGE(list[i]);
1550                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1551
1552                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1553                 devpriv->ai_offset[i] = offset;
1554                 switch( aref )
1555                 {
1556                         case AREF_DIFF:
1557                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1558                                 break;
1559                         case AREF_COMMON:
1560                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1561                                 break;
1562                         case AREF_GROUND:
1563                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1564                                 break;
1565                         case AREF_OTHER:
1566                                 break;
1567                 }
1568                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1569                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1570                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1571                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1572                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1573                 // don't use 2's complement encoding
1574                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1575                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1576         }
1577         ni_prime_channelgain_list(dev);
1578 }
1579
1580 /*
1581  * Notes on the 6110 and 6111:
1582  * These boards a slightly different than the rest of the series, since
1583  * they have multiple A/D converters.
1584  * From the driver side, the configuration memory is a
1585  * little different.
1586  * Configuration Memory Low:
1587  *   bits 15-9: same
1588  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1589  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1590  *       1001 gain=0.1 (+/- 50)
1591  *       1010 0.2
1592  *       1011 0.1
1593  *       0001 1
1594  *       0010 2
1595  *       0011 5
1596  *       0100 10
1597  *       0101 20
1598  *       0110 50
1599  * Configuration Memory High:
1600  *   bits 12-14: Channel Type
1601  *       001 for differential
1602  *       000 for calibration
1603  *   bit 11: coupling  (this is not currently handled)
1604  *       1 AC coupling
1605  *       0 DC coupling
1606  *   bits 0-2: channel
1607  *       valid channels are 0-3
1608  */
1609 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1610         unsigned int *list)
1611 {
1612         unsigned int chan,range,aref;
1613         unsigned int i;
1614         unsigned int hi,lo;
1615         unsigned offset;
1616         unsigned int dither;
1617
1618         if(boardtype.reg_type & ni_reg_m_series_mask)
1619         {
1620                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1621                 return;
1622         }
1623         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1624                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1625                         // ready to go.
1626                         return;
1627                 }
1628                 devpriv->changain_state=1;
1629                 devpriv->changain_spec=list[0];
1630         }else{
1631                 devpriv->changain_state=0;
1632         }
1633
1634         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1635
1636         // Set up Calibration mode if required
1637         if(boardtype.reg_type == ni_reg_6143){
1638                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1639                         // Strobe Relay enable bit
1640                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1641                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1642                         devpriv->ai_calib_source_enabled = 1;
1643                         msleep_interruptible(100);      // Allow relays to change
1644                 }
1645                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1646                         // Strobe Relay disable bit
1647                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1648                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1649                         devpriv->ai_calib_source_enabled = 0;
1650                         msleep_interruptible(100);      // Allow relays to change
1651                 }
1652         }
1653
1654         offset=1<<(boardtype.adbits-1);
1655         for(i=0;i<n_chan;i++){
1656                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1657                         chan=devpriv->ai_calib_source;
1658                 }else{
1659                         chan=CR_CHAN(list[i]);
1660                 }
1661                 aref=CR_AREF(list[i]);
1662                 range=CR_RANGE(list[i]);
1663                 dither=((list[i]&CR_ALT_FILTER)!=0);
1664
1665                 /* fix the external/internal range differences */
1666                 range = ni_gainlkup[boardtype.gainlkup][range];
1667                 if(boardtype.reg_type == ni_reg_611x)
1668                         devpriv->ai_offset[i] = offset;
1669                 else
1670                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1671
1672                 hi = 0;
1673                 if( ( list[i] & CR_ALT_SOURCE ) )
1674                 {
1675                         if(boardtype.reg_type == ni_reg_611x)
1676                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1677                 }else
1678                 {
1679                         if(boardtype.reg_type == ni_reg_611x)
1680                                 aref = AREF_DIFF;
1681                         else if(boardtype.reg_type == ni_reg_6143)
1682                                 aref = AREF_OTHER;
1683                         switch( aref )
1684                         {
1685                                 case AREF_DIFF:
1686                                         hi |= AI_DIFFERENTIAL;
1687                                         break;
1688                                 case AREF_COMMON:
1689                                         hi |= AI_COMMON;
1690                                         break;
1691                                 case AREF_GROUND:
1692                                         hi |= AI_GROUND;
1693                                         break;
1694                                 case AREF_OTHER:
1695                                         break;
1696                         }
1697                 }
1698                 hi |= AI_CONFIG_CHANNEL( chan );
1699
1700                 ni_writew(hi,Configuration_Memory_High);
1701
1702                 if(boardtype.reg_type != ni_reg_6143){
1703                         lo = range;
1704                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1705                         if( dither ) lo |= AI_DITHER;
1706
1707                         ni_writew(lo,Configuration_Memory_Low);
1708                 }
1709         }
1710
1711         /* prime the channel/gain list */
1712         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1713                 ni_prime_channelgain_list(dev);
1714         }
1715 }
1716
1717 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode)
1718 {
1719         int divider;
1720         switch(round_mode)
1721         {
1722         case TRIG_ROUND_NEAREST:
1723         default:
1724                 divider = (*nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1725                 break;
1726         case TRIG_ROUND_DOWN:
1727                 divider = (*nanosec) / devpriv->clock_ns;
1728                 break;
1729         case TRIG_ROUND_UP:
1730                 divider=(*nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1731                 break;
1732         }
1733
1734         *nanosec = devpriv->clock_ns * divider;
1735         return divider - 1;
1736 }
1737
1738 static unsigned ni_min_ai_scan_period_ns(comedi_device *dev, unsigned num_channels)
1739 {
1740         switch(boardtype.reg_type)
1741         {
1742         case ni_reg_611x:
1743         case ni_reg_6143:
1744         // simultaneously-sampled inputs
1745                 return boardtype.ai_speed;
1746                 break;
1747         default:
1748         // multiplexed inputs
1749                 break;
1750         };
1751         return boardtype.ai_speed * num_channels;
1752 }
1753
1754 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1755 {
1756         int err=0;
1757         int tmp;
1758         int sources;
1759
1760         /* step 1: make sure trigger sources are trivially valid */
1761
1762         tmp=cmd->start_src;
1763         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1764         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1765
1766         tmp=cmd->scan_begin_src;
1767         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1768         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1769
1770         tmp=cmd->convert_src;
1771         sources = TRIG_TIMER | TRIG_EXT;
1772         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1773         cmd->convert_src &= sources;
1774         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1775
1776         tmp=cmd->scan_end_src;
1777         cmd->scan_end_src &= TRIG_COUNT;
1778         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1779
1780         tmp=cmd->stop_src;
1781         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1782         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1783
1784         if(err)return 1;
1785
1786         /* step 2: make sure trigger sources are unique and mutually compatible */
1787
1788         /* note that mutual compatiblity is not an issue here */
1789         if(cmd->start_src!=TRIG_NOW &&
1790            cmd->start_src!=TRIG_INT &&
1791            cmd->start_src!=TRIG_EXT)err++;
1792         if(cmd->scan_begin_src!=TRIG_TIMER &&
1793            cmd->scan_begin_src!=TRIG_EXT &&
1794            cmd->scan_begin_src!=TRIG_OTHER)err++;
1795         if(cmd->convert_src!=TRIG_TIMER &&
1796            cmd->convert_src!=TRIG_EXT &&
1797            cmd->convert_src!=TRIG_NOW)err++;
1798         if(cmd->stop_src!=TRIG_COUNT &&
1799            cmd->stop_src!=TRIG_NONE)err++;
1800
1801         if(err)return 2;
1802
1803         /* step 3: make sure arguments are trivially compatible */
1804
1805         if(cmd->start_src==TRIG_EXT){
1806                 /* external trigger */
1807                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1808
1809                 if(tmp > 16) tmp = 16;
1810                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1811                 if(cmd->start_arg != tmp){
1812                         cmd->start_arg = tmp;
1813                         err++;
1814                 }
1815         }else{
1816                 if(cmd->start_arg!=0){
1817                         /* true for both TRIG_NOW and TRIG_INT */
1818                         cmd->start_arg=0;
1819                         err++;
1820                 }
1821         }
1822         if(cmd->scan_begin_src==TRIG_TIMER){
1823                 if(cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, cmd->chanlist_len))
1824                 {
1825                         cmd->scan_begin_arg = ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
1826                         err++;
1827                 }
1828                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1829                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1830                         err++;
1831                 }
1832         }else if(cmd->scan_begin_src==TRIG_EXT){
1833                 /* external trigger */
1834                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1835
1836                 if(tmp>16)tmp=16;
1837                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1838                 if(cmd->scan_begin_arg!=tmp){
1839                         cmd->scan_begin_arg = tmp;
1840                         err++;
1841                 }
1842         }else{ /* TRIG_OTHER */
1843                 if(cmd->scan_begin_arg){
1844                         cmd->scan_begin_arg=0;
1845                         err++;
1846                 }
1847         }
1848         if(cmd->convert_src==TRIG_TIMER){
1849                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1850                         if(cmd->convert_arg != 0){
1851                                 cmd->convert_arg = 0;
1852                                 err++;
1853                         }
1854                 }else{
1855                         if(cmd->convert_arg<boardtype.ai_speed){
1856                                 cmd->convert_arg=boardtype.ai_speed;
1857                                 err++;
1858                         }
1859                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1860                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1861                                 err++;
1862                         }
1863                 }
1864         }else if(cmd->convert_src == TRIG_EXT){
1865                 /* external trigger */
1866                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1867
1868                 if(tmp>16)tmp=16;
1869                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1870                 if(cmd->convert_arg!=tmp){
1871                         cmd->convert_arg = tmp;
1872                         err++;
1873                 }
1874         }else if(cmd->convert_src == TRIG_NOW){
1875                 if(cmd->convert_arg != 0){
1876                         cmd->convert_arg = 0;
1877                         err++;
1878                 }
1879         }
1880
1881         if(cmd->scan_end_arg!=cmd->chanlist_len){
1882                 cmd->scan_end_arg=cmd->chanlist_len;
1883                 err++;
1884         }
1885         if(cmd->stop_src==TRIG_COUNT){
1886                 unsigned int max_count = 0x01000000;
1887
1888                 if(boardtype.reg_type == ni_reg_611x )
1889                         max_count -= num_adc_stages_611x;
1890                 if(cmd->stop_arg > max_count){
1891                         cmd->stop_arg = max_count;
1892                         err++;
1893                 }
1894                 if(cmd->stop_arg < 1){
1895                         cmd->stop_arg = 1;
1896                         err++;
1897                 }
1898         }else{
1899                 /* TRIG_NONE */
1900                 if(cmd->stop_arg!=0){
1901                         cmd->stop_arg=0;
1902                         err++;
1903                 }
1904         }
1905
1906         if(err)return 3;
1907
1908         /* step 4: fix up any arguments */
1909
1910         if(cmd->scan_begin_src==TRIG_TIMER){
1911                 tmp=cmd->scan_begin_arg;
1912                 ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
1913                 if(tmp!=cmd->scan_begin_arg)err++;
1914         }
1915         if(cmd->convert_src==TRIG_TIMER){
1916                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1917                         tmp=cmd->convert_arg;
1918                         ni_ns_to_timer(dev, &cmd->convert_arg, cmd->flags&TRIG_ROUND_MASK);
1919                         if(tmp!=cmd->convert_arg)err++;
1920                         if(cmd->scan_begin_src==TRIG_TIMER &&
1921                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1922                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1923                                 err++;
1924                         }
1925                 }
1926         }
1927
1928         if(err)return 4;
1929
1930         return 0;
1931 }
1932
1933 static void ni_ai_cmd_cleanup(comedi_device *dev, comedi_subdevice *s)
1934 {
1935         ni_release_ai_mite_channel(dev);
1936 }
1937
1938 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1939 {
1940         comedi_cmd *cmd=&s->async->cmd;
1941         int timer;
1942         int mode1=0; /* mode1 is needed for both stop and convert */
1943         int mode2=0;
1944         int start_stop_select=0;
1945         unsigned int stop_count;
1946         int interrupt_a_enable=0;
1947
1948         MDPRINTK("ni_ai_cmd\n");
1949         if(dev->irq == 0)
1950         {
1951                 comedi_error(dev, "cannot run command without an irq");
1952                 return -EIO;
1953         }
1954         ni_clear_ai_fifo(dev);
1955
1956         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1957
1958         /* start configuration */
1959         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1960
1961         /* disable analog triggering for now, since it
1962          * interferes with the use of pfi0 */
1963         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1964         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1965
1966         switch(cmd->start_src){
1967                 case TRIG_INT:
1968                 case TRIG_NOW:
1969                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1970                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1971                                 AI_Trigger_Select_Register);
1972                         break;
1973                 case TRIG_EXT:
1974                 {
1975                         int chan = CR_CHAN(cmd->start_arg);
1976                         unsigned int bits = AI_START2_Select(0)|
1977                                 AI_START1_Sync |
1978                                 AI_START1_Select(chan + 1);
1979
1980                         if(cmd->start_arg & CR_INVERT)
1981                                 bits |= AI_START1_Polarity;
1982                         if(cmd->start_arg & CR_EDGE)
1983                                 bits |= AI_START1_Edge;
1984                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1985                         break;
1986                 }
1987         }
1988
1989         mode2 &= ~AI_Pre_Trigger;
1990         mode2 &= ~AI_SC_Initial_Load_Source;
1991         mode2 &= ~AI_SC_Reload_Mode;
1992         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1993
1994         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1995                 start_stop_select |= AI_STOP_Polarity;
1996                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1997                 start_stop_select |= AI_STOP_Sync;
1998         }else
1999         {
2000                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
2001         }
2002         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2003
2004         devpriv->ai_cmd2 = 0;
2005         switch(cmd->stop_src){
2006         case TRIG_COUNT:
2007                 stop_count = cmd->stop_arg - 1;
2008
2009                 if(boardtype.reg_type == ni_reg_611x){
2010                         // have to take 3 stage adc pipeline into account
2011                         stop_count += num_adc_stages_611x;
2012                 }
2013                 /* stage number of scans */
2014                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
2015
2016                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2017                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2018                 /* load SC (Scan Count) */
2019                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2020
2021                 devpriv->ai_continuous = 0;
2022                 if( stop_count == 0 ){
2023                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2024                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2025                         // this is required to get the last sample for chanlist_len > 1, not sure why
2026                         if(cmd->chanlist_len > 1)
2027                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
2028                 }
2029                 break;
2030         case TRIG_NONE:
2031                 /* stage number of scans */
2032                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
2033
2034                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2035                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2036
2037                 /* load SC (Scan Count) */
2038                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2039
2040                 devpriv->ai_continuous = 1;
2041
2042                 break;
2043         }
2044
2045         switch(cmd->scan_begin_src){
2046         case TRIG_TIMER:
2047                 /*
2048                         stop bits for non 611x boards
2049                         AI_SI_Special_Trigger_Delay=0
2050                         AI_Pre_Trigger=0
2051                         AI_START_STOP_Select_Register:
2052                         AI_START_Polarity=0 (?) rising edge
2053                         AI_START_Edge=1         edge triggered
2054                         AI_START_Sync=1 (?)
2055                         AI_START_Select=0               SI_TC
2056                         AI_STOP_Polarity=0              rising edge
2057                         AI_STOP_Edge=0          level
2058                         AI_STOP_Sync=1
2059                         AI_STOP_Select=19               external pin (configuration mem)
2060                  */
2061                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2062                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2063
2064                 mode2 |= AI_SI_Reload_Mode(0);
2065                 /* AI_SI_Initial_Load_Source=A */
2066                 mode2 &= ~AI_SI_Initial_Load_Source;
2067                 //mode2 |= AI_SC_Reload_Mode;
2068                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2069
2070                 /* load SI */
2071                 timer = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2072                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
2073                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
2074                 break;
2075         case TRIG_EXT:
2076                 if( cmd->scan_begin_arg & CR_EDGE )
2077                         start_stop_select |= AI_START_Edge;
2078                 /* AI_START_Polarity==1 is falling edge */
2079                 if( cmd->scan_begin_arg & CR_INVERT )
2080                         start_stop_select |= AI_START_Polarity;
2081                 if( cmd->scan_begin_src != cmd->convert_src ||
2082                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
2083                         start_stop_select |= AI_START_Sync;
2084                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2085                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2086                 break;
2087         }
2088
2089         switch(cmd->convert_src){
2090         case TRIG_TIMER:
2091         case TRIG_NOW:
2092                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
2093                         timer = 1;
2094                 else
2095                         timer = ni_ns_to_timer(dev, &cmd->convert_arg, TRIG_ROUND_NEAREST);
2096                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
2097                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
2098
2099                 /* AI_SI2_Reload_Mode = alternate */
2100                 /* AI_SI2_Initial_Load_Source = A */
2101                 mode2 &= ~AI_SI2_Initial_Load_Source;
2102                 mode2 |= AI_SI2_Reload_Mode;
2103                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2104
2105                 /* AI_SI2_Load */
2106                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2107
2108                 mode2 |= AI_SI2_Reload_Mode; // alternate
2109                 mode2 |= AI_SI2_Initial_Load_Source; // B
2110
2111                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2112                 break;
2113         case TRIG_EXT:
2114                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2115                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2116                         mode1 |= AI_CONVERT_Source_Polarity;
2117                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2118
2119                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2120                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2121
2122                 break;
2123         }
2124
2125         if(dev->irq){
2126
2127                 /* interrupt on FIFO, errors, SC_TC */
2128                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2129                         AI_SC_TC_Interrupt_Enable;
2130
2131 #ifndef PCIDMA
2132                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2133 #endif
2134
2135                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2136                         /* wake on end-of-scan */
2137                         devpriv->aimode=AIMODE_SCAN;
2138                 }else{
2139                         devpriv->aimode=AIMODE_HALF_FULL;
2140                 }
2141
2142                 switch(devpriv->aimode){
2143                 case AIMODE_HALF_FULL:
2144                         /*generate FIFO interrupts and DMA requests on half-full */
2145 #ifdef PCIDMA
2146                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2147 #else
2148                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2149 #endif
2150                         break;
2151                 case AIMODE_SAMPLE:
2152                         /*generate FIFO interrupts on non-empty */
2153                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2154                         break;
2155                 case AIMODE_SCAN:
2156 #ifdef PCIDMA
2157                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2158 #else
2159                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2160 #endif
2161                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2162                         break;
2163                 default:
2164                         break;
2165                 }
2166
2167                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2168
2169                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2170
2171                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2172         }else{
2173                 /* interrupt on nothing */
2174                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2175
2176                 /* XXX start polling if necessary */
2177                 MDPRINTK("interrupting on nothing\n");
2178         }
2179
2180         /* end configuration */
2181         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2182
2183         switch(cmd->scan_begin_src){
2184         case TRIG_TIMER:
2185                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2186                         AI_Command_1_Register);
2187                 break;
2188         case TRIG_EXT:
2189                 /* XXX AI_SI_Arm? */
2190                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2191                         AI_Command_1_Register);
2192                 break;
2193         }
2194
2195 #ifdef PCIDMA
2196         {
2197                 int retval = ni_ai_setup_MITE_dma(dev,cmd);
2198                 if(retval) return retval;
2199         }
2200         //mite_dump_regs(devpriv->mite);
2201 #endif
2202
2203         switch(cmd->start_src){
2204         case TRIG_NOW:
2205                 /* AI_START1_Pulse */
2206                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2207                 s->async->inttrig=NULL;
2208                 break;
2209         case TRIG_EXT:
2210                 s->async->inttrig=NULL;
2211                 break;
2212         case TRIG_INT:
2213                 s->async->inttrig=ni_ai_inttrig;
2214                 break;
2215         }
2216
2217         MDPRINTK("exit ni_ai_cmd\n");
2218
2219         return 0;
2220 }
2221
2222 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2223         unsigned int trignum)
2224 {
2225         if(trignum!=0)return -EINVAL;
2226
2227         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2228         s->async->inttrig=NULL;
2229
2230         return 1;
2231 }
2232
2233 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2234         comedi_insn *insn, lsampl_t *data);
2235
2236 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2237         comedi_insn *insn, lsampl_t *data)
2238 {
2239         if(insn->n<1)return -EINVAL;
2240
2241         switch(data[0]){
2242         case INSN_CONFIG_ANALOG_TRIG:
2243                 return ni_ai_config_analog_trig(dev,s,insn,data);
2244         case INSN_CONFIG_ALT_SOURCE:
2245                 if(boardtype.reg_type & ni_reg_m_series_mask)
2246                 {
2247                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2248                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2249                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2250                         {
2251                                 return -EINVAL;
2252                         }
2253                         devpriv->ai_calib_source = data[1];
2254                 } else if(boardtype.reg_type == ni_reg_6143)
2255                 {
2256                         unsigned int calib_source;
2257
2258                         calib_source = data[1] & 0xf;
2259
2260
2261                         if(calib_source > 0xF)
2262                                 return -EINVAL;
2263
2264                         devpriv->ai_calib_source = calib_source;
2265                         ni_writew(calib_source, Calibration_Channel_6143);
2266                 }else
2267                 {
2268                         unsigned int calib_source;
2269                         unsigned int calib_source_adjust;
2270
2271                         calib_source = data[1] & 0xf;
2272                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2273
2274                         if(calib_source >= 8)
2275                                 return -EINVAL;
2276                         devpriv->ai_calib_source = calib_source;
2277                         if(boardtype.reg_type == ni_reg_611x){
2278                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2279                         }
2280                 }
2281                 return 2;
2282         default:
2283                 break;
2284         }
2285
2286         return -EINVAL;
2287 }
2288
2289 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2290         comedi_insn *insn, lsampl_t *data)
2291 {
2292         unsigned int a,b,modebits;
2293         int err=0;
2294
2295         /* data[1] is flags
2296          * data[2] is analog line
2297          * data[3] is set level
2298          * data[4] is reset level */
2299         if(!boardtype.has_analog_trig)return -EINVAL;
2300         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2301                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2302                 err++;
2303         }
2304         if(data[2]>=boardtype.n_adchan){
2305                 data[2]=boardtype.n_adchan-1;
2306                 err++;
2307         }
2308         if(data[3]>255){ /* a */
2309                 data[3]=255;
2310                 err++;
2311         }
2312         if(data[4]>255){ /* b */
2313                 data[4]=255;
2314                 err++;
2315         }
2316         /*
2317          * 00 ignore
2318          * 01 set
2319          * 10 reset
2320          *
2321          * modes:
2322          *   1 level:                    +b-   +a-
2323          *     high mode                00 00 01 10
2324          *     low mode                 00 00 10 01
2325          *   2 level: (a<b)
2326          *     hysteresis low mode      10 00 00 01
2327          *     hysteresis high mode     01 00 00 10
2328          *     middle mode              10 01 01 10
2329          */
2330
2331         a=data[3];
2332         b=data[4];
2333         modebits=data[1]&0xff;
2334         if(modebits&0xf0){
2335                 /* two level mode */
2336                 if(b<a){
2337                         /* swap order */
2338                         a=data[4];
2339                         b=data[3];
2340                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2341                 }
2342                 devpriv->atrig_low = a;
2343                 devpriv->atrig_high = b;
2344                 switch(modebits){
2345                 case 0x81:      /* low hysteresis mode */
2346                         devpriv->atrig_mode = 6;
2347                         break;
2348                 case 0x42:      /* high hysteresis mode */
2349                         devpriv->atrig_mode = 3;
2350                         break;
2351                 case 0x96:      /* middle window mode */
2352                         devpriv->atrig_mode = 2;
2353                         break;
2354                 default:
2355                         data[1]&=~0xff;
2356                         err++;
2357                 }
2358         }else{
2359                 /* one level mode */
2360                 if(b!=0){
2361                         data[4]=0;
2362                         err++;
2363                 }
2364                 switch(modebits){
2365                 case 0x06:      /* high window mode */
2366                         devpriv->atrig_high = a;
2367                         devpriv->atrig_mode = 0;
2368                         break;
2369                 case 0x09:      /* low window mode */
2370                         devpriv->atrig_low = a;
2371                         devpriv->atrig_mode = 1;
2372                         break;
2373                 default:
2374                         data[1]&=~0xff;
2375                         err++;
2376                 }
2377         }
2378         if(err)return -EAGAIN;
2379         return 5;
2380 }
2381
2382 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2383 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2384         void *data, unsigned int num_bytes, unsigned int chan_index )
2385 {
2386         comedi_async *async = s->async;
2387         unsigned int range;
2388         unsigned int i;
2389         unsigned int offset;
2390         unsigned int length = num_bytes / sizeof( sampl_t );
2391         sampl_t *array = data;
2392
2393         offset = 1 << (boardtype.aobits - 1);
2394         for(i = 0; i < length; i++)
2395         {
2396                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2397                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2398                         array[i] -= offset;
2399 #ifdef PCIDMA
2400                 array[i] = cpu_to_le16( array[i] );
2401 #endif
2402                 chan_index++;
2403                 chan_index %= async->cmd.chanlist_len;
2404         }
2405 }
2406
2407 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2408         unsigned int chanspec[], unsigned int n_chans, int timed)
2409 {
2410         unsigned int range;
2411         unsigned int chan;
2412         unsigned int conf;
2413         int i;
2414         int invert = 0;
2415
2416         for(i = 0; i < boardtype.n_aochan; ++i)
2417         {
2418                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2419         }
2420         for(i=0;i<n_chans;i++)
2421         {
2422                 comedi_krange *krange;
2423                 chan = CR_CHAN(chanspec[i]);
2424                 range = CR_RANGE(chanspec[i]);
2425                 krange = s->range_table->range + range;
2426                 invert = 0;
2427                 conf = 0;
2428                 switch(krange->max - krange->min)
2429                 {
2430                 case 20000000:
2431                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2432                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2433                         break;
2434                 case 10000000:
2435                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2436                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2437                         break;
2438                 case 4000000:
2439                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2440                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2441                         break;
2442                 case 2000000:
2443                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2444                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2445                         break;
2446                 default:
2447                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2448                         break;
2449                 }
2450                 switch(krange->max + krange->min)
2451                 {
2452                 case 0:
2453                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2454                         break;
2455                 case 10000000:
2456                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2457                         break;
2458                 default:
2459                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2460                         break;
2461                 }
2462                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2463                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2464                 devpriv->ao_conf[chan] = conf;
2465                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2466         }
2467         return invert;
2468 }
2469
2470 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2471         unsigned int chanspec[], unsigned int n_chans)
2472 {
2473         unsigned int range;
2474         unsigned int chan;
2475         unsigned int conf;
2476         int i;
2477         int invert = 0;
2478
2479         for(i=0;i<n_chans;i++)
2480         {
2481                 chan = CR_CHAN(chanspec[i]);
2482                 range = CR_RANGE(chanspec[i]);
2483                 conf = AO_Channel(chan);
2484
2485                 if(boardtype.ao_unipolar){
2486                         if((range&1) == 0){
2487                                 conf |= AO_Bipolar;
2488                                 invert = (1<<(boardtype.aobits-1));
2489                         }else{
2490                                 invert = 0;
2491                         }
2492                         if(range&2)
2493                                 conf |= AO_Ext_Ref;
2494                 }else{
2495                         conf |= AO_Bipolar;
2496                         invert = (1<<(boardtype.aobits-1));
2497                 }
2498
2499                 /* not all boards can deglitch, but this shouldn't hurt */
2500                 if(chanspec[i] & CR_DEGLITCH)
2501                         conf |= AO_Deglitch;
2502
2503                 /* analog reference */
2504                 /* AREF_OTHER connects AO ground to AI ground, i think */
2505                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2506
2507                 ni_writew(conf,AO_Configuration);
2508                 devpriv->ao_conf[chan] = conf;
2509         }
2510         return invert;
2511 }
2512
2513 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2514         unsigned int chanspec[], unsigned int n_chans, int timed)
2515 {
2516         if(boardtype.reg_type & ni_reg_m_series_mask)
2517                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2518         else
2519                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2520 }
2521 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2522         comedi_insn *insn,lsampl_t *data)
2523 {
2524         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2525
2526         return 1;
2527 }
2528
2529 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2530         comedi_insn *insn,lsampl_t *data)
2531 {
2532         unsigned int chan = CR_CHAN(insn->chanspec);
2533         unsigned int invert;
2534
2535         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2536
2537         devpriv->ao[chan] = data[0];
2538
2539         if(boardtype.reg_type & ni_reg_m_series_mask)
2540         {
2541                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2542         }
2543         else
2544                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2545
2546         return 1;
2547 }
2548
2549 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2550         comedi_insn *insn,lsampl_t *data)
2551 {
2552         unsigned int chan = CR_CHAN(insn->chanspec);
2553         unsigned int invert;
2554
2555         ao_win_out(1 << chan, AO_Immediate_671x);
2556         invert = 1 << (boardtype.aobits - 1);
2557
2558         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2559
2560         devpriv->ao[chan] = data[0];
2561         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2562
2563         return 1;
2564 }
2565
2566 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2567         unsigned int trignum)
2568 {
2569         int ret;
2570         int interrupt_b_bits;
2571         int i;
2572         static const int timeout = 1000;
2573
2574         if(trignum!=0) return -EINVAL;
2575
2576         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2577         interrupt_b_bits = AO_Error_Interrupt_Enable;
2578 #ifdef PCIDMA
2579         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2580         if(boardtype.reg_type & ni_reg_6xxx_mask)
2581                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2582         ret = ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2583         if(ret) return ret;
2584         ret = ni_ao_wait_for_dma_load(dev);
2585         if(ret < 0) return ret;
2586
2587 #else
2588         ret = ni_ao_prep_fifo(dev,s);
2589         if(ret==0)return -EPIPE;
2590
2591         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2592 #endif
2593
2594         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2595         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2596         /* wait for DACs to be loaded */
2597         for(i = 0; i < timeout; i++)
2598         {
2599                 comedi_udelay(1);
2600                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2601                         break;
2602         }
2603         if(i == timeout)
2604         {
2605                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2606                 return -EIO;
2607         }
2608         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2609         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2610
2611         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2612
2613         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2614                 AO_Command_1_Register);
2615
2616         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2617
2618         s->async->inttrig=NULL;
2619
2620         return 0;
2621 }
2622
2623 static void ni_ao_cmd_cleanup(comedi_device *dev,comedi_subdevice *s)
2624 {
2625         ni_release_ao_mite_channel(dev);
2626 }
2627
2628 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2629 {
2630         comedi_cmd *cmd = &s->async->cmd;
2631         int trigvar;
2632         int bits;
2633         int i;
2634
2635         if(dev->irq == 0)
2636         {
2637                 comedi_error(dev, "cannot run command without an irq");
2638                 return -EIO;
2639         }
2640         trigvar = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2641
2642         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2643
2644         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2645
2646         if(boardtype.reg_type & ni_reg_6xxx_mask)
2647         {
2648                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2649
2650                 bits = 0;
2651                 for(i = 0; i < cmd->chanlist_len; i++)
2652                 {
2653                         int chan;
2654
2655                         chan = CR_CHAN(cmd->chanlist[i]);
2656                         bits |= 1 << chan;
2657                         ao_win_out(chan, AO_Waveform_Generation_611x);
2658                 }
2659                 ao_win_out(bits, AO_Timed_611x);
2660         }
2661
2662         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2663
2664         if(cmd->stop_src==TRIG_NONE){
2665                 devpriv->ao_mode1|=AO_Continuous;
2666                 devpriv->ao_mode1&=~AO_Trigger_Once;
2667         }else{
2668                 devpriv->ao_mode1&=~AO_Continuous;
2669                 devpriv->ao_mode1|=AO_Trigger_Once;
2670         }
2671         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2672         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2673         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2674         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2675         devpriv->ao_mode3&=~AO_Trigger_Length;
2676         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2677
2678         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2679         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2680         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2681         if(cmd->stop_src==TRIG_NONE){
2682                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2683         }else{
2684                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2685         }
2686         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2687         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2688         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2689         switch(cmd->stop_src){
2690         case TRIG_COUNT:
2691                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2692                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2693                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2694                 break;
2695         case TRIG_NONE:
2696                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2697                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2698                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2699                 break;
2700         default:
2701                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2702                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2703                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2704         }
2705
2706         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2707         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2708         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2709         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2710         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2711         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2712         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2713         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2714         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2715
2716         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2717                 if(cmd->scan_end_arg>1){
2718                         devpriv->ao_mode1|=AO_Multiple_Channels;
2719                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2720                                 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
2721                                 AO_Output_Control_Register);
2722                 }else{
2723                         unsigned bits;
2724                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2725                         bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
2726                         if(boardtype.reg_type & ni_reg_m_series_mask)
2727                         {
2728                                 bits |= AO_Number_Of_Channels(0);
2729                         }else
2730                         {
2731                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2732                         }
2733                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2734                 }
2735                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2736         }
2737
2738         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2739
2740         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2741         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2742
2743         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
2744 #ifdef PCIDMA
2745         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2746 #else
2747         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2748 #endif
2749         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2750         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2751
2752         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2753                 AO_TMRDACWR_Pulse_Width;
2754         if( boardtype.ao_fifo_depth )
2755                 bits |= AO_FIFO_Enable;
2756         else
2757                 bits |= AO_DMA_PIO_Control;
2758         if(boardtype.reg_type & ni_reg_m_series_mask)
2759                 bits |= AO_Number_Of_DAC_Packages/* | AO_Multiple_DACS_Per_Package*/;
2760         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2761         // enable sending of ao dma requests
2762         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2763
2764         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2765
2766         if(cmd->stop_src==TRIG_COUNT) {
2767                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2768                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2769                         AO_BC_TC_Interrupt_Enable, 1);
2770         }
2771
2772         s->async->inttrig=ni_ao_inttrig;
2773
2774         return 0;
2775 }
2776
2777 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2778 {
2779         int err=0;
2780         int tmp;
2781
2782         /* step 1: make sure trigger sources are trivially valid */
2783
2784         tmp=cmd->start_src;
2785         cmd->start_src &= TRIG_INT;
2786         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2787
2788         tmp=cmd->scan_begin_src;
2789         cmd->scan_begin_src &= TRIG_TIMER;
2790         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2791
2792         tmp=cmd->convert_src;
2793         cmd->convert_src &= TRIG_NOW;
2794         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2795
2796         tmp=cmd->scan_end_src;
2797         cmd->scan_end_src &= TRIG_COUNT;
2798         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2799
2800         tmp=cmd->stop_src;
2801         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2802         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2803
2804         if(err)return 1;
2805
2806         /* step 2: make sure trigger sources are unique and mutually compatible */
2807
2808         if(cmd->stop_src!=TRIG_COUNT &&
2809            cmd->stop_src!=TRIG_NONE)err++;
2810
2811         if(err)return 2;
2812
2813         /* step 3: make sure arguments are trivially compatible */
2814
2815         if(cmd->start_arg!=0){
2816                 cmd->start_arg=0;
2817                 err++;
2818         }
2819         if(cmd->scan_begin_arg < boardtype.ao_speed){
2820                 cmd->scan_begin_arg = boardtype.ao_speed;
2821                 err++;
2822         }
2823         if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){ /* XXX check */
2824                 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2825                 err++;
2826         }
2827         if(cmd->convert_arg!=0){
2828                 cmd->convert_arg=0;
2829                 err++;
2830         }
2831         if(cmd->scan_end_arg!=cmd->chanlist_len){
2832                 cmd->scan_end_arg=cmd->chanlist_len;
2833                 err++;
2834         }
2835         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2836                 if(cmd->stop_arg>0x00ffffff){
2837                         cmd->stop_arg=0x00ffffff;
2838                         err++;
2839                 }
2840         }else{
2841                 /* TRIG_NONE */
2842                 if(cmd->stop_arg!=0){
2843                         cmd->stop_arg=0;
2844                         err++;
2845                 }
2846         }
2847
2848         if(err)return 3;
2849
2850         /* step 4: fix up any arguments */
2851
2852         tmp = cmd->scan_begin_arg;
2853         ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
2854         if(tmp!=cmd->scan_begin_arg)err++;
2855
2856         if(err)return 4;
2857
2858         /* step 5: fix up chanlist */
2859
2860         if(err)return 5;
2861
2862         return 0;
2863 }
2864
2865
2866 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2867 {
2868         //devpriv->ao0p=0x0000;
2869         //ni_writew(devpriv->ao0p,AO_Configuration);
2870
2871         //devpriv->ao1p=AO_Channel(1);
2872         //ni_writew(devpriv->ao1p,AO_Configuration);
2873
2874 #ifdef PCIDMA
2875         if(devpriv->ao_mite_chan)
2876         {
2877                 mite_dma_disarm(devpriv->ao_mite_chan);
2878                 mite_dma_reset(devpriv->ao_mite_chan);
2879         }
2880 #endif
2881
2882         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2883         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2884         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2885         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2886         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2887         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2888                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2889         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2890         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2891         devpriv->ao_cmd1=0;
2892         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2893         devpriv->ao_cmd2=0;
2894         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
2895         devpriv->ao_mode1=0;
2896         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
2897         devpriv->ao_mode2=0;
2898         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
2899         if(boardtype.reg_type & ni_reg_m_series_mask)
2900                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2901         else
2902                 devpriv->ao_mode3 = 0;
2903         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2904         devpriv->ao_trigger_select = 0;
2905         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2906         if(boardtype.reg_type & ni_reg_6xxx_mask){
2907                 ao_win_out(0x3, AO_Immediate_671x);
2908                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2909         }
2910         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2911
2912         return 0;
2913 }
2914
2915 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2916         comedi_insn *insn,lsampl_t *data)
2917 {
2918 #ifdef DEBUG_DIO
2919         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2920                 CR_CHAN(insn->chanspec),data[0]);
2921 #endif
2922         switch(data[0]){
2923         case INSN_CONFIG_DIO_OUTPUT:
2924                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2925                 break;
2926         case INSN_CONFIG_DIO_INPUT:
2927                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2928                 break;
2929         case INSN_CONFIG_DIO_QUERY:
2930                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2931                 return insn->n;
2932                 break;
2933         default:
2934                 return -EINVAL;
2935         }
2936
2937         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2938         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2939         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2940
2941         return 1;
2942 }
2943
2944 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2945         comedi_insn *insn,lsampl_t *data)
2946 {
2947 #ifdef DEBUG_DIO
2948         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2949 #endif
2950         if(insn->n!=2)return -EINVAL;
2951         if(data[0]){
2952                 /* Perform check to make sure we're not using the
2953                    serial part of the dio */
2954                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2955                         return -EBUSY;
2956
2957                 s->state &= ~data[0];
2958                 s->state |= (data[0]&data[1]);
2959                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2960                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2961                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2962         }
2963         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2964
2965         return 2;
2966 }
2967
2968 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2969         comedi_insn *insn, lsampl_t *data)
2970 {
2971 #ifdef DEBUG_DIO
2972         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
2973                 CR_CHAN(insn->chanspec), data[0]);
2974 #endif
2975         switch(data[0])
2976         {
2977         case INSN_CONFIG_DIO_OUTPUT:
2978                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2979                 break;
2980         case INSN_CONFIG_DIO_INPUT:
2981                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2982                 break;
2983         case INSN_CONFIG_DIO_QUERY:
2984                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2985                 return insn->n;
2986                 break;
2987         default:
2988                 return -EINVAL;
2989         }
2990
2991         ni_writel(s->io_bits, M_Offset_DIO_Direction);
2992
2993         return 1;
2994 }
2995
2996 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2997         comedi_insn *insn, lsampl_t *data)
2998 {
2999 #ifdef DEBUG_DIO
3000         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3001 #endif
3002         if(insn->n!=2)return -EINVAL;
3003         if(data[0]){
3004                 s->state &= ~data[0];
3005                 s->state |= (data[0] & data[1]);
3006                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3007         }
3008         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3009
3010         return 2;
3011 }
3012
3013 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
3014                                  comedi_insn *insn,lsampl_t *data)
3015 {
3016         int err = insn->n;
3017         unsigned char byte_out, byte_in;
3018
3019         if(insn->n!=2)return -EINVAL;
3020
3021         switch(data[0]) {
3022         case INSN_CONFIG_SERIAL_CLOCK:
3023
3024 #ifdef DEBUG_DIO
3025                 rt_printk("SPI serial clock Config cd\n", data[1]);
3026 #endif
3027                 devpriv->serial_hw_mode = 1;
3028                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3029
3030                 if(data[1] == SERIAL_DISABLED) {
3031                         devpriv->serial_hw_mode = 0;
3032                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3033                                                   DIO_Software_Serial_Control);
3034                         data[1] = SERIAL_DISABLED;
3035                         devpriv->serial_interval_ns = data[1];
3036                 }
3037                 else if(data[1] <= SERIAL_600NS) {
3038                         /* Warning: this clock speed is too fast to reliably
3039                         control SCXI. */
3040                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3041                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3042                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3043                         data[1] = SERIAL_600NS;
3044                         devpriv->serial_interval_ns = data[1];
3045                 }
3046                 else if(data[1] <= SERIAL_1_2US) {
3047                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3048                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3049                                 DIO_Serial_Out_Divide_By_2;
3050                         data[1] = SERIAL_1_2US;
3051                         devpriv->serial_interval_ns = data[1];
3052                 }
3053                 else if(data[1] <= SERIAL_10US) {
3054                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3055                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3056                                 DIO_Serial_Out_Divide_By_2;
3057                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3058                         600ns/1.2us. If you turn divide_by_2 off with the
3059                         slow clock, you will still get 10us, except then
3060                         all your delays are wrong. */
3061                         data[1] = SERIAL_10US;
3062                         devpriv->serial_interval_ns = data[1];
3063                 }
3064                 else {
3065                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3066                                                   DIO_Software_Serial_Control);
3067                         devpriv->serial_hw_mode = 0;
3068                         data[1] = (data[1] / 1000) * 1000;
3069                         devpriv->serial_interval_ns = data[1];
3070                 }
3071
3072                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3073                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
3074                 return 1;
3075
3076         break;
3077
3078         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3079
3080                 if(devpriv->serial_interval_ns == 0) {
3081                         return -EINVAL;
3082                 }
3083
3084                 byte_out = data[1] & 0xFF;
3085
3086                 if(devpriv->serial_hw_mode) {
3087                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
3088                 } else if(devpriv->serial_interval_ns > 0) {
3089                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
3090                 } else {
3091                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3092                         return -EINVAL;
3093                 }
3094                 if(err < 0) return err;
3095                 data[1] = byte_in & 0xFF;
3096                 return insn->n;
3097
3098         break;
3099         default:
3100                 return -EINVAL;
3101         }
3102
3103 }
3104
3105 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3106                                    unsigned char data_out,
3107                                    unsigned char *data_in)
3108 {
3109         unsigned int status1;
3110         int err = 0, count = 20;
3111
3112 #ifdef DEBUG_DIO
3113         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3114 #endif
3115
3116         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3117         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3118         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3119
3120         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3121         if(status1 & DIO_Serial_IO_In_Progress_St) {
3122                 err = -EBUSY;
3123                 goto Error;
3124         }
3125
3126         devpriv->dio_control |= DIO_HW_Serial_Start;
3127         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3128         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3129
3130         /* Wait until STC says we're done, but don't loop infinitely. */
3131         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3132                 /* Delay one bit per loop */
3133                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3134                 if(--count < 0) {
3135                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3136                         err = -ETIME;
3137                         goto Error;
3138                 }
3139         }
3140
3141         /* Delay for last bit. This delay is absolutely necessary, because
3142            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3143         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3144
3145         if(data_in != NULL) {
3146                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3147 #ifdef DEBUG_DIO
3148                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3149 #endif
3150         }
3151
3152  Error:
3153         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3154
3155         return err;
3156 }
3157
3158 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3159                                    unsigned char data_out,
3160                                    unsigned char *data_in)
3161 {
3162         unsigned char mask, input = 0;
3163
3164 #ifdef DEBUG_DIO
3165         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3166 #endif
3167
3168         /* Wait for one bit before transfer */
3169         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3170
3171         for(mask = 0x80; mask; mask >>= 1) {
3172                 /* Output current bit; note that we cannot touch s->state
3173            because it is a per-subdevice field, and serial is
3174                    a separate subdevice from DIO. */
3175                 devpriv->dio_output &= ~DIO_SDOUT;
3176                 if(data_out & mask) {
3177                         devpriv->dio_output |= DIO_SDOUT;
3178                 }
3179                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3180
3181                 /* Assert SDCLK (active low, inverted), wait for half of
3182                    the delay, deassert SDCLK, and wait for the other half. */
3183                 devpriv->dio_control |= DIO_Software_Serial_Control;
3184                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3185
3186                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3187
3188                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3189                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3190
3191                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3192
3193                 /* Input current bit */
3194                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3195 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3196                         input |= mask;
3197                 }
3198         }
3199 #ifdef DEBUG_DIO
3200         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3201 #endif
3202         if(data_in) *data_in = input;
3203
3204         return 0;
3205 }
3206
3207 static void mio_common_detach(comedi_device *dev)
3208 {
3209         if(dev->subdevices && boardtype.has_8255)
3210                 subdev_8255_cleanup(dev,dev->subdevices+3);
3211 }
3212
3213 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3214 {
3215         int i;
3216
3217         for(i = 0; i < s->n_chan; i++)
3218                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3219 }
3220
3221 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3222 {
3223         unsigned stc_register;
3224         switch(reg)
3225         {
3226         case NITIO_G0_Autoincrement_Reg:
3227                 stc_register = G_Autoincrement_Register(0);
3228                 break;
3229         case NITIO_G1_Autoincrement_Reg:
3230                 stc_register = G_Autoincrement_Register(1);
3231                 break;
3232         case NITIO_G0_Command_Reg:
3233                 stc_register = G_Command_Register(0);
3234                 break;
3235         case NITIO_G1_Command_Reg:
3236                 stc_register = G_Command_Register(1);
3237                 break;
3238         case NITIO_G0_HW_Save_Reg:
3239                 stc_register = G_HW_Save_Register(0);
3240                 break;
3241         case NITIO_G1_HW_Save_Reg:
3242                 stc_register = G_HW_Save_Register(1);
3243                 break;
3244         case NITIO_G0_SW_Save_Reg:
3245                 stc_register = G_Save_Register(0);
3246                 break;
3247         case NITIO_G1_SW_Save_Reg:
3248                 stc_register = G_Save_Register(1);
3249                 break;
3250         case NITIO_G0_Mode_Reg:
3251                 stc_register = G_Mode_Register(0);
3252                 break;
3253         case NITIO_G1_Mode_Reg:
3254                 stc_register = G_Mode_Register(1);
3255                 break;
3256         case NITIO_G0_LoadA_Reg:
3257                 stc_register = G_Load_A_Register(0);
3258                 break;
3259         case NITIO_G1_LoadA_Reg:
3260                 stc_register = G_Load_A_Register(1);
3261                 break;
3262         case NITIO_G0_LoadB_Reg:
3263                 stc_register = G_Load_B_Register(0);
3264                 break;
3265         case NITIO_G1_LoadB_Reg:
3266                 stc_register = G_Load_B_Register(1);
3267                 break;
3268         case NITIO_G0_Input_Select_Reg:
3269                 stc_register = G_Input_Select_Register(0);
3270                 break;
3271         case NITIO_G1_Input_Select_Reg:
3272                 stc_register = G_Input_Select_Register(1);
3273                 break;
3274         case NITIO_G01_Status_Reg:
3275                 stc_register = G_Status_Register;
3276                 break;
3277         case NITIO_G01_Joint_Reset_Reg:
3278                 stc_register = Joint_Reset_Register;
3279                 break;
3280         case NITIO_G01_Joint_Status1_Reg:
3281                 stc_register = Joint_Status_1_Register;
3282                 break;
3283         case NITIO_G01_Joint_Status2_Reg:
3284                 stc_register = Joint_Status_2_Register;
3285                 break;
3286         default:
3287                 rt_printk("%s: unhandled register 0x%x in switch.\n", __FUNCTION__, reg);
3288                 BUG();
3289                 return 0;
3290                 break;
3291         }
3292         return stc_register;
3293 }
3294
3295 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg)
3296 {
3297         comedi_device *dev = counter->dev;
3298         unsigned stc_register;
3299         /* bits in the join reset register which are relevant to counters */
3300         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3301         switch(reg)
3302         {
3303         /* m-series-only registers */
3304         case NITIO_G0_Counting_Mode_Reg:
3305                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3306                 break;
3307         case NITIO_G1_Counting_Mode_Reg:
3308                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3309                 break;
3310         case NITIO_G0_Second_Gate_Reg:
3311                 ni_writew(bits, M_Offset_G0_Second_Gate);
3312                 break;
3313         case NITIO_G1_Second_Gate_Reg:
3314                 ni_writew(bits, M_Offset_G1_Second_Gate);
3315                 break;
3316         /* 32 bit registers */
3317         case NITIO_G0_LoadA_Reg:
3318         case NITIO_G1_LoadA_Reg:
3319         case NITIO_G0_LoadB_Reg:
3320         case NITIO_G1_LoadB_Reg:
3321                 stc_register = ni_gpct_to_stc_register(reg);
3322                 devpriv->stc_writel(dev, bits, stc_register);
3323                 break;
3324         /* 16 bit registers */
3325         case NITIO_G01_Joint_Reset_Reg:
3326                 BUG_ON(bits & ~gpct_joint_reset_mask);
3327                 /* fall-through */
3328         default:
3329                 stc_register = ni_gpct_to_stc_register(reg);
3330                 devpriv->stc_writew(dev, bits, stc_register);
3331         }
3332 }
3333
3334 static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg)
3335 {
3336         comedi_device *dev = counter->dev;
3337         unsigned stc_register;
3338         switch(reg)
3339         {
3340         /* 32 bit registers */
3341         case NITIO_G0_HW_Save_Reg:
3342         case NITIO_G1_HW_Save_Reg:
3343         case NITIO_G0_SW_Save_Reg:
3344         case NITIO_G1_SW_Save_Reg:
3345                 stc_register = ni_gpct_to_stc_register(reg);
3346                 return devpriv->stc_readl(dev, stc_register);
3347                 break;
3348         /* 16 bit registers */
3349         default:
3350                 stc_register = ni_gpct_to_stc_register(reg);
3351                 return devpriv->stc_readw(dev, stc_register);
3352                 break;
3353         }
3354         return 0;
3355 }
3356
3357 static int ni_alloc_private(comedi_device *dev)
3358 {
3359         int ret;
3360
3361         ret = alloc_private(dev, sizeof(ni_private));
3362         if(ret < 0) return ret;
3363
3364         spin_lock_init(&devpriv->window_lock);
3365         spin_lock_init(&devpriv->soft_reg_copy_lock);
3366         spin_lock_init(&devpriv->mite_channel_lock);
3367
3368         return 0;
3369 };
3370
3371 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3372 {
3373         comedi_subdevice *s;
3374         unsigned j;
3375
3376         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3377         {
3378                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3379                 return -EINVAL;
3380         }
3381
3382         if(alloc_subdevices(dev, 11 + NUM_GPCT) < 0)
3383                 return -ENOMEM;
3384
3385         /* analog input subdevice */
3386
3387         s=dev->subdevices+0;
3388         dev->read_subdev=s;
3389         if(boardtype.n_adchan){
3390                 s->type=COMEDI_SUBD_AI;
3391                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
3392                 if(boardtype.reg_type != ni_reg_611x)
3393                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3394                 if(boardtype.adbits > 16)
3395                         s->subdev_flags |= SDF_LSAMPL;
3396                 if(boardtype.reg_type & ni_reg_m_series_mask)
3397                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3398                 s->n_chan=boardtype.n_adchan;
3399                 s->len_chanlist=512;
3400                 s->maxdata=(1<<boardtype.adbits)-1;
3401                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3402                 s->insn_read = &ni_ai_insn_read;
3403                 s->insn_config = &ni_ai_insn_config;
3404                 s->do_cmdtest = &ni_ai_cmdtest;
3405                 s->do_cmd = &ni_ai_cmd;
3406                 s->cmd_cleanup = &ni_ai_cmd_cleanup;
3407                 s->cancel = &ni_ai_reset;
3408                 s->poll = &ni_ai_poll;
3409                 s->munge = &ni_ai_munge;
3410 #ifdef PCIDMA
3411                 s->async_dma_dir = DMA_FROM_DEVICE;
3412 #endif
3413         }else{
3414                 s->type=COMEDI_SUBD_UNUSED;
3415         }
3416
3417         /* analog output subdevice */
3418
3419         s = dev->subdevices + 1;
3420         if(boardtype.n_aochan){
3421                 s->type = COMEDI_SUBD_AO;
3422                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
3423                 if(boardtype.reg_type & ni_reg_m_series_mask)
3424                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3425                 s->n_chan = boardtype.n_aochan;
3426                 s->maxdata = (1 << boardtype.aobits) - 1;
3427                 s->range_table = boardtype.ao_range_table;
3428                 s->insn_read = &ni_ao_insn_read;
3429                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3430                         s->insn_write = &ni_ao_insn_write_671x;
3431                 }else{
3432                         s->insn_write = &ni_ao_insn_write;
3433                 }
3434 #ifdef PCIDMA
3435                 if(boardtype.n_aochan){
3436                         s->async_dma_dir = DMA_TO_DEVICE;
3437 #else
3438                 if(boardtype.ao_fifo_depth){
3439 #endif
3440                         dev->write_subdev=s;
3441                         s->subdev_flags |= SDF_CMD_WRITE;
3442                         s->do_cmd = &ni_ao_cmd;
3443                         s->cmd_cleanup = &ni_ao_cmd_cleanup;
3444                         s->do_cmdtest = &ni_ao_cmdtest;
3445                         s->len_chanlist = boardtype.n_aochan;
3446                         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
3447                                 s->munge=ni_ao_munge;
3448                 }
3449                 s->cancel = &ni_ao_reset;
3450         }else{
3451                 s->type = COMEDI_SUBD_UNUSED;
3452         }
3453         if((boardtype.reg_type & ni_reg_67xx_mask))
3454                 init_ao_67xx(dev, s);
3455
3456         /* digital i/o subdevice */
3457
3458         s=dev->subdevices+2;
3459         s->type=COMEDI_SUBD_DIO;
3460         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3461         s->maxdata=1;
3462         s->io_bits=0;           /* all bits input */
3463         s->range_table=&range_digital;
3464         s->n_chan = boardtype.num_p0_dio_channels;
3465         if(boardtype.reg_type & ni_reg_m_series_mask)
3466         {
3467                 s->insn_bits = ni_m_series_dio_insn_bits;
3468                 s->insn_config=ni_m_series_dio_insn_config;
3469                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3470         }else
3471         {
3472                 s->insn_bits=ni_dio_insn_bits;
3473                 s->insn_config=ni_dio_insn_config;
3474                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3475                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3476         }
3477
3478         /* 8255 device */
3479         s=dev->subdevices+3;
3480         if(boardtype.has_8255){
3481                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3482         }else{
3483                 s->type=COMEDI_SUBD_UNUSED;
3484         }
3485
3486         /* formerly general purpose counter/timer device, but no longer used */
3487         s=dev->subdevices+4;
3488         s->type = COMEDI_SUBD_UNUSED;
3489
3490         /* calibration subdevice -- ai and ao */
3491         s=dev->subdevices+5;
3492         s->type=COMEDI_SUBD_CALIB;
3493         if(boardtype.reg_type & ni_reg_m_series_mask)
3494         {
3495                 // internal PWM analog output used for AI nonlinearity calibration
3496                 s->subdev_flags = SDF_INTERNAL;
3497                 s->insn_config = &ni_m_series_pwm_config;
3498                 s->n_chan = 1;
3499                 s->maxdata = 0;
3500                 ni_writel(0x0, M_Offset_Cal_PWM);
3501         } else if(boardtype.reg_type == ni_reg_6143)
3502         {
3503                 // internal PWM analog output used for AI nonlinearity calibration
3504                 s->subdev_flags = SDF_INTERNAL;
3505                 s->insn_config = &ni_6143_pwm_config;
3506                 s->n_chan = 1;
3507                 s->maxdata = 0;
3508         }else
3509         {
3510                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3511                 s->insn_read = &ni_calib_insn_read;
3512                 s->insn_write = &ni_calib_insn_write;
3513                 caldac_setup(dev, s);
3514         }
3515
3516         /* EEPROM */
3517         s=dev->subdevices+6;
3518         s->type=COMEDI_SUBD_MEMORY;
3519         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3520         s->maxdata=0xff;
3521         if(boardtype.reg_type & ni_reg_m_series_mask)
3522         {
3523                 s->n_chan = M_SERIES_EEPROM_SIZE;
3524                 s->insn_read = &ni_m_series_eeprom_insn_read;
3525         }else
3526         {
3527                 s->n_chan = 512;
3528                 s->insn_read = &ni_eeprom_insn_read;
3529         }
3530         /* PFI */
3531         s=dev->subdevices + 7;
3532         s->type = COMEDI_SUBD_DIO;
3533         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3534         if(boardtype.reg_type & ni_reg_m_series_mask)
3535         {
3536                 unsigned i;
3537                 s->n_chan = 16;
3538                 ni_writew(s->state, M_Offset_PFI_DO);
3539                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3540                 {
3541                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3542                 }
3543         }else
3544         {
3545                 s->n_chan = 10;
3546         }
3547         s->maxdata = 1;
3548         s->insn_bits = ni_pfi_insn_bits;
3549         s->insn_config = ni_pfi_insn_config;
3550         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3551
3552         /* cs5529 calibration adc */
3553         s = dev->subdevices + 8;
3554         if(boardtype.reg_type & ni_reg_67xx_mask)
3555         {
3556                 s->type = COMEDI_SUBD_AI;
3557                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3558                 // one channel for each analog output channel
3559                 s->n_chan = boardtype.n_aochan;
3560                 s->maxdata = (1 << 16) - 1;
3561                 s->range_table = &range_unknown; /* XXX */
3562                 s->insn_read=cs5529_ai_insn_read;
3563                 s->insn_config=NULL;
3564                 init_cs5529(dev);
3565         }else
3566         {
3567                 s->type=COMEDI_SUBD_UNUSED;
3568         }
3569
3570         /* Serial */
3571         s=dev->subdevices+9;
3572         s->type=COMEDI_SUBD_SERIAL;
3573         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3574         s->n_chan=1;
3575         s->maxdata=0xff;
3576         s->insn_config = ni_serial_insn_config;
3577         devpriv->serial_interval_ns = 0;
3578         devpriv->serial_hw_mode = 0;
3579
3580         /* RTSI */
3581         s=dev->subdevices + 10;
3582         s->type = COMEDI_SUBD_DIO;
3583         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3584         s->n_chan = 8;
3585         s->maxdata = 1;
3586         s->insn_bits = ni_rtsi_insn_bits;
3587         s->insn_config = ni_rtsi_insn_config;
3588         ni_rtsi_init(dev);
3589
3590         /* General purpose counters */
3591         for(j = 0; j < NUM_GPCT; ++j)
3592         {
3593                 s = dev->subdevices + 11 + j;
3594                 s->type = COMEDI_SUBD_COUNTER;
3595                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
3596                 s->n_chan = 3;
3597                 if(boardtype.reg_type & ni_reg_m_series_mask)
3598                         s->maxdata = 0xffffffff;
3599                 else
3600                         s->maxdata = 0xffffff;
3601                 s->insn_read = ni_gpct_insn_read;
3602                 s->insn_write = ni_gpct_insn_write;
3603                 s->insn_config = ni_gpct_insn_config;
3604                 s->do_cmd = ni_gpct_cmd;
3605                 s->do_cmdtest = ni_gpct_cmdtest;
3606                 s->cancel = ni_gpct_cancel;
3607                 s->async_dma_dir = DMA_BIDIRECTIONAL;
3608                 s->private = &devpriv->counters[j];
3609
3610                 devpriv->counters[j].dev = dev;
3611                 devpriv->counters[j].chip_index = 0;
3612                 devpriv->counters[j].counter_index = j;
3613                 devpriv->counters[j].write_register = ni_gpct_write_register;
3614                 devpriv->counters[j].read_register = ni_gpct_read_register;
3615                 if(boardtype.reg_type & ni_reg_m_series_mask)
3616                 {
3617                         devpriv->counters[j].variant = ni_gpct_variant_m_series;
3618                 }else
3619                 {
3620                         devpriv->counters[j].variant = ni_gpct_variant_e_series;
3621                 }
3622                 devpriv->counters[j].clock_period_ps = 0;
3623                 devpriv->counters[j].mite_chan = NULL;
3624                 ni_tio_init_counter(&devpriv->counters[j]);
3625         }
3626
3627         /* ai configuration */
3628         ni_ai_reset(dev,dev->subdevices+0);
3629         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3630                 // BEAM is this needed for PCI-6143 ??
3631                 devpriv->clock_and_fout =
3632                         Slow_Internal_Time_Divide_By_2 |
3633                         Slow_Internal_Timebase |
3634                         Clock_To_Board_Divide_By_2 |
3635                         Clock_To_Board |
3636                         AI_Output_Divide_By_2 |
3637                         AO_Output_Divide_By_2;
3638         }else{
3639                 devpriv->clock_and_fout =
3640                         Slow_Internal_Time_Divide_By_2 |
3641                         Slow_Internal_Timebase |
3642                         Clock_To_Board_Divide_By_2 |
3643                         Clock_To_Board;
3644         }
3645         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3646
3647         /* analog output configuration */
3648         ni_ao_reset(dev,dev->subdevices + 1);
3649
3650         if(dev->irq){
3651                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3652                         (Interrupt_Output_On_3_Pins&0) |
3653                         Interrupt_A_Enable |
3654                         Interrupt_B_Enable |
3655                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3656                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3657                         Interrupt_Control_Register
3658                 );
3659         }
3660
3661         /* DMA setup */
3662         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
3663         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
3664
3665         if(boardtype.reg_type & ni_reg_6xxx_mask)
3666         {
3667                 ni_writeb( 0, Magic_611x );
3668         }else if(boardtype.reg_type & ni_reg_m_series_mask)
3669         {
3670                 int channel;
3671                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3672                 {
3673                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3674                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3675                 }
3676                 ni_writeb(0x0, M_Offset_AO_Calibration);
3677         }
3678
3679         printk("\n");
3680         return 0;
3681 }
3682
3683
3684
3685 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3686 {
3687         comedi_device *dev=(comedi_device *)arg;
3688
3689         if(dir){
3690                 ni_writeb(data,Port_A+2*port);
3691                 return 0;
3692         }else{
3693                 return ni_readb(Port_A+2*port);
3694         }
3695 }
3696
3697 /*
3698         presents the EEPROM as a subdevice
3699 */
3700
3701 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3702         comedi_insn *insn,lsampl_t *data)
3703 {
3704         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3705
3706         return 1;
3707 }
3708
3709 /*
3710         reads bytes out of eeprom
3711 */
3712
3713 static int ni_read_eeprom(comedi_device *dev,int addr)
3714 {
3715         int bit;
3716         int bitstring;
3717
3718         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3719         ni_writeb(0x04,Serial_Command);
3720         for(bit=0x8000;bit;bit>>=1){
3721                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3722                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3723         }
3724         bitstring=0;
3725         for(bit=0x80;bit;bit>>=1){
3726                 ni_writeb(0x04,Serial_Command);
3727                 ni_writeb(0x05,Serial_Command);
3728                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3729         }
3730         ni_writeb(0x00,Serial_Command);
3731
3732         return bitstring;
3733 }
3734
3735 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3736         comedi_insn *insn,lsampl_t *data)
3737 {
3738         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3739
3740         return 1;
3741 }
3742
3743 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3744 {
3745         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3746         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3747         return 3;
3748 }
3749
3750 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3751         comedi_insn *insn, lsampl_t *data)
3752 {
3753         unsigned up_count, down_count;
3754         switch(data[0])
3755         {
3756         case INSN_CONFIG_PWM_OUTPUT:
3757                 switch(data[1])
3758                 {
3759                 case TRIG_ROUND_NEAREST:
3760                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3761                         break;
3762                 case TRIG_ROUND_DOWN:
3763                         up_count = data[2] / devpriv->clock_ns;
3764                         break;
3765                 case TRIG_ROUND_UP:
3766                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3767                         break;
3768                 default:
3769                         return -EINVAL;
3770                         break;
3771                 }
3772                 switch(data[3])
3773                 {
3774                 case TRIG_ROUND_NEAREST:
3775                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3776                         break;
3777                 case TRIG_ROUND_DOWN:
3778                         down_count = data[4] / devpriv->clock_ns;
3779                         break;
3780                 case TRIG_ROUND_UP:
3781                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3782                         break;
3783                 default:
3784                         return -EINVAL;
3785                         break;
3786                 }
3787                 if(up_count * devpriv->clock_ns != data[2] ||
3788                         down_count * devpriv->clock_ns != data[4])
3789                 {
3790                         data[2] = up_count * devpriv->clock_ns;
3791                         data[4] = down_count * devpriv->clock_ns;
3792                         return -EAGAIN;
3793                 }
3794                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3795                 devpriv->pwm_up_count = up_count;
3796                 devpriv->pwm_down_count = down_count;
3797                 return 5;
3798                 break;
3799         case INSN_CONFIG_GET_PWM_OUTPUT:
3800                 return ni_get_pwm_config(dev, data);
3801                 break;
3802         default:
3803                 return -EINVAL;
3804                 break;
3805         }
3806         return 0;
3807 }
3808
3809 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3810         comedi_insn *insn, lsampl_t *data)
3811 {
3812         unsigned up_count, down_count;
3813         switch(data[0])
3814         {
3815         case INSN_CONFIG_PWM_OUTPUT:
3816                 switch(data[1])
3817                 {
3818                 case TRIG_ROUND_NEAREST:
3819                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3820                         break;
3821                 case TRIG_ROUND_DOWN:
3822                         up_count = data[2] / devpriv->clock_ns;
3823                         break;
3824                 case TRIG_ROUND_UP:
3825                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3826                         break;
3827                 default:
3828                         return -EINVAL;
3829                         break;
3830                 }
3831                 switch(data[3])
3832                 {
3833                 case TRIG_ROUND_NEAREST:
3834                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3835                         break;
3836                 case TRIG_ROUND_DOWN:
3837                         down_count = data[4] / devpriv->clock_ns;
3838                         break;
3839                 case TRIG_ROUND_UP:
3840                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3841                         break;
3842                 default:
3843                         return -EINVAL;
3844                         break;
3845                 }
3846                 if(up_count * devpriv->clock_ns != data[2] ||
3847                         down_count * devpriv->clock_ns != data[4])
3848                 {
3849                         data[2] = up_count * devpriv->clock_ns;
3850                         data[4] = down_count * devpriv->clock_ns;
3851                         return -EAGAIN;
3852                 }
3853                 ni_writel(up_count, Calibration_HighTime_6143);
3854                 devpriv->pwm_up_count = up_count;
3855                 ni_writel(down_count, Calibration_LowTime_6143);
3856                 devpriv->pwm_down_count = down_count;
3857                 return 5;
3858                 break;
3859         case INSN_CONFIG_GET_PWM_OUTPUT:
3860                 return ni_get_pwm_config(dev, data);
3861         default:
3862                 return -EINVAL;
3863                 break;
3864         }
3865         return 0;
3866 }
3867
3868 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3869 /*
3870         calibration subdevice
3871 */
3872 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3873         comedi_insn *insn,lsampl_t *data)
3874 {
3875         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3876
3877         return 1;
3878 }
3879
3880 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3881         comedi_insn *insn,lsampl_t *data)
3882 {
3883         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3884
3885         return 1;
3886 }
3887
3888 static int pack_mb88341(int addr,int val,int *bitstring);
3889 static int pack_dac8800(int addr,int val,int *bitstring);
3890 static int pack_dac8043(int addr,int val,int *bitstring);
3891 static int pack_ad8522(int addr,int val,int *bitstring);
3892 static int pack_ad8804(int addr,int val,int *bitstring);
3893 static int pack_ad8842(int addr,int val,int *bitstring);
3894
3895 struct caldac_struct{
3896         int n_chans;
3897         int n_bits;
3898         int (*packbits)(int,int,int *);
3899 };
3900
3901 static struct caldac_struct caldacs[] = {
3902         [mb88341] = { 12, 8, pack_mb88341 },
3903         [dac8800] = { 8, 8, pack_dac8800 },
3904         [dac8043] = { 1, 12, pack_dac8043 },
3905         [ad8522]  = { 2, 12, pack_ad8522 },
3906         [ad8804] = { 12, 8, pack_ad8804 },
3907         [ad8842] = { 8, 8, pack_ad8842 },
3908         [ad8804_debug] = { 16, 8, pack_ad8804 },
3909 };
3910
3911 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3912 {
3913         int i,j;
3914         int n_dacs;
3915         int n_chans=0;
3916         int n_bits;
3917         int diffbits=0;
3918         int type;
3919         int chan;
3920
3921         type = boardtype.caldac[0];
3922         if(type==caldac_none)return;
3923         n_bits=caldacs[type].n_bits;
3924         for(i=0;i<3;i++){
3925                 type = boardtype.caldac[i];
3926                 if(type==caldac_none)break;
3927                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3928                 n_chans+=caldacs[type].n_chans;
3929         }
3930         n_dacs=i;
3931         s->n_chan=n_chans;
3932
3933         if(diffbits){
3934
3935                 if(n_chans>MAX_N_CALDACS){
3936                         printk("BUG! MAX_N_CALDACS too small\n");
3937                 }
3938                 s->maxdata_list=devpriv->caldac_maxdata_list;
3939                 chan=0;
3940                 for(i=0;i<n_dacs;i++){
3941                         type = boardtype.caldac[i];
3942                         for(j=0;j<caldacs[type].n_chans;j++){
3943                                 s->maxdata_list[chan]=
3944                                         (1<<caldacs[type].n_bits)-1;
3945                                 chan++;
3946                         }
3947                 }
3948
3949                 for( chan = 0; chan < s->n_chan; chan++ )
3950                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3951         }else{
3952                 type = boardtype.caldac[0];
3953                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3954
3955                 for( chan = 0; chan < s->n_chan; chan++ )
3956                         ni_write_caldac( dev, i, s->maxdata / 2 );
3957         }
3958 }
3959
3960 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3961 {
3962         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3963         int i;
3964         int type;
3965
3966         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3967         if( devpriv->caldacs[ addr ] == val ) return;
3968         devpriv->caldacs[ addr ] = val;
3969
3970         for(i=0;i<3;i++){
3971                 type = boardtype.caldac[i];
3972                 if(type==caldac_none)break;
3973                 if(addr<caldacs[type].n_chans){
3974                         bits=caldacs[type].packbits(addr,val,&bitstring);
3975                         loadbit=SerDacLd(i);
3976                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3977                         break;
3978                 }
3979                 addr-=caldacs[type].n_chans;
3980         }
3981
3982         for(bit=1<<(bits-1);bit;bit>>=1){
3983                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3984                 comedi_udelay(1);
3985                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3986                 comedi_udelay(1);
3987         }
3988         ni_writeb(loadbit,Serial_Command);
3989         comedi_udelay(1);
3990         ni_writeb(0,Serial_Command);
3991 }
3992
3993
3994
3995 static int pack_mb88341(int addr,int val,int *bitstring)
3996 {
3997         /*
3998            Fujitsu MB 88341
3999            Note that address bits are reversed.  Thanks to
4000            Ingo Keen for noticing this.
4001
4002            Note also that the 88341 expects address values from
4003            1-12, whereas we use channel numbers 0-11.  The NI
4004            docs use 1-12, also, so be careful here.
4005         */
4006         addr++;
4007         *bitstring=((addr&0x1)<<11) |
4008                   ((addr&0x2)<<9)  |
4009                   ((addr&0x4)<<7)  |
4010                   ((addr&0x8)<<5)  |
4011                   (val&0xff);
4012         return 12;
4013 }
4014
4015 static int pack_dac8800(int addr,int val,int *bitstring)
4016 {
4017         *bitstring=((addr&0x7)<<8)|(val&0xff);
4018         return 11;
4019 }
4020
4021 static int pack_dac8043(int addr,int val,int *bitstring)
4022 {
4023         *bitstring=val&0xfff;
4024         return 12;
4025 }
4026
4027 static int pack_ad8522(int addr,int val,int *bitstring)
4028 {
4029         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
4030         return 16;
4031 }
4032
4033 static int pack_ad8804(int addr,int val,int *bitstring)
4034 {
4035         *bitstring=((addr&0xf)<<8) | (val&0xff);
4036         return 12;
4037 }
4038
4039 static int pack_ad8842(int addr,int val,int *bitstring)
4040 {
4041         *bitstring=((addr+1)<<8) | (val&0xff);
4042         return 12;
4043 }
4044
4045
4046 #if 0
4047 /*
4048  *      Read the GPCTs current value.
4049  */
4050 static int GPCT_G_Watch(comedi_device *dev, int chan)
4051 {
4052         unsigned int hi1,hi2,lo;
4053
4054         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4055         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4056
4057         devpriv->gpct_command[chan] |= G_Save_Trace;
4058         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
4059
4060         /* This procedure is used because the two registers cannot
4061          * be read atomically. */
4062         do{
4063                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4064                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4065                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4066         }while(hi1!=hi2);
4067
4068         return (hi1<<16)|lo;
4069 }
4070
4071 static void GPCT_Reset(comedi_device *dev, int chan)
4072 {
4073         int temp_ack_reg=0;
4074
4075         //printk("GPCT_Reset...");
4076         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4077
4078         switch (chan) {
4079                 case 0:
4080                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4081                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4082                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4083                         temp_ack_reg |= G0_Gate_Error_Confirm;
4084                         temp_ack_reg |= G0_TC_Error_Confirm;
4085                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4086                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4087                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4088
4089                         //problem...this interferes with the other ctr...
4090                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4091                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4092                         break;
4093                 case 1:
4094                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4095                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4096                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4097                         temp_ack_reg |= G1_Gate_Error_Confirm;
4098                         temp_ack_reg |= G1_TC_Error_Confirm;
4099                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4100                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4101                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4102
4103                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4104                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4105                         break;
4106         };
4107
4108         devpriv->gpct_mode[chan] = 0;
4109         devpriv->gpct_input_select[chan] = 0;
4110         devpriv->gpct_command[chan] = 0;
4111
4112         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4113
4114         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4115         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4116         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4117
4118         //printk("exit GPCT_Reset\n");
4119 }
4120
4121 #endif
4122
4123 static int ni_gpct_insn_config(comedi_device *dev, comedi_subdevice *s,
4124         comedi_insn *insn, lsampl_t *data)
4125 {
4126         struct ni_gpct *counter = s->private;
4127         return ni_tio_insn_config(counter, insn, data);
4128 }
4129
4130 static int ni_gpct_insn_read(comedi_device *dev, comedi_subdevice *s,
4131         comedi_insn *insn,lsampl_t *data)
4132 {
4133         struct ni_gpct *counter = s->private;
4134         return ni_tio_rinsn(counter, insn, data);
4135 }
4136
4137 static int ni_gpct_insn_write(comedi_device *dev, comedi_subdevice *s,
4138         comedi_insn *insn, lsampl_t *data)
4139 {
4140         struct ni_gpct *counter = s->private;
4141         return ni_tio_winsn(counter, insn, data);
4142 }
4143
4144 static int ni_gpct_cmd(comedi_device *dev, comedi_subdevice *s)
4145 {
4146 #ifdef PCIDMA
4147         struct ni_gpct *counter = s->private;
4148         return ni_tio_cmd(counter, s->async);
4149 #else
4150         return -EIO;
4151 #endif
4152 }
4153
4154 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
4155 {
4156         struct ni_gpct *counter = s->private;
4157         return ni_tio_cmdtest(counter);
4158 }
4159
4160 static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s)
4161 {
4162         struct ni_gpct *counter = s->private;
4163         return ni_tio_cancel(counter);
4164 }
4165
4166 /*
4167  *
4168  *  Programmable Function Inputs
4169  *
4170  */
4171
4172 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4173 {
4174         unsigned pfi_reg_index;
4175         unsigned array_offset;
4176         if((source & 0x1f) != source) return -EINVAL;
4177         pfi_reg_index = 1 + chan / 3;
4178         array_offset = pfi_reg_index - 1;
4179         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4180         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4181         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4182         return 2;
4183 }
4184
4185 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4186 {
4187         // pre-m-series boards have fixed signals on pfi pins
4188         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4189         return 2;
4190 }
4191
4192 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4193 {
4194         if(boardtype.reg_type & ni_reg_m_series_mask)
4195                 return ni_m_series_set_pfi_routing(dev, chan, source);
4196         else
4197                 return ni_old_set_pfi_routing(dev, chan, source);
4198 }
4199
4200 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4201 {
4202         const unsigned array_offset = chan / 3;
4203         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4204 }
4205
4206 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4207 {
4208         // pre-m-series boards have fixed signals on pfi pins
4209         switch(chan)
4210         {
4211         case 0:
4212                 return NI_PFI_OUTPUT_AI_START1;
4213                 break;
4214         case 1:
4215                 return NI_PFI_OUTPUT_AI_START2;
4216                 break;
4217         case 2:
4218                 return NI_PFI_OUTPUT_AI_CONVERT;
4219                 break;
4220         case 3:
4221                 return NI_PFI_OUTPUT_G_SRC1;
4222                 break;
4223         case 4:
4224                 return NI_PFI_OUTPUT_G_GATE1;
4225                 break;
4226         case 5:
4227                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4228                 break;
4229         case 6:
4230                 return NI_PFI_OUTPUT_AO_START1;
4231                 break;
4232         case 7:
4233                 return NI_PFI_OUTPUT_AI_START_PULSE;
4234                 break;
4235         case 8:
4236                 return NI_PFI_OUTPUT_G_SRC0;
4237                 break;
4238         case 9:
4239                 return NI_PFI_OUTPUT_G_GATE0;
4240                 break;
4241         default:
4242                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4243                 break;
4244         }
4245         return 0;
4246 }
4247
4248 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4249 {
4250         if(boardtype.reg_type & ni_reg_m_series_mask)
4251                 return ni_m_series_get_pfi_routing(dev, chan);
4252         else
4253                 return ni_old_get_pfi_routing(dev, chan);
4254 }
4255
4256 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4257         comedi_insn *insn,lsampl_t *data)
4258 {
4259         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4260         {
4261                 data[1] = 0;
4262                 return 2;
4263         }
4264         if(data[0])
4265         {
4266                 s->state &= ~data[0];
4267                 s->state |= (data[0] & data[1]);
4268                 ni_writew(s->state, M_Offset_PFI_DO);
4269         }
4270         data[1] = ni_readw(M_Offset_PFI_DI);
4271         return 2;
4272 }
4273
4274 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4275         comedi_insn *insn,lsampl_t *data)
4276 {
4277         unsigned int chan;
4278
4279         if(insn->n < 1)return -EINVAL;
4280
4281         chan = CR_CHAN(insn->chanspec);
4282
4283         switch(data[0]){
4284         case COMEDI_OUTPUT:
4285                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4286                 break;
4287         case COMEDI_INPUT:
4288                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4289                 break;
4290         case INSN_CONFIG_DIO_QUERY:
4291                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4292                 return insn->n;
4293                 break;
4294         case INSN_CONFIG_SET_ROUTING:
4295                 return ni_set_pfi_routing(dev, chan, data[1]);
4296                 break;
4297         case INSN_CONFIG_GET_ROUTING:
4298                 data[1] = ni_get_pfi_routing(dev, chan);
4299                 return 2;
4300                 break;
4301         default:
4302                 return -EINVAL;
4303         }
4304
4305         return 1;
4306 }
4307
4308 /*
4309  *
4310  *  NI RTSI Bus Functions
4311  *
4312  */
4313 static void ni_rtsi_init(comedi_device *dev)
4314 {
4315         // Initialises the RTSI bus signal switch to a default state
4316
4317         // Set clock mode to internal
4318         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4319         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4320         {
4321                 rt_printk("ni_set_master_clock failed, bug?");
4322         }
4323         // default internal lines routing to RTSI bus lines
4324         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4325                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4326                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4327                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4328         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4329                 RTSI_Trig_A_Output_Register);
4330         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4331                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4332                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4333         if(boardtype.reg_type & ni_reg_m_series_mask)
4334                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4335         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4336                 RTSI_Trig_B_Output_Register);
4337
4338         // Sets the source and direction of the 4 on board lines
4339 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4340 }
4341
4342 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4343         comedi_insn *insn,lsampl_t *data)
4344 {
4345         if(insn->n != 2) return -EINVAL;
4346
4347         data[1] = 0;
4348
4349         return 2;
4350 }
4351
4352 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4353  * given an arbitrary frequency input clock */
4354 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4355         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4356 {
4357         unsigned div;
4358         unsigned best_div = 1;
4359         static const unsigned max_div = 0x10;
4360         unsigned mult;
4361         unsigned best_mult = 1;
4362         static const unsigned max_mult = 0x100;
4363         static const unsigned pico_per_nano = 1000;
4364
4365         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4366         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4367          * 20 MHz for most timing clocks */
4368         static const unsigned target_picosec = 12500;
4369         static const unsigned fudge_factor_80_to_20Mhz = 4;
4370         int best_period_picosec = 0;
4371         for(div = 1; div <= max_div; ++div)
4372         {
4373                 for(mult = 1; mult <= max_mult; ++mult)
4374                 {
4375                         unsigned new_period_ps = (reference_picosec * div) / mult;
4376                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4377                         {
4378                                 best_period_picosec = new_period_ps;
4379                                 best_div = div;
4380                                 best_mult = mult;
4381                         }
4382                 }
4383         }
4384         if(best_period_picosec == 0)
4385         {
4386                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4387                 return -EIO;
4388         }
4389         *freq_divider = best_div;
4390         *freq_multiplier = best_mult;
4391         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4392         return 0;
4393 }
4394
4395 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4396 {
4397         if(boardtype.reg_type & ni_reg_m_series_mask) return 8;
4398         else return 7;
4399 }
4400
4401 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4402 {
4403         static const unsigned min_period_ns = 50;
4404         static const unsigned max_period_ns = 1000;
4405         static const unsigned timeout = 1000;
4406         unsigned pll_control_bits;
4407         unsigned freq_divider;
4408         unsigned freq_multiplier;
4409         unsigned i;
4410         int retval;
4411         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4412         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4413         if(period_ns < min_period_ns || period_ns > max_period_ns)
4414         {
4415                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4416                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4417                 return -EINVAL;
4418         }
4419         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4420         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4421         pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4422         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4423         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4424         switch(source)
4425         {
4426         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4427                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4428                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4429                         &freq_multiplier, &devpriv->clock_ns);
4430                 if(retval < 0) return retval;
4431                 break;
4432         case NI_MIO_PLL_PXI10_CLOCK:
4433                 /* pxi clock is 10MHz */
4434                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4435                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4436                         &freq_multiplier, &devpriv->clock_ns);
4437                 if(retval < 0) return retval;
4438                 break;
4439         default:
4440                 {
4441                         unsigned rtsi_channel;
4442                         static const unsigned max_rtsi_channel = 7;
4443                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4444                         {
4445                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4446                                 {
4447                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4448                                         break;
4449                                 }
4450                         }
4451                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4452                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4453                                 &freq_multiplier, &devpriv->clock_ns);
4454                         if(retval < 0) return retval;
4455                 }
4456                 break;
4457         }
4458         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4459         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4460 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4461 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4462         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4463         devpriv->clock_source = source;
4464         /* it seems to typically take a few hundred microseconds for PLL to lock */
4465         for(i = 0; i < timeout; ++i)
4466         {
4467                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4468                 {
4469                         break;
4470                 }
4471                 udelay(1);
4472         }
4473         if(i == timeout)
4474         {
4475                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4476                         __FUNCTION__, source, period_ns);
4477                 return -ETIMEDOUT;
4478         }
4479         return 3;
4480 }
4481
4482 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4483 {
4484         if(source == NI_MIO_INTERNAL_CLOCK)
4485         {
4486                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4487                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4488                 devpriv->clock_ns = 50;
4489                 if(boardtype.reg_type & ni_reg_m_series_mask)
4490                 {
4491                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4492                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4493                         ni_writew(0, M_Offset_PLL_Control);
4494                 }
4495                 devpriv->clock_source = source;
4496         }else
4497         {
4498                 if(boardtype.reg_type & ni_reg_m_series_mask)
4499                 {
4500                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4501                 }else
4502                 {
4503                         if(source == NI_MIO_RTSI_CLOCK)
4504                         {
4505                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4506                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4507                                 if(devpriv->clock_ns == 0)
4508                                 {
4509                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4510                                                 __FUNCTION__);
4511                                         return -EINVAL;
4512                                 }else
4513                                 {
4514                                         devpriv->clock_ns = period_ns;
4515                                 }
4516                                 devpriv->clock_source = source;
4517                         }else
4518                                 return -EINVAL;
4519                 }
4520         }
4521         return 3;
4522 }
4523
4524 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4525 {
4526         if(chan >= num_configurable_rtsi_channels(dev))
4527         {
4528                 if(chan == old_RTSI_clock_channel)
4529                 {
4530                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4531                         else
4532                         {
4533                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4534                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4535                                 return 0;
4536                         }
4537                 }
4538                 return 0;
4539         }
4540         switch(source)
4541         {
4542         case NI_RTSI_OUTPUT_ADR_START1:
4543         case NI_RTSI_OUTPUT_ADR_START2:
4544         case NI_RTSI_OUTPUT_SCLKG:
4545         case NI_RTSI_OUTPUT_DACUPDN:
4546         case NI_RTSI_OUTPUT_DA_START1:
4547         case NI_RTSI_OUTPUT_G_SRC0:
4548         case NI_RTSI_OUTPUT_G_GATE0:
4549         case NI_RTSI_OUTPUT_RGOUT0:
4550         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4551                 return 1;
4552                 break;
4553         case NI_RTSI_OUTPUT_RTSI_OSC:
4554                 if(boardtype.reg_type & ni_reg_m_series_mask)
4555                         return 1;
4556                 else return 0;
4557                 break;
4558         default:
4559                 return 0;
4560                 break;
4561         }
4562 }
4563
4564 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4565 {
4566         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4567         if(chan < 4)
4568         {
4569                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4570                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4571                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4572                         RTSI_Trig_A_Output_Register);
4573         }else if(chan < 8)
4574         {
4575                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4576                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4577                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4578                         RTSI_Trig_B_Output_Register);
4579         }
4580         return 2;
4581 }
4582
4583 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4584 {
4585         if(chan < 4)
4586         {
4587                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4588         }else if(chan < num_configurable_rtsi_channels(dev))
4589         {
4590                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4591         }else
4592         {
4593                 if(chan == old_RTSI_clock_channel)
4594                         return NI_RTSI_OUTPUT_RTSI_OSC;
4595                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4596                 return 0;
4597         }
4598 }
4599
4600 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4601         comedi_insn *insn,lsampl_t *data)
4602 {
4603         unsigned int chan = CR_CHAN(insn->chanspec);
4604         switch(data[0]){
4605         case INSN_CONFIG_DIO_OUTPUT:
4606                 if(chan < num_configurable_rtsi_channels(dev))
4607                 {
4608                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4609                 }else if(chan == old_RTSI_clock_channel)
4610                 {
4611                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4612                 }
4613                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4614                 break;
4615         case INSN_CONFIG_DIO_INPUT:
4616                 if(chan < num_configurable_rtsi_channels(dev))
4617                 {
4618                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4619                 }else if(chan == old_RTSI_clock_channel)
4620                 {
4621                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4622                 }
4623                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4624                 break;
4625         case INSN_CONFIG_DIO_QUERY:
4626                 if(chan < num_configurable_rtsi_channels(dev))
4627                 {
4628                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0)) ?
4629                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4630                 }else if(chan == old_RTSI_clock_channel)
4631                 {
4632                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4633                 }
4634                 return 2;
4635                 break;
4636         case INSN_CONFIG_SET_CLOCK_SRC:
4637                 return ni_set_master_clock(dev, data[1], data[2]);
4638                 break;
4639         case INSN_CONFIG_GET_CLOCK_SRC:
4640                 data[1] = devpriv->clock_source;
4641                 data[2] = devpriv->clock_ns;
4642                 return 3;
4643                 break;
4644         case INSN_CONFIG_SET_ROUTING:
4645                 return ni_set_rtsi_routing(dev, chan, data[1]);
4646                 break;
4647         case INSN_CONFIG_GET_ROUTING:
4648                 data[1] = ni_get_rtsi_routing(dev, chan);
4649                 return 2;
4650                 break;
4651         default:
4652                 return -EINVAL;
4653                 break;
4654         }
4655         return 1;
4656 }
4657
4658 static int cs5529_wait_for_idle(comedi_device *dev)
4659 {
4660         unsigned short status;
4661         const int timeout = HZ;
4662         int i;
4663
4664         for(i = 0; i < timeout; i++)
4665         {
4666                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4667                 if((status & CSS_ADC_BUSY) == 0)
4668                 {
4669                         break;
4670                 }
4671                 set_current_state(TASK_INTERRUPTIBLE);
4672                 if(schedule_timeout(1))
4673                 {
4674                         return -EIO;
4675                 }
4676         }
4677 //printk("looped %i times waiting for idle\n", i);
4678         if(i == timeout)
4679         {
4680                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4681                 return -ETIME;
4682         }
4683         return 0;
4684 }
4685
4686 static void cs5529_command(comedi_device *dev, unsigned short value)
4687 {
4688         static const int timeout = 100;
4689         int i;
4690
4691         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4692         /* give time for command to start being serially clocked into cs5529.
4693          * this insures that the CSS_ADC_BUSY bit will get properly
4694          * set before we exit this function.
4695         */
4696         for(i = 0; i < timeout; i++)
4697         {
4698                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4699                         break;
4700                 comedi_udelay(1);
4701         }
4702 //printk("looped %i times writing command to cs5529\n", i);
4703         if(i == timeout)
4704         {
4705                 comedi_error(dev, "possible problem - never saw adc go busy?");
4706         }
4707 }
4708
4709 /* write to cs5529 register */
4710 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4711 {
4712         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4713         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4714         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4715         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4716         if(cs5529_wait_for_idle(dev))
4717                 comedi_error(dev, "time or signal in cs5529_config_write()");
4718 }
4719
4720 /* read from cs5529 register */
4721 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4722 {
4723         unsigned int value;
4724
4725         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4726         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4727         if(cs5529_wait_for_idle(dev))
4728                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4729         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4730         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4731         return value;
4732 }
4733
4734 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4735 {
4736         int retval;
4737         unsigned short status;
4738
4739         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4740         retval = cs5529_wait_for_idle(dev);
4741         if(retval)
4742         {
4743                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4744                 return -ETIME;
4745         }
4746         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4747         if(status & CSS_OSC_DETECT)
4748         {
4749                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4750                 return -EIO;
4751         }
4752         if(status & CSS_OVERRANGE)
4753         {
4754                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4755         }
4756         if(data)
4757         {
4758                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4759                 /* cs5529 returns 16 bit signed data in bipolar mode */
4760                 *data ^= (1 << 15);
4761         }
4762         return 0;
4763 }
4764
4765 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4766 {
4767         int n, retval;
4768         unsigned short sample;
4769         unsigned int channel_select;
4770         const unsigned int INTERNAL_REF = 0x1000;
4771
4772         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4773          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4774          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4775         if(insn->chanspec & CR_ALT_SOURCE)
4776                 channel_select = INTERNAL_REF;
4777         else
4778                 channel_select = CR_CHAN(insn->chanspec);
4779         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4780
4781         for(n = 0; n < insn->n; n++)
4782         {
4783                 retval = cs5529_do_conversion(dev, &sample);
4784                 if(retval < 0) return retval;
4785                 data[n] = sample;
4786         }
4787         return insn->n;
4788 }
4789
4790 static int init_cs5529(comedi_device *dev)
4791 {
4792         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4793
4794 #if 1
4795         /* do self-calibration */
4796         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4797         /* need to force a conversion for calibration to run */
4798         cs5529_do_conversion(dev, NULL);
4799 #else
4800         /* force gain calibration to 1 */
4801         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4802         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4803         if(cs5529_wait_for_idle(dev))
4804                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4805 #endif
4806         if(0)
4807         {
4808                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4809                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4810                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4811         }
4812         return 0;
4813 }
4814
4815