comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 264         comedi_insn *insn,lsampl_t *data);
 265 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 266         comedi_insn *insn,lsampl_t *data);
 267 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 268         comedi_insn *insn,lsampl_t *data);
 269 static int ni_gpct_cmd(comedi_device *dev,comedi_subdevice *s);
 270 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 271 static int ni_gpct_cancel(comedi_device *dev,comedi_subdevice *s);
 272
 273 static int init_cs5529(comedi_device *dev);
 274 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 275 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 276 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 277 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 278
 279 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 280         comedi_insn *insn,lsampl_t *data);
 281 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 282         comedi_insn *insn, lsampl_t *data);
 283
 284 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 285
 286 enum aimodes
 287 {
 288         AIMODE_NONE = 0,
 289         AIMODE_HALF_FULL = 1,
 290         AIMODE_SCAN = 2,
 291         AIMODE_SAMPLE = 3,
 292 };
 293
 294 #define SERIAL_DISABLED         0
 295 #define SERIAL_600NS            600
 296 #define SERIAL_1_2US            1200
 297 #define SERIAL_10US                     10000
 298
 299 static const int num_adc_stages_611x = 3;
 300
 301 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 302         unsigned ai_mite_status, unsigned gpct0_mite_status);
 303 static void handle_b_interrupt(comedi_device *dev, unsigned short status,
 304         unsigned ao_mite_status, unsigned gpct1_mite_status);
 305 static void get_last_sample_611x( comedi_device *dev );
 306 static void get_last_sample_6143( comedi_device *dev );
 307 #ifdef PCIDMA
 308 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 309 static int ni_ai_drain_dma(comedi_device *dev );
 310
 311 /* DMA channel setup */
 312
 313 // negative channel means no channel
 314 static inline void ni_set_ai_dma_channel(comedi_device *dev, int channel)
 315 {
 316         unsigned long flags;
 317
 318         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 319         devpriv->ai_ao_select_reg &= ~AI_DMA_Select_Mask;
 320         if(channel >= 0)
 321         {
 322                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 323         }
 324         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 325         mmiowb();
 326         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 327 }
 328
 329 // negative channel means no channel
 330 static inline void ni_set_ao_dma_channel(comedi_device *dev, int channel)
 331 {
 332         unsigned long flags;
 333
 334         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 335         devpriv->ai_ao_select_reg &= ~AO_DMA_Select_Mask;
 336         if(channel >= 0)
 337         {
 338                 devpriv->ai_ao_select_reg |= (ni_stc_dma_channel_select_bitfield(channel) << AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 339         }
 340         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 341         mmiowb();
 342         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 343 }
 344
 345 // negative mite_channel means no channel
 346 static inline void ni_set_gpct_dma_channel(comedi_device *dev, unsigned gpct_index, int mite_channel)
 347 {
 348         unsigned long flags;
 349
 350         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 351         devpriv->g0_g1_select_reg &= ~GPCT_DMA_Select_Mask(gpct_index);
 352         if(mite_channel >= 0)
 353         {
 354                 devpriv->g0_g1_select_reg |= GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 355         }
 356         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 357         mmiowb();
 358         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 359 }
 360
 361 static int ni_request_ai_mite_channel(comedi_device *dev)
 362 {
 363         unsigned long flags;
 364
 365         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 366         BUG_ON(devpriv->ai_mite_chan);
 367         devpriv->ai_mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 368         if(devpriv->ai_mite_chan == NULL)
 369         {
 370                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 371                 comedi_error(dev, "failed to reserve mite dma channel for analog input.");
 372                 return -EBUSY;
 373         }
 374         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 375         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 376         return 0;
 377 }
 378
 379 static int ni_request_ao_mite_channel(comedi_device *dev)
 380 {
 381         unsigned long flags;
 382
 383         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 384         BUG_ON(devpriv->ao_mite_chan);
 385         devpriv->ao_mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 386         if(devpriv->ao_mite_chan == NULL)
 387         {
 388                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 389                 comedi_error(dev, "failed to reserve mite dma channel for analog outut.");
 390                 return -EBUSY;
 391         }
 392         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 393         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 394         return 0;
 395 }
 396
 397 static int ni_request_gpct_mite_channel(comedi_device *dev, unsigned gpct_index)
 398 {
 399         unsigned long flags;
 400
 401         BUG_ON(gpct_index >= NUM_GPCT);
 402         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 403         BUG_ON(devpriv->gpct_mite_chan[gpct_index]);
 404         devpriv->gpct_mite_chan[gpct_index] = mite_request_channel(devpriv->mite, devpriv->gpct_mite_ring[gpct_index]);
 405         if(devpriv->gpct_mite_chan[gpct_index] == NULL)
 406         {
 407                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 408                 comedi_error(dev, "failed to reserve mite dma channel for counter.");
 409                 return -EBUSY;
 410         }
 411         ni_set_gpct_dma_channel(dev, gpct_index, devpriv->gpct_mite_chan[gpct_index]->channel);
 412         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 413         return 0;
 414 }
 415
 416 #endif  // PCIDMA
 417
 418 static void ni_release_ai_mite_channel(comedi_device *dev)
 419 {
 420 #ifdef PCIDMA
 421         unsigned long flags;
 422
 423         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 424         if(devpriv->ai_mite_chan)
 425         {
 426                 ni_set_ai_dma_channel(dev, -1);
 427                 mite_dma_disarm(devpriv->ai_mite_chan);
 428                 mite_dma_reset(devpriv->ai_mite_chan);
 429                 mite_release_channel(devpriv->ai_mite_chan);
 430                 devpriv->ai_mite_chan = NULL;
 431         }
 432         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 433 #endif  // PCIDMA
 434 }
 435
 436 static void ni_release_ao_mite_channel(comedi_device *dev)
 437 {
 438 #ifdef PCIDMA
 439         unsigned long flags;
 440
 441         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 442         if(devpriv->ao_mite_chan)
 443         {
 444                 ni_set_ao_dma_channel(dev, -1);
 445                 mite_dma_disarm(devpriv->ao_mite_chan);
 446                 mite_dma_reset(devpriv->ao_mite_chan);
 447                 mite_release_channel(devpriv->ao_mite_chan);
 448                 devpriv->ao_mite_chan = NULL;
 449         }
 450         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 451 #endif  // PCIDMA
 452 }
 453
 454 void ni_release_gpct_mite_channel(comedi_device *dev, unsigned gpct_index)
 455 {
 456 #ifdef PCIDMA
 457         unsigned long flags;
 458
 459         BUG_ON(gpct_index >= NUM_GPCT);
 460         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 461         if(devpriv->gpct_mite_chan[gpct_index])
 462         {
 463                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 464                 mite_dma_disarm(devpriv->gpct_mite_chan[gpct_index]);
 465                 mite_dma_reset(devpriv->gpct_mite_chan[gpct_index]);
 466                 mite_release_channel(devpriv->gpct_mite_chan[gpct_index]);
 467                 devpriv->gpct_mite_chan[gpct_index] = NULL;
 468         }
 469         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 470 #endif  // PCIDMA
 471 }
 472
 473 static void ni_clear_ai_fifo(comedi_device *dev){
 474         if(boardtype.reg_type == ni_reg_6143){
 475                 // Flush the 6143 data FIFO
 476                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 477                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 478                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 479         }else {
 480                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 481                 if(boardtype.reg_type == ni_reg_625x)
 482                 {
 483                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 484                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 485 #if 0
 486                 /* the NI example code does 3 convert pulses for 625x boards,
 487                 but that appears to be wrong in practice. */
 488                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 489                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 490                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
 491 #endif
 492                 }
 493         }
 494 }
 495
 496 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 497 {
 498         devpriv->stc_writew(dev, data >> 16, reg);
 499         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 500 }
 501
 502 static uint32_t win_in2(comedi_device *dev, int reg)
 503 {
 504         uint32_t bits;
 505         bits = devpriv->stc_readw(dev, reg) << 16;
 506         bits |= devpriv->stc_readw(dev, reg + 1);
 507         return bits;
 508 }
 509
 510 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 511 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 512 {
 513         unsigned long flags;
 514
 515         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 516         ni_writew(addr,AO_Window_Address_611x);
 517         ni_writew(data,AO_Window_Data_611x);
 518         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 519 }
 520
 521 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 522 {
 523         unsigned long flags;
 524
 525         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 526         ni_writew(addr,AO_Window_Address_611x);
 527         ni_writel(data,AO_Window_Data_611x);
 528         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 529 }
 530
 531 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 532 {
 533         unsigned long flags;
 534         unsigned short data;
 535
 536         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 537         ni_writew(addr, AO_Window_Address_611x);
 538         data = ni_readw(AO_Window_Data_611x);
 539         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 540         return data;
 541 }
 542
 543 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 544 * share registers (such as Interrupt_A_Register) without interfering with
 545 * each other.
 546 *
 547 * NOTE: the switch/case statements are optimized out for a constant argument
 548 * so this is actually quite fast---  If you must wrap another function around this
 549 * make it inline to avoid a large speed penalty.
 550 *
 551 * value should only be 1 or 0.
 552 */
 553 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 554 {
 555         unsigned long flags;
 556
 557         comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 558         switch (reg){
 559                 case Interrupt_A_Enable_Register:
 560                         if(value)
 561                                 devpriv->int_a_enable_reg |= bits;
 562                         else
 563                                 devpriv->int_a_enable_reg &= ~bits;
 564                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 565                         break;
 566                 case Interrupt_B_Enable_Register:
 567                         if(value)
 568                                 devpriv->int_b_enable_reg |= bits;
 569                         else
 570                                 devpriv->int_b_enable_reg &= ~bits;
 571                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 572                         break;
 573                 case IO_Bidirection_Pin_Register:
 574                         if(value)
 575                                 devpriv->io_bidirection_pin_reg |= bits;
 576                         else
 577                                 devpriv->io_bidirection_pin_reg &= ~bits;
 578                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 579                         break;
 580                 default:
 581                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 582                         rt_printk("reg is %d\n",reg);
 583                         break;
 584         }
 585         comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags );
 586 }
 587
 588
 589 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
 590 {
 591         comedi_device *dev=d;
 592         unsigned short a_status;
 593         unsigned short b_status;
 594         unsigned int ai_mite_status = 0;
 595         unsigned int ao_mite_status = 0;
 596         unsigned gpct0_mite_status = 0;
 597         unsigned gpct1_mite_status = 0;
 598         unsigned long flags;
 599         struct mite_struct *mite = devpriv->mite;
 600
 601         if(dev->attached == 0) return IRQ_NONE;
 602         smp_mb();       // make sure dev->attached is checked before handler does anything else.
 603
 604         // lock to avoid race with comedi_poll
 605         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 606         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 607         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 608         if(mite)
 609         {
 610                 unsigned long flags_too;
 611
 612                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 613                 if(devpriv->ai_mite_chan)
 614                         ai_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ai_mite_chan->channel));
 615                 if(devpriv->ao_mite_chan)
 616                         ao_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->ao_mite_chan->channel));
 617                 if(devpriv->gpct_mite_chan[0])
 618                         gpct0_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->gpct_mite_chan[0]->channel));
 619                 if(devpriv->gpct_mite_chan[1])
 620                         gpct1_mite_status = readl(mite->mite_io_addr + MITE_CHSR(devpriv->gpct_mite_chan[1]->channel));
 621                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 622         }
 623         if((a_status & Interrupt_A_St) || ((ai_mite_status | gpct0_mite_status) & CHSR_INT))
 624                 handle_a_interrupt(dev, a_status, ai_mite_status, gpct0_mite_status);
 625         if((b_status & Interrupt_B_St) || ((ao_mite_status | gpct1_mite_status) & CHSR_INT))
 626                 handle_b_interrupt(dev, b_status, ao_mite_status, gpct1_mite_status);
 627         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 628         return IRQ_HANDLED;
 629 }
 630
 631 #ifdef PCIDMA
 632 static void ni_sync_ai_dma(comedi_device *dev)
 633 {
 634         comedi_subdevice *s = dev->subdevices + 0;
 635         unsigned long flags;
 636
 637         comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 638         if(devpriv->ai_mite_chan)
 639                 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
 640         comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641 }
 642
 643 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 644 {
 645         comedi_subdevice *s = dev->subdevices + 1;
 646
 647         if(devpriv->ao_mite_chan == NULL) return;
 648         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 649
 650         if(mite_sync_output_dma(devpriv->ao_mite_chan, s->async) < 0)
 651         {
 652                 s->async->events |= COMEDI_CB_ERROR;
 653                 return;
 654         }
 655 }
 656
 657 // #define DEBUG_DMA_TIMING
 658 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 659 {
 660         static const int timeout = 10000;
 661         int i;
 662 #ifdef DEBUG_DMA_TIMING
 663         struct timeval start;
 664         do_gettimeofday(&start);
 665 #endif
 666         for(i = 0; i < timeout; i++)
 667         {
 668                 unsigned short b_status;
 669
 670                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 671                 if( b_status & AO_FIFO_Half_Full_St )
 672                         break;
 673                 /* if we poll too often, the pci bus activity seems
 674                  to slow the dma transfer down */
 675                 comedi_udelay(10);
 676         }
 677 #ifdef DEBUG_DMA_TIMING
 678         rt_printk("looped %i times waiting for ao fifo load.\n", i);
 679         struct timeval now;
 680         do_gettimeofday(&now);
 681         unsigned elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 682         rt_printk("total elapsed usec=%i\n", elapsed_usec);
 683         do_gettimeofday(&start);
 684         unsigned b_status;
 685         for(i = 0; i < 100; ++i)
 686         {
 687 //              devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
 688                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 689         }
 690         do_gettimeofday(&now);
 691         elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 692         rt_printk("usec to do 100 word xfers=%i\n", elapsed_usec);
 693 #endif
 694         if( i == timeout )
 695         {
 696                 comedi_error(dev, "timed out waiting for dma load");
 697                 return -EPIPE;
 698         }
 699         return 0;
 700 }
 701
 702 #endif //PCIDMA
 703 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 704 {
 705         if(devpriv->aimode == AIMODE_SCAN)
 706         {
 707 #ifdef PCIDMA
 708                 static const int timeout = 10;
 709                 int i;
 710
 711                 for(i = 0; i < timeout; i++)
 712                 {
 713                         ni_sync_ai_dma(dev);
 714                         if((s->async->events & COMEDI_CB_EOS)) break;
 715                         comedi_udelay(1);
 716                 }
 717 #else
 718                 ni_handle_fifo_dregs(dev);
 719                 s->async->events |= COMEDI_CB_EOS;
 720 #endif
 721         }
 722         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 723         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 724                 shutdown_ai_command( dev );
 725         }
 726 }
 727
 728 static void shutdown_ai_command( comedi_device *dev )
 729 {
 730         comedi_subdevice *s = dev->subdevices + 0;
 731
 732 #ifdef PCIDMA
 733         ni_ai_drain_dma( dev );
 734 #endif
 735         ni_handle_fifo_dregs(dev);
 736         get_last_sample_611x(dev);
 737         get_last_sample_6143(dev);
 738
 739         s->async->events |= COMEDI_CB_EOA;
 740 }
 741
 742 static void handle_gpct_interrupt(comedi_device *dev, struct mite_channel *mite_chan, unsigned short is_terminal_count)
 743 {
 744         unsigned gpct_mite_status;
 745
 746         gpct_mite_status = readl(mite_chan->mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 747         if(gpct_mite_status & CHSR_INT)
 748         {}
 749 }
 750
 751 static void ni_event(comedi_device *dev, comedi_subdevice *s, unsigned events)
 752 {
 753         if(events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
 754         {
 755                 switch(s->type)
 756                 {
 757                 case COMEDI_SUBD_AI:
 758                         ni_ai_reset(dev, s);
 759                         break;
 760                 case COMEDI_SUBD_AO:
 761                         ni_ao_reset(dev, s);
 762                         break;
 763                 default:
 764                         break;
 765                 }
 766         }
 767         comedi_event(dev, s, events);
 768 }
 769
 770 static void handle_a_interrupt(comedi_device *dev, unsigned short status,
 771         unsigned ai_mite_status, unsigned gpct0_mite_status)
 772 {
 773         comedi_subdevice *s=dev->subdevices+0;
 774         unsigned short ack=0;
 775
 776         s->async->events = 0;
 777
 778 #ifdef DEBUG_INTERRUPT
 779         rt_printk("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
 780                 status, ai_mite_status);
 781         ni_mio_print_status_a(status);
 782 #endif
 783
 784
 785 #ifdef PCIDMA
 786         /* Currently, mite.c requires us to handle LINKC and DONE */
 787         if(ai_mite_status & CHSR_LINKC){
 788                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 789                 ni_sync_ai_dma(dev);
 790         }
 791
 792         if(ai_mite_status & CHSR_DONE){
 793                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ai_mite_chan->channel));
 794         }
 795
 796         if(ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 797                 rt_printk("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", ai_mite_status);
 798                 //mite_print_chsr(ai_mite_status);
 799                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 800                 //disable_irq(dev->irq);
 801         }
 802 #endif
 803
 804         /* test for all uncommon interrupt events at the same time */
 805         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 806                 if(status==0xffff){
 807                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 808                         /* we probably aren't even running a command now,
 809                          * so it's a good idea to be careful. */
 810                         if(s->subdev_flags&SDF_RUNNING){
 811                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 812                                 ni_event(dev, s, s->async->events);
 813                         }
 814                         return;
 815                 }
 816                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 817                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 818                                 status);
 819                         ni_mio_print_status_a(status);
 820
 821                         shutdown_ai_command( dev );
 822
 823                         s->async->events |= COMEDI_CB_ERROR;
 824                         if(status & (AI_Overrun_St | AI_Overflow_St))
 825                                 s->async->events |= COMEDI_CB_OVERFLOW;
 826
 827                         ni_event(dev, s, s->async->events);
 828
 829                         return;
 830                 }
 831                 if(status&AI_SC_TC_St){
 832 #ifdef DEBUG_INTERRUPT
 833                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 834 #endif
 835                         if(!devpriv->ai_continuous){
 836                                 shutdown_ai_command(dev);
 837                         }
 838                         ack|=AI_SC_TC_Interrupt_Ack;
 839                 }
 840                 if(status&AI_START1_St){
 841                         ack|=AI_START1_Interrupt_Ack;
 842                 }
 843         }
 844 #ifndef PCIDMA
 845         if(status&AI_FIFO_Half_Full_St){
 846                 int i;
 847                 static const int timeout = 10;
 848                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 849                  *fail to get the fifo less than half full, so loop to be sure.*/
 850                 for(i = 0; i < timeout; ++i)
 851                 {
 852                         ni_handle_fifo_half_full(dev);
 853                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 854                                 break;
 855                 }
 856         }
 857 #endif // !PCIDMA
 858
 859         if( (status & AI_STOP_St) ){
 860                 ni_handle_eos(dev, s);
 861                 /* we need to ack the START, also */
 862                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 863         }
 864
 865         if(status & G0_TC_St)
 866         {
 867                 ack |= G0_TC_Interrupt_Ack;
 868         }
 869         if(status & G0_Gate_Interrupt_St)
 870         {
 871                 ack |= G0_Gate_Interrupt_Ack;
 872         }
 873         if(status & (G0_TC_St | G0_Gate_Interrupt_St))
 874         {
 875                 unsigned long flags;
 876
 877                 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 878                 if(devpriv->gpct_mite_chan)
 879                         handle_gpct_interrupt(dev, devpriv->gpct_mite_chan[0], (status & G0_TC_St));
 880                 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 881         }
 882
 883         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 884         ni_event(dev,s,s->async->events);
 885
 886 #ifdef DEBUG_INTERRUPT
 887         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 888         if(status&Interrupt_A_St){
 889                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 890         }
 891 #endif
 892 }
 893
 894 static void handle_b_interrupt(comedi_device *dev, unsigned short b_status,
 895         unsigned ao_mite_status, unsigned gpct1_mite_status)
 896 {
 897         comedi_subdevice *s=dev->subdevices+1;
 898         //unsigned short ack=0;
 899 #ifdef DEBUG_INTERRUPT
 900         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 901                 b_status,ao_mite_status);
 902         ni_mio_print_status_b(b_status);
 903 #endif
 904
 905
 906 #ifdef PCIDMA
 907         /* Currently, mite.c requires us to handle LINKC and DONE */
 908         if(ao_mite_status & CHSR_LINKC){
 909                 mite_handle_b_linkc(devpriv->mite, dev);
 910         }
 911
 912         if(ao_mite_status & CHSR_DONE){
 913                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(devpriv->ao_mite_chan->channel));
 914         }
 915
 916         if(ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 917                 rt_printk("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", ao_mite_status);
 918                 //mite_print_chsr(ao_mite_status);
 919                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
 920         }
 921 #endif
 922
 923         if(b_status==0xffff)return;
 924         if(b_status&AO_Overrun_St){
 925                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 926                 s->async->events |= COMEDI_CB_OVERFLOW;
 927         }
 928
 929         if(b_status&AO_BC_TC_St){
 930                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 931                 s->async->events |= COMEDI_CB_EOA;
 932         }
 933
 934 #ifndef PCIDMA
 935         if(b_status&AO_FIFO_Request_St){
 936                 int ret;
 937
 938                 ret = ni_ao_fifo_half_empty(dev,s);
 939                 if(!ret){
 940                         rt_printk("ni_mio_common: AO buffer underrun\n");
 941                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 942                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 943                         s->async->events |= COMEDI_CB_OVERFLOW;
 944                 }
 945         }
 946 #endif
 947
 948         ni_event(dev,s,s->async->events);
 949 }
 950
 951 #ifdef DEBUG_STATUS_A
 952 static char *status_a_strings[]={
 953         "passthru0","fifo","G0_gate","G0_TC",
 954         "stop","start","sc_tc","start1",
 955         "start2","sc_tc_error","overflow","overrun",
 956         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 957 };
 958
 959 static void ni_mio_print_status_a(int status)
 960 {
 961         int i;
 962
 963         rt_printk("A status:");
 964         for(i=15;i>=0;i--){
 965                 if(status&(1<<i)){
 966                         rt_printk(" %s",status_a_strings[i]);
 967                 }
 968         }
 969         rt_printk("\n");
 970 }
 971 #endif
 972
 973 #ifdef DEBUG_STATUS_B
 974 static char *status_b_strings[]={
 975         "passthru1","fifo","G1_gate","G1_TC",
 976         "UI2_TC","UPDATE","UC_TC","BC_TC",
 977         "start1","overrun","start","bc_tc_error",
 978         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 979 };
 980
 981 static void ni_mio_print_status_b(int status)
 982 {
 983         int i;
 984
 985         rt_printk("B status:");
 986         for(i=15;i>=0;i--){
 987                 if(status&(1<<i)){
 988                         rt_printk(" %s",status_b_strings[i]);
 989                 }
 990         }
 991         rt_printk("\n");
 992 }
 993 #endif
 994
 995 #ifndef PCIDMA
 996
 997 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 998 {
 999         comedi_async *async = s->async;
1000         comedi_cmd *cmd = &async->cmd;
1001         int chan;
1002         int i;
1003         sampl_t d;
1004         u32 packed_data;
1005         int range;
1006         int err = 1;
1007
1008         chan = async->cur_chan;
1009         for(i=0;i<n;i++){
1010                 err &= comedi_buf_get(async, &d);
1011                 if(err == 0) break;
1012
1013                 range = CR_RANGE(cmd->chanlist[chan]);
1014
1015                 if(boardtype.reg_type & ni_reg_6xxx_mask)
1016                 {
1017                         packed_data = d & 0xffff;
1018                         /* 6711 only has 16 bit wide ao fifo */
1019                         if(boardtype.reg_type != ni_reg_6711)
1020                         {
1021                                 err &= comedi_buf_get(async, &d);
1022                                 if(err == 0) break;
1023                                 chan++;
1024                                 i++;
1025                                 packed_data |= ( d << 16 ) & 0xffff0000;
1026                         }
1027                         ni_writel( packed_data, DAC_FIFO_Data_611x );
1028                 }else{
1029                         ni_writew(d, DAC_FIFO_Data);
1030                 }
1031                 chan++;
1032                 chan %= cmd->chanlist_len;
1033         }
1034         async->cur_chan = chan;
1035         if(err==0){
1036                 async->events |= COMEDI_CB_OVERFLOW;
1037         }
1038 }
1039
1040 /*
1041  *  There's a small problem if the FIFO gets really low and we
1042  *  don't have the data to fill it.  Basically, if after we fill
1043  *  the FIFO with all the data available, the FIFO is _still_
1044  *  less than half full, we never clear the interrupt.  If the
1045  *  IRQ is in edge mode, we never get another interrupt, because
1046  *  this one wasn't cleared.  If in level mode, we get flooded
1047  *  with interrupts that we can't fulfill, because nothing ever
1048  *  gets put into the buffer.
1049  *
1050  *  This kind of situation is recoverable, but it is easier to
1051  *  just pretend we had a FIFO underrun, since there is a good
1052  *  chance it will happen anyway.  This is _not_ the case for
1053  *  RT code, as RT code might purposely be running close to the
1054  *  metal.  Needs to be fixed eventually.
1055  */
1056 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
1057 {
1058         int n;
1059
1060         n = comedi_buf_read_n_available(s->async);
1061         if(n==0){
1062                 s->async->events |= COMEDI_CB_OVERFLOW;
1063                 return 0;
1064         }
1065
1066         n /= sizeof(sampl_t);
1067         if(n > boardtype.ao_fifo_depth / 2)
1068                 n = boardtype.ao_fifo_depth / 2;
1069
1070         ni_ao_fifo_load(dev,s,n);
1071
1072         s->async->events |= COMEDI_CB_BLOCK;
1073
1074         return 1;
1075 }
1076
1077 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
1078 {
1079         int n;
1080
1081         /* reset fifo */
1082         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
1083         if(boardtype.reg_type & ni_reg_6xxx_mask)
1084                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1085
1086         /* load some data */
1087         n = comedi_buf_read_n_available(s->async);
1088         if(n==0)return 0;
1089
1090         n /= sizeof(sampl_t);
1091         if(n > boardtype.ao_fifo_depth)
1092                 n = boardtype.ao_fifo_depth;
1093
1094         ni_ao_fifo_load(dev,s,n);
1095
1096         return n;
1097 }
1098
1099 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
1100         int n)
1101 {
1102         comedi_async *async = s->async;
1103         int i;
1104
1105         if(boardtype.reg_type == ni_reg_611x){
1106                 sampl_t data[2];
1107                 u32 dl;
1108
1109                 for( i = 0; i < n / 2; i++ ){
1110                         dl=ni_readl(ADC_FIFO_Data_611x);
1111                         /* This may get the hi/lo data in the wrong order */
1112                         data[0] = (dl>>16) & 0xffff;
1113                         data[1] = dl & 0xffff;
1114                         cfc_write_array_to_buffer(s, data, sizeof(data));
1115                 }
1116                 /* Check if there's a single sample stuck in the FIFO */
1117                 if( n % 2){
1118                         dl=ni_readl(ADC_FIFO_Data_611x);
1119                         data[0] = dl & 0xffff;
1120                         cfc_write_to_buffer(s, data[0]);
1121                 }
1122         } else if(boardtype.reg_type == ni_reg_6143){
1123                 sampl_t data[2];
1124                 u32     dl;
1125
1126                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1127                 for(i = 0; i < n / 2; i++){
1128                         dl = ni_readl(AIFIFO_Data_6143);
1129
1130                         data[0] = (dl >> 16) & 0xffff;
1131                         data[1] = dl & 0xffff;
1132                         cfc_write_array_to_buffer(s, data, sizeof(data));
1133                 }
1134                 if(n % 2){
1135                         /* Assume there is a single sample stuck in the FIFO */
1136                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1137                         dl = ni_readl(AIFIFO_Data_6143);
1138                         data[0] = (dl >> 16) & 0xffff;
1139                         cfc_write_to_buffer(s, data[0]);
1140                 }
1141         } else{
1142                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1143                 {
1144                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1145                         async->events |= COMEDI_CB_ERROR;
1146                         return;
1147                 }
1148                 for(i = 0; i < n; i++){
1149                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1150                 }
1151                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1152                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1153         }
1154 }
1155
1156 static void ni_handle_fifo_half_full(comedi_device *dev)
1157 {
1158         int n;
1159         comedi_subdevice *s=dev->subdevices+0;
1160
1161         n=boardtype.ai_fifo_depth/2;
1162
1163         ni_ai_fifo_read(dev,s,n);
1164 }
1165 #endif
1166
1167 #ifdef PCIDMA
1168 static int ni_ai_drain_dma(comedi_device *dev )
1169 {
1170         int i;
1171         static const int timeout = 10000;
1172
1173         if(devpriv->ai_mite_chan == NULL) return 0;
1174         for( i = 0; i < timeout; i++ )
1175         {
1176                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1177                         mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
1178                         break;
1179                 comedi_udelay(2);
1180         }
1181         if(i == timeout)
1182         {
1183                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1184                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1185                         mite_bytes_in_transit(devpriv->ai_mite_chan), devpriv->stc_readw(dev, AI_Status_1_Register));
1186                 return -1;
1187         }
1188
1189         ni_sync_ai_dma(dev);
1190
1191         return 0;
1192 }
1193 #endif
1194 /*
1195    Empties the AI fifo
1196 */
1197 static void ni_handle_fifo_dregs(comedi_device *dev)
1198 {
1199         comedi_subdevice *s=dev->subdevices+0;
1200         sampl_t data[2];
1201         u32 dl;
1202         short fifo_empty;
1203         int i;
1204
1205         if(boardtype.reg_type == ni_reg_611x){
1206                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1207                         dl=ni_readl(ADC_FIFO_Data_611x);
1208
1209                         /* This may get the hi/lo data in the wrong order */
1210                         data[0] = (dl>>16);
1211                         data[1] = (dl&0xffff);
1212                         cfc_write_array_to_buffer(s, data, sizeof(data));
1213                 }
1214         }else if(boardtype.reg_type == ni_reg_6143){
1215                 i = 0;
1216                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1217                         dl = ni_readl(AIFIFO_Data_6143);
1218
1219                         /* This may get the hi/lo data in the wrong order */
1220                         data[0] = (dl >> 16);
1221                         data[1] = (dl & 0xffff);
1222                         cfc_write_array_to_buffer(s, data, sizeof(data));
1223                         i += 2;
1224                 }
1225                 // Check if stranded sample is present
1226                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1227                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1228                         dl = ni_readl(AIFIFO_Data_6143);
1229                         data[0] = (dl >> 16) & 0xffff;
1230                         cfc_write_to_buffer(s, data[0]);
1231                 }
1232
1233         }else{
1234                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1235                 while(fifo_empty == 0)
1236                 {
1237                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1238                         {
1239                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1240                                 if(fifo_empty) break;
1241                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1242                         }
1243                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1244                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1245                 }
1246         }
1247 }
1248
1249 static void get_last_sample_611x( comedi_device *dev )
1250 {
1251         comedi_subdevice *s=dev->subdevices+0;
1252         sampl_t data;
1253         u32 dl;
1254
1255         if(boardtype.reg_type != ni_reg_611x) return;
1256
1257         /* Check if there's a single sample stuck in the FIFO */
1258         if(ni_readb(XXX_Status)&0x80){
1259                 dl=ni_readl(ADC_FIFO_Data_611x);
1260                 data = (dl&0xffff);
1261                 cfc_write_to_buffer(s, data);
1262         }
1263 }
1264
1265 static void get_last_sample_6143(comedi_device* dev)
1266 {
1267         comedi_subdevice*       s = dev->subdevices + 0;
1268         sampl_t                 data;
1269         u32                     dl;
1270
1271         if(boardtype.reg_type != ni_reg_6143) return;
1272
1273         /* Check if there's a single sample stuck in the FIFO */
1274         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1275                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1276                 dl = ni_readl(AIFIFO_Data_6143);
1277
1278                 /* This may get the hi/lo data in the wrong order */
1279                 data = (dl >> 16) & 0xffff;
1280                 cfc_write_to_buffer(s, data);
1281         }
1282 }
1283
1284 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1285         void *data, unsigned int num_bytes, unsigned int chan_index )
1286 {
1287         comedi_async *async = s->async;
1288         unsigned int i;
1289         unsigned int length = num_bytes / bytes_per_sample(s);
1290         sampl_t *array = data;
1291         lsampl_t *larray = data;
1292         for(i = 0; i < length; i++)
1293         {
1294 #ifdef PCIDMA
1295                 if(s->subdev_flags & SDF_LSAMPL)
1296                         larray[i] = le32_to_cpu(larray[i]);
1297                 else
1298                         array[i] = le16_to_cpu(array[i]);
1299 #endif
1300                 if(s->subdev_flags & SDF_LSAMPL)
1301                         larray[i] += devpriv->ai_offset[chan_index];
1302                 else
1303                         array[i] += devpriv->ai_offset[chan_index];
1304                 chan_index++;
1305                 chan_index %= async->cmd.chanlist_len;
1306         }
1307 }
1308
1309 #ifdef PCIDMA
1310
1311 static int ni_ai_setup_MITE_dma(comedi_device *dev)
1312 {
1313         comedi_subdevice *s = dev->subdevices + 0;
1314         int retval;
1315
1316         retval = ni_request_ai_mite_channel(dev);
1317         if(retval) return retval;
1318 //      rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1319
1320         /* write alloc the entire buffer */
1321         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1322
1323         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
1324         switch(boardtype.reg_type)
1325         {
1326         case ni_reg_611x:
1327         case ni_reg_6143:
1328                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1329                 break;
1330         case ni_reg_628x:
1331                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1332                 break;
1333         default:
1334                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1335                 break;
1336         };
1337         /*start the MITE*/
1338         mite_dma_arm(devpriv->ai_mite_chan);
1339         return 0;
1340 }
1341
1342 static int ni_ao_setup_MITE_dma(comedi_device *dev)
1343 {
1344         comedi_subdevice *s = dev->subdevices + 1;
1345         int retval;
1346
1347         retval = ni_request_ao_mite_channel(dev);
1348         if(retval) return retval;
1349         //rt_printk("comedi_debug: using mite channel %i for ao.\n", devpriv->ao_mite_chan->channel);
1350
1351         /* read alloc the entire buffer */
1352         comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1353
1354         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
1355         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1356         {
1357                 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1358         }else
1359         {
1360                 /* doing 32 instead of 16 bit wide transfers from memory
1361                  makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1362                 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1363         }
1364         /*start the MITE*/
1365         mite_dma_arm(devpriv->ao_mite_chan);
1366         return 0;
1367 }
1368
1369 #endif // PCIDMA
1370
1371 /*
1372    used for both cancel ioctl and board initialization
1373
1374    this is pretty harsh for a cancel, but it works...
1375  */
1376
1377 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1378 {
1379         ni_release_ai_mite_channel(dev);
1380         /* ai configuration */
1381         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1382
1383         ni_set_bits(dev, Interrupt_A_Enable_Register,
1384                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1385                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1386                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1387                 AI_FIFO_Interrupt_Enable,0);
1388
1389         ni_clear_ai_fifo(dev);
1390
1391         if(boardtype.reg_type != ni_reg_6143)
1392                 ni_writeb(0, Misc_Command);
1393
1394         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1395         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1396                 AI_Mode_1_Register);
1397         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1398         /* generate FIFO interrupts on non-empty */
1399         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1400         if(boardtype.reg_type == ni_reg_611x){
1401                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1402                         AI_SOC_Polarity |
1403                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1404                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1405                         AI_EXTMUX_CLK_Output_Select(0) |
1406                         AI_LOCALMUX_CLK_Output_Select(2) |
1407                         AI_SC_TC_Output_Select(3) |
1408                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High), AI_Output_Control_Register);
1409         }else if(boardtype.reg_type == ni_reg_6143){
1410                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1411                         AI_SOC_Polarity |
1412                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1413                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1414                         AI_EXTMUX_CLK_Output_Select(0) |
1415                         AI_LOCALMUX_CLK_Output_Select(2) |
1416                         AI_SC_TC_Output_Select(3) |
1417                         AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),AI_Output_Control_Register);
1418         }else{
1419                 unsigned ai_output_control_bits;
1420                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1421                         AI_SOC_Polarity |
1422                         AI_CONVERT_Pulse_Width |
1423                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1424                 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1425                         AI_EXTMUX_CLK_Output_Select(0) |
1426                         AI_LOCALMUX_CLK_Output_Select(2) |
1427                         AI_SC_TC_Output_Select(3);
1428                 if(boardtype.reg_type == ni_reg_622x)
1429                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High);
1430                 else
1431                         ai_output_control_bits |= AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low);
1432                 devpriv->stc_writew(dev, ai_output_control_bits, AI_Output_Control_Register);
1433         }
1434         /* the following registers should not be changed, because there
1435          * are no backup registers in devpriv.  If you want to change
1436          * any of these, add a backup register and other appropriate code:
1437          *      AI_Mode_1_Register
1438          *      AI_Mode_3_Register
1439          *      AI_Personal_Register
1440          *      AI_Output_Control_Register
1441         */
1442         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1443                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1444                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1445                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1446
1447         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1448
1449         return 0;
1450 }
1451
1452 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1453 {
1454         unsigned long flags = 0;
1455         int count;
1456
1457         // lock to avoid race with interrupt handler
1458         if(in_interrupt() == 0)
1459                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1460 #ifndef PCIDMA
1461         ni_handle_fifo_dregs(dev);
1462 #else
1463         ni_sync_ai_dma(dev);
1464 #endif
1465         count = s->async->buf_write_count - s->async->buf_read_count;
1466         if(in_interrupt() == 0)
1467                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1468
1469         return count;
1470 }
1471
1472
1473 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1474 {
1475         int i,n;
1476         const unsigned int mask = (1 << boardtype.adbits) - 1;
1477         unsigned signbits;
1478         unsigned short d;
1479         unsigned long dl;
1480
1481         ni_load_channelgain_list(dev,1,&insn->chanspec);
1482
1483         ni_clear_ai_fifo(dev);
1484
1485         signbits=devpriv->ai_offset[0];
1486         if(boardtype.reg_type == ni_reg_611x){
1487                 for(n=0; n < num_adc_stages_611x; n++){
1488                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1489                         comedi_udelay(1);
1490                 }
1491                 for(n=0; n<insn->n; n++){
1492                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1493                         /* The 611x has screwy 32-bit FIFOs. */
1494                         d = 0;
1495                         for(i=0; i<NI_TIMEOUT; i++){
1496                                 if(ni_readb(XXX_Status)&0x80)
1497                                 {
1498                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1499                                         break;
1500                                 }
1501                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1502                                 {
1503                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1504                                         break;
1505                                 }
1506                         }
1507                         if(i==NI_TIMEOUT){
1508                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1509                                 return -ETIME;
1510                         }
1511                         d += signbits;
1512                         data[ n ] = d;
1513                 }
1514         }else if(boardtype.reg_type == ni_reg_6143){
1515                 for(n = 0; n < insn->n; n++){
1516                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1517
1518                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1519                         dl = 0;
1520                         for(i = 0; i < NI_TIMEOUT; i++){
1521                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1522                                 {
1523                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1524                                         dl = ni_readl(AIFIFO_Data_6143);
1525                                         break;
1526                                 }
1527                         }
1528                         if(i == NI_TIMEOUT){
1529                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1530                                 return -ETIME;
1531                         }
1532                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1533                 }
1534         }else{
1535                 for(n = 0; n < insn->n; n++){
1536                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1537                         for(i = 0; i < NI_TIMEOUT; i++){
1538                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1539                                         break;
1540                         }
1541                         if(i == NI_TIMEOUT){
1542                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1543                                 return -ETIME;
1544                         }
1545                         if(boardtype.reg_type & ni_reg_m_series_mask)
1546                         {
1547                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1548                         }else
1549                         {
1550                                 d = ni_readw(ADC_FIFO_Data_Register);
1551                                 d += signbits; /* subtle: needs to be short addition */
1552                                 data[n] = d;
1553                         }
1554                 }
1555         }
1556         return insn->n;
1557 }
1558
1559 void ni_prime_channelgain_list(comedi_device *dev)
1560 {
1561         int i;
1562         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1563         for(i = 0; i < NI_TIMEOUT; ++i)
1564         {
1565                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1566                 {
1567                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1568                         return;
1569                 }
1570                 comedi_udelay(1);
1571         }
1572         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1573 }
1574
1575 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1576         unsigned int *list)
1577 {
1578         unsigned int chan, range, aref;
1579         unsigned int i;
1580         unsigned offset;
1581         unsigned int dither;
1582         unsigned range_code;
1583
1584         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1585
1586 //      offset = 1 << (boardtype.adbits - 1);
1587         if((list[0] & CR_ALT_SOURCE))
1588         {
1589                 unsigned bypass_bits;
1590                 chan = CR_CHAN(list[0]);
1591                 range = CR_RANGE(list[0]);
1592                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1593                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1594                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1595                 bypass_bits |= chan;
1596                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1597                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1598                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1599                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1600                 if(dither)
1601                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1602                 // don't use 2's complement encoding
1603                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1604                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1605         }else
1606         {
1607                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1608         }
1609         offset = 0;
1610         for(i = 0; i < n_chan; i++)
1611         {
1612                 unsigned config_bits = 0;
1613                 chan = CR_CHAN(list[i]);
1614                 aref = CR_AREF(list[i]);
1615                 range = CR_RANGE(list[i]);
1616                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1617
1618                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1619                 devpriv->ai_offset[i] = offset;
1620                 switch( aref )
1621                 {
1622                         case AREF_DIFF:
1623                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1624                                 break;
1625                         case AREF_COMMON:
1626                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1627                                 break;
1628                         case AREF_GROUND:
1629                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1630                                 break;
1631                         case AREF_OTHER:
1632                                 break;
1633                 }
1634                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1635                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1636                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1637                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1638                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1639                 // don't use 2's complement encoding
1640                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1641                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1642         }
1643         ni_prime_channelgain_list(dev);
1644 }
1645
1646 /*
1647  * Notes on the 6110 and 6111:
1648  * These boards a slightly different than the rest of the series, since
1649  * they have multiple A/D converters.
1650  * From the driver side, the configuration memory is a
1651  * little different.
1652  * Configuration Memory Low:
1653  *   bits 15-9: same
1654  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1655  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1656  *       1001 gain=0.1 (+/- 50)
1657  *       1010 0.2
1658  *       1011 0.1
1659  *       0001 1
1660  *       0010 2
1661  *       0011 5
1662  *       0100 10
1663  *       0101 20
1664  *       0110 50
1665  * Configuration Memory High:
1666  *   bits 12-14: Channel Type
1667  *       001 for differential
1668  *       000 for calibration
1669  *   bit 11: coupling  (this is not currently handled)
1670  *       1 AC coupling
1671  *       0 DC coupling
1672  *   bits 0-2: channel
1673  *       valid channels are 0-3
1674  */
1675 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1676         unsigned int *list)
1677 {
1678         unsigned int chan,range,aref;
1679         unsigned int i;
1680         unsigned int hi,lo;
1681         unsigned offset;
1682         unsigned int dither;
1683
1684         if(boardtype.reg_type & ni_reg_m_series_mask)
1685         {
1686                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1687                 return;
1688         }
1689         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1690                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1691                         // ready to go.
1692                         return;
1693                 }
1694                 devpriv->changain_state=1;
1695                 devpriv->changain_spec=list[0];
1696         }else{
1697                 devpriv->changain_state=0;
1698         }
1699
1700         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1701
1702         // Set up Calibration mode if required
1703         if(boardtype.reg_type == ni_reg_6143){
1704                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1705                         // Strobe Relay enable bit
1706                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1707                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1708                         devpriv->ai_calib_source_enabled = 1;
1709                         msleep_interruptible(100);      // Allow relays to change
1710                 }
1711                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1712                         // Strobe Relay disable bit
1713                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1714                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1715                         devpriv->ai_calib_source_enabled = 0;
1716                         msleep_interruptible(100);      // Allow relays to change
1717                 }
1718         }
1719
1720         offset=1<<(boardtype.adbits-1);
1721         for(i=0;i<n_chan;i++){
1722                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1723                         chan=devpriv->ai_calib_source;
1724                 }else{
1725                         chan=CR_CHAN(list[i]);
1726                 }
1727                 aref=CR_AREF(list[i]);
1728                 range=CR_RANGE(list[i]);
1729                 dither=((list[i]&CR_ALT_FILTER)!=0);
1730
1731                 /* fix the external/internal range differences */
1732                 range = ni_gainlkup[boardtype.gainlkup][range];
1733                 if(boardtype.reg_type == ni_reg_611x)
1734                         devpriv->ai_offset[i] = offset;
1735                 else
1736                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1737
1738                 hi = 0;
1739                 if( ( list[i] & CR_ALT_SOURCE ) )
1740                 {
1741                         if(boardtype.reg_type == ni_reg_611x)
1742                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1743                 }else
1744                 {
1745                         if(boardtype.reg_type == ni_reg_611x)
1746                                 aref = AREF_DIFF;
1747                         else if(boardtype.reg_type == ni_reg_6143)
1748                                 aref = AREF_OTHER;
1749                         switch( aref )
1750                         {
1751                                 case AREF_DIFF:
1752                                         hi |= AI_DIFFERENTIAL;
1753                                         break;
1754                                 case AREF_COMMON:
1755                                         hi |= AI_COMMON;
1756                                         break;
1757                                 case AREF_GROUND:
1758                                         hi |= AI_GROUND;
1759                                         break;
1760                                 case AREF_OTHER:
1761                                         break;
1762                         }
1763                 }
1764                 hi |= AI_CONFIG_CHANNEL( chan );
1765
1766                 ni_writew(hi,Configuration_Memory_High);
1767
1768                 if(boardtype.reg_type != ni_reg_6143){
1769                         lo = range;
1770                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1771                         if( dither ) lo |= AI_DITHER;
1772
1773                         ni_writew(lo,Configuration_Memory_Low);
1774                 }
1775         }
1776
1777         /* prime the channel/gain list */
1778         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1779                 ni_prime_channelgain_list(dev);
1780         }
1781 }
1782
1783 static int ni_ns_to_timer(const comedi_device *dev, unsigned nanosec, int round_mode)
1784 {
1785         int divider;
1786         switch(round_mode)
1787         {
1788         case TRIG_ROUND_NEAREST:
1789         default:
1790                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1791                 break;
1792         case TRIG_ROUND_DOWN:
1793                 divider = (nanosec) / devpriv->clock_ns;
1794                 break;
1795         case TRIG_ROUND_UP:
1796                 divider=(nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1797                 break;
1798         }
1799         return divider - 1;
1800 }
1801
1802 static unsigned ni_timer_to_ns(const comedi_device *dev, int timer)
1803 {
1804         return devpriv->clock_ns * (timer + 1);
1805 }
1806
1807 static unsigned ni_min_ai_scan_period_ns(comedi_device *dev, unsigned num_channels)
1808 {
1809         switch(boardtype.reg_type)
1810         {
1811         case ni_reg_611x:
1812         case ni_reg_6143:
1813         // simultaneously-sampled inputs
1814                 return boardtype.ai_speed;
1815                 break;
1816         default:
1817         // multiplexed inputs
1818                 break;
1819         };
1820         return boardtype.ai_speed * num_channels;
1821 }
1822
1823 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1824 {
1825         int err=0;
1826         int tmp;
1827         int sources;
1828
1829         /* step 1: make sure trigger sources are trivially valid */
1830
1831         tmp=cmd->start_src;
1832         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1833         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1834
1835         tmp=cmd->scan_begin_src;
1836         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1837         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1838
1839         tmp=cmd->convert_src;
1840         sources = TRIG_TIMER | TRIG_EXT;
1841         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1842         cmd->convert_src &= sources;
1843         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1844
1845         tmp=cmd->scan_end_src;
1846         cmd->scan_end_src &= TRIG_COUNT;
1847         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1848
1849         tmp=cmd->stop_src;
1850         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1851         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1852
1853         if(err)return 1;
1854
1855         /* step 2: make sure trigger sources are unique and mutually compatible */
1856
1857         /* note that mutual compatiblity is not an issue here */
1858         if(cmd->start_src!=TRIG_NOW &&
1859            cmd->start_src!=TRIG_INT &&
1860            cmd->start_src!=TRIG_EXT)err++;
1861         if(cmd->scan_begin_src!=TRIG_TIMER &&
1862            cmd->scan_begin_src!=TRIG_EXT &&
1863            cmd->scan_begin_src!=TRIG_OTHER)err++;
1864         if(cmd->convert_src!=TRIG_TIMER &&
1865            cmd->convert_src!=TRIG_EXT &&
1866            cmd->convert_src!=TRIG_NOW)err++;
1867         if(cmd->stop_src!=TRIG_COUNT &&
1868            cmd->stop_src!=TRIG_NONE)err++;
1869
1870         if(err)return 2;
1871
1872         /* step 3: make sure arguments are trivially compatible */
1873
1874         if(cmd->start_src==TRIG_EXT){
1875                 /* external trigger */
1876                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1877
1878                 if(tmp > 16) tmp = 16;
1879                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1880                 if(cmd->start_arg != tmp){
1881                         cmd->start_arg = tmp;
1882                         err++;
1883                 }
1884         }else{
1885                 if(cmd->start_arg!=0){
1886                         /* true for both TRIG_NOW and TRIG_INT */
1887                         cmd->start_arg=0;
1888                         err++;
1889                 }
1890         }
1891         if(cmd->scan_begin_src==TRIG_TIMER){
1892                 if(cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev, cmd->chanlist_len))
1893                 {
1894                         cmd->scan_begin_arg = ni_min_ai_scan_period_ns(dev, cmd->chanlist_len);
1895                         err++;
1896                 }
1897                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1898                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1899                         err++;
1900                 }
1901         }else if(cmd->scan_begin_src==TRIG_EXT){
1902                 /* external trigger */
1903                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1904
1905                 if(tmp>16)tmp=16;
1906                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1907                 if(cmd->scan_begin_arg!=tmp){
1908                         cmd->scan_begin_arg = tmp;
1909                         err++;
1910                 }
1911         }else{ /* TRIG_OTHER */
1912                 if(cmd->scan_begin_arg){
1913                         cmd->scan_begin_arg=0;
1914                         err++;
1915                 }
1916         }
1917         if(cmd->convert_src==TRIG_TIMER){
1918                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1919                         if(cmd->convert_arg != 0){
1920                                 cmd->convert_arg = 0;
1921                                 err++;
1922                         }
1923                 }else{
1924                         if(cmd->convert_arg<boardtype.ai_speed){
1925                                 cmd->convert_arg=boardtype.ai_speed;
1926                                 err++;
1927                         }
1928                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1929                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1930                                 err++;
1931                         }
1932                 }
1933         }else if(cmd->convert_src == TRIG_EXT){
1934                 /* external trigger */
1935                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1936
1937                 if(tmp>16)tmp=16;
1938                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1939                 if(cmd->convert_arg!=tmp){
1940                         cmd->convert_arg = tmp;
1941                         err++;
1942                 }
1943         }else if(cmd->convert_src == TRIG_NOW){
1944                 if(cmd->convert_arg != 0){
1945                         cmd->convert_arg = 0;
1946                         err++;
1947                 }
1948         }
1949
1950         if(cmd->scan_end_arg!=cmd->chanlist_len){
1951                 cmd->scan_end_arg=cmd->chanlist_len;
1952                 err++;
1953         }
1954         if(cmd->stop_src==TRIG_COUNT){
1955                 unsigned int max_count = 0x01000000;
1956
1957                 if(boardtype.reg_type == ni_reg_611x )
1958                         max_count -= num_adc_stages_611x;
1959                 if(cmd->stop_arg > max_count){
1960                         cmd->stop_arg = max_count;
1961                         err++;
1962                 }
1963                 if(cmd->stop_arg < 1){
1964                         cmd->stop_arg = 1;
1965                         err++;
1966                 }
1967         }else{
1968                 /* TRIG_NONE */
1969                 if(cmd->stop_arg!=0){
1970                         cmd->stop_arg=0;
1971                         err++;
1972                 }
1973         }
1974
1975         if(err)return 3;
1976
1977         /* step 4: fix up any arguments */
1978
1979         if(cmd->scan_begin_src==TRIG_TIMER){
1980                 tmp=cmd->scan_begin_arg;
1981                 cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags & TRIG_ROUND_MASK));
1982                 if(tmp!=cmd->scan_begin_arg)err++;
1983         }
1984         if(cmd->convert_src==TRIG_TIMER){
1985                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1986                         tmp=cmd->convert_arg;
1987                         cmd->convert_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->convert_arg, cmd->flags & TRIG_ROUND_MASK));
1988                         if(tmp!=cmd->convert_arg)err++;
1989                         if(cmd->scan_begin_src==TRIG_TIMER &&
1990                                 cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg)
1991                         {
1992                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1993                                 err++;
1994                         }
1995                 }
1996         }
1997
1998         if(err)return 4;
1999
2000         return 0;
2001 }
2002
2003 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
2004 {
2005         const comedi_cmd *cmd=&s->async->cmd;
2006         int timer;
2007         int mode1=0; /* mode1 is needed for both stop and convert */
2008         int mode2=0;
2009         int start_stop_select=0;
2010         unsigned int stop_count;
2011         int interrupt_a_enable=0;
2012
2013         MDPRINTK("ni_ai_cmd\n");
2014         if(dev->irq == 0)
2015         {
2016                 comedi_error(dev, "cannot run command without an irq");
2017                 return -EIO;
2018         }
2019         ni_clear_ai_fifo(dev);
2020
2021         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
2022
2023         /* start configuration */
2024         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
2025
2026         /* disable analog triggering for now, since it
2027          * interferes with the use of pfi0 */
2028         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2029         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
2030
2031         switch(cmd->start_src){
2032                 case TRIG_INT:
2033                 case TRIG_NOW:
2034                         devpriv->stc_writew(dev, AI_START2_Select(0)|
2035                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
2036                                 AI_Trigger_Select_Register);
2037                         break;
2038                 case TRIG_EXT:
2039                 {
2040                         int chan = CR_CHAN(cmd->start_arg);
2041                         unsigned int bits = AI_START2_Select(0)|
2042                                 AI_START1_Sync |
2043                                 AI_START1_Select(chan + 1);
2044
2045                         if(cmd->start_arg & CR_INVERT)
2046                                 bits |= AI_START1_Polarity;
2047                         if(cmd->start_arg & CR_EDGE)
2048                                 bits |= AI_START1_Edge;
2049                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
2050                         break;
2051                 }
2052         }
2053
2054         mode2 &= ~AI_Pre_Trigger;
2055         mode2 &= ~AI_SC_Initial_Load_Source;
2056         mode2 &= ~AI_SC_Reload_Mode;
2057         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2058
2059         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
2060                 start_stop_select |= AI_STOP_Polarity;
2061                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
2062                 start_stop_select |= AI_STOP_Sync;
2063         }else
2064         {
2065                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
2066         }
2067         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2068
2069         devpriv->ai_cmd2 = 0;
2070         switch(cmd->stop_src){
2071         case TRIG_COUNT:
2072                 stop_count = cmd->stop_arg - 1;
2073
2074                 if(boardtype.reg_type == ni_reg_611x){
2075                         // have to take 3 stage adc pipeline into account
2076                         stop_count += num_adc_stages_611x;
2077                 }
2078                 /* stage number of scans */
2079                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
2080
2081                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2082                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2083                 /* load SC (Scan Count) */
2084                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2085
2086                 devpriv->ai_continuous = 0;
2087                 if( stop_count == 0 ){
2088                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2089                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2090                         // this is required to get the last sample for chanlist_len > 1, not sure why
2091                         if(cmd->chanlist_len > 1)
2092                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
2093                 }
2094                 break;
2095         case TRIG_NONE:
2096                 /* stage number of scans */
2097                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
2098
2099                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2100                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2101
2102                 /* load SC (Scan Count) */
2103                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
2104
2105                 devpriv->ai_continuous = 1;
2106
2107                 break;
2108         }
2109
2110         switch(cmd->scan_begin_src){
2111         case TRIG_TIMER:
2112                 /*
2113                         stop bits for non 611x boards
2114                         AI_SI_Special_Trigger_Delay=0
2115                         AI_Pre_Trigger=0
2116                         AI_START_STOP_Select_Register:
2117                         AI_START_Polarity=0 (?) rising edge
2118                         AI_START_Edge=1         edge triggered
2119                         AI_START_Sync=1 (?)
2120                         AI_START_Select=0               SI_TC
2121                         AI_STOP_Polarity=0              rising edge
2122                         AI_STOP_Edge=0          level
2123                         AI_STOP_Sync=1
2124                         AI_STOP_Select=19               external pin (configuration mem)
2125                  */
2126                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2127                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2128
2129                 mode2 |= AI_SI_Reload_Mode(0);
2130                 /* AI_SI_Initial_Load_Source=A */
2131                 mode2 &= ~AI_SI_Initial_Load_Source;
2132                 //mode2 |= AI_SC_Reload_Mode;
2133                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2134
2135                 /* load SI */
2136                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2137                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
2138                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
2139                 break;
2140         case TRIG_EXT:
2141                 if( cmd->scan_begin_arg & CR_EDGE )
2142                         start_stop_select |= AI_START_Edge;
2143                 /* AI_START_Polarity==1 is falling edge */
2144                 if( cmd->scan_begin_arg & CR_INVERT )
2145                         start_stop_select |= AI_START_Polarity;
2146                 if( cmd->scan_begin_src != cmd->convert_src ||
2147                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
2148                         start_stop_select |= AI_START_Sync;
2149                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2150                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2151                 break;
2152         }
2153
2154         switch(cmd->convert_src){
2155         case TRIG_TIMER:
2156         case TRIG_NOW:
2157                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
2158                         timer = 1;
2159                 else
2160                         timer = ni_ns_to_timer(dev, cmd->convert_arg, TRIG_ROUND_NEAREST);
2161                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
2162                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
2163
2164                 /* AI_SI2_Reload_Mode = alternate */
2165                 /* AI_SI2_Initial_Load_Source = A */
2166                 mode2 &= ~AI_SI2_Initial_Load_Source;
2167                 mode2 |= AI_SI2_Reload_Mode;
2168                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2169
2170                 /* AI_SI2_Load */
2171                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2172
2173                 mode2 |= AI_SI2_Reload_Mode; // alternate
2174                 mode2 |= AI_SI2_Initial_Load_Source; // B
2175
2176                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2177                 break;
2178         case TRIG_EXT:
2179                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2180                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2181                         mode1 |= AI_CONVERT_Source_Polarity;
2182                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2183
2184                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2185                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2186
2187                 break;
2188         }
2189
2190         if(dev->irq){
2191
2192                 /* interrupt on FIFO, errors, SC_TC */
2193                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2194                         AI_SC_TC_Interrupt_Enable;
2195
2196 #ifndef PCIDMA
2197                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2198 #endif
2199
2200                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2201                         /* wake on end-of-scan */
2202                         devpriv->aimode=AIMODE_SCAN;
2203                 }else{
2204                         devpriv->aimode=AIMODE_HALF_FULL;
2205                 }
2206
2207                 switch(devpriv->aimode){
2208                 case AIMODE_HALF_FULL:
2209                         /*generate FIFO interrupts and DMA requests on half-full */
2210 #ifdef PCIDMA
2211                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2212 #else
2213                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2214 #endif
2215                         break;
2216                 case AIMODE_SAMPLE:
2217                         /*generate FIFO interrupts on non-empty */
2218                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2219                         break;
2220                 case AIMODE_SCAN:
2221 #ifdef PCIDMA
2222                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2223 #else
2224                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2225 #endif
2226                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2227                         break;
2228                 default:
2229                         break;
2230                 }
2231
2232                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2233
2234                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2235
2236                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2237         }else{
2238                 /* interrupt on nothing */
2239                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2240
2241                 /* XXX start polling if necessary */
2242                 MDPRINTK("interrupting on nothing\n");
2243         }
2244
2245         /* end configuration */
2246         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2247
2248         switch(cmd->scan_begin_src){
2249         case TRIG_TIMER:
2250                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2251                         AI_Command_1_Register);
2252                 break;
2253         case TRIG_EXT:
2254                 /* XXX AI_SI_Arm? */
2255                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2256                         AI_Command_1_Register);
2257                 break;
2258         }
2259
2260 #ifdef PCIDMA
2261         {
2262                 int retval = ni_ai_setup_MITE_dma(dev);
2263                 if(retval) return retval;
2264         }
2265         //mite_dump_regs(devpriv->mite);
2266 #endif
2267
2268         switch(cmd->start_src){
2269         case TRIG_NOW:
2270                 /* AI_START1_Pulse */
2271                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2272                 s->async->inttrig=NULL;
2273                 break;
2274         case TRIG_EXT:
2275                 s->async->inttrig=NULL;
2276                 break;
2277         case TRIG_INT:
2278                 s->async->inttrig=ni_ai_inttrig;
2279                 break;
2280         }
2281
2282         MDPRINTK("exit ni_ai_cmd\n");
2283
2284         return 0;
2285 }
2286
2287 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2288         unsigned int trignum)
2289 {
2290         if(trignum!=0)return -EINVAL;
2291
2292         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2293         s->async->inttrig=NULL;
2294
2295         return 1;
2296 }
2297
2298 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2299         comedi_insn *insn, lsampl_t *data);
2300
2301 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2302         comedi_insn *insn, lsampl_t *data)
2303 {
2304         if(insn->n<1)return -EINVAL;
2305
2306         switch(data[0]){
2307         case INSN_CONFIG_ANALOG_TRIG:
2308                 return ni_ai_config_analog_trig(dev,s,insn,data);
2309         case INSN_CONFIG_ALT_SOURCE:
2310                 if(boardtype.reg_type & ni_reg_m_series_mask)
2311                 {
2312                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2313                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2314                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2315                         {
2316                                 return -EINVAL;
2317                         }
2318                         devpriv->ai_calib_source = data[1];
2319                 } else if(boardtype.reg_type == ni_reg_6143)
2320                 {
2321                         unsigned int calib_source;
2322
2323                         calib_source = data[1] & 0xf;
2324
2325
2326                         if(calib_source > 0xF)
2327                                 return -EINVAL;
2328
2329                         devpriv->ai_calib_source = calib_source;
2330                         ni_writew(calib_source, Calibration_Channel_6143);
2331                 }else
2332                 {
2333                         unsigned int calib_source;
2334                         unsigned int calib_source_adjust;
2335
2336                         calib_source = data[1] & 0xf;
2337                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2338
2339                         if(calib_source >= 8)
2340                                 return -EINVAL;
2341                         devpriv->ai_calib_source = calib_source;
2342                         if(boardtype.reg_type == ni_reg_611x){
2343                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2344                         }
2345                 }
2346                 return 2;
2347         default:
2348                 break;
2349         }
2350
2351         return -EINVAL;
2352 }
2353
2354 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2355         comedi_insn *insn, lsampl_t *data)
2356 {
2357         unsigned int a,b,modebits;
2358         int err=0;
2359
2360         /* data[1] is flags
2361          * data[2] is analog line
2362          * data[3] is set level
2363          * data[4] is reset level */
2364         if(!boardtype.has_analog_trig)return -EINVAL;
2365         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2366                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2367                 err++;
2368         }
2369         if(data[2]>=boardtype.n_adchan){
2370                 data[2]=boardtype.n_adchan-1;
2371                 err++;
2372         }
2373         if(data[3]>255){ /* a */
2374                 data[3]=255;
2375                 err++;
2376         }
2377         if(data[4]>255){ /* b */
2378                 data[4]=255;
2379                 err++;
2380         }
2381         /*
2382          * 00 ignore
2383          * 01 set
2384          * 10 reset
2385          *
2386          * modes:
2387          *   1 level:                    +b-   +a-
2388          *     high mode                00 00 01 10
2389          *     low mode                 00 00 10 01
2390          *   2 level: (a<b)
2391          *     hysteresis low mode      10 00 00 01
2392          *     hysteresis high mode     01 00 00 10
2393          *     middle mode              10 01 01 10
2394          */
2395
2396         a=data[3];
2397         b=data[4];
2398         modebits=data[1]&0xff;
2399         if(modebits&0xf0){
2400                 /* two level mode */
2401                 if(b<a){
2402                         /* swap order */
2403                         a=data[4];
2404                         b=data[3];
2405                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2406                 }
2407                 devpriv->atrig_low = a;
2408                 devpriv->atrig_high = b;
2409                 switch(modebits){
2410                 case 0x81:      /* low hysteresis mode */
2411                         devpriv->atrig_mode = 6;
2412                         break;
2413                 case 0x42:      /* high hysteresis mode */
2414                         devpriv->atrig_mode = 3;
2415                         break;
2416                 case 0x96:      /* middle window mode */
2417                         devpriv->atrig_mode = 2;
2418                         break;
2419                 default:
2420                         data[1]&=~0xff;
2421                         err++;
2422                 }
2423         }else{
2424                 /* one level mode */
2425                 if(b!=0){
2426                         data[4]=0;
2427                         err++;
2428                 }
2429                 switch(modebits){
2430                 case 0x06:      /* high window mode */
2431                         devpriv->atrig_high = a;
2432                         devpriv->atrig_mode = 0;
2433                         break;
2434                 case 0x09:      /* low window mode */
2435                         devpriv->atrig_low = a;
2436                         devpriv->atrig_mode = 1;
2437                         break;
2438                 default:
2439                         data[1]&=~0xff;
2440                         err++;
2441                 }
2442         }
2443         if(err)return -EAGAIN;
2444         return 5;
2445 }
2446
2447 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2448 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2449         void *data, unsigned int num_bytes, unsigned int chan_index )
2450 {
2451         comedi_async *async = s->async;
2452         unsigned int range;
2453         unsigned int i;
2454         unsigned int offset;
2455         unsigned int length = num_bytes / sizeof( sampl_t );
2456         sampl_t *array = data;
2457
2458         offset = 1 << (boardtype.aobits - 1);
2459         for(i = 0; i < length; i++)
2460         {
2461                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2462                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2463                         array[i] -= offset;
2464 #ifdef PCIDMA
2465                 array[i] = cpu_to_le16( array[i] );
2466 #endif
2467                 chan_index++;
2468                 chan_index %= async->cmd.chanlist_len;
2469         }
2470 }
2471
2472 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2473         unsigned int chanspec[], unsigned int n_chans, int timed)
2474 {
2475         unsigned int range;
2476         unsigned int chan;
2477         unsigned int conf;
2478         int i;
2479         int invert = 0;
2480
2481         for(i = 0; i < boardtype.n_aochan; ++i)
2482         {
2483                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2484         }
2485         for(i=0;i<n_chans;i++)
2486         {
2487                 comedi_krange *krange;
2488                 chan = CR_CHAN(chanspec[i]);
2489                 range = CR_RANGE(chanspec[i]);
2490                 krange = s->range_table->range + range;
2491                 invert = 0;
2492                 conf = 0;
2493                 switch(krange->max - krange->min)
2494                 {
2495                 case 20000000:
2496                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2497                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2498                         break;
2499                 case 10000000:
2500                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2501                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2502                         break;
2503                 case 4000000:
2504                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2505                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2506                         break;
2507                 case 2000000:
2508                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2509                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2510                         break;
2511                 default:
2512                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2513                         break;
2514                 }
2515                 switch(krange->max + krange->min)
2516                 {
2517                 case 0:
2518                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2519                         break;
2520                 case 10000000:
2521                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2522                         break;
2523                 default:
2524                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2525                         break;
2526                 }
2527                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2528                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2529                 devpriv->ao_conf[chan] = conf;
2530                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2531         }
2532         return invert;
2533 }
2534
2535 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2536         unsigned int chanspec[], unsigned int n_chans)
2537 {
2538         unsigned int range;
2539         unsigned int chan;
2540         unsigned int conf;
2541         int i;
2542         int invert = 0;
2543
2544         for(i=0;i<n_chans;i++)
2545         {
2546                 chan = CR_CHAN(chanspec[i]);
2547                 range = CR_RANGE(chanspec[i]);
2548                 conf = AO_Channel(chan);
2549
2550                 if(boardtype.ao_unipolar){
2551                         if((range&1) == 0){
2552                                 conf |= AO_Bipolar;
2553                                 invert = (1<<(boardtype.aobits-1));
2554                         }else{
2555                                 invert = 0;
2556                         }
2557                         if(range&2)
2558                                 conf |= AO_Ext_Ref;
2559                 }else{
2560                         conf |= AO_Bipolar;
2561                         invert = (1<<(boardtype.aobits-1));
2562                 }
2563
2564                 /* not all boards can deglitch, but this shouldn't hurt */
2565                 if(chanspec[i] & CR_DEGLITCH)
2566                         conf |= AO_Deglitch;
2567
2568                 /* analog reference */
2569                 /* AREF_OTHER connects AO ground to AI ground, i think */
2570                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2571
2572                 ni_writew(conf,AO_Configuration);
2573                 devpriv->ao_conf[chan] = conf;
2574         }
2575         return invert;
2576 }
2577
2578 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2579         unsigned int chanspec[], unsigned int n_chans, int timed)
2580 {
2581         if(boardtype.reg_type & ni_reg_m_series_mask)
2582                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2583         else
2584                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2585 }
2586 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2587         comedi_insn *insn,lsampl_t *data)
2588 {
2589         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2590
2591         return 1;
2592 }
2593
2594 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2595         comedi_insn *insn,lsampl_t *data)
2596 {
2597         unsigned int chan = CR_CHAN(insn->chanspec);
2598         unsigned int invert;
2599
2600         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2601
2602         devpriv->ao[chan] = data[0];
2603
2604         if(boardtype.reg_type & ni_reg_m_series_mask)
2605         {
2606                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2607         }
2608         else
2609                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2610
2611         return 1;
2612 }
2613
2614 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2615         comedi_insn *insn,lsampl_t *data)
2616 {
2617         unsigned int chan = CR_CHAN(insn->chanspec);
2618         unsigned int invert;
2619
2620         ao_win_out(1 << chan, AO_Immediate_671x);
2621         invert = 1 << (boardtype.aobits - 1);
2622
2623         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2624
2625         devpriv->ao[chan] = data[0];
2626         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2627
2628         return 1;
2629 }
2630
2631 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2632         unsigned int trignum)
2633 {
2634         int ret;
2635         int interrupt_b_bits;
2636         int i;
2637         static const int timeout = 1000;
2638
2639         if(trignum!=0) return -EINVAL;
2640
2641         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2642         interrupt_b_bits = AO_Error_Interrupt_Enable;
2643 #ifdef PCIDMA
2644         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2645         if(boardtype.reg_type & ni_reg_6xxx_mask)
2646                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2647         ret = ni_ao_setup_MITE_dma(dev);
2648         if(ret) return ret;
2649         ret = ni_ao_wait_for_dma_load(dev);
2650         if(ret < 0) return ret;
2651
2652 #else
2653         ret = ni_ao_prep_fifo(dev,s);
2654         if(ret==0)return -EPIPE;
2655
2656         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2657 #endif
2658
2659         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2660         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2661         /* wait for DACs to be loaded */
2662         for(i = 0; i < timeout; i++)
2663         {
2664                 comedi_udelay(1);
2665                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2666                         break;
2667         }
2668         if(i == timeout)
2669         {
2670                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2671                 return -EIO;
2672         }
2673         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2674         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2675
2676         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2677
2678         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2679                 AO_Command_1_Register);
2680
2681         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2682
2683         s->async->inttrig=NULL;
2684
2685         return 0;
2686 }
2687
2688 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2689 {
2690         const comedi_cmd *cmd = &s->async->cmd;
2691         int trigvar;
2692         int bits;
2693         int i;
2694
2695         if(dev->irq == 0)
2696         {
2697                 comedi_error(dev, "cannot run command without an irq");
2698                 return -EIO;
2699         }
2700         trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2701
2702         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2703
2704         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2705
2706         if(boardtype.reg_type & ni_reg_6xxx_mask)
2707         {
2708                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2709
2710                 bits = 0;
2711                 for(i = 0; i < cmd->chanlist_len; i++)
2712                 {
2713                         int chan;
2714
2715                         chan = CR_CHAN(cmd->chanlist[i]);
2716                         bits |= 1 << chan;
2717                         ao_win_out(chan, AO_Waveform_Generation_611x);
2718                 }
2719                 ao_win_out(bits, AO_Timed_611x);
2720         }
2721
2722         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2723
2724         if(cmd->stop_src==TRIG_NONE){
2725                 devpriv->ao_mode1|=AO_Continuous;
2726                 devpriv->ao_mode1&=~AO_Trigger_Once;
2727         }else{
2728                 devpriv->ao_mode1&=~AO_Continuous;
2729                 devpriv->ao_mode1|=AO_Trigger_Once;
2730         }
2731         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2732         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2733         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2734         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2735         devpriv->ao_mode3&=~AO_Trigger_Length;
2736         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2737
2738         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2739         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2740         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2741         if(cmd->stop_src==TRIG_NONE){
2742                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2743         }else{
2744                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2745         }
2746         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2747         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2748         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2749         switch(cmd->stop_src){
2750         case TRIG_COUNT:
2751                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2752                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2753                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2754                 break;
2755         case TRIG_NONE:
2756                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2757                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2758                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2759                 break;
2760         default:
2761                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2762                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2763                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2764         }
2765
2766         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2767         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2768         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2769         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2770         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2771         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2772         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2773         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2774         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2775
2776         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2777                 if(cmd->scan_end_arg>1){
2778                         devpriv->ao_mode1|=AO_Multiple_Channels;
2779                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2780                                 AO_UPDATE_Output_Select(AO_Update_Output_High_Z),
2781                                 AO_Output_Control_Register);
2782                 }else{
2783                         unsigned bits;
2784                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2785                         bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
2786                         if(boardtype.reg_type & ni_reg_m_series_mask)
2787                         {
2788                                 bits |= AO_Number_Of_Channels(0);
2789                         }else
2790                         {
2791                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2792                         }
2793                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2794                 }
2795                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2796         }
2797
2798         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2799
2800         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2801         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2802
2803         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
2804 #ifdef PCIDMA
2805         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2806 #else
2807         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2808 #endif
2809         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2810         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2811
2812         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2813                 AO_TMRDACWR_Pulse_Width;
2814         if( boardtype.ao_fifo_depth )
2815                 bits |= AO_FIFO_Enable;
2816         else
2817                 bits |= AO_DMA_PIO_Control;
2818 #if 0
2819         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
2820         verified with bus analyzer. */
2821         if(boardtype.reg_type & ni_reg_m_series_mask)
2822                 bits |= AO_Number_Of_DAC_Packages;
2823 #endif
2824         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2825         // enable sending of ao dma requests
2826         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2827
2828         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2829
2830         if(cmd->stop_src==TRIG_COUNT) {
2831                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2832                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2833                         AO_BC_TC_Interrupt_Enable, 1);
2834         }
2835
2836         s->async->inttrig=ni_ao_inttrig;
2837
2838         return 0;
2839 }
2840
2841 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2842 {
2843         int err=0;
2844         int tmp;
2845
2846         /* step 1: make sure trigger sources are trivially valid */
2847
2848         tmp=cmd->start_src;
2849         cmd->start_src &= TRIG_INT;
2850         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2851
2852         tmp=cmd->scan_begin_src;
2853         cmd->scan_begin_src &= TRIG_TIMER;
2854         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2855
2856         tmp=cmd->convert_src;
2857         cmd->convert_src &= TRIG_NOW;
2858         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2859
2860         tmp=cmd->scan_end_src;
2861         cmd->scan_end_src &= TRIG_COUNT;
2862         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2863
2864         tmp=cmd->stop_src;
2865         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2866         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2867
2868         if(err)return 1;
2869
2870         /* step 2: make sure trigger sources are unique and mutually compatible */
2871
2872         if(cmd->stop_src!=TRIG_COUNT &&
2873            cmd->stop_src!=TRIG_NONE)err++;
2874
2875         if(err)return 2;
2876
2877         /* step 3: make sure arguments are trivially compatible */
2878
2879         if(cmd->start_arg!=0){
2880                 cmd->start_arg=0;
2881                 err++;
2882         }
2883         if(cmd->scan_begin_arg < boardtype.ao_speed){
2884                 cmd->scan_begin_arg = boardtype.ao_speed;
2885                 err++;
2886         }
2887         if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){ /* XXX check */
2888                 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2889                 err++;
2890         }
2891         if(cmd->convert_arg!=0){
2892                 cmd->convert_arg=0;
2893                 err++;
2894         }
2895         if(cmd->scan_end_arg!=cmd->chanlist_len){
2896                 cmd->scan_end_arg=cmd->chanlist_len;
2897                 err++;
2898         }
2899         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2900                 if(cmd->stop_arg>0x00ffffff){
2901                         cmd->stop_arg=0x00ffffff;
2902                         err++;
2903                 }
2904         }else{
2905                 /* TRIG_NONE */
2906                 if(cmd->stop_arg!=0){
2907                         cmd->stop_arg=0;
2908                         err++;
2909                 }
2910         }
2911
2912         if(err)return 3;
2913
2914         /* step 4: fix up any arguments */
2915
2916         tmp = cmd->scan_begin_arg;
2917         cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK));
2918         if(tmp!=cmd->scan_begin_arg)err++;
2919
2920         if(err)return 4;
2921
2922         /* step 5: fix up chanlist */
2923
2924         if(err)return 5;
2925
2926         return 0;
2927 }
2928
2929
2930 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2931 {
2932         //devpriv->ao0p=0x0000;
2933         //ni_writew(devpriv->ao0p,AO_Configuration);
2934
2935         //devpriv->ao1p=AO_Channel(1);
2936         //ni_writew(devpriv->ao1p,AO_Configuration);
2937
2938         ni_release_ao_mite_channel(dev);
2939
2940         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2941         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2942         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2943         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2944         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2945         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2946                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2947         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2948         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2949         devpriv->ao_cmd1=0;
2950         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2951         devpriv->ao_cmd2=0;
2952         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
2953         devpriv->ao_mode1=0;
2954         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
2955         devpriv->ao_mode2=0;
2956         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
2957         if(boardtype.reg_type & ni_reg_m_series_mask)
2958                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2959         else
2960                 devpriv->ao_mode3 = 0;
2961         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2962         devpriv->ao_trigger_select = 0;
2963         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2964         if(boardtype.reg_type & ni_reg_6xxx_mask){
2965                 ao_win_out(0x3, AO_Immediate_671x);
2966                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2967         }
2968         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2969
2970         return 0;
2971 }
2972
2973 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2974         comedi_insn *insn,lsampl_t *data)
2975 {
2976 #ifdef DEBUG_DIO
2977         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2978                 CR_CHAN(insn->chanspec),data[0]);
2979 #endif
2980         switch(data[0]){
2981         case INSN_CONFIG_DIO_OUTPUT:
2982                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2983                 break;
2984         case INSN_CONFIG_DIO_INPUT:
2985                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2986                 break;
2987         case INSN_CONFIG_DIO_QUERY:
2988                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2989                 return insn->n;
2990                 break;
2991         default:
2992                 return -EINVAL;
2993         }
2994
2995         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2996         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2997         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2998
2999         return 1;
3000 }
3001
3002 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3003         comedi_insn *insn,lsampl_t *data)
3004 {
3005 #ifdef DEBUG_DIO
3006         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3007 #endif
3008         if(insn->n!=2)return -EINVAL;
3009         if(data[0]){
3010                 /* Perform check to make sure we're not using the
3011                    serial part of the dio */
3012                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3013                         return -EBUSY;
3014
3015                 s->state &= ~data[0];
3016                 s->state |= (data[0]&data[1]);
3017                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3018                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3019                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3020         }
3021         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3022
3023         return 2;
3024 }
3025
3026 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
3027         comedi_insn *insn, lsampl_t *data)
3028 {
3029 #ifdef DEBUG_DIO
3030         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3031                 CR_CHAN(insn->chanspec), data[0]);
3032 #endif
3033         switch(data[0])
3034         {
3035         case INSN_CONFIG_DIO_OUTPUT:
3036                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3037                 break;
3038         case INSN_CONFIG_DIO_INPUT:
3039                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3040                 break;
3041         case INSN_CONFIG_DIO_QUERY:
3042                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
3043                 return insn->n;
3044                 break;
3045         default:
3046                 return -EINVAL;
3047         }
3048
3049         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3050
3051         return 1;
3052 }
3053
3054 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
3055         comedi_insn *insn, lsampl_t *data)
3056 {
3057 #ifdef DEBUG_DIO
3058         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
3059 #endif
3060         if(insn->n!=2)return -EINVAL;
3061         if(data[0]){
3062                 s->state &= ~data[0];
3063                 s->state |= (data[0] & data[1]);
3064                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3065         }
3066         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3067
3068         return 2;
3069 }
3070
3071 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
3072                                  comedi_insn *insn,lsampl_t *data)
3073 {
3074         int err = insn->n;
3075         unsigned char byte_out, byte_in;
3076
3077         if(insn->n!=2)return -EINVAL;
3078
3079         switch(data[0]) {
3080         case INSN_CONFIG_SERIAL_CLOCK:
3081
3082 #ifdef DEBUG_DIO
3083                 rt_printk("SPI serial clock Config cd\n", data[1]);
3084 #endif
3085                 devpriv->serial_hw_mode = 1;
3086                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3087
3088                 if(data[1] == SERIAL_DISABLED) {
3089                         devpriv->serial_hw_mode = 0;
3090                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3091                                                   DIO_Software_Serial_Control);
3092                         data[1] = SERIAL_DISABLED;
3093                         devpriv->serial_interval_ns = data[1];
3094                 }
3095                 else if(data[1] <= SERIAL_600NS) {
3096                         /* Warning: this clock speed is too fast to reliably
3097                         control SCXI. */
3098                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3099                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3100                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3101                         data[1] = SERIAL_600NS;
3102                         devpriv->serial_interval_ns = data[1];
3103                 }
3104                 else if(data[1] <= SERIAL_1_2US) {
3105                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3106                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3107                                 DIO_Serial_Out_Divide_By_2;
3108                         data[1] = SERIAL_1_2US;
3109                         devpriv->serial_interval_ns = data[1];
3110                 }
3111                 else if(data[1] <= SERIAL_10US) {
3112                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3113                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3114                                 DIO_Serial_Out_Divide_By_2;
3115                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3116                         600ns/1.2us. If you turn divide_by_2 off with the
3117                         slow clock, you will still get 10us, except then
3118                         all your delays are wrong. */
3119                         data[1] = SERIAL_10US;
3120                         devpriv->serial_interval_ns = data[1];
3121                 }
3122                 else {
3123                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3124                                                   DIO_Software_Serial_Control);
3125                         devpriv->serial_hw_mode = 0;
3126                         data[1] = (data[1] / 1000) * 1000;
3127                         devpriv->serial_interval_ns = data[1];
3128                 }
3129
3130                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3131                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
3132                 return 1;
3133
3134         break;
3135
3136         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3137
3138                 if(devpriv->serial_interval_ns == 0) {
3139                         return -EINVAL;
3140                 }
3141
3142                 byte_out = data[1] & 0xFF;
3143
3144                 if(devpriv->serial_hw_mode) {
3145                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
3146                 } else if(devpriv->serial_interval_ns > 0) {
3147                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
3148                 } else {
3149                         rt_printk("ni_serial_insn_config: serial disabled!\n");
3150                         return -EINVAL;
3151                 }
3152                 if(err < 0) return err;
3153                 data[1] = byte_in & 0xFF;
3154                 return insn->n;
3155
3156         break;
3157         default:
3158                 return -EINVAL;
3159         }
3160
3161 }
3162
3163 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3164                                    unsigned char data_out,
3165                                    unsigned char *data_in)
3166 {
3167         unsigned int status1;
3168         int err = 0, count = 20;
3169
3170 #ifdef DEBUG_DIO
3171         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3172 #endif
3173
3174         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3175         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3176         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3177
3178         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3179         if(status1 & DIO_Serial_IO_In_Progress_St) {
3180                 err = -EBUSY;
3181                 goto Error;
3182         }
3183
3184         devpriv->dio_control |= DIO_HW_Serial_Start;
3185         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3186         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3187
3188         /* Wait until STC says we're done, but don't loop infinitely. */
3189         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3190                 /* Delay one bit per loop */
3191                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3192                 if(--count < 0) {
3193                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3194                         err = -ETIME;
3195                         goto Error;
3196                 }
3197         }
3198
3199         /* Delay for last bit. This delay is absolutely necessary, because
3200            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3201         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3202
3203         if(data_in != NULL) {
3204                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3205 #ifdef DEBUG_DIO
3206                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3207 #endif
3208         }
3209
3210  Error:
3211         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3212
3213         return err;
3214 }
3215
3216 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3217                                    unsigned char data_out,
3218                                    unsigned char *data_in)
3219 {
3220         unsigned char mask, input = 0;
3221
3222 #ifdef DEBUG_DIO
3223         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3224 #endif
3225
3226         /* Wait for one bit before transfer */
3227         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3228
3229         for(mask = 0x80; mask; mask >>= 1) {
3230                 /* Output current bit; note that we cannot touch s->state
3231            because it is a per-subdevice field, and serial is
3232                    a separate subdevice from DIO. */
3233                 devpriv->dio_output &= ~DIO_SDOUT;
3234                 if(data_out & mask) {
3235                         devpriv->dio_output |= DIO_SDOUT;
3236                 }
3237                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3238
3239                 /* Assert SDCLK (active low, inverted), wait for half of
3240                    the delay, deassert SDCLK, and wait for the other half. */
3241                 devpriv->dio_control |= DIO_Software_Serial_Control;
3242                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3243
3244                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3245
3246                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3247                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3248
3249                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3250
3251                 /* Input current bit */
3252                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3253 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3254                         input |= mask;
3255                 }
3256         }
3257 #ifdef DEBUG_DIO
3258         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3259 #endif
3260         if(data_in) *data_in = input;
3261
3262         return 0;
3263 }
3264
3265 static void mio_common_detach(comedi_device *dev)
3266 {
3267         if(dev->subdevices && boardtype.has_8255)
3268                 subdev_8255_cleanup(dev,dev->subdevices+3);
3269 }
3270
3271 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3272 {
3273         int i;
3274
3275         for(i = 0; i < s->n_chan; i++)
3276                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3277 }
3278
3279 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3280 {
3281         unsigned stc_register;
3282         switch(reg)
3283         {
3284         case NITIO_G0_Autoincrement_Reg:
3285                 stc_register = G_Autoincrement_Register(0);
3286                 break;
3287         case NITIO_G1_Autoincrement_Reg:
3288                 stc_register = G_Autoincrement_Register(1);
3289                 break;
3290         case NITIO_G0_Command_Reg:
3291                 stc_register = G_Command_Register(0);
3292                 break;
3293         case NITIO_G1_Command_Reg:
3294                 stc_register = G_Command_Register(1);
3295                 break;
3296         case NITIO_G0_HW_Save_Reg:
3297                 stc_register = G_HW_Save_Register(0);
3298                 break;
3299         case NITIO_G1_HW_Save_Reg:
3300                 stc_register = G_HW_Save_Register(1);
3301                 break;
3302         case NITIO_G0_SW_Save_Reg:
3303                 stc_register = G_Save_Register(0);
3304                 break;
3305         case NITIO_G1_SW_Save_Reg:
3306                 stc_register = G_Save_Register(1);
3307                 break;
3308         case NITIO_G0_Mode_Reg:
3309                 stc_register = G_Mode_Register(0);
3310                 break;
3311         case NITIO_G1_Mode_Reg:
3312                 stc_register = G_Mode_Register(1);
3313                 break;
3314         case NITIO_G0_LoadA_Reg:
3315                 stc_register = G_Load_A_Register(0);
3316                 break;
3317         case NITIO_G1_LoadA_Reg:
3318                 stc_register = G_Load_A_Register(1);
3319                 break;
3320         case NITIO_G0_LoadB_Reg:
3321                 stc_register = G_Load_B_Register(0);
3322                 break;
3323         case NITIO_G1_LoadB_Reg:
3324                 stc_register = G_Load_B_Register(1);
3325                 break;
3326         case NITIO_G0_Input_Select_Reg:
3327                 stc_register = G_Input_Select_Register(0);
3328                 break;
3329         case NITIO_G1_Input_Select_Reg:
3330                 stc_register = G_Input_Select_Register(1);
3331                 break;
3332         case NITIO_G01_Status_Reg:
3333                 stc_register = G_Status_Register;
3334                 break;
3335         case NITIO_G01_Joint_Reset_Reg:
3336                 stc_register = Joint_Reset_Register;
3337                 break;
3338         case NITIO_G01_Joint_Status1_Reg:
3339                 stc_register = Joint_Status_1_Register;
3340                 break;
3341         case NITIO_G01_Joint_Status2_Reg:
3342                 stc_register = Joint_Status_2_Register;
3343                 break;
3344         default:
3345                 rt_printk("%s: unhandled register 0x%x in switch.\n", __FUNCTION__, reg);
3346                 BUG();
3347                 return 0;
3348                 break;
3349         }
3350         return stc_register;
3351 }
3352
3353 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg)
3354 {
3355         comedi_device *dev = counter->dev;
3356         unsigned stc_register;
3357         /* bits in the join reset register which are relevant to counters */
3358         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3359         switch(reg)
3360         {
3361         /* m-series-only registers */
3362         case NITIO_G0_Counting_Mode_Reg:
3363                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3364                 break;
3365         case NITIO_G1_Counting_Mode_Reg:
3366                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3367                 break;
3368         case NITIO_G0_Second_Gate_Reg:
3369                 ni_writew(bits, M_Offset_G0_Second_Gate);
3370                 break;
3371         case NITIO_G1_Second_Gate_Reg:
3372                 ni_writew(bits, M_Offset_G1_Second_Gate);
3373                 break;
3374         /* 32 bit registers */
3375         case NITIO_G0_LoadA_Reg:
3376         case NITIO_G1_LoadA_Reg:
3377         case NITIO_G0_LoadB_Reg:
3378         case NITIO_G1_LoadB_Reg:
3379                 stc_register = ni_gpct_to_stc_register(reg);
3380                 devpriv->stc_writel(dev, bits, stc_register);
3381                 break;
3382         /* 16 bit registers */
3383         case NITIO_G01_Joint_Reset_Reg:
3384                 BUG_ON(bits & ~gpct_joint_reset_mask);
3385                 /* fall-through */
3386         default:
3387                 stc_register = ni_gpct_to_stc_register(reg);
3388                 devpriv->stc_writew(dev, bits, stc_register);
3389         }
3390 }
3391
3392 static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg)
3393 {
3394         comedi_device *dev = counter->dev;
3395         unsigned stc_register;
3396         switch(reg)
3397         {
3398         /* 32 bit registers */
3399         case NITIO_G0_HW_Save_Reg:
3400         case NITIO_G1_HW_Save_Reg:
3401         case NITIO_G0_SW_Save_Reg:
3402         case NITIO_G1_SW_Save_Reg:
3403                 stc_register = ni_gpct_to_stc_register(reg);
3404                 return devpriv->stc_readl(dev, stc_register);
3405                 break;
3406         /* 16 bit registers */
3407         default:
3408                 stc_register = ni_gpct_to_stc_register(reg);
3409                 return devpriv->stc_readw(dev, stc_register);
3410                 break;
3411         }
3412         return 0;
3413 }
3414
3415 static int ni_alloc_private(comedi_device *dev)
3416 {
3417         int ret;
3418
3419         ret = alloc_private(dev, sizeof(ni_private));
3420         if(ret < 0) return ret;
3421
3422         spin_lock_init(&devpriv->window_lock);
3423         spin_lock_init(&devpriv->soft_reg_copy_lock);
3424         spin_lock_init(&devpriv->mite_channel_lock);
3425
3426         return 0;
3427 };
3428
3429 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3430 {
3431         comedi_subdevice *s;
3432         unsigned j;
3433
3434         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3435         {
3436                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3437                 return -EINVAL;
3438         }
3439
3440         if(alloc_subdevices(dev, 11 + NUM_GPCT) < 0)
3441                 return -ENOMEM;
3442
3443         /* analog input subdevice */
3444
3445         s=dev->subdevices+0;
3446         dev->read_subdev=s;
3447         if(boardtype.n_adchan){
3448                 s->type=COMEDI_SUBD_AI;
3449                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
3450                 if(boardtype.reg_type != ni_reg_611x)
3451                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3452                 if(boardtype.adbits > 16)
3453                         s->subdev_flags |= SDF_LSAMPL;
3454                 if(boardtype.reg_type & ni_reg_m_series_mask)
3455                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3456                 s->n_chan=boardtype.n_adchan;
3457                 s->len_chanlist=512;
3458                 s->maxdata=(1<<boardtype.adbits)-1;
3459                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3460                 s->insn_read = &ni_ai_insn_read;
3461                 s->insn_config = &ni_ai_insn_config;
3462                 s->do_cmdtest = &ni_ai_cmdtest;
3463                 s->do_cmd = &ni_ai_cmd;
3464                 s->cancel = &ni_ai_reset;
3465                 s->poll = &ni_ai_poll;
3466                 s->munge = &ni_ai_munge;
3467 #ifdef PCIDMA
3468                 s->async_dma_dir = DMA_FROM_DEVICE;
3469 #endif
3470         }else{
3471                 s->type=COMEDI_SUBD_UNUSED;
3472         }
3473
3474         /* analog output subdevice */
3475
3476         s = dev->subdevices + 1;
3477         if(boardtype.n_aochan){
3478                 s->type = COMEDI_SUBD_AO;
3479                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
3480                 if(boardtype.reg_type & ni_reg_m_series_mask)
3481                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3482                 s->n_chan = boardtype.n_aochan;
3483                 s->maxdata = (1 << boardtype.aobits) - 1;
3484                 s->range_table = boardtype.ao_range_table;
3485                 s->insn_read = &ni_ao_insn_read;
3486                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3487                         s->insn_write = &ni_ao_insn_write_671x;
3488                 }else{
3489                         s->insn_write = &ni_ao_insn_write;
3490                 }
3491 #ifdef PCIDMA
3492                 if(boardtype.n_aochan){
3493                         s->async_dma_dir = DMA_TO_DEVICE;
3494 #else
3495                 if(boardtype.ao_fifo_depth){
3496 #endif
3497                         dev->write_subdev=s;
3498                         s->subdev_flags |= SDF_CMD_WRITE;
3499                         s->do_cmd = &ni_ao_cmd;
3500                         s->do_cmdtest = &ni_ao_cmdtest;
3501                         s->len_chanlist = boardtype.n_aochan;
3502                         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
3503                                 s->munge=ni_ao_munge;
3504                 }
3505                 s->cancel = &ni_ao_reset;
3506         }else{
3507                 s->type = COMEDI_SUBD_UNUSED;
3508         }
3509         if((boardtype.reg_type & ni_reg_67xx_mask))
3510                 init_ao_67xx(dev, s);
3511
3512         /* digital i/o subdevice */
3513
3514         s=dev->subdevices+2;
3515         s->type=COMEDI_SUBD_DIO;
3516         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3517         s->maxdata=1;
3518         s->io_bits=0;           /* all bits input */
3519         s->range_table=&range_digital;
3520         s->n_chan = boardtype.num_p0_dio_channels;
3521         if(boardtype.reg_type & ni_reg_m_series_mask)
3522         {
3523                 s->insn_bits = ni_m_series_dio_insn_bits;
3524                 s->insn_config=ni_m_series_dio_insn_config;
3525                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3526         }else
3527         {
3528                 s->insn_bits=ni_dio_insn_bits;
3529                 s->insn_config=ni_dio_insn_config;
3530                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3531                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3532         }
3533
3534         /* 8255 device */
3535         s=dev->subdevices+3;
3536         if(boardtype.has_8255){
3537                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3538         }else{
3539                 s->type=COMEDI_SUBD_UNUSED;
3540         }
3541
3542         /* formerly general purpose counter/timer device, but no longer used */
3543         s=dev->subdevices+4;
3544         s->type = COMEDI_SUBD_UNUSED;
3545
3546         /* calibration subdevice -- ai and ao */
3547         s=dev->subdevices+5;
3548         s->type=COMEDI_SUBD_CALIB;
3549         if(boardtype.reg_type & ni_reg_m_series_mask)
3550         {
3551                 // internal PWM analog output used for AI nonlinearity calibration
3552                 s->subdev_flags = SDF_INTERNAL;
3553                 s->insn_config = &ni_m_series_pwm_config;
3554                 s->n_chan = 1;
3555                 s->maxdata = 0;
3556                 ni_writel(0x0, M_Offset_Cal_PWM);
3557         } else if(boardtype.reg_type == ni_reg_6143)
3558         {
3559                 // internal PWM analog output used for AI nonlinearity calibration
3560                 s->subdev_flags = SDF_INTERNAL;
3561                 s->insn_config = &ni_6143_pwm_config;
3562                 s->n_chan = 1;
3563                 s->maxdata = 0;
3564         }else
3565         {
3566                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3567                 s->insn_read = &ni_calib_insn_read;
3568                 s->insn_write = &ni_calib_insn_write;
3569                 caldac_setup(dev, s);
3570         }
3571
3572         /* EEPROM */
3573         s=dev->subdevices+6;
3574         s->type=COMEDI_SUBD_MEMORY;
3575         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3576         s->maxdata=0xff;
3577         if(boardtype.reg_type & ni_reg_m_series_mask)
3578         {
3579                 s->n_chan = M_SERIES_EEPROM_SIZE;
3580                 s->insn_read = &ni_m_series_eeprom_insn_read;
3581         }else
3582         {
3583                 s->n_chan = 512;
3584                 s->insn_read = &ni_eeprom_insn_read;
3585         }
3586         /* PFI */
3587         s=dev->subdevices + 7;
3588         s->type = COMEDI_SUBD_DIO;
3589         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3590         if(boardtype.reg_type & ni_reg_m_series_mask)
3591         {
3592                 unsigned i;
3593                 s->n_chan = 16;
3594                 ni_writew(s->state, M_Offset_PFI_DO);
3595                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3596                 {
3597                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3598                 }
3599         }else
3600         {
3601                 s->n_chan = 10;
3602         }
3603         s->maxdata = 1;
3604         s->insn_bits = ni_pfi_insn_bits;
3605         s->insn_config = ni_pfi_insn_config;
3606         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3607
3608         /* cs5529 calibration adc */
3609         s = dev->subdevices + 8;
3610         if(boardtype.reg_type & ni_reg_67xx_mask)
3611         {
3612                 s->type = COMEDI_SUBD_AI;
3613                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3614                 // one channel for each analog output channel
3615                 s->n_chan = boardtype.n_aochan;
3616                 s->maxdata = (1 << 16) - 1;
3617                 s->range_table = &range_unknown; /* XXX */
3618                 s->insn_read=cs5529_ai_insn_read;
3619                 s->insn_config=NULL;
3620                 init_cs5529(dev);
3621         }else
3622         {
3623                 s->type=COMEDI_SUBD_UNUSED;
3624         }
3625
3626         /* Serial */
3627         s=dev->subdevices+9;
3628         s->type=COMEDI_SUBD_SERIAL;
3629         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3630         s->n_chan=1;
3631         s->maxdata=0xff;
3632         s->insn_config = ni_serial_insn_config;
3633         devpriv->serial_interval_ns = 0;
3634         devpriv->serial_hw_mode = 0;
3635
3636         /* RTSI */
3637         s=dev->subdevices + 10;
3638         s->type = COMEDI_SUBD_DIO;
3639         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3640         s->n_chan = 8;
3641         s->maxdata = 1;
3642         s->insn_bits = ni_rtsi_insn_bits;
3643         s->insn_config = ni_rtsi_insn_config;
3644         ni_rtsi_init(dev);
3645
3646         /* General purpose counters */
3647         for(j = 0; j < NUM_GPCT; ++j)
3648         {
3649                 s = dev->subdevices + 11 + j;
3650                 s->type = COMEDI_SUBD_COUNTER;
3651                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
3652                 s->n_chan = 3;
3653                 if(boardtype.reg_type & ni_reg_m_series_mask)
3654                         s->maxdata = 0xffffffff;
3655                 else
3656                         s->maxdata = 0xffffff;
3657                 s->insn_read = ni_gpct_insn_read;
3658                 s->insn_write = ni_gpct_insn_write;
3659                 s->insn_config = ni_gpct_insn_config;
3660                 s->do_cmd = ni_gpct_cmd;
3661                 s->do_cmdtest = ni_gpct_cmdtest;
3662                 s->cancel = ni_gpct_cancel;
3663                 s->async_dma_dir = DMA_BIDIRECTIONAL;
3664                 s->private = &devpriv->counters[j];
3665
3666                 devpriv->counters[j].dev = dev;
3667                 devpriv->counters[j].chip_index = 0;
3668                 devpriv->counters[j].counter_index = j;
3669                 devpriv->counters[j].write_register = ni_gpct_write_register;
3670                 devpriv->counters[j].read_register = ni_gpct_read_register;
3671                 if(boardtype.reg_type & ni_reg_m_series_mask)
3672                 {
3673                         devpriv->counters[j].variant = ni_gpct_variant_m_series;
3674                 }else
3675                 {
3676                         devpriv->counters[j].variant = ni_gpct_variant_e_series;
3677                 }
3678                 devpriv->counters[j].clock_period_ps = 0;
3679                 devpriv->counters[j].mite_chan = NULL;
3680                 ni_tio_init_counter(&devpriv->counters[j]);
3681         }
3682
3683         /* ai configuration */
3684         ni_ai_reset(dev,dev->subdevices+0);
3685         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3686                 // BEAM is this needed for PCI-6143 ??
3687                 devpriv->clock_and_fout =
3688                         Slow_Internal_Time_Divide_By_2 |
3689                         Slow_Internal_Timebase |
3690                         Clock_To_Board_Divide_By_2 |
3691                         Clock_To_Board |
3692                         AI_Output_Divide_By_2 |
3693                         AO_Output_Divide_By_2;
3694         }else{
3695                 devpriv->clock_and_fout =
3696                         Slow_Internal_Time_Divide_By_2 |
3697                         Slow_Internal_Timebase |
3698                         Clock_To_Board_Divide_By_2 |
3699                         Clock_To_Board;
3700         }
3701         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3702
3703         /* analog output configuration */
3704         ni_ao_reset(dev,dev->subdevices + 1);
3705
3706         if(dev->irq){
3707                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3708                         (Interrupt_Output_On_3_Pins&0) |
3709                         Interrupt_A_Enable |
3710                         Interrupt_B_Enable |
3711                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3712                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3713                         Interrupt_Control_Register
3714                 );
3715         }
3716
3717         /* DMA setup */
3718         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
3719         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
3720
3721         if(boardtype.reg_type & ni_reg_6xxx_mask)
3722         {
3723                 ni_writeb( 0, Magic_611x );
3724         }else if(boardtype.reg_type & ni_reg_m_series_mask)
3725         {
3726                 int channel;
3727                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3728                 {
3729                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3730                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3731                 }
3732                 ni_writeb(0x0, M_Offset_AO_Calibration);
3733         }
3734
3735         printk("\n");
3736         return 0;
3737 }
3738
3739
3740
3741 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3742 {
3743         comedi_device *dev=(comedi_device *)arg;
3744
3745         if(dir){
3746                 ni_writeb(data,Port_A+2*port);
3747                 return 0;
3748         }else{
3749                 return ni_readb(Port_A+2*port);
3750         }
3751 }
3752
3753 /*
3754         presents the EEPROM as a subdevice
3755 */
3756
3757 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3758         comedi_insn *insn,lsampl_t *data)
3759 {
3760         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3761
3762         return 1;
3763 }
3764
3765 /*
3766         reads bytes out of eeprom
3767 */
3768
3769 static int ni_read_eeprom(comedi_device *dev,int addr)
3770 {
3771         int bit;
3772         int bitstring;
3773
3774         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3775         ni_writeb(0x04,Serial_Command);
3776         for(bit=0x8000;bit;bit>>=1){
3777                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3778                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3779         }
3780         bitstring=0;
3781         for(bit=0x80;bit;bit>>=1){
3782                 ni_writeb(0x04,Serial_Command);
3783                 ni_writeb(0x05,Serial_Command);
3784                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3785         }
3786         ni_writeb(0x00,Serial_Command);
3787
3788         return bitstring;
3789 }
3790
3791 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3792         comedi_insn *insn,lsampl_t *data)
3793 {
3794         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3795
3796         return 1;
3797 }
3798
3799 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3800 {
3801         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3802         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3803         return 3;
3804 }
3805
3806 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3807         comedi_insn *insn, lsampl_t *data)
3808 {
3809         unsigned up_count, down_count;
3810         switch(data[0])
3811         {
3812         case INSN_CONFIG_PWM_OUTPUT:
3813                 switch(data[1])
3814                 {
3815                 case TRIG_ROUND_NEAREST:
3816                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3817                         break;
3818                 case TRIG_ROUND_DOWN:
3819                         up_count = data[2] / devpriv->clock_ns;
3820                         break;
3821                 case TRIG_ROUND_UP:
3822                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3823                         break;
3824                 default:
3825                         return -EINVAL;
3826                         break;
3827                 }
3828                 switch(data[3])
3829                 {
3830                 case TRIG_ROUND_NEAREST:
3831                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3832                         break;
3833                 case TRIG_ROUND_DOWN:
3834                         down_count = data[4] / devpriv->clock_ns;
3835                         break;
3836                 case TRIG_ROUND_UP:
3837                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3838                         break;
3839                 default:
3840                         return -EINVAL;
3841                         break;
3842                 }
3843                 if(up_count * devpriv->clock_ns != data[2] ||
3844                         down_count * devpriv->clock_ns != data[4])
3845                 {
3846                         data[2] = up_count * devpriv->clock_ns;
3847                         data[4] = down_count * devpriv->clock_ns;
3848                         return -EAGAIN;
3849                 }
3850                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3851                 devpriv->pwm_up_count = up_count;
3852                 devpriv->pwm_down_count = down_count;
3853                 return 5;
3854                 break;
3855         case INSN_CONFIG_GET_PWM_OUTPUT:
3856                 return ni_get_pwm_config(dev, data);
3857                 break;
3858         default:
3859                 return -EINVAL;
3860                 break;
3861         }
3862         return 0;
3863 }
3864
3865 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3866         comedi_insn *insn, lsampl_t *data)
3867 {
3868         unsigned up_count, down_count;
3869         switch(data[0])
3870         {
3871         case INSN_CONFIG_PWM_OUTPUT:
3872                 switch(data[1])
3873                 {
3874                 case TRIG_ROUND_NEAREST:
3875                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3876                         break;
3877                 case TRIG_ROUND_DOWN:
3878                         up_count = data[2] / devpriv->clock_ns;
3879                         break;
3880                 case TRIG_ROUND_UP:
3881                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3882                         break;
3883                 default:
3884                         return -EINVAL;
3885                         break;
3886                 }
3887                 switch(data[3])
3888                 {
3889                 case TRIG_ROUND_NEAREST:
3890                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3891                         break;
3892                 case TRIG_ROUND_DOWN:
3893                         down_count = data[4] / devpriv->clock_ns;
3894                         break;
3895                 case TRIG_ROUND_UP:
3896                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3897                         break;
3898                 default:
3899                         return -EINVAL;
3900                         break;
3901                 }
3902                 if(up_count * devpriv->clock_ns != data[2] ||
3903                         down_count * devpriv->clock_ns != data[4])
3904                 {
3905                         data[2] = up_count * devpriv->clock_ns;
3906                         data[4] = down_count * devpriv->clock_ns;
3907                         return -EAGAIN;
3908                 }
3909                 ni_writel(up_count, Calibration_HighTime_6143);
3910                 devpriv->pwm_up_count = up_count;
3911                 ni_writel(down_count, Calibration_LowTime_6143);
3912                 devpriv->pwm_down_count = down_count;
3913                 return 5;
3914                 break;
3915         case INSN_CONFIG_GET_PWM_OUTPUT:
3916                 return ni_get_pwm_config(dev, data);
3917         default:
3918                 return -EINVAL;
3919                 break;
3920         }
3921         return 0;
3922 }
3923
3924 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3925 /*
3926         calibration subdevice
3927 */
3928 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3929         comedi_insn *insn,lsampl_t *data)
3930 {
3931         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3932
3933         return 1;
3934 }
3935
3936 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3937         comedi_insn *insn,lsampl_t *data)
3938 {
3939         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3940
3941         return 1;
3942 }
3943
3944 static int pack_mb88341(int addr,int val,int *bitstring);
3945 static int pack_dac8800(int addr,int val,int *bitstring);
3946 static int pack_dac8043(int addr,int val,int *bitstring);
3947 static int pack_ad8522(int addr,int val,int *bitstring);
3948 static int pack_ad8804(int addr,int val,int *bitstring);
3949 static int pack_ad8842(int addr,int val,int *bitstring);
3950
3951 struct caldac_struct{
3952         int n_chans;
3953         int n_bits;
3954         int (*packbits)(int,int,int *);
3955 };
3956
3957 static struct caldac_struct caldacs[] = {
3958         [mb88341] = { 12, 8, pack_mb88341 },
3959         [dac8800] = { 8, 8, pack_dac8800 },
3960         [dac8043] = { 1, 12, pack_dac8043 },
3961         [ad8522]  = { 2, 12, pack_ad8522 },
3962         [ad8804] = { 12, 8, pack_ad8804 },
3963         [ad8842] = { 8, 8, pack_ad8842 },
3964         [ad8804_debug] = { 16, 8, pack_ad8804 },
3965 };
3966
3967 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3968 {
3969         int i,j;
3970         int n_dacs;
3971         int n_chans=0;
3972         int n_bits;
3973         int diffbits=0;
3974         int type;
3975         int chan;
3976
3977         type = boardtype.caldac[0];
3978         if(type==caldac_none)return;
3979         n_bits=caldacs[type].n_bits;
3980         for(i=0;i<3;i++){
3981                 type = boardtype.caldac[i];
3982                 if(type==caldac_none)break;
3983                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3984                 n_chans+=caldacs[type].n_chans;
3985         }
3986         n_dacs=i;
3987         s->n_chan=n_chans;
3988
3989         if(diffbits){
3990
3991                 if(n_chans>MAX_N_CALDACS){
3992                         printk("BUG! MAX_N_CALDACS too small\n");
3993                 }
3994                 s->maxdata_list=devpriv->caldac_maxdata_list;
3995                 chan=0;
3996                 for(i=0;i<n_dacs;i++){
3997                         type = boardtype.caldac[i];
3998                         for(j=0;j<caldacs[type].n_chans;j++){
3999                                 s->maxdata_list[chan]=
4000                                         (1<<caldacs[type].n_bits)-1;
4001                                 chan++;
4002                         }
4003                 }
4004
4005                 for( chan = 0; chan < s->n_chan; chan++ )
4006                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
4007         }else{
4008                 type = boardtype.caldac[0];
4009                 s->maxdata=(1<<caldacs[type].n_bits)-1;
4010
4011                 for( chan = 0; chan < s->n_chan; chan++ )
4012                         ni_write_caldac( dev, i, s->maxdata / 2 );
4013         }
4014 }
4015
4016 static void ni_write_caldac(comedi_device *dev,int addr,int val)
4017 {
4018         unsigned int loadbit=0,bits=0,bit,bitstring=0;
4019         int i;
4020         int type;
4021
4022         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4023         if( devpriv->caldacs[ addr ] == val ) return;
4024         devpriv->caldacs[ addr ] = val;
4025
4026         for(i=0;i<3;i++){
4027                 type = boardtype.caldac[i];
4028                 if(type==caldac_none)break;
4029                 if(addr<caldacs[type].n_chans){
4030                         bits=caldacs[type].packbits(addr,val,&bitstring);
4031                         loadbit=SerDacLd(i);
4032                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4033                         break;
4034                 }
4035                 addr-=caldacs[type].n_chans;
4036         }
4037
4038         for(bit=1<<(bits-1);bit;bit>>=1){
4039                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
4040                 comedi_udelay(1);
4041                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
4042                 comedi_udelay(1);
4043         }
4044         ni_writeb(loadbit,Serial_Command);
4045         comedi_udelay(1);
4046         ni_writeb(0,Serial_Command);
4047 }
4048
4049
4050
4051 static int pack_mb88341(int addr,int val,int *bitstring)
4052 {
4053         /*
4054            Fujitsu MB 88341
4055            Note that address bits are reversed.  Thanks to
4056            Ingo Keen for noticing this.
4057
4058            Note also that the 88341 expects address values from
4059            1-12, whereas we use channel numbers 0-11.  The NI
4060            docs use 1-12, also, so be careful here.
4061         */
4062         addr++;
4063         *bitstring=((addr&0x1)<<11) |
4064                   ((addr&0x2)<<9)  |
4065                   ((addr&0x4)<<7)  |
4066                   ((addr&0x8)<<5)  |
4067                   (val&0xff);
4068         return 12;
4069 }
4070
4071 static int pack_dac8800(int addr,int val,int *bitstring)
4072 {
4073         *bitstring=((addr&0x7)<<8)|(val&0xff);
4074         return 11;
4075 }
4076
4077 static int pack_dac8043(int addr,int val,int *bitstring)
4078 {
4079         *bitstring=val&0xfff;
4080         return 12;
4081 }
4082
4083 static int pack_ad8522(int addr,int val,int *bitstring)
4084 {
4085         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
4086         return 16;
4087 }
4088
4089 static int pack_ad8804(int addr,int val,int *bitstring)
4090 {
4091         *bitstring=((addr&0xf)<<8) | (val&0xff);
4092         return 12;
4093 }
4094
4095 static int pack_ad8842(int addr,int val,int *bitstring)
4096 {
4097         *bitstring=((addr+1)<<8) | (val&0xff);
4098         return 12;
4099 }
4100
4101
4102 #if 0
4103 /*
4104  *      Read the GPCTs current value.
4105  */
4106 static int GPCT_G_Watch(comedi_device *dev, int chan)
4107 {
4108         unsigned int hi1,hi2,lo;
4109
4110         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4111         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4112
4113         devpriv->gpct_command[chan] |= G_Save_Trace;
4114         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
4115
4116         /* This procedure is used because the two registers cannot
4117          * be read atomically. */
4118         do{
4119                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4120                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4121                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
4122         }while(hi1!=hi2);
4123
4124         return (hi1<<16)|lo;
4125 }
4126
4127 static void GPCT_Reset(comedi_device *dev, int chan)
4128 {
4129         int temp_ack_reg=0;
4130
4131         //printk("GPCT_Reset...");
4132         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4133
4134         switch (chan) {
4135                 case 0:
4136                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4137                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4138                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4139                         temp_ack_reg |= G0_Gate_Error_Confirm;
4140                         temp_ack_reg |= G0_TC_Error_Confirm;
4141                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4142                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4143                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4144
4145                         //problem...this interferes with the other ctr...
4146                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4147                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4148                         break;
4149                 case 1:
4150                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4151                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4152                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4153                         temp_ack_reg |= G1_Gate_Error_Confirm;
4154                         temp_ack_reg |= G1_TC_Error_Confirm;
4155                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4156                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4157                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4158
4159                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4160                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4161                         break;
4162         };
4163
4164         devpriv->gpct_mode[chan] = 0;
4165         devpriv->gpct_input_select[chan] = 0;
4166         devpriv->gpct_command[chan] = 0;
4167
4168         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4169
4170         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4171         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4172         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4173
4174         //printk("exit GPCT_Reset\n");
4175 }
4176
4177 #endif
4178
4179 static int ni_gpct_insn_config(comedi_device *dev, comedi_subdevice *s,
4180         comedi_insn *insn, lsampl_t *data)
4181 {
4182         struct ni_gpct *counter = s->private;
4183         return ni_tio_insn_config(counter, insn, data);
4184 }
4185
4186 static int ni_gpct_insn_read(comedi_device *dev, comedi_subdevice *s,
4187         comedi_insn *insn,lsampl_t *data)
4188 {
4189         struct ni_gpct *counter = s->private;
4190         return ni_tio_rinsn(counter, insn, data);
4191 }
4192
4193 static int ni_gpct_insn_write(comedi_device *dev, comedi_subdevice *s,
4194         comedi_insn *insn, lsampl_t *data)
4195 {
4196         struct ni_gpct *counter = s->private;
4197         return ni_tio_winsn(counter, insn, data);
4198 }
4199
4200 static int ni_gpct_cmd(comedi_device *dev, comedi_subdevice *s)
4201 {
4202 // XXX set M_Offset_GX_DMA_Config for m-series
4203 #ifdef PCIDMA
4204         struct ni_gpct *counter = s->private;
4205         const comedi_cmd *cmd = &s->async->cmd;
4206         int retval = ni_request_gpct_mite_channel(dev, counter->counter_index);
4207         if(retval)
4208         {
4209                 comedi_error(dev, "no dma channel available for use by counter");
4210                 return retval;
4211         }
4212         return ni_tio_cmd(counter, s->async);
4213 #else
4214         return -ENOTSUPP;
4215 #endif
4216 }
4217
4218 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
4219 {
4220         struct ni_gpct *counter = s->private;
4221         //XXX check chanlist_len == 1
4222         return ni_tio_cmdtest(counter);
4223 }
4224
4225 static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s)
4226 {
4227         struct ni_gpct *counter = s->private;
4228         int retval = ni_tio_cancel(counter);
4229         ni_release_gpct_mite_channel(dev, counter->counter_index);
4230         return retval;
4231 }
4232
4233 /*
4234  *
4235  *  Programmable Function Inputs
4236  *
4237  */
4238
4239 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4240 {
4241         unsigned pfi_reg_index;
4242         unsigned array_offset;
4243         if((source & 0x1f) != source) return -EINVAL;
4244         pfi_reg_index = 1 + chan / 3;
4245         array_offset = pfi_reg_index - 1;
4246         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4247         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4248         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4249         return 2;
4250 }
4251
4252 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4253 {
4254         // pre-m-series boards have fixed signals on pfi pins
4255         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4256         return 2;
4257 }
4258
4259 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4260 {
4261         if(boardtype.reg_type & ni_reg_m_series_mask)
4262                 return ni_m_series_set_pfi_routing(dev, chan, source);
4263         else
4264                 return ni_old_set_pfi_routing(dev, chan, source);
4265 }
4266
4267 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4268 {
4269         const unsigned array_offset = chan / 3;
4270         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4271 }
4272
4273 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4274 {
4275         // pre-m-series boards have fixed signals on pfi pins
4276         switch(chan)
4277         {
4278         case 0:
4279                 return NI_PFI_OUTPUT_AI_START1;
4280                 break;
4281         case 1:
4282                 return NI_PFI_OUTPUT_AI_START2;
4283                 break;
4284         case 2:
4285                 return NI_PFI_OUTPUT_AI_CONVERT;
4286                 break;
4287         case 3:
4288                 return NI_PFI_OUTPUT_G_SRC1;
4289                 break;
4290         case 4:
4291                 return NI_PFI_OUTPUT_G_GATE1;
4292                 break;
4293         case 5:
4294                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4295                 break;
4296         case 6:
4297                 return NI_PFI_OUTPUT_AO_START1;
4298                 break;
4299         case 7:
4300                 return NI_PFI_OUTPUT_AI_START_PULSE;
4301                 break;
4302         case 8:
4303                 return NI_PFI_OUTPUT_G_SRC0;
4304                 break;
4305         case 9:
4306                 return NI_PFI_OUTPUT_G_GATE0;
4307                 break;
4308         default:
4309                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4310                 break;
4311         }
4312         return 0;
4313 }
4314
4315 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4316 {
4317         if(boardtype.reg_type & ni_reg_m_series_mask)
4318                 return ni_m_series_get_pfi_routing(dev, chan);
4319         else
4320                 return ni_old_get_pfi_routing(dev, chan);
4321 }
4322
4323 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4324         comedi_insn *insn,lsampl_t *data)
4325 {
4326         if((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4327         {
4328                 data[1] = 0;
4329                 return 2;
4330         }
4331         if(data[0])
4332         {
4333                 s->state &= ~data[0];
4334                 s->state |= (data[0] & data[1]);
4335                 ni_writew(s->state, M_Offset_PFI_DO);
4336         }
4337         data[1] = ni_readw(M_Offset_PFI_DI);
4338         return 2;
4339 }
4340
4341 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4342         comedi_insn *insn,lsampl_t *data)
4343 {
4344         unsigned int chan;
4345
4346         if(insn->n < 1)return -EINVAL;
4347
4348         chan = CR_CHAN(insn->chanspec);
4349
4350         switch(data[0]){
4351         case COMEDI_OUTPUT:
4352                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4353                 break;
4354         case COMEDI_INPUT:
4355                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4356                 break;
4357         case INSN_CONFIG_DIO_QUERY:
4358                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4359                 return insn->n;
4360                 break;
4361         case INSN_CONFIG_SET_ROUTING:
4362                 return ni_set_pfi_routing(dev, chan, data[1]);
4363                 break;
4364         case INSN_CONFIG_GET_ROUTING:
4365                 data[1] = ni_get_pfi_routing(dev, chan);
4366                 return 2;
4367                 break;
4368         default:
4369                 return -EINVAL;
4370         }
4371
4372         return 1;
4373 }
4374
4375 /*
4376  *
4377  *  NI RTSI Bus Functions
4378  *
4379  */
4380 static void ni_rtsi_init(comedi_device *dev)
4381 {
4382         // Initialises the RTSI bus signal switch to a default state
4383
4384         // Set clock mode to internal
4385         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4386         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4387         {
4388                 rt_printk("ni_set_master_clock failed, bug?");
4389         }
4390         // default internal lines routing to RTSI bus lines
4391         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4392                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4393                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4394                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4395         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4396                 RTSI_Trig_A_Output_Register);
4397         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4398                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4399                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4400         if(boardtype.reg_type & ni_reg_m_series_mask)
4401                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4402         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4403                 RTSI_Trig_B_Output_Register);
4404
4405         // Sets the source and direction of the 4 on board lines
4406 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4407 }
4408
4409 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4410         comedi_insn *insn,lsampl_t *data)
4411 {
4412         if(insn->n != 2) return -EINVAL;
4413
4414         data[1] = 0;
4415
4416         return 2;
4417 }
4418
4419 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4420  * given an arbitrary frequency input clock */
4421 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4422         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4423 {
4424         unsigned div;
4425         unsigned best_div = 1;
4426         static const unsigned max_div = 0x10;
4427         unsigned mult;
4428         unsigned best_mult = 1;
4429         static const unsigned max_mult = 0x100;
4430         static const unsigned pico_per_nano = 1000;
4431
4432         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4433         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4434          * 20 MHz for most timing clocks */
4435         static const unsigned target_picosec = 12500;
4436         static const unsigned fudge_factor_80_to_20Mhz = 4;
4437         int best_period_picosec = 0;
4438         for(div = 1; div <= max_div; ++div)
4439         {
4440                 for(mult = 1; mult <= max_mult; ++mult)
4441                 {
4442                         unsigned new_period_ps = (reference_picosec * div) / mult;
4443                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4444                         {
4445                                 best_period_picosec = new_period_ps;
4446                                 best_div = div;
4447                                 best_mult = mult;
4448                         }
4449                 }
4450         }
4451         if(best_period_picosec == 0)
4452         {
4453                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4454                 return -EIO;
4455         }
4456         *freq_divider = best_div;
4457         *freq_multiplier = best_mult;
4458         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4459         return 0;
4460 }
4461
4462 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4463 {
4464         if(boardtype.reg_type & ni_reg_m_series_mask) return 8;
4465         else return 7;
4466 }
4467
4468 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4469 {
4470         static const unsigned min_period_ns = 50;
4471         static const unsigned max_period_ns = 1000;
4472         static const unsigned timeout = 1000;
4473         unsigned pll_control_bits;
4474         unsigned freq_divider;
4475         unsigned freq_multiplier;
4476         unsigned i;
4477         int retval;
4478         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4479         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4480         if(period_ns < min_period_ns || period_ns > max_period_ns)
4481         {
4482                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4483                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4484                 return -EINVAL;
4485         }
4486         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4487         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4488         pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4489         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
4490         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4491         switch(source)
4492         {
4493         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4494                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4495                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4496                         &freq_multiplier, &devpriv->clock_ns);
4497                 if(retval < 0) return retval;
4498                 break;
4499         case NI_MIO_PLL_PXI10_CLOCK:
4500                 /* pxi clock is 10MHz */
4501                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4502                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4503                         &freq_multiplier, &devpriv->clock_ns);
4504                 if(retval < 0) return retval;
4505                 break;
4506         default:
4507                 {
4508                         unsigned rtsi_channel;
4509                         static const unsigned max_rtsi_channel = 7;
4510                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4511                         {
4512                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4513                                 {
4514                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4515                                         break;
4516                                 }
4517                         }
4518                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4519                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4520                                 &freq_multiplier, &devpriv->clock_ns);
4521                         if(retval < 0) return retval;
4522                 }
4523                 break;
4524         }
4525         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4526         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4527 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4528 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4529         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4530         devpriv->clock_source = source;
4531         /* it seems to typically take a few hundred microseconds for PLL to lock */
4532         for(i = 0; i < timeout; ++i)
4533         {
4534                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4535                 {
4536                         break;
4537                 }
4538                 udelay(1);
4539         }
4540         if(i == timeout)
4541         {
4542                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4543                         __FUNCTION__, source, period_ns);
4544                 return -ETIMEDOUT;
4545         }
4546         return 3;
4547 }
4548
4549 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4550 {
4551         if(source == NI_MIO_INTERNAL_CLOCK)
4552         {
4553                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4554                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4555                 devpriv->clock_ns = 50;
4556                 if(boardtype.reg_type & ni_reg_m_series_mask)
4557                 {
4558                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4559                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4560                         ni_writew(0, M_Offset_PLL_Control);
4561                 }
4562                 devpriv->clock_source = source;
4563         }else
4564         {
4565                 if(boardtype.reg_type & ni_reg_m_series_mask)
4566                 {
4567                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4568                 }else
4569                 {
4570                         if(source == NI_MIO_RTSI_CLOCK)
4571                         {
4572                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4573                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4574                                 if(devpriv->clock_ns == 0)
4575                                 {
4576                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4577                                                 __FUNCTION__);
4578                                         return -EINVAL;
4579                                 }else
4580                                 {
4581                                         devpriv->clock_ns = period_ns;
4582                                 }
4583                                 devpriv->clock_source = source;
4584                         }else
4585                                 return -EINVAL;
4586                 }
4587         }
4588         return 3;
4589 }
4590
4591 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4592 {
4593         if(chan >= num_configurable_rtsi_channels(dev))
4594         {
4595                 if(chan == old_RTSI_clock_channel)
4596                 {
4597                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4598                         else
4599                         {
4600                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4601                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4602                                 return 0;
4603                         }
4604                 }
4605                 return 0;
4606         }
4607         switch(source)
4608         {
4609         case NI_RTSI_OUTPUT_ADR_START1:
4610         case NI_RTSI_OUTPUT_ADR_START2:
4611         case NI_RTSI_OUTPUT_SCLKG:
4612         case NI_RTSI_OUTPUT_DACUPDN:
4613         case NI_RTSI_OUTPUT_DA_START1:
4614         case NI_RTSI_OUTPUT_G_SRC0:
4615         case NI_RTSI_OUTPUT_G_GATE0:
4616         case NI_RTSI_OUTPUT_RGOUT0:
4617         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4618                 return 1;
4619                 break;
4620         case NI_RTSI_OUTPUT_RTSI_OSC:
4621                 if(boardtype.reg_type & ni_reg_m_series_mask)
4622                         return 1;
4623                 else return 0;
4624                 break;
4625         default:
4626                 return 0;
4627                 break;
4628         }
4629 }
4630
4631 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4632 {
4633         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4634         if(chan < 4)
4635         {
4636                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4637                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4638                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4639                         RTSI_Trig_A_Output_Register);
4640         }else if(chan < 8)
4641         {
4642                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4643                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4644                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4645                         RTSI_Trig_B_Output_Register);
4646         }
4647         return 2;
4648 }
4649
4650 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4651 {
4652         if(chan < 4)
4653         {
4654                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4655         }else if(chan < num_configurable_rtsi_channels(dev))
4656         {
4657                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4658         }else
4659         {
4660                 if(chan == old_RTSI_clock_channel)
4661                         return NI_RTSI_OUTPUT_RTSI_OSC;
4662                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4663                 return 0;
4664         }
4665 }
4666
4667 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4668         comedi_insn *insn,lsampl_t *data)
4669 {
4670         unsigned int chan = CR_CHAN(insn->chanspec);
4671         switch(data[0]){
4672         case INSN_CONFIG_DIO_OUTPUT:
4673                 if(chan < num_configurable_rtsi_channels(dev))
4674                 {
4675                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4676                 }else if(chan == old_RTSI_clock_channel)
4677                 {
4678                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4679                 }
4680                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4681                 break;
4682         case INSN_CONFIG_DIO_INPUT:
4683                 if(chan < num_configurable_rtsi_channels(dev))
4684                 {
4685                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0);
4686                 }else if(chan == old_RTSI_clock_channel)
4687                 {
4688                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4689                 }
4690                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4691                 break;
4692         case INSN_CONFIG_DIO_QUERY:
4693                 if(chan < num_configurable_rtsi_channels(dev))
4694                 {
4695                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, (boardtype.reg_type & ni_reg_m_series_mask) != 0)) ?
4696                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4697                 }else if(chan == old_RTSI_clock_channel)
4698                 {
4699                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4700                 }
4701                 return 2;
4702                 break;
4703         case INSN_CONFIG_SET_CLOCK_SRC:
4704                 return ni_set_master_clock(dev, data[1], data[2]);
4705                 break;
4706         case INSN_CONFIG_GET_CLOCK_SRC:
4707                 data[1] = devpriv->clock_source;
4708                 data[2] = devpriv->clock_ns;
4709                 return 3;
4710                 break;
4711         case INSN_CONFIG_SET_ROUTING:
4712                 return ni_set_rtsi_routing(dev, chan, data[1]);
4713                 break;
4714         case INSN_CONFIG_GET_ROUTING:
4715                 data[1] = ni_get_rtsi_routing(dev, chan);
4716                 return 2;
4717                 break;
4718         default:
4719                 return -EINVAL;
4720                 break;
4721         }
4722         return 1;
4723 }
4724
4725 static int cs5529_wait_for_idle(comedi_device *dev)
4726 {
4727         unsigned short status;
4728         const int timeout = HZ;
4729         int i;
4730
4731         for(i = 0; i < timeout; i++)
4732         {
4733                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4734                 if((status & CSS_ADC_BUSY) == 0)
4735                 {
4736                         break;
4737                 }
4738                 set_current_state(TASK_INTERRUPTIBLE);
4739                 if(schedule_timeout(1))
4740                 {
4741                         return -EIO;
4742                 }
4743         }
4744 //printk("looped %i times waiting for idle\n", i);
4745         if(i == timeout)
4746         {
4747                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4748                 return -ETIME;
4749         }
4750         return 0;
4751 }
4752
4753 static void cs5529_command(comedi_device *dev, unsigned short value)
4754 {
4755         static const int timeout = 100;
4756         int i;
4757
4758         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4759         /* give time for command to start being serially clocked into cs5529.
4760          * this insures that the CSS_ADC_BUSY bit will get properly
4761          * set before we exit this function.
4762         */
4763         for(i = 0; i < timeout; i++)
4764         {
4765                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4766                         break;
4767                 comedi_udelay(1);
4768         }
4769 //printk("looped %i times writing command to cs5529\n", i);
4770         if(i == timeout)
4771         {
4772                 comedi_error(dev, "possible problem - never saw adc go busy?");
4773         }
4774 }
4775
4776 /* write to cs5529 register */
4777 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4778 {
4779         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4780         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4781         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4782         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4783         if(cs5529_wait_for_idle(dev))
4784                 comedi_error(dev, "time or signal in cs5529_config_write()");
4785 }
4786
4787 /* read from cs5529 register */
4788 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4789 {
4790         unsigned int value;
4791
4792         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4793         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4794         if(cs5529_wait_for_idle(dev))
4795                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4796         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4797         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4798         return value;
4799 }
4800
4801 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4802 {
4803         int retval;
4804         unsigned short status;
4805
4806         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4807         retval = cs5529_wait_for_idle(dev);
4808         if(retval)
4809         {
4810                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4811                 return -ETIME;
4812         }
4813         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4814         if(status & CSS_OSC_DETECT)
4815         {
4816                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4817                 return -EIO;
4818         }
4819         if(status & CSS_OVERRANGE)
4820         {
4821                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4822         }
4823         if(data)
4824         {
4825                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4826                 /* cs5529 returns 16 bit signed data in bipolar mode */
4827                 *data ^= (1 << 15);
4828         }
4829         return 0;
4830 }
4831
4832 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4833 {
4834         int n, retval;
4835         unsigned short sample;
4836         unsigned int channel_select;
4837         const unsigned int INTERNAL_REF = 0x1000;
4838
4839         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4840          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4841          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4842         if(insn->chanspec & CR_ALT_SOURCE)
4843                 channel_select = INTERNAL_REF;
4844         else
4845                 channel_select = CR_CHAN(insn->chanspec);
4846         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4847
4848         for(n = 0; n < insn->n; n++)
4849         {
4850                 retval = cs5529_do_conversion(dev, &sample);
4851                 if(retval < 0) return retval;
4852                 data[n] = sample;
4853         }
4854         return insn->n;
4855 }
4856
4857 static int init_cs5529(comedi_device *dev)
4858 {
4859         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4860
4861 #if 1
4862         /* do self-calibration */
4863         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4864         /* need to force a conversion for calibration to run */
4865         cs5529_do_conversion(dev, NULL);
4866 #else
4867         /* force gain calibration to 1 */
4868         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
4869         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
4870         if(cs5529_wait_for_idle(dev))
4871                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
4872 #endif
4873         if(0)
4874         {
4875                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
4876                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
4877                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
4878         }
4879         return 0;
4880 }
4881
4882