comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 /*
  26         This file is meant to be included by another file, e.g.,
  27         ni_atmio.c or ni_pcimio.c.
  28
  29         Interrupt support originally added by Truxton Fulton
  30         <trux@truxton.com>
  31
  32         References (from ftp://ftp.natinst.com/support/manuals):
  33
  34            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  35            341079b.pdf  PCI E Series RLPM
  36            340934b.pdf  DAQ-STC reference manual
  37         67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
  38         release_ni611x.pdf
  39         release_ni67xx.pdf
  40         Other possibly relevant info:
  41
  42            320517c.pdf  User manual (obsolete)
  43            320517f.pdf  User manual (new)
  44            320889a.pdf  delete
  45            320906c.pdf  maximum signal ratings
  46            321066a.pdf  about 16x
  47            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  48            321808a.pdf  about at-mio-16e-10 rev P
  49            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  50            321838a.pdf  about at-mio-16de-10 rev N
  51
  52         ISSUES:
  53
  54          - the interrupt routine needs to be cleaned up
  55
  56         2006-02-07: S-Series PCI-6143: Support has been added but is not
  57                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  58 */
  59
  60 //#define DEBUG_INTERRUPT
  61 //#define DEBUG_STATUS_A
  62 //#define DEBUG_STATUS_B
  63
  64 #include "8255.h"
  65 #include "mite.h"
  66 #include "comedi_fc.h"
  67
  68 #ifndef MDPRINTK
  69 #define MDPRINTK(format,args...)
  70 #endif
  71
  72 /* A timeout count */
  73 #define NI_TIMEOUT 1000
  74 static const unsigned old_RTSI_clock_channel = 7;
  75
  76 /* Note: this table must match the ai_gain_* definitions */
  77 static short ni_gainlkup[][16]={
  78         /* ai_gain_16 */
  79         { 0, 1, 2, 3, 4, 5, 6, 7, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105,
  80                 0x106, 0x107 },
  81         /* ai_gain_8 */
  82         { 1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107 },
  83         /* ai_gain_14 */
  84         { 1, 2, 3, 4, 5, 6, 7, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106,
  85                 0x107 },
  86         /* ai_gain_4 */
  87         { 0, 1, 4, 7 },
  88         /* ai_gain_611x */
  89         { 0x00a, 0x00b, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006 },
  90         /* ai_gain_622x */
  91         { 0, 1, 4, 5},
  92         /* ai_gain_628x */
  93         { 1, 2, 3, 4, 5, 6, 7},
  94         /* ai_gain_6143 */
  95         { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
  96 };
  97
  98 static comedi_lrange range_ni_E_ai={    16, {
  99         RANGE( -10,     10      ),
 100         RANGE( -5,      5       ),
 101         RANGE( -2.5,    2.5     ),
 102         RANGE( -1,      1       ),
 103         RANGE( -0.5,    0.5     ),
 104         RANGE( -0.25,   0.25    ),
 105         RANGE( -0.1,    0.1     ),
 106         RANGE( -0.05,   0.05    ),
 107         RANGE( 0,       20      ),
 108         RANGE( 0,       10      ),
 109         RANGE( 0,       5       ),
 110         RANGE( 0,       2       ),
 111         RANGE( 0,       1       ),
 112         RANGE( 0,       0.5     ),
 113         RANGE( 0,       0.2     ),
 114         RANGE( 0,       0.1     ),
 115 }};
 116 static comedi_lrange range_ni_E_ai_limited={    8, {
 117         RANGE( -10,     10      ),
 118         RANGE( -5,      5       ),
 119         RANGE( -1,      1       ),
 120         RANGE( -0.1,    0.1     ),
 121         RANGE( 0,       10      ),
 122         RANGE( 0,       5       ),
 123         RANGE( 0,       1       ),
 124         RANGE( 0,       0.1     ),
 125 }};
 126 static comedi_lrange range_ni_E_ai_limited14={  14, {
 127         RANGE( -10,     10      ),
 128         RANGE( -5,      5       ),
 129         RANGE( -2,      2       ),
 130         RANGE( -1,      1       ),
 131         RANGE( -0.5,    0.5     ),
 132         RANGE( -0.2,    0.2     ),
 133         RANGE( -0.1,    0.1     ),
 134         RANGE( 0,       10      ),
 135         RANGE( 0,       5       ),
 136         RANGE( 0,       2       ),
 137         RANGE( 0,       1       ),
 138         RANGE( 0,       0.5     ),
 139         RANGE( 0,       0.2     ),
 140         RANGE( 0,       0.1     ),
 141 }};
 142 static comedi_lrange range_ni_E_ai_bipolar4={ 4, {
 143         RANGE( -10,     10      ),
 144         RANGE( -5,      5       ),
 145         RANGE( -0.5,    0.5     ),
 146         RANGE( -0.05,   0.05    ),
 147 }};
 148 static comedi_lrange range_ni_E_ai_611x={ 8, {
 149         RANGE( -50,     50      ),
 150         RANGE( -20,     20      ),
 151         RANGE( -10,     10      ),
 152         RANGE( -5,      5       ),
 153         RANGE( -2,      2       ),
 154         RANGE( -1,      1       ),
 155         RANGE( -0.5,    0.5     ),
 156         RANGE( -0.2,    0.2     ),
 157 }};
 158 static comedi_lrange range_ni_M_ai_622x={ 4, {
 159         RANGE(-10, 10),
 160         RANGE(-5, 5),
 161         RANGE(-1, 1),
 162         RANGE(-0.2, 0.2),
 163 }};
 164 static comedi_lrange range_ni_M_ai_628x={ 7, {
 165         RANGE( -10,     10      ),
 166         RANGE( -5,      5       ),
 167         RANGE( -2,      2       ),
 168         RANGE( -1,      1       ),
 169         RANGE( -0.5,    0.5     ),
 170         RANGE( -0.2,    0.2     ),
 171         RANGE( -0.1,    0.1     ),
 172 }};
 173 static comedi_lrange range_ni_S_ai_6143 = { 1, {
 174         RANGE( -5,      +5      ),
 175 }};
 176 static comedi_lrange range_ni_E_ao_ext = { 4, {
 177         RANGE( -10,     10      ),
 178         RANGE( 0,       10      ),
 179         RANGE_ext( -1,  1       ),
 180         RANGE_ext( 0,   1       ),
 181 }};
 182
 183 static comedi_lrange *ni_range_lkup[]={
 184         &range_ni_E_ai,
 185         &range_ni_E_ai_limited,
 186         &range_ni_E_ai_limited14,
 187         &range_ni_E_ai_bipolar4,
 188         &range_ni_E_ai_611x,
 189         &range_ni_M_ai_622x,
 190         &range_ni_M_ai_628x,
 191         &range_ni_S_ai_6143
 192 };
 193
 194
 195
 196 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
 197         comedi_insn *insn,lsampl_t *data);
 198 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
 199         comedi_insn *insn,lsampl_t *data);
 200
 201 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
 202         comedi_insn *insn,lsampl_t *data);
 203 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 204         unsigned char data_out, unsigned char *data_in);
 205 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
 206         unsigned char data_out, unsigned char *data_in);
 207
 208 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
 209         comedi_insn *insn,lsampl_t *data);
 210 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
 211         comedi_insn *insn,lsampl_t *data);
 212
 213 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 214         comedi_insn *insn,lsampl_t *data);
 215 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
 216         comedi_insn *insn,lsampl_t *data);
 217
 218 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 219         comedi_insn *insn,lsampl_t *data);
 220 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
 221         comedi_insn *insn,lsampl_t *data);
 222 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan);
 223
 224 static void ni_rtsi_init(comedi_device *dev);
 225 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
 226         comedi_insn *insn,lsampl_t *data);
 227 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
 228         comedi_insn *insn,lsampl_t *data);
 229
 230 static void caldac_setup(comedi_device *dev,comedi_subdevice *s);
 231 static int ni_read_eeprom(comedi_device *dev,int addr);
 232
 233 #ifdef DEBUG_STATUS_A
 234 static void ni_mio_print_status_a(int status);
 235 #else
 236 #define ni_mio_print_status_a(a)
 237 #endif
 238 #ifdef DEBUG_STATUS_B
 239 static void ni_mio_print_status_b(int status);
 240 #else
 241 #define ni_mio_print_status_b(a)
 242 #endif
 243
 244 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s);
 245 #ifndef PCIDMA
 246 static void ni_handle_fifo_half_full(comedi_device *dev);
 247 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s);
 248 #endif
 249 static void ni_handle_fifo_dregs(comedi_device *dev);
 250 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
 251         unsigned int trignum);
 252 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
 253         unsigned int *list);
 254 static void shutdown_ai_command( comedi_device *dev );
 255
 256 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
 257         unsigned int trignum);
 258
 259 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s);
 260
 261 static int ni_8255_callback(int dir,int port,int data,unsigned long arg);
 262
 263 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode);
 264
 265
 266 /*GPCT function def's*/
 267 static int GPCT_G_Watch(comedi_device *dev, int chan);
 268
 269 static void GPCT_Reset(comedi_device *dev, int chan);
 270 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length);
 271 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length);
 272 static void GPCT_Period_Meas(comedi_device *dev, int chan);
 273 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan);
 274 static void GPCT_Event_Counting(comedi_device *dev,int chan);
 275 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction);
 276 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate);
 277 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source);
 278
 279 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
 280         comedi_insn *insn,lsampl_t *data);
 281 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
 282         comedi_insn *insn,lsampl_t *data);
 283 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
 284         comedi_insn *insn,lsampl_t *data);
 285 static int ni_gpct_cmd(comedi_device *dev,comedi_subdevice *s);
 286 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd);
 287 static int ni_gpct_cancel(comedi_device *dev,comedi_subdevice *s);
 288
 289 static int init_cs5529(comedi_device *dev);
 290 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data);
 291 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data);
 292 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits);
 293 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits);
 294
 295 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
 296         comedi_insn *insn,lsampl_t *data);
 297 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
 298         comedi_insn *insn, lsampl_t *data);
 299
 300 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns);
 301
 302 enum aimodes
 303 {
 304         AIMODE_NONE = 0,
 305         AIMODE_HALF_FULL = 1,
 306         AIMODE_SCAN = 2,
 307         AIMODE_SAMPLE = 3,
 308 };
 309
 310 #define SERIAL_DISABLED         0
 311 #define SERIAL_600NS            600
 312 #define SERIAL_1_2US            1200
 313 #define SERIAL_10US                     10000
 314
 315 static const int num_adc_stages_611x = 3;
 316
 317 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 318         unsigned int m_status);
 319 static void handle_b_interrupt(comedi_device *dev,unsigned short status,
 320         unsigned int m_status);
 321 static void get_last_sample_611x( comedi_device *dev );
 322 static void get_last_sample_6143( comedi_device *dev );
 323 #ifdef PCIDMA
 324 //static void mite_handle_interrupt(comedi_device *dev,unsigned int status);
 325 static int ni_ai_drain_dma(comedi_device *dev );
 326 #endif
 327
 328 static void ni_flush_ai_fifo(comedi_device *dev){
 329         if(boardtype.reg_type == ni_reg_6143){
 330                 // Flush the 6143 data FIFO
 331                 ni_writel(0x10, AIFIFO_Control_6143);           // Flush fifo
 332                 ni_writel(0x00, AIFIFO_Control_6143);           // Flush fifo
 333                 while(ni_readl(AIFIFO_Status_6143) & 0x10);     // Wait for complete
 334         }
 335         else {
 336                 devpriv->stc_writew(dev, 1,ADC_FIFO_Clear);
 337         }
 338 }
 339
 340 static void win_out2(comedi_device *dev, uint32_t data, int reg)
 341 {
 342         devpriv->stc_writew(dev, data >> 16, reg);
 343         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 344 }
 345
 346 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
 347 static inline void ni_ao_win_outw( comedi_device *dev, uint16_t data, int addr )
 348 {
 349         unsigned long flags;
 350
 351         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 352         ni_writew(addr,AO_Window_Address_611x);
 353         ni_writew(data,AO_Window_Data_611x);
 354         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 355 }
 356
 357 static inline void ni_ao_win_outl(comedi_device *dev, uint32_t data, int addr)
 358 {
 359         unsigned long flags;
 360
 361         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 362         ni_writew(addr,AO_Window_Address_611x);
 363         ni_writel(data,AO_Window_Data_611x);
 364         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 365 }
 366
 367 static inline unsigned short ni_ao_win_inw( comedi_device *dev, int addr )
 368 {
 369         unsigned long flags;
 370         unsigned short data;
 371
 372         comedi_spin_lock_irqsave(&devpriv->window_lock,flags);
 373         ni_writew(addr, AO_Window_Address_611x);
 374         data = ni_readw(AO_Window_Data_611x);
 375         comedi_spin_unlock_irqrestore(&devpriv->window_lock,flags);
 376         return data;
 377 }
 378
 379 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 380 * share registers (such as Interrupt_A_Register) without interfering with
 381 * each other.
 382 *
 383 * NOTE: the switch/case statements are optimized out for a constant argument
 384 * so this is actually quite fast---  If you must wrap another function around this
 385 * make it inline to avoid a large speed penalty.
 386 *
 387 * value should only be 1 or 0.
 388 */
 389 static inline void ni_set_bits(comedi_device *dev, int reg, int bits, int value)
 390 {
 391         unsigned long flags;
 392
 393         comedi_spin_lock_irqsave( &devpriv->window_lock, flags );
 394         switch (reg){
 395                 case Interrupt_A_Enable_Register:
 396                         if(value)
 397                                 devpriv->int_a_enable_reg |= bits;
 398                         else
 399                                 devpriv->int_a_enable_reg &= ~bits;
 400                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 401                         devpriv->stc_writew(dev, devpriv->int_a_enable_reg,Interrupt_A_Enable_Register);
 402                         break;
 403                 case Interrupt_B_Enable_Register:
 404                         if(value)
 405                                 devpriv->int_b_enable_reg |= bits;
 406                         else
 407                                 devpriv->int_b_enable_reg &= ~bits;
 408                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 409                         devpriv->stc_writew(dev, devpriv->int_b_enable_reg,Interrupt_B_Enable_Register);
 410                         break;
 411                 case IO_Bidirection_Pin_Register:
 412                         if(value)
 413                                 devpriv->io_bidirection_pin_reg |= bits;
 414                         else
 415                                 devpriv->io_bidirection_pin_reg &= ~bits;
 416                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 417                         devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,IO_Bidirection_Pin_Register);
 418                         break;
 419                 default:
 420                         rt_printk("Warning ni_set_bits() called with invalid arguments\n");
 421                         rt_printk("reg is %d\n",reg);
 422                         comedi_spin_unlock_irqrestore( &devpriv->window_lock, flags );
 423                         break;
 424         }
 425 }
 426
 427
 428 static irqreturn_t ni_E_interrupt(int irq,void *d,struct pt_regs * regs)
 429 {
 430         comedi_device *dev=d;
 431         unsigned short a_status;
 432         unsigned short b_status;
 433         unsigned int m0_status;
 434         unsigned int m1_status;
 435         unsigned long flags;
 436 #ifdef PCIDMA
 437         struct mite_struct *mite = devpriv->mite;
 438 #endif
 439
 440         if(dev->attached == 0) return IRQ_NONE;
 441         // lock to avoid race with comedi_poll
 442         comedi_spin_lock_irqsave(&dev->spinlock, flags);
 443         a_status=devpriv->stc_readw(dev, AI_Status_1_Register);
 444         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 445 #ifdef PCIDMA
 446         m0_status=readl(mite->mite_io_addr + MITE_CHSR(AI_DMA_CHAN));
 447         m1_status=readl(mite->mite_io_addr + MITE_CHSR(AO_DMA_CHAN));
 448 #else
 449         m0_status = 0;
 450         m1_status = 0;
 451 #endif
 452
 453         if(a_status&Interrupt_A_St || m0_status & CHSR_INT )
 454                 handle_a_interrupt(dev, a_status, m0_status);
 455         if(b_status&Interrupt_B_St || m1_status & CHSR_INT )
 456                 handle_b_interrupt(dev, b_status, m1_status);
 457         comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
 458         return IRQ_HANDLED;
 459 }
 460
 461 #ifdef PCIDMA
 462 static void ni_sync_ai_dma(struct mite_struct *mite, comedi_device *dev)
 463 {
 464         int count;
 465         comedi_subdevice *s = dev->subdevices + 0;
 466         comedi_async *async = s->async;
 467         unsigned int nbytes, old_alloc_count;
 468         unsigned int bytes_per_scan = bytes_per_sample(s) * async->cmd.chanlist_len;
 469
 470         old_alloc_count = async->buf_write_alloc_count;
 471         // write alloc as much as we can
 472         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
 473
 474         nbytes = mite_bytes_written_to_memory_lb(mite, AI_DMA_CHAN);
 475         rmb();
 476         if( (int)(mite_bytes_written_to_memory_ub(mite, AI_DMA_CHAN) - old_alloc_count) > 0 ){
 477                 rt_printk("ni_mio_common: DMA overwrite of free area\n");
 478                 ni_ai_reset(dev,s);
 479                 async->events |= COMEDI_CB_OVERFLOW;
 480                 return;
 481         }
 482
 483         count = nbytes - async->buf_write_count;
 484         if( count <= 0 ){
 485                 /* it's possible count will be negative due to
 486                  * conservative value returned by mite_bytes_transferred */
 487                 return;
 488         }
 489         comedi_buf_write_free(async, count);
 490
 491         async->scan_progress += count;
 492         if( async->scan_progress >= bytes_per_scan )
 493         {
 494                 async->scan_progress %= bytes_per_scan;
 495                 async->events |= COMEDI_CB_EOS;
 496         }
 497         async->events |= COMEDI_CB_BLOCK;
 498 }
 499
 500 static void mite_handle_b_linkc(struct mite_struct *mite, comedi_device *dev)
 501 {
 502         int count;
 503         comedi_subdevice *s = dev->subdevices + 1;
 504         comedi_async *async = s->async;
 505         u32 nbytes_ub, nbytes_lb;
 506         unsigned int new_write_count;
 507         u32 stop_count = async->cmd.stop_arg * sizeof(sampl_t);
 508
 509         writel(CHOR_CLRLC, mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 510
 511         new_write_count = async->buf_write_count;
 512         mb();
 513         nbytes_lb = mite_bytes_read_from_memory_lb(mite, AO_DMA_CHAN);
 514         if(async->cmd.stop_src == TRIG_COUNT &&
 515                 (int) (nbytes_lb - stop_count) > 0)
 516                 nbytes_lb = stop_count;
 517         mb();
 518         nbytes_ub = mite_bytes_read_from_memory_ub(mite, AO_DMA_CHAN);
 519         if(async->cmd.stop_src == TRIG_COUNT &&
 520                 (int) (nbytes_ub - stop_count) > 0)
 521                 nbytes_ub = stop_count;
 522         if((int)(nbytes_ub - devpriv->last_buf_write_count) > 0){
 523                 rt_printk("ni_mio_common: DMA underrun\n");
 524                 ni_ao_reset(dev,s);
 525                 async->events |= COMEDI_CB_OVERFLOW;
 526                 return;
 527         }
 528         mb();
 529         devpriv->last_buf_write_count = new_write_count;
 530
 531         count = nbytes_lb - async->buf_read_count;
 532         if(count < 0){
 533                 return;
 534         }
 535         comedi_buf_read_free(async, count);
 536
 537         async->events |= COMEDI_CB_BLOCK;
 538 }
 539 // #define DEBUG_DMA_TIMING
 540 static int ni_ao_wait_for_dma_load( comedi_device *dev )
 541 {
 542         static const int timeout = 10000;
 543         int i;
 544 #ifdef DEBUG_DMA_TIMING
 545         struct timeval start;
 546         do_gettimeofday(&start);
 547 #endif
 548         for(i = 0; i < timeout; i++)
 549         {
 550                 unsigned short b_status;
 551
 552                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 553                 if( b_status & AO_FIFO_Half_Full_St )
 554                         break;
 555                 /* if we poll too often, the pci bus activity seems
 556                  to slow the dma transfer down */
 557                 comedi_udelay(10);
 558         }
 559 #ifdef DEBUG_DMA_TIMING
 560         rt_printk("looped %i times waiting for ao fifo load.\n", i);
 561         struct timeval now;
 562         do_gettimeofday(&now);
 563         unsigned elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 564         rt_printk("total elapsed usec=%i\n", elapsed_usec);
 565         do_gettimeofday(&start);
 566         unsigned b_status;
 567         for(i = 0; i < 100; ++i)
 568         {
 569 //              devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
 570                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 571         }
 572         do_gettimeofday(&now);
 573         elapsed_usec = 1000000 * (now.tv_sec - start.tv_sec) + now.tv_usec - start.tv_usec;
 574         rt_printk("usec to do 100 word xfers=%i\n", elapsed_usec);
 575 #endif
 576         if( i == timeout )
 577         {
 578                 comedi_error(dev, "timed out waiting for dma load");
 579                 return -EPIPE;
 580         }
 581         return 0;
 582 }
 583
 584 #endif //PCIDMA
 585 static void ni_handle_eos(comedi_device *dev, comedi_subdevice *s)
 586 {
 587         if(devpriv->aimode == AIMODE_SCAN)
 588         {
 589 #ifdef PCIDMA
 590                 static const int timeout = 10;
 591                 int i;
 592
 593                 for(i = 0; i < timeout; i++)
 594                 {
 595                         ni_sync_ai_dma(devpriv->mite, dev);
 596                         if((s->async->events & COMEDI_CB_EOS)) break;
 597                         comedi_udelay(1);
 598                 }
 599 #else
 600                 ni_handle_fifo_dregs(dev);
 601                 s->async->events |= COMEDI_CB_EOS;
 602 #endif
 603         }
 604         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 605         if((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
 606                 shutdown_ai_command( dev );
 607                 ni_ai_reset(dev, s);
 608         }
 609 }
 610
 611 static void shutdown_ai_command( comedi_device *dev )
 612 {
 613         comedi_subdevice *s = dev->subdevices + 0;
 614
 615 #ifdef PCIDMA
 616         ni_ai_drain_dma( dev );
 617         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
 618 #endif
 619         ni_handle_fifo_dregs(dev);
 620         get_last_sample_611x(dev);
 621         get_last_sample_6143(dev);
 622
 623         ni_set_bits(dev, Interrupt_A_Enable_Register,
 624                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
 625                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
 626                 AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
 627                 AI_FIFO_Interrupt_Enable,0);
 628
 629         s->async->events |= COMEDI_CB_EOA;
 630 }
 631
 632 static void handle_a_interrupt(comedi_device *dev,unsigned short status,
 633         unsigned int m_status)
 634 {
 635         comedi_subdevice *s=dev->subdevices+0;
 636         unsigned short ack=0;
 637
 638         s->async->events = 0;
 639
 640 #ifdef DEBUG_INTERRUPT
 641         rt_printk("ni_mio_common: interrupt: a_status=%04x m0_status=%08x\n",
 642                 status, m_status);
 643         ni_mio_print_status_a(status);
 644 #endif
 645
 646
 647 #ifdef PCIDMA
 648         /* Currently, mite.c requires us to handle LINKC and DONE */
 649         if(m_status & CHSR_LINKC){
 650                 writel(CHOR_CLRLC, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 651                 ni_sync_ai_dma(devpriv->mite, dev);
 652         }
 653
 654         if(m_status & CHSR_DONE){
 655                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 656         }
 657
 658         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 659                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 660                 //mite_print_chsr(m_status);
 661                 mite_dma_disarm(devpriv->mite, AI_DMA_CHAN );
 662                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AI_DMA_CHAN));
 663                 //disable_irq(dev->irq);
 664         }
 665 #endif
 666
 667         /* test for all uncommon interrupt events at the same time */
 668         if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St|AI_SC_TC_St|AI_START1_St)){
 669                 if(status==0xffff){
 670                         rt_printk("ni_mio_common: a_status=0xffff.  Card removed?\n");
 671                         /* we probably aren't even running a command now,
 672                          * so it's a good idea to be careful. */
 673                         if(s->subdev_flags&SDF_RUNNING){
 674                                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
 675                                 //comedi_event(dev,s,s->async->events);
 676                         }
 677                         return;
 678                 }
 679                 if(status&(AI_Overrun_St|AI_Overflow_St|AI_SC_TC_Error_St)){
 680                         rt_printk("ni_mio_common: ai error a_status=%04x\n",
 681                                 status);
 682                         ni_mio_print_status_a(status);
 683
 684                         ni_ai_reset(dev,dev->subdevices);
 685
 686
 687                         shutdown_ai_command( dev );
 688
 689                         s->async->events |= COMEDI_CB_ERROR;
 690                         if(status & (AI_Overrun_St | AI_Overflow_St))
 691                                 s->async->events |= COMEDI_CB_OVERFLOW;
 692
 693                         comedi_event(dev,s,s->async->events);
 694
 695                         return;
 696                 }
 697                 if(status&AI_SC_TC_St){
 698 #ifdef DEBUG_INTERRUPT
 699                         rt_printk("ni_mio_common: SC_TC interrupt\n");
 700 #endif
 701                         if(!devpriv->ai_continuous){
 702                                 shutdown_ai_command( dev );
 703                         }
 704                         ack|=AI_SC_TC_Interrupt_Ack;
 705                 }
 706                 if(status&AI_START1_St){
 707                         ack|=AI_START1_Interrupt_Ack;
 708                 }
 709         }
 710 #ifndef PCIDMA
 711         if(status&AI_FIFO_Half_Full_St){
 712                 int i;
 713                 static const int timeout = 10;
 714                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
 715                  *fail to get the fifo less than half full, so loop to be sure.*/
 716                 for(i = 0; i < timeout; ++i)
 717                 {
 718                         ni_handle_fifo_half_full(dev);
 719                         if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Half_Full_St) == 0)
 720                                 break;
 721                 }
 722         }
 723 #endif // !PCIDMA
 724
 725         if( (status & AI_STOP_St) ){
 726                 ni_handle_eos(dev, s);
 727                 /* we need to ack the START, also */
 728                 ack |= AI_STOP_Interrupt_Ack|AI_START_Interrupt_Ack;
 729         }
 730 #if 0
 731         if(devpriv->aimode==AIMODE_SAMPLE){
 732                 ni_handle_fifo_dregs(dev);
 733
 734                 //s->async->events |= COMEDI_CB_SAMPLE;
 735         }
 736 #endif
 737         if(ack) devpriv->stc_writew(dev, ack,Interrupt_A_Ack_Register);
 738
 739         comedi_event(dev,s,s->async->events);
 740
 741 #ifdef DEBUG_INTERRUPT
 742         status=devpriv->stc_readw(dev, AI_Status_1_Register);
 743         if(status&Interrupt_A_St){
 744                 rt_printk("handle_a_interrupt: didn't clear interrupt? status=0x%x\n", status);
 745         }
 746 #endif
 747 }
 748
 749 static void handle_b_interrupt(comedi_device *dev,unsigned short b_status, unsigned int m_status)
 750 {
 751         comedi_subdevice *s=dev->subdevices+1;
 752         //unsigned short ack=0;
 753 #ifdef DEBUG_INTERRUPT
 754         rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
 755                 b_status,m_status);
 756         ni_mio_print_status_b(b_status);
 757 #endif
 758
 759
 760 #ifdef PCIDMA
 761         /* Currently, mite.c requires us to handle LINKC and DONE */
 762         if(m_status & CHSR_LINKC){
 763                 mite_handle_b_linkc(devpriv->mite, dev);
 764         }
 765
 766         if(m_status & CHSR_DONE){
 767                 writel(CHOR_CLRDONE, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 768         }
 769
 770         if(m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)){
 771                 rt_printk("unknown mite interrupt, ack! (m_status=%08x)\n", m_status);
 772                 //mite_print_chsr(m_status);
 773                 mite_dma_disarm(devpriv->mite, AO_DMA_CHAN );
 774                 writel(CHOR_DMARESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
 775        }
 776 #endif
 777
 778         if(b_status==0xffff)return;
 779         if(b_status&AO_Overrun_St){
 780                 rt_printk("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 781                 ni_ao_reset(dev,s);
 782                 s->async->events |= COMEDI_CB_OVERFLOW;
 783         }
 784
 785         if(b_status&AO_BC_TC_St){
 786                 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,devpriv->stc_readw(dev, AO_Status_2_Register));
 787                 ni_ao_reset(dev,s);
 788                 s->async->events |= COMEDI_CB_EOA;
 789         }
 790
 791 #ifndef PCIDMA
 792         if(b_status&AO_FIFO_Request_St){
 793                 int ret;
 794
 795                 ret = ni_ao_fifo_half_empty(dev,s);
 796                 if(!ret){
 797                         rt_printk("ni_mio_common: AO buffer underrun\n");
 798                         ni_set_bits(dev, Interrupt_B_Enable_Register,
 799                                 AO_FIFO_Interrupt_Enable|AO_Error_Interrupt_Enable, 0);
 800                         s->async->events |= COMEDI_CB_OVERFLOW;
 801                 }
 802         }
 803 #endif
 804
 805         b_status=devpriv->stc_readw(dev, AO_Status_1_Register);
 806         if(b_status&Interrupt_B_St){
 807                 if(b_status&AO_FIFO_Request_St){
 808                         rt_printk("ni_mio_common: AO buffer underrun\n");
 809                 }
 810                 rt_printk("Ack! didn't clear AO interrupt. b_status=0x%04x\n",b_status);
 811                 ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
 812                 ni_ao_reset(dev,s);
 813                 s->async->events |= COMEDI_CB_OVERFLOW;
 814         }
 815
 816         comedi_event(dev,s,s->async->events);
 817 }
 818
 819 #ifdef DEBUG_STATUS_A
 820 static char *status_a_strings[]={
 821         "passthru0","fifo","G0_gate","G0_TC",
 822         "stop","start","sc_tc","start1",
 823         "start2","sc_tc_error","overflow","overrun",
 824         "fifo_empty","fifo_half_full","fifo_full","interrupt_a"
 825 };
 826
 827 static void ni_mio_print_status_a(int status)
 828 {
 829         int i;
 830
 831         rt_printk("A status:");
 832         for(i=15;i>=0;i--){
 833                 if(status&(1<<i)){
 834                         rt_printk(" %s",status_a_strings[i]);
 835                 }
 836         }
 837         rt_printk("\n");
 838 }
 839 #endif
 840
 841 #ifdef DEBUG_STATUS_B
 842 static char *status_b_strings[]={
 843         "passthru1","fifo","G1_gate","G1_TC",
 844         "UI2_TC","UPDATE","UC_TC","BC_TC",
 845         "start1","overrun","start","bc_tc_error",
 846         "fifo_empty","fifo_half_full","fifo_full","interrupt_b"
 847 };
 848
 849 static void ni_mio_print_status_b(int status)
 850 {
 851         int i;
 852
 853         rt_printk("B status:");
 854         for(i=15;i>=0;i--){
 855                 if(status&(1<<i)){
 856                         rt_printk(" %s",status_b_strings[i]);
 857                 }
 858         }
 859         rt_printk("\n");
 860 }
 861 #endif
 862
 863 #ifndef PCIDMA
 864
 865 static void ni_ao_fifo_load(comedi_device *dev,comedi_subdevice *s, int n)
 866 {
 867         comedi_async *async = s->async;
 868         comedi_cmd *cmd = &async->cmd;
 869         int chan;
 870         int i;
 871         sampl_t d;
 872         u32 packed_data;
 873         int range;
 874         int err = 1;
 875
 876         chan = async->cur_chan;
 877         for(i=0;i<n;i++){
 878                 err &= comedi_buf_get(async, &d);
 879                 if(err == 0) break;
 880
 881                 range = CR_RANGE(cmd->chanlist[chan]);
 882
 883                 if(boardtype.reg_type & ni_reg_6xxx_mask)
 884                 {
 885                         packed_data = d & 0xffff;
 886                         /* 6711 only has 16 bit wide ao fifo */
 887                         if(boardtype.reg_type != ni_reg_6711)
 888                         {
 889                                 err &= comedi_buf_get(async, &d);
 890                                 if(err == 0) break;
 891                                 chan++;
 892                                 i++;
 893                                 packed_data |= ( d << 16 ) & 0xffff0000;
 894                         }
 895                         ni_writel( packed_data, DAC_FIFO_Data_611x );
 896                 }else{
 897                         ni_writew(d, DAC_FIFO_Data);
 898                 }
 899                 chan++;
 900                 chan %= cmd->chanlist_len;
 901         }
 902         async->cur_chan = chan;
 903         if(err==0){
 904                 async->events |= COMEDI_CB_OVERFLOW;
 905         }
 906 }
 907
 908 /*
 909  *  There's a small problem if the FIFO gets really low and we
 910  *  don't have the data to fill it.  Basically, if after we fill
 911  *  the FIFO with all the data available, the FIFO is _still_
 912  *  less than half full, we never clear the interrupt.  If the
 913  *  IRQ is in edge mode, we never get another interrupt, because
 914  *  this one wasn't cleared.  If in level mode, we get flooded
 915  *  with interrupts that we can't fulfill, because nothing ever
 916  *  gets put into the buffer.
 917  *
 918  *  This kind of situation is recoverable, but it is easier to
 919  *  just pretend we had a FIFO underrun, since there is a good
 920  *  chance it will happen anyway.  This is _not_ the case for
 921  *  RT code, as RT code might purposely be running close to the
 922  *  metal.  Needs to be fixed eventually.
 923  */
 924 static int ni_ao_fifo_half_empty(comedi_device *dev,comedi_subdevice *s)
 925 {
 926         int n;
 927
 928         n = comedi_buf_read_n_available(s);
 929         if(n==0){
 930                 s->async->events |= COMEDI_CB_OVERFLOW;
 931                 return 0;
 932         }
 933
 934         n /= sizeof(sampl_t);
 935         if(n > boardtype.ao_fifo_depth / 2)
 936                 n = boardtype.ao_fifo_depth / 2;
 937
 938         ni_ao_fifo_load(dev,s,n);
 939
 940         s->async->events |= COMEDI_CB_BLOCK;
 941
 942         return 1;
 943 }
 944
 945 static int ni_ao_prep_fifo(comedi_device *dev,comedi_subdevice *s)
 946 {
 947         int n;
 948
 949         /* reset fifo */
 950         devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
 951         if(boardtype.reg_type & ni_reg_6xxx_mask)
 952                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
 953
 954         /* load some data */
 955         n = comedi_buf_read_n_available(s);
 956         if(n==0)return 0;
 957
 958         n /= sizeof(sampl_t);
 959         if(n > boardtype.ao_fifo_depth)
 960                 n = boardtype.ao_fifo_depth;
 961
 962         ni_ao_fifo_load(dev,s,n);
 963
 964         return n;
 965 }
 966
 967 static void ni_ai_fifo_read(comedi_device *dev,comedi_subdevice *s,
 968         int n)
 969 {
 970         comedi_async *async = s->async;
 971         int i;
 972
 973         if(boardtype.reg_type == ni_reg_611x){
 974                 sampl_t data[2];
 975                 u32 dl;
 976
 977                 for( i = 0; i < n / 2; i++ ){
 978                         dl=ni_readl(ADC_FIFO_Data_611x);
 979                         /* This may get the hi/lo data in the wrong order */
 980                         data[0] = (dl>>16) & 0xffff;
 981                         data[1] = dl & 0xffff;
 982                         cfc_write_array_to_buffer(s, data, sizeof(data));
 983                 }
 984                 /* Check if there's a single sample stuck in the FIFO */
 985                 if( n % 2){
 986                         dl=ni_readl(ADC_FIFO_Data_611x);
 987                         data[0] = dl & 0xffff;
 988                         cfc_write_to_buffer(s, data[0]);
 989                 }
 990         } else if(boardtype.reg_type == ni_reg_6143){
 991                 sampl_t data[2];
 992                 u32     dl;
 993
 994                 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
 995                 for(i = 0; i < n / 2; i++){
 996                         dl = ni_readl(AIFIFO_Data_6143);
 997
 998                         data[0] = (dl >> 16) & 0xffff;
 999                         data[1] = dl & 0xffff;
1000                         cfc_write_array_to_buffer(s, data, sizeof(data));
1001                 }
1002                 if(n % 2){
1003                         /* Assume there is a single sample stuck in the FIFO */
1004                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1005                         dl = ni_readl(AIFIFO_Data_6143);
1006                         data[0] = (dl >> 16) & 0xffff;
1007                         cfc_write_to_buffer(s, data[0]);
1008                 }
1009         } else{
1010                 if( n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]))
1011                 {
1012                         comedi_error( dev, "bug! ai_fifo_buffer too small" );
1013                         async->events |= COMEDI_CB_ERROR;
1014                         return;
1015                 }
1016                 for(i = 0; i < n; i++){
1017                         devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1018                 }
1019                 cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1020                         n * sizeof(devpriv->ai_fifo_buffer[0]) );
1021         }
1022 }
1023
1024 static void ni_handle_fifo_half_full(comedi_device *dev)
1025 {
1026         int n;
1027         comedi_subdevice *s=dev->subdevices+0;
1028
1029         n=boardtype.ai_fifo_depth/2;
1030
1031         ni_ai_fifo_read(dev,s,n);
1032 }
1033 #endif
1034
1035 #ifdef PCIDMA
1036 static int ni_ai_drain_dma(comedi_device *dev )
1037 {
1038         struct mite_struct *mite = devpriv->mite;
1039         int i;
1040         static const int timeout = 10000;
1041
1042         for( i = 0; i < timeout; i++ )
1043         {
1044                 if((devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) &&
1045                         mite_bytes_in_transit(mite, AI_DMA_CHAN) == 0)
1046                         break;
1047                 comedi_udelay(2);
1048         }
1049         if(i == timeout)
1050         {
1051                 rt_printk("ni_mio_common: wait for dma drain timed out\n");
1052                 rt_printk("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1053                         mite_bytes_in_transit(mite, AI_DMA_CHAN), devpriv->stc_readw(dev, AI_Status_1_Register));
1054                 return -1;
1055         }
1056
1057         ni_sync_ai_dma( mite, dev );
1058
1059         return 0;
1060 }
1061 #endif
1062 /*
1063    Empties the AI fifo
1064 */
1065 static void ni_handle_fifo_dregs(comedi_device *dev)
1066 {
1067         comedi_subdevice *s=dev->subdevices+0;
1068         sampl_t data[2];
1069         u32 dl;
1070         short fifo_empty;
1071         int i;
1072
1073         if(boardtype.reg_type == ni_reg_611x){
1074                 while((devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St) == 0){
1075                         dl=ni_readl(ADC_FIFO_Data_611x);
1076
1077                         /* This may get the hi/lo data in the wrong order */
1078                         data[0] = (dl>>16);
1079                         data[1] = (dl&0xffff);
1080                         cfc_write_array_to_buffer(s, data, sizeof(data));
1081                 }
1082         }else if(boardtype.reg_type == ni_reg_6143){
1083                 i = 0;
1084                 while(ni_readl(AIFIFO_Status_6143) & 0x04){
1085                         dl = ni_readl(AIFIFO_Data_6143);
1086
1087                         /* This may get the hi/lo data in the wrong order */
1088                         data[0] = (dl >> 16);
1089                         data[1] = (dl & 0xffff);
1090                         cfc_write_array_to_buffer(s, data, sizeof(data));
1091                         i += 2;
1092                 }
1093                 // Check if stranded sample is present
1094                 if(ni_readl(AIFIFO_Status_6143) & 0x01){
1095                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1096                         dl = ni_readl(AIFIFO_Data_6143);
1097                         data[0] = (dl >> 16) & 0xffff;
1098                         cfc_write_to_buffer(s, data[0]);
1099                 }
1100
1101         }else{
1102                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1103                 while(fifo_empty == 0)
1104                 {
1105                         for(i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++)
1106                         {
1107                                 fifo_empty = devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St;
1108                                 if(fifo_empty) break;
1109                                 devpriv->ai_fifo_buffer[i] = ni_readw(ADC_FIFO_Data_Register);
1110                         }
1111                         cfc_write_array_to_buffer( s, devpriv->ai_fifo_buffer,
1112                                 i * sizeof(devpriv->ai_fifo_buffer[0]) );
1113                 }
1114         }
1115 }
1116
1117 static void get_last_sample_611x( comedi_device *dev )
1118 {
1119         comedi_subdevice *s=dev->subdevices+0;
1120         sampl_t data;
1121         u32 dl;
1122
1123         if(boardtype.reg_type != ni_reg_611x) return;
1124
1125         /* Check if there's a single sample stuck in the FIFO */
1126         if(ni_readb(XXX_Status)&0x80){
1127                 dl=ni_readl(ADC_FIFO_Data_611x);
1128                 data = (dl&0xffff);
1129                 cfc_write_to_buffer(s, data);
1130         }
1131 }
1132
1133 static void get_last_sample_6143(comedi_device* dev)
1134 {
1135         comedi_subdevice*       s = dev->subdevices + 0;
1136         sampl_t                 data;
1137         u32                     dl;
1138
1139         if(boardtype.reg_type != ni_reg_6143) return;
1140
1141         /* Check if there's a single sample stuck in the FIFO */
1142         if(ni_readl(AIFIFO_Status_6143) & 0x01){
1143                 ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1144                 dl = ni_readl(AIFIFO_Data_6143);
1145
1146                 /* This may get the hi/lo data in the wrong order */
1147                 data = (dl >> 16) & 0xffff;
1148                 cfc_write_to_buffer(s, data);
1149         }
1150 }
1151
1152 static void ni_ai_munge(comedi_device *dev, comedi_subdevice *s,
1153         void *data, unsigned int num_bytes, unsigned int chan_index )
1154 {
1155         comedi_async *async = s->async;
1156         unsigned int i;
1157         unsigned int length = num_bytes / bytes_per_sample(s);
1158         sampl_t *array = data;
1159         lsampl_t *larray = data;
1160         for(i = 0; i < length; i++)
1161         {
1162 #ifdef PCIDMA
1163                 if(s->subdev_flags & SDF_LSAMPL)
1164                         larray[i] = le32_to_cpu(larray[i]);
1165                 else
1166                         array[i] = le16_to_cpu(array[i]);
1167 #endif
1168                 if(s->subdev_flags & SDF_LSAMPL)
1169                         larray[i] += devpriv->ai_offset[chan_index];
1170                 else
1171                         array[i] += devpriv->ai_offset[chan_index];
1172                 chan_index++;
1173                 chan_index %= async->cmd.chanlist_len;
1174         }
1175 }
1176
1177 #ifdef PCIDMA
1178
1179 static void ni_ai_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1180 {
1181         struct mite_struct *mite = devpriv->mite;
1182         struct mite_channel *mite_chan = &mite->channels[ AI_DMA_CHAN ];
1183         comedi_subdevice *s = dev->subdevices + 0;
1184
1185         /* write alloc the entire buffer */
1186         comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1187
1188         mite_chan->current_link = 0;
1189         mite_chan->dir = COMEDI_INPUT;
1190         switch(boardtype.reg_type)
1191         {
1192         case ni_reg_611x:
1193         case ni_reg_6143:
1194                 mite_prep_dma(mite, AI_DMA_CHAN, 32, 16);
1195                 break;
1196         case ni_reg_m_series:
1197                 if(boardtype.adbits > 16)
1198                         mite_prep_dma(mite, AI_DMA_CHAN, 32, 32);
1199                 else
1200                         mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);       //guess
1201                 break;
1202         default:
1203                 mite_prep_dma(mite, AI_DMA_CHAN, 16, 16);
1204                 break;
1205         };
1206         /*start the MITE*/
1207         mite_dma_arm(mite, AI_DMA_CHAN);
1208 }
1209
1210 static void ni_ao_setup_MITE_dma(comedi_device *dev,comedi_cmd *cmd)
1211 {
1212         struct mite_struct *mite = devpriv->mite;
1213         struct mite_channel *mite_chan = &mite->channels[ AO_DMA_CHAN ];
1214         comedi_subdevice *s = dev->subdevices + 1;
1215
1216         devpriv->last_buf_write_count = s->async->buf_write_count;
1217         mite_chan->current_link = 0;
1218         mite_chan->dir = COMEDI_OUTPUT;
1219         if(boardtype.reg_type & (ni_reg_611x | ni_reg_6713))
1220         {
1221                 mite_prep_dma(mite, AO_DMA_CHAN, 32, 32);
1222         }else
1223         {
1224                 /* doing 32 instead of 16 bit wide transfers from memory
1225                  makes the mite do 32 bit pci transfers, doubling pci bandwidth.
1226                  However, it causes the sample order to get screwed up so
1227                  I'm not going to bother. */
1228                 mite_prep_dma(mite, AO_DMA_CHAN, 16, 16);
1229         }
1230         /*start the MITE*/
1231         mite_dma_arm(mite, AO_DMA_CHAN);
1232 }
1233
1234 #endif // PCIDMA
1235
1236 void ni_m_series_adc_reset(comedi_device *dev)
1237 {
1238         ni_writeb(0, M_Offset_Static_AI_Control(0));
1239         ni_writeb(1, M_Offset_Static_AI_Control(0));
1240         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1241         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1242         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1243 }
1244
1245 /*
1246    used for both cancel ioctl and board initialization
1247
1248    this is pretty harsh for a cancel, but it works...
1249  */
1250
1251 static int ni_ai_reset(comedi_device *dev,comedi_subdevice *s)
1252 {
1253 #ifdef PCIDMA
1254         mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
1255 #endif
1256         /* ai configuration */
1257         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, Joint_Reset_Register);
1258
1259         ni_set_bits(dev, Interrupt_A_Enable_Register,
1260                 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
1261                 AI_START2_Interrupt_Enable| AI_START_Interrupt_Enable|
1262                 AI_STOP_Interrupt_Enable|   AI_Error_Interrupt_Enable|
1263                 AI_FIFO_Interrupt_Enable,0);
1264
1265         ni_flush_ai_fifo(dev);
1266
1267         if(boardtype.reg_type != ni_reg_6143)
1268                 ni_writeb(0, Misc_Command);
1269
1270         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1271         devpriv->stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */,
1272                 AI_Mode_1_Register);
1273         devpriv->stc_writew(dev, 0x0000,AI_Mode_2_Register);
1274         /* generate FIFO interrupts on non-empty */
1275         devpriv->stc_writew(dev, (0<<6)|0x0000,AI_Mode_3_Register);
1276         if(boardtype.reg_type == ni_reg_611x){
1277                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1278                         AI_SOC_Polarity |
1279                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1280                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1281                         AI_EXTMUX_CLK_Output_Select(0) |
1282                         AI_LOCALMUX_CLK_Output_Select(2) |
1283                         AI_SC_TC_Output_Select(3) |
1284                         AI_CONVERT_Output_Select(3),AI_Output_Control_Register);
1285         }else if(boardtype.reg_type == ni_reg_6143){
1286                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1287                         AI_SOC_Polarity |
1288                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1289                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1290                         AI_EXTMUX_CLK_Output_Select(0) |
1291                         AI_LOCALMUX_CLK_Output_Select(2) |
1292                         AI_SC_TC_Output_Select(3) |
1293                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1294         }else{
1295                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1296                         AI_SOC_Polarity |
1297                         AI_CONVERT_Pulse_Width |
1298                         AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1299                 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1300                         AI_EXTMUX_CLK_Output_Select(0) |
1301                         AI_LOCALMUX_CLK_Output_Select(2) |
1302                         AI_SC_TC_Output_Select(3) |
1303                         AI_CONVERT_Output_Select(2),AI_Output_Control_Register);
1304         }
1305         /* the following registers should not be changed, because there
1306          * are no backup registers in devpriv.  If you want to change
1307          * any of these, add a backup register and other appropriate code:
1308          *      AI_Mode_1_Register
1309          *      AI_Mode_3_Register
1310          *      AI_Personal_Register
1311          *      AI_Output_Control_Register
1312         */
1313         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack |
1314                 AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack |
1315                 AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack |
1316                 AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1317
1318         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
1319
1320         return 0;
1321 }
1322
1323 static int ni_ai_poll(comedi_device *dev,comedi_subdevice *s)
1324 {
1325         unsigned long flags = 0;
1326         int count;
1327
1328         // lock to avoid race with interrupt handler
1329         if(in_interrupt() == 0)
1330                 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1331 #ifndef PCIDMA
1332         ni_handle_fifo_dregs(dev);
1333 #else
1334         ni_sync_ai_dma(devpriv->mite, dev);
1335 #endif
1336         count = s->async->buf_write_count - s->async->buf_read_count;
1337         if(in_interrupt() == 0)
1338                 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1339
1340         return count;
1341 }
1342
1343
1344 static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
1345 {
1346         int i,n;
1347         const unsigned int mask = (1 << boardtype.adbits) - 1;
1348         unsigned signbits;
1349         unsigned short d;
1350         unsigned long dl;
1351
1352         ni_load_channelgain_list(dev,1,&insn->chanspec);
1353
1354         ni_flush_ai_fifo(dev);
1355
1356         signbits=devpriv->ai_offset[0];
1357         if(boardtype.reg_type == ni_reg_611x){
1358                 for(n=0; n < num_adc_stages_611x; n++){
1359                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1360                         comedi_udelay(1);
1361                 }
1362                 for(n=0; n<insn->n; n++){
1363                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1364                         /* The 611x has screwy 32-bit FIFOs. */
1365                         d = 0;
1366                         for(i=0; i<NI_TIMEOUT; i++){
1367                                 if(ni_readb(XXX_Status)&0x80)
1368                                 {
1369                                         d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
1370                                         break;
1371                                 }
1372                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1373                                 {
1374                                         d = ni_readl(ADC_FIFO_Data_611x) & 0xffff;
1375                                         break;
1376                                 }
1377                         }
1378                         if(i==NI_TIMEOUT){
1379                                 rt_printk("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1380                                 return -ETIME;
1381                         }
1382                         d += signbits;
1383                         data[ n ] = d;
1384                 }
1385         }else if(boardtype.reg_type == ni_reg_6143){
1386                 for(n = 0; n < insn->n; n++){
1387                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1388
1389                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1390                         dl = 0;
1391                         for(i = 0; i < NI_TIMEOUT; i++){
1392                                 if(ni_readl(AIFIFO_Status_6143) & 0x01)
1393                                 {
1394                                         ni_writel(0x01, AIFIFO_Control_6143);   // Get stranded sample into FIFO
1395                                         dl = ni_readl(AIFIFO_Data_6143);
1396                                         break;
1397                                 }
1398                         }
1399                         if(i == NI_TIMEOUT){
1400                                 rt_printk("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1401                                 return -ETIME;
1402                         }
1403                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1404                 }
1405         }else{
1406                 for(n=0;n<insn->n;n++){
1407                         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1408                         for(i=0;i<NI_TIMEOUT;i++){
1409                                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register)&AI_FIFO_Empty_St))
1410                                         break;
1411                         }
1412                         if(i==NI_TIMEOUT){
1413                                 rt_printk("ni_mio_common: timeout in ni_ai_insn_read\n");
1414                                 return -ETIME;
1415                         }
1416                         if(boardtype.reg_type == ni_reg_m_series)
1417                         {
1418                                 data[n] = ni_readl(M_Offset_AI_FIFO_Data) & mask;
1419                         }else
1420                         {
1421                                 d = ni_readw(ADC_FIFO_Data_Register);
1422                                 d += signbits; /* subtle: needs to be short addition */
1423                                 data[n] = d;
1424                         }
1425                 }
1426         }
1427         return insn->n;
1428 }
1429
1430 void ni_prime_channelgain_list(comedi_device *dev)
1431 {
1432         int i;
1433         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1434         for(i = 0; i < NI_TIMEOUT; ++i)
1435         {
1436                 if(!(devpriv->stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St))
1437                 {
1438                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1439                         return;
1440                 }
1441                 comedi_udelay(1);
1442         }
1443         rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1444 }
1445
1446 static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1447         unsigned int *list)
1448 {
1449         unsigned int chan, range, aref;
1450         unsigned int i;
1451         unsigned config_bits = 0;
1452         unsigned offset;
1453         unsigned int dither;
1454         unsigned range_code;
1455
1456         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1457
1458 //      offset = 1 << (boardtype.adbits - 1);
1459         if((list[0] & CR_ALT_SOURCE))
1460         {
1461                 unsigned bypass_bits;
1462                 chan = CR_CHAN(list[0]);
1463                 range = CR_RANGE(list[0]);
1464                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1465                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1466                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1467                 bypass_bits |= chan;
1468                 bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1469                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
1470                         MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1471                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1472                 if(dither)
1473                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1474                 // don't use 2's complement encoding
1475                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1476                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1477         }else
1478         {
1479                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1480         }
1481         offset = 0;
1482         for(i = 0; i < n_chan; i++)
1483         {
1484                 chan = CR_CHAN(list[i]);
1485                 aref = CR_AREF(list[i]);
1486                 range = CR_RANGE(list[i]);
1487                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1488
1489                 range_code = ni_gainlkup[boardtype.gainlkup][range];
1490                 devpriv->ai_offset[i] = offset;
1491
1492                 switch( aref )
1493                 {
1494                         case AREF_DIFF:
1495                                 config_bits |= MSeries_AI_Config_Channel_Type_Differential_Bits;
1496                                 break;
1497                         case AREF_COMMON:
1498                                 config_bits |= MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1499                                 break;
1500                         case AREF_GROUND:
1501                                 config_bits |= MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1502                                 break;
1503                         case AREF_OTHER:
1504                                 break;
1505                 }
1506                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1507                 config_bits |= MSeries_AI_Config_Bank_Bits(chan);
1508                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1509                 if(i == n_chan - 1) config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1510                 if(dither) config_bits |= MSeries_AI_Config_Dither_Bit;
1511                 // don't use 2's complement encoding
1512                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1513                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1514         }
1515         ni_prime_channelgain_list(dev);
1516 }
1517
1518 /*
1519  * Notes on the 6110 and 6111:
1520  * These boards a slightly different than the rest of the series, since
1521  * they have multiple A/D converters.
1522  * From the driver side, the configuration memory is a
1523  * little different.
1524  * Configuration Memory Low:
1525  *   bits 15-9: same
1526  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1527  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1528  *       1001 gain=0.1 (+/- 50)
1529  *       1010 0.2
1530  *       1011 0.1
1531  *       0001 1
1532  *       0010 2
1533  *       0011 5
1534  *       0100 10
1535  *       0101 20
1536  *       0110 50
1537  * Configuration Memory High:
1538  *   bits 12-14: Channel Type
1539  *       001 for differential
1540  *       000 for calibration
1541  *   bit 11: coupling  (this is not currently handled)
1542  *       1 AC coupling
1543  *       0 DC coupling
1544  *   bits 0-2: channel
1545  *       valid channels are 0-3
1546  */
1547 static void ni_load_channelgain_list(comedi_device *dev,unsigned int n_chan,
1548         unsigned int *list)
1549 {
1550         unsigned int chan,range,aref;
1551         unsigned int i;
1552         unsigned int hi,lo;
1553         unsigned offset;
1554         unsigned int dither;
1555
1556         if(boardtype.reg_type == ni_reg_m_series)
1557         {
1558                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1559                 return;
1560         }
1561         if(n_chan == 1 && (boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1562                 if(devpriv->changain_state && devpriv->changain_spec==list[0]){
1563                         // ready to go.
1564                         return;
1565                 }
1566                 devpriv->changain_state=1;
1567                 devpriv->changain_spec=list[0];
1568         }else{
1569                 devpriv->changain_state=0;
1570         }
1571
1572         devpriv->stc_writew(dev, 1,Configuration_Memory_Clear);
1573
1574         // Set up Calibration mode if required
1575         if(boardtype.reg_type == ni_reg_6143){
1576                 if((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled){
1577                         // Strobe Relay enable bit
1578                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOn, Calibration_Channel_6143);
1579                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1580                         devpriv->ai_calib_source_enabled = 1;
1581                         msleep_interruptible(100);      // Allow relays to change
1582                 }
1583                 else if(!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled){
1584                         // Strobe Relay disable bit
1585                         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, Calibration_Channel_6143);
1586                         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1587                         devpriv->ai_calib_source_enabled = 0;
1588                         msleep_interruptible(100);      // Allow relays to change
1589                 }
1590         }
1591
1592         offset=1<<(boardtype.adbits-1);
1593         for(i=0;i<n_chan;i++){
1594                 if((boardtype.reg_type != ni_reg_6143) && (list[i] & CR_ALT_SOURCE)){
1595                         chan=devpriv->ai_calib_source;
1596                 }else{
1597                         chan=CR_CHAN(list[i]);
1598                 }
1599                 aref=CR_AREF(list[i]);
1600                 range=CR_RANGE(list[i]);
1601                 dither=((list[i]&CR_ALT_FILTER)!=0);
1602
1603                 /* fix the external/internal range differences */
1604                 range = ni_gainlkup[boardtype.gainlkup][range];
1605                 if(boardtype.reg_type == ni_reg_611x)
1606                         devpriv->ai_offset[i] = offset;
1607                 else
1608                         devpriv->ai_offset[i] = (range&0x100)?0:offset;
1609
1610                 hi = 0;
1611                 if( ( list[i] & CR_ALT_SOURCE ) )
1612                 {
1613                         if(boardtype.reg_type == ni_reg_611x)
1614                                 ni_writew(CR_CHAN(list[i])&0x0003, Calibration_Channel_Select_611x);
1615                 }else
1616                 {
1617                         if(boardtype.reg_type == ni_reg_611x)
1618                                 aref = AREF_DIFF;
1619                         else if(boardtype.reg_type == ni_reg_6143)
1620                                 aref = AREF_OTHER;
1621                         switch( aref )
1622                         {
1623                                 case AREF_DIFF:
1624                                         hi |= AI_DIFFERENTIAL;
1625                                         break;
1626                                 case AREF_COMMON:
1627                                         hi |= AI_COMMON;
1628                                         break;
1629                                 case AREF_GROUND:
1630                                         hi |= AI_GROUND;
1631                                         break;
1632                                 case AREF_OTHER:
1633                                         break;
1634                         }
1635                 }
1636                 hi |= AI_CONFIG_CHANNEL( chan );
1637
1638                 ni_writew(hi,Configuration_Memory_High);
1639
1640                 if(boardtype.reg_type != ni_reg_6143){
1641                         lo = range;
1642                         if(i == n_chan - 1) lo |= AI_LAST_CHANNEL;
1643                         if( dither ) lo |= AI_DITHER;
1644
1645                         ni_writew(lo,Configuration_Memory_Low);
1646                 }
1647         }
1648
1649         /* prime the channel/gain list */
1650         if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1651                 ni_prime_channelgain_list(dev);
1652         }
1653 }
1654
1655 static int ni_ns_to_timer(comedi_device *dev, int *nanosec, int round_mode)
1656 {
1657         int divider;
1658         switch(round_mode)
1659         {
1660         case TRIG_ROUND_NEAREST:
1661         default:
1662                 divider = (*nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
1663                 break;
1664         case TRIG_ROUND_DOWN:
1665                 divider = (*nanosec) / devpriv->clock_ns;
1666                 break;
1667         case TRIG_ROUND_UP:
1668                 divider=(*nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
1669                 break;
1670         }
1671
1672         *nanosec = devpriv->clock_ns * divider;
1673         return divider - 1;
1674 }
1675
1676 static int ni_ai_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
1677 {
1678         int err=0;
1679         int tmp;
1680         int sources;
1681
1682         /* step 1: make sure trigger sources are trivially valid */
1683
1684         tmp=cmd->start_src;
1685         cmd->start_src &= TRIG_NOW|TRIG_INT|TRIG_EXT;
1686         if(!cmd->start_src || tmp!=cmd->start_src)err++;
1687
1688         tmp=cmd->scan_begin_src;
1689         cmd->scan_begin_src &= TRIG_TIMER|TRIG_EXT;
1690         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
1691
1692         tmp=cmd->convert_src;
1693         sources = TRIG_TIMER | TRIG_EXT;
1694         if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)) sources |= TRIG_NOW;
1695         cmd->convert_src &= sources;
1696         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
1697
1698         tmp=cmd->scan_end_src;
1699         cmd->scan_end_src &= TRIG_COUNT;
1700         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
1701
1702         tmp=cmd->stop_src;
1703         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
1704         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
1705
1706         if(err)return 1;
1707
1708         /* step 2: make sure trigger sources are unique and mutually compatible */
1709
1710         /* note that mutual compatiblity is not an issue here */
1711         if(cmd->start_src!=TRIG_NOW &&
1712            cmd->start_src!=TRIG_INT &&
1713            cmd->start_src!=TRIG_EXT)err++;
1714         if(cmd->scan_begin_src!=TRIG_TIMER &&
1715            cmd->scan_begin_src!=TRIG_EXT &&
1716            cmd->scan_begin_src!=TRIG_OTHER)err++;
1717         if(cmd->convert_src!=TRIG_TIMER &&
1718            cmd->convert_src!=TRIG_EXT &&
1719            cmd->convert_src!=TRIG_NOW)err++;
1720         if(cmd->stop_src!=TRIG_COUNT &&
1721            cmd->stop_src!=TRIG_NONE)err++;
1722
1723         if(err)return 2;
1724
1725         /* step 3: make sure arguments are trivially compatible */
1726
1727         if(cmd->start_src==TRIG_EXT){
1728                 /* external trigger */
1729                 unsigned int tmp = CR_CHAN(cmd->start_arg);
1730
1731                 if(tmp > 16) tmp = 16;
1732                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
1733                 if(cmd->start_arg != tmp){
1734                         cmd->start_arg = tmp;
1735                         err++;
1736                 }
1737         }else{
1738                 if(cmd->start_arg!=0){
1739                         /* true for both TRIG_NOW and TRIG_INT */
1740                         cmd->start_arg=0;
1741                         err++;
1742                 }
1743         }
1744         if(cmd->scan_begin_src==TRIG_TIMER){
1745                 if(cmd->scan_begin_arg<boardtype.ai_speed){
1746                         cmd->scan_begin_arg=boardtype.ai_speed;
1747                         err++;
1748                 }
1749                 if(cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff){
1750                         cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
1751                         err++;
1752                 }
1753         }else if(cmd->scan_begin_src==TRIG_EXT){
1754                 /* external trigger */
1755                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
1756
1757                 if(tmp>16)tmp=16;
1758                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
1759                 if(cmd->scan_begin_arg!=tmp){
1760                         cmd->scan_begin_arg = tmp;
1761                         err++;
1762                 }
1763         }else{ /* TRIG_OTHER */
1764                 if(cmd->scan_begin_arg){
1765                         cmd->scan_begin_arg=0;
1766                         err++;
1767                 }
1768         }
1769         if(cmd->convert_src==TRIG_TIMER){
1770                 if((boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1771                         if(cmd->convert_arg != 0){
1772                                 cmd->convert_arg = 0;
1773                                 err++;
1774                         }
1775                 }else{
1776                         if(cmd->convert_arg<boardtype.ai_speed){
1777                                 cmd->convert_arg=boardtype.ai_speed;
1778                                 err++;
1779                         }
1780                         if(cmd->convert_arg>devpriv->clock_ns*0xffff){
1781                                 cmd->convert_arg=devpriv->clock_ns*0xffff;
1782                                 err++;
1783                         }
1784                 }
1785         }else if(cmd->convert_src == TRIG_EXT){
1786                 /* external trigger */
1787                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
1788
1789                 if(tmp>16)tmp=16;
1790                 tmp |= (cmd->convert_arg&(CR_ALT_FILTER|CR_INVERT));
1791                 if(cmd->convert_arg!=tmp){
1792                         cmd->convert_arg = tmp;
1793                         err++;
1794                 }
1795         }else if(cmd->convert_src == TRIG_NOW){
1796                 if(cmd->convert_arg != 0){
1797                         cmd->convert_arg = 0;
1798                         err++;
1799                 }
1800         }
1801
1802         if(cmd->scan_end_arg!=cmd->chanlist_len){
1803                 cmd->scan_end_arg=cmd->chanlist_len;
1804                 err++;
1805         }
1806         if(cmd->stop_src==TRIG_COUNT){
1807                 unsigned int max_count = 0x01000000;
1808
1809                 if(boardtype.reg_type == ni_reg_611x )
1810                         max_count -= num_adc_stages_611x;
1811                 if(cmd->stop_arg > max_count){
1812                         cmd->stop_arg = max_count;
1813                         err++;
1814                 }
1815                 if(cmd->stop_arg < 1){
1816                         cmd->stop_arg = 1;
1817                         err++;
1818                 }
1819         }else{
1820                 /* TRIG_NONE */
1821                 if(cmd->stop_arg!=0){
1822                         cmd->stop_arg=0;
1823                         err++;
1824                 }
1825         }
1826
1827         if(err)return 3;
1828
1829         /* step 4: fix up any arguments */
1830
1831         if(cmd->scan_begin_src==TRIG_TIMER){
1832                 tmp=cmd->scan_begin_arg;
1833                 ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
1834                 if(tmp!=cmd->scan_begin_arg)err++;
1835         }
1836         if(cmd->convert_src==TRIG_TIMER){
1837                 if((boardtype.reg_type != ni_reg_611x) && (boardtype.reg_type != ni_reg_6143)){
1838                         tmp=cmd->convert_arg;
1839                         ni_ns_to_timer(dev, &cmd->convert_arg, cmd->flags&TRIG_ROUND_MASK);
1840                         if(tmp!=cmd->convert_arg)err++;
1841                         if(cmd->scan_begin_src==TRIG_TIMER &&
1842                         cmd->scan_begin_arg<cmd->convert_arg*cmd->scan_end_arg){
1843                                 cmd->scan_begin_arg=cmd->convert_arg*cmd->scan_end_arg;
1844                                 err++;
1845                         }
1846                 }
1847         }
1848
1849         if(err)return 4;
1850
1851         return 0;
1852 }
1853
1854 static int ni_ai_cmd(comedi_device *dev,comedi_subdevice *s)
1855 {
1856         comedi_cmd *cmd=&s->async->cmd;
1857         int timer;
1858         int mode1=0; /* mode1 is needed for both stop and convert */
1859         int mode2=0;
1860         int start_stop_select=0;
1861         unsigned int stop_count;
1862         int interrupt_a_enable=0;
1863
1864         MDPRINTK("ni_ai_cmd\n");
1865         if(dev->irq == 0)
1866         {
1867                 comedi_error(dev, "cannot run command without an irq");
1868                 return -EIO;
1869         }
1870         ni_flush_ai_fifo(dev);
1871
1872         ni_load_channelgain_list(dev,cmd->chanlist_len,cmd->chanlist);
1873
1874         /* start configuration */
1875         devpriv->stc_writew(dev, AI_Configuration_Start,Joint_Reset_Register);
1876
1877         /* disable analog triggering for now, since it
1878          * interferes with the use of pfi0 */
1879         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
1880         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
1881
1882         switch(cmd->start_src){
1883                 case TRIG_INT:
1884                 case TRIG_NOW:
1885                         devpriv->stc_writew(dev, AI_START2_Select(0)|
1886                                 AI_START1_Sync|AI_START1_Edge|AI_START1_Select(0),
1887                                 AI_Trigger_Select_Register);
1888                         break;
1889                 case TRIG_EXT:
1890                 {
1891                         int chan = CR_CHAN(cmd->start_arg);
1892                         unsigned int bits = AI_START2_Select(0)|
1893                                 AI_START1_Sync |
1894                                 AI_START1_Select(chan + 1);
1895
1896                         if(cmd->start_arg & CR_INVERT)
1897                                 bits |= AI_START1_Polarity;
1898                         if(cmd->start_arg & CR_EDGE)
1899                                 bits |= AI_START1_Edge;
1900                         devpriv->stc_writew(dev, bits, AI_Trigger_Select_Register);
1901                         break;
1902                 }
1903         }
1904
1905         mode2 &= ~AI_Pre_Trigger;
1906         mode2 &= ~AI_SC_Initial_Load_Source;
1907         mode2 &= ~AI_SC_Reload_Mode;
1908         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1909
1910         if(cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x) || (boardtype.reg_type == ni_reg_6143)){
1911                 start_stop_select |= AI_STOP_Polarity;
1912                 start_stop_select |= AI_STOP_Select( 31 ); // logic low
1913                 start_stop_select |= AI_STOP_Sync;
1914         }else
1915         {
1916                 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
1917         }
1918         devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1919
1920         devpriv->ai_cmd2 = 0;
1921         switch(cmd->stop_src){
1922         case TRIG_COUNT:
1923                 stop_count = cmd->stop_arg - 1;
1924
1925                 if(boardtype.reg_type == ni_reg_611x){
1926                         // have to take 3 stage adc pipeline into account
1927                         stop_count += num_adc_stages_611x;
1928                 }
1929                 /* stage number of scans */
1930                 devpriv->stc_writel(dev,  stop_count, AI_SC_Load_A_Registers);
1931
1932                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
1933                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1934                 /* load SC (Scan Count) */
1935                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1936
1937                 devpriv->ai_continuous = 0;
1938                 if( stop_count == 0 ){
1939                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
1940                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
1941                         // this is required to get the last sample for chanlist_len > 1, not sure why
1942                         if(cmd->chanlist_len > 1)
1943                                 start_stop_select |= AI_STOP_Polarity | AI_STOP_Edge;
1944                 }
1945                 break;
1946         case TRIG_NONE:
1947                 /* stage number of scans */
1948                 devpriv->stc_writel(dev, 0,AI_SC_Load_A_Registers);
1949
1950                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
1951                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
1952
1953                 /* load SC (Scan Count) */
1954                 devpriv->stc_writew(dev, AI_SC_Load,AI_Command_1_Register);
1955
1956                 devpriv->ai_continuous = 1;
1957
1958                 break;
1959         }
1960
1961         switch(cmd->scan_begin_src){
1962         case TRIG_TIMER:
1963                 /*
1964                         stop bits for non 611x boards
1965                         AI_SI_Special_Trigger_Delay=0
1966                         AI_Pre_Trigger=0
1967                         AI_START_STOP_Select_Register:
1968                         AI_START_Polarity=0 (?) rising edge
1969                         AI_START_Edge=1         edge triggered
1970                         AI_START_Sync=1 (?)
1971                         AI_START_Select=0               SI_TC
1972                         AI_STOP_Polarity=0              rising edge
1973                         AI_STOP_Edge=0          level
1974                         AI_STOP_Sync=1
1975                         AI_STOP_Select=19               external pin (configuration mem)
1976                  */
1977                 start_stop_select |= AI_START_Edge | AI_START_Sync;
1978                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
1979
1980                 mode2 |= AI_SI_Reload_Mode(0);
1981                 /* AI_SI_Initial_Load_Source=A */
1982                 mode2 &= ~AI_SI_Initial_Load_Source;
1983                 //mode2 |= AI_SC_Reload_Mode;
1984                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
1985
1986                 /* load SI */
1987                 timer = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
1988                 devpriv->stc_writel(dev, timer,AI_SI_Load_A_Registers);
1989                 devpriv->stc_writew(dev, AI_SI_Load,AI_Command_1_Register);
1990                 break;
1991         case TRIG_EXT:
1992                 if( cmd->scan_begin_arg & CR_EDGE )
1993                         start_stop_select |= AI_START_Edge;
1994                 /* AI_START_Polarity==1 is falling edge */
1995                 if( cmd->scan_begin_arg & CR_INVERT )
1996                         start_stop_select |= AI_START_Polarity;
1997                 if( cmd->scan_begin_src != cmd->convert_src ||
1998                         ( cmd->scan_begin_arg & ~CR_EDGE ) != ( cmd->convert_arg & ~CR_EDGE ) )
1999                         start_stop_select |= AI_START_Sync;
2000                 start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2001                 devpriv->stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register);
2002                 break;
2003         }
2004
2005         switch(cmd->convert_src){
2006         case TRIG_TIMER:
2007         case TRIG_NOW:
2008                 if( cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW )
2009                         timer = 1;
2010                 else
2011                         timer = ni_ns_to_timer(dev, &cmd->convert_arg, TRIG_ROUND_NEAREST);
2012                 devpriv->stc_writew(dev, 1,AI_SI2_Load_A_Register); /* 0,0 does not work. */
2013                 devpriv->stc_writew(dev, timer,AI_SI2_Load_B_Register);
2014
2015                 /* AI_SI2_Reload_Mode = alternate */
2016                 /* AI_SI2_Initial_Load_Source = A */
2017                 mode2 &= ~AI_SI2_Initial_Load_Source;
2018                 mode2 |= AI_SI2_Reload_Mode;
2019                 devpriv->stc_writew(dev,  mode2, AI_Mode_2_Register);
2020
2021                 /* AI_SI2_Load */
2022                 devpriv->stc_writew(dev, AI_SI2_Load,AI_Command_1_Register);
2023
2024                 mode2 |= AI_SI2_Reload_Mode; // alternate
2025                 mode2 |= AI_SI2_Initial_Load_Source; // B
2026
2027                 devpriv->stc_writew(dev, mode2,AI_Mode_2_Register);
2028                 break;
2029         case TRIG_EXT:
2030                 mode1 |= AI_CONVERT_Source_Select(1+cmd->convert_arg);
2031                 if( ( cmd->convert_arg & CR_INVERT ) == 0 )
2032                         mode1 |= AI_CONVERT_Source_Polarity;
2033                 devpriv->stc_writew(dev, mode1,AI_Mode_1_Register);
2034
2035                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2036                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2037
2038                 break;
2039         }
2040
2041         if(dev->irq){
2042
2043                 /* interrupt on FIFO, errors, SC_TC */
2044                 interrupt_a_enable |= AI_Error_Interrupt_Enable|
2045                         AI_SC_TC_Interrupt_Enable;
2046
2047 #ifndef PCIDMA
2048                 interrupt_a_enable|=AI_FIFO_Interrupt_Enable;
2049 #endif
2050
2051                 if(cmd->flags & TRIG_WAKE_EOS || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)){
2052                         /* wake on end-of-scan */
2053                         devpriv->aimode=AIMODE_SCAN;
2054                 }else{
2055                         devpriv->aimode=AIMODE_HALF_FULL;
2056                 }
2057
2058                 switch(devpriv->aimode){
2059                 case AIMODE_HALF_FULL:
2060                         /*generate FIFO interrupts and DMA requests on half-full */
2061 #ifdef PCIDMA
2062                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, AI_Mode_3_Register);
2063 #else
2064                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2065 #endif
2066                         break;
2067                 case AIMODE_SAMPLE:
2068                         /*generate FIFO interrupts on non-empty */
2069                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2070                         break;
2071                 case AIMODE_SCAN:
2072 #ifdef PCIDMA
2073                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE, AI_Mode_3_Register);
2074 #else
2075                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF, AI_Mode_3_Register);
2076 #endif
2077                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2078                         break;
2079                 default:
2080                         break;
2081                 }
2082
2083                 devpriv->stc_writew(dev, 0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
2084
2085                 ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1);
2086
2087                 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",devpriv->int_a_enable_reg);
2088         }else{
2089                 /* interrupt on nothing */
2090                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2091
2092                 /* XXX start polling if necessary */
2093                 MDPRINTK("interrupting on nothing\n");
2094         }
2095
2096         /* end configuration */
2097         devpriv->stc_writew(dev, AI_Configuration_End,Joint_Reset_Register);
2098
2099         switch(cmd->scan_begin_src){
2100         case TRIG_TIMER:
2101                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2102                         AI_Command_1_Register);
2103                 break;
2104         case TRIG_EXT:
2105                 /* XXX AI_SI_Arm? */
2106                 devpriv->stc_writew(dev, AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2107                         AI_Command_1_Register);
2108                 break;
2109         }
2110
2111 #ifdef PCIDMA
2112         ni_ai_setup_MITE_dma(dev,cmd);
2113         //mite_dump_regs(devpriv->mite);
2114 #endif
2115
2116         switch(cmd->start_src){
2117         case TRIG_NOW:
2118                 /* AI_START1_Pulse */
2119                 devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2120                 s->async->inttrig=NULL;
2121                 break;
2122         case TRIG_EXT:
2123                 s->async->inttrig=NULL;
2124                 break;
2125         case TRIG_INT:
2126                 s->async->inttrig=ni_ai_inttrig;
2127                 break;
2128         }
2129
2130         MDPRINTK("exit ni_ai_cmd\n");
2131
2132         return 0;
2133 }
2134
2135 static int ni_ai_inttrig(comedi_device *dev,comedi_subdevice *s,
2136         unsigned int trignum)
2137 {
2138         if(trignum!=0)return -EINVAL;
2139
2140         devpriv->stc_writew(dev,  AI_START1_Pulse | devpriv->ai_cmd2, AI_Command_2_Register );
2141         s->async->inttrig=NULL;
2142
2143         return 1;
2144 }
2145
2146 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2147         comedi_insn *insn, lsampl_t *data);
2148
2149 static int ni_ai_insn_config(comedi_device *dev,comedi_subdevice *s,
2150         comedi_insn *insn, lsampl_t *data)
2151 {
2152         if(insn->n<1)return -EINVAL;
2153
2154         switch(data[0]){
2155         case INSN_CONFIG_ANALOG_TRIG:
2156                 return ni_ai_config_analog_trig(dev,s,insn,data);
2157         case INSN_CONFIG_ALT_SOURCE:
2158                 if(boardtype.reg_type == ni_reg_m_series)
2159                 {
2160                         if(data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2161                                 MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask |
2162                                 MSeries_AO_Bypass_AO_Cal_Sel_Mask))
2163                         {
2164                                 return -EINVAL;
2165                         }
2166                         devpriv->ai_calib_source = data[1];
2167                 } else if(boardtype.reg_type == ni_reg_6143)
2168                 {
2169                         unsigned int calib_source;
2170
2171                         calib_source = data[1] & 0xf;
2172
2173
2174                         if(calib_source > 0xF)
2175                                 return -EINVAL;
2176
2177                         devpriv->ai_calib_source = calib_source;
2178                         ni_writew(calib_source, Calibration_Channel_6143);
2179                 }else
2180                 {
2181                         unsigned int calib_source;
2182                         unsigned int calib_source_adjust;
2183
2184                         calib_source = data[1] & 0xf;
2185                         calib_source_adjust = ( data[1] >> 4 ) & 0xff;
2186
2187                         if(calib_source >= 8)
2188                                 return -EINVAL;
2189                         devpriv->ai_calib_source = calib_source;
2190                         if(boardtype.reg_type == ni_reg_611x){
2191                                 ni_writeb( calib_source_adjust, Cal_Gain_Select_611x );
2192                         }
2193                 }
2194                 return 2;
2195         default:
2196                 break;
2197         }
2198
2199         return -EINVAL;
2200 }
2201
2202 static int ni_ai_config_analog_trig(comedi_device *dev,comedi_subdevice *s,
2203         comedi_insn *insn, lsampl_t *data)
2204 {
2205         unsigned int a,b,modebits;
2206         int err=0;
2207
2208         /* data[1] is flags
2209          * data[2] is analog line
2210          * data[3] is set level
2211          * data[4] is reset level */
2212         if(!boardtype.has_analog_trig)return -EINVAL;
2213         if((data[1]&0xffff0000) != COMEDI_EV_SCAN_BEGIN){
2214                 data[1]&= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2215                 err++;
2216         }
2217         if(data[2]>=boardtype.n_adchan){
2218                 data[2]=boardtype.n_adchan-1;
2219                 err++;
2220         }
2221         if(data[3]>255){ /* a */
2222                 data[3]=255;
2223                 err++;
2224         }
2225         if(data[4]>255){ /* b */
2226                 data[4]=255;
2227                 err++;
2228         }
2229         /*
2230          * 00 ignore
2231          * 01 set
2232          * 10 reset
2233          *
2234          * modes:
2235          *   1 level:                    +b-   +a-
2236          *     high mode                00 00 01 10
2237          *     low mode                 00 00 10 01
2238          *   2 level: (a<b)
2239          *     hysteresis low mode      10 00 00 01
2240          *     hysteresis high mode     01 00 00 10
2241          *     middle mode              10 01 01 10
2242          */
2243
2244         a=data[3];
2245         b=data[4];
2246         modebits=data[1]&0xff;
2247         if(modebits&0xf0){
2248                 /* two level mode */
2249                 if(b<a){
2250                         /* swap order */
2251                         a=data[4];
2252                         b=data[3];
2253                         modebits=((data[1]&0xf)<<4)|((data[1]&0xf0)>>4);
2254                 }
2255                 devpriv->atrig_low = a;
2256                 devpriv->atrig_high = b;
2257                 switch(modebits){
2258                 case 0x81:      /* low hysteresis mode */
2259                         devpriv->atrig_mode = 6;
2260                         break;
2261                 case 0x42:      /* high hysteresis mode */
2262                         devpriv->atrig_mode = 3;
2263                         break;
2264                 case 0x96:      /* middle window mode */
2265                         devpriv->atrig_mode = 2;
2266                         break;
2267                 default:
2268                         data[1]&=~0xff;
2269                         err++;
2270                 }
2271         }else{
2272                 /* one level mode */
2273                 if(b!=0){
2274                         data[4]=0;
2275                         err++;
2276                 }
2277                 switch(modebits){
2278                 case 0x06:      /* high window mode */
2279                         devpriv->atrig_high = a;
2280                         devpriv->atrig_mode = 0;
2281                         break;
2282                 case 0x09:      /* low window mode */
2283                         devpriv->atrig_low = a;
2284                         devpriv->atrig_mode = 1;
2285                         break;
2286                 default:
2287                         data[1]&=~0xff;
2288                         err++;
2289                 }
2290         }
2291         if(err)return -EAGAIN;
2292         return 5;
2293 }
2294
2295 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2296 static void ni_ao_munge(comedi_device *dev, comedi_subdevice *s,
2297         void *data, unsigned int num_bytes, unsigned int chan_index )
2298 {
2299         comedi_async *async = s->async;
2300         unsigned int range;
2301         unsigned int i;
2302         unsigned int offset;
2303         unsigned int length = num_bytes / sizeof( sampl_t );
2304         sampl_t *array = data;
2305
2306         offset = 1 << (boardtype.aobits - 1);
2307         for(i = 0; i < length; i++)
2308         {
2309                 range = CR_RANGE( async->cmd.chanlist[ chan_index ] );
2310                 if(boardtype.ao_unipolar == 0 || (range & 1) == 0 )
2311                         array[i] -= offset;
2312 #ifdef PCIDMA
2313                 array[i] = cpu_to_le16( array[i] );
2314 #endif
2315                 chan_index++;
2316                 chan_index %= async->cmd.chanlist_len;
2317         }
2318 }
2319
2320 static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2321         unsigned int chanspec[], unsigned int n_chans, int timed)
2322 {
2323         unsigned int range;
2324         unsigned int chan;
2325         unsigned int conf;
2326         int i;
2327         int invert = 0;
2328
2329         for(i = 0; i < boardtype.n_aochan; ++i)
2330         {
2331                 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2332         }
2333         for(i=0;i<n_chans;i++)
2334         {
2335                 comedi_krange *krange;
2336                 chan = CR_CHAN(chanspec[i]);
2337                 range = CR_RANGE(chanspec[i]);
2338                 krange = s->range_table->range + range;
2339                 invert = 0;
2340                 conf = 0;
2341                 switch(krange->max - krange->min)
2342                 {
2343                 case 20000000:
2344                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2345                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2346                         break;
2347                 case 10000000:
2348                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2349                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2350                         break;
2351                 case 4000000:
2352                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2353                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2354                         break;
2355                 case 2000000:
2356                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2357                         ni_writeb(MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan));
2358                         break;
2359                 default:
2360                         rt_printk("%s: bug! unhandled ao reference voltage\n", __FUNCTION__);
2361                         break;
2362                 }
2363                 switch(krange->max + krange->min)
2364                 {
2365                 case 0:
2366                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2367                         break;
2368                 case 10000000:
2369                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2370                         break;
2371                 default:
2372                         rt_printk("%s: bug! unhandled ao offset voltage\n", __FUNCTION__);
2373                         break;
2374                 }
2375                 if(timed) conf |= MSeries_AO_Update_Timed_Bit;
2376                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2377                 devpriv->ao_conf[chan] = conf;
2378                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2379         }
2380         return invert;
2381 }
2382
2383 static int ni_old_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2384         unsigned int chanspec[], unsigned int n_chans)
2385 {
2386         unsigned int range;
2387         unsigned int chan;
2388         unsigned int conf;
2389         int i;
2390         int invert = 0;
2391
2392         for(i=0;i<n_chans;i++)
2393         {
2394                 chan = CR_CHAN(chanspec[i]);
2395                 range = CR_RANGE(chanspec[i]);
2396                 conf = AO_Channel(chan);
2397
2398                 if(boardtype.ao_unipolar){
2399                         if((range&1) == 0){
2400                                 conf |= AO_Bipolar;
2401                                 invert = (1<<(boardtype.aobits-1));
2402                         }else{
2403                                 invert = 0;
2404                         }
2405                         if(range&2)
2406                                 conf |= AO_Ext_Ref;
2407                 }else{
2408                         conf |= AO_Bipolar;
2409                         invert = (1<<(boardtype.aobits-1));
2410                 }
2411
2412                 /* not all boards can deglitch, but this shouldn't hurt */
2413                 if(chanspec[i] & CR_DEGLITCH)
2414                         conf |= AO_Deglitch;
2415
2416                 /* analog reference */
2417                 /* AREF_OTHER connects AO ground to AI ground, i think */
2418                 conf |= (CR_AREF(chanspec[i])==AREF_OTHER)? AO_Ground_Ref : 0;
2419
2420                 ni_writew(conf,AO_Configuration);
2421                 devpriv->ao_conf[chan] = conf;
2422         }
2423         return invert;
2424 }
2425
2426 static int ni_ao_config_chanlist(comedi_device *dev, comedi_subdevice *s,
2427         unsigned int chanspec[], unsigned int n_chans, int timed)
2428 {
2429         if(boardtype.reg_type == ni_reg_m_series)
2430                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed);
2431         else
2432                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2433 }
2434 static int ni_ao_insn_read(comedi_device *dev,comedi_subdevice *s,
2435         comedi_insn *insn,lsampl_t *data)
2436 {
2437         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2438
2439         return 1;
2440 }
2441
2442 static int ni_ao_insn_write(comedi_device *dev,comedi_subdevice *s,
2443         comedi_insn *insn,lsampl_t *data)
2444 {
2445         unsigned int chan = CR_CHAN(insn->chanspec);
2446         unsigned int invert;
2447
2448         invert = ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2449
2450         devpriv->ao[chan] = data[0];
2451
2452         if(boardtype.reg_type == ni_reg_m_series)
2453         {
2454                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2455         }
2456         else
2457                 ni_writew(data[0] ^ invert,(chan)? DAC1_Direct_Data : DAC0_Direct_Data);
2458
2459         return 1;
2460 }
2461
2462 static int ni_ao_insn_write_671x(comedi_device *dev,comedi_subdevice *s,
2463         comedi_insn *insn,lsampl_t *data)
2464 {
2465         unsigned int chan = CR_CHAN(insn->chanspec);
2466         unsigned int invert;
2467
2468         ao_win_out(1 << chan, AO_Immediate_671x);
2469         invert = 1 << (boardtype.aobits - 1);
2470
2471         ni_ao_config_chanlist(dev,s,&insn->chanspec, 1, 0);
2472
2473         devpriv->ao[chan] = data[0];
2474         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2475
2476         return 1;
2477 }
2478
2479 static int ni_ao_inttrig(comedi_device *dev,comedi_subdevice *s,
2480         unsigned int trignum)
2481 {
2482         int ret;
2483         int interrupt_b_bits;
2484         int i;
2485         static const int timeout = 1000;
2486
2487         if(trignum!=0)return -EINVAL;
2488
2489         ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2490         interrupt_b_bits = AO_Error_Interrupt_Enable;
2491 #ifdef PCIDMA
2492         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2493         if(boardtype.reg_type & ni_reg_6xxx_mask)
2494                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2495         ni_ao_setup_MITE_dma(dev, &s->async->cmd);
2496         ret = ni_ao_wait_for_dma_load(dev);
2497         if(ret < 0) return ret;
2498
2499 #else
2500         ret = ni_ao_prep_fifo(dev,s);
2501         if(ret==0)return -EPIPE;
2502
2503         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2504 #endif
2505
2506         devpriv->stc_writew(dev, devpriv->ao_mode3|AO_Not_An_UPDATE,AO_Mode_3_Register);
2507         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2508         /* wait for DACs to be loaded */
2509         for(i = 0; i < timeout; i++)
2510         {
2511                 comedi_udelay(1);
2512                 if((devpriv->stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0)
2513                         break;
2514         }
2515         if(i == timeout)
2516         {
2517                 comedi_error(dev, "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
2518                 return -EIO;
2519         }
2520         // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
2521         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register);
2522
2523         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
2524
2525         devpriv->stc_writew(dev, devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
2526                 AO_Command_1_Register);
2527
2528         devpriv->stc_writew(dev, devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register);
2529
2530         s->async->inttrig=NULL;
2531
2532         return 0;
2533 }
2534
2535 static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s)
2536 {
2537         comedi_cmd *cmd = &s->async->cmd;
2538         int trigvar;
2539         int bits;
2540         int i;
2541
2542         if(dev->irq == 0)
2543         {
2544                 comedi_error(dev, "cannot run command without an irq");
2545                 return -EIO;
2546         }
2547         trigvar = ni_ns_to_timer(dev, &cmd->scan_begin_arg, TRIG_ROUND_NEAREST);
2548
2549         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2550
2551         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2552
2553         if(boardtype.reg_type & ni_reg_6xxx_mask)
2554         {
2555                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2556
2557                 bits = 0;
2558                 for(i = 0; i < cmd->chanlist_len; i++)
2559                 {
2560                         int chan;
2561
2562                         chan = CR_CHAN(cmd->chanlist[i]);
2563                         bits |= 1 << chan;
2564                         ao_win_out(chan, AO_Waveform_Generation_611x);
2565                 }
2566                 ao_win_out(bits, AO_Timed_611x);
2567         }
2568
2569         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2570
2571         if(cmd->stop_src==TRIG_NONE){
2572                 devpriv->ao_mode1|=AO_Continuous;
2573                 devpriv->ao_mode1&=~AO_Trigger_Once;
2574         }else{
2575                 devpriv->ao_mode1&=~AO_Continuous;
2576                 devpriv->ao_mode1|=AO_Trigger_Once;
2577         }
2578         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2579         devpriv->ao_trigger_select&=~(AO_START1_Polarity|AO_START1_Select(-1));
2580         devpriv->ao_trigger_select|=AO_START1_Edge|AO_START1_Sync;
2581         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2582         devpriv->ao_mode3&=~AO_Trigger_Length;
2583         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2584
2585         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2586         devpriv->ao_mode2&=~AO_BC_Initial_Load_Source;
2587         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2588         if(cmd->stop_src==TRIG_NONE){
2589                 devpriv->stc_writel(dev, 0xffffff,AO_BC_Load_A_Register);
2590         }else{
2591                 devpriv->stc_writel(dev, 0,AO_BC_Load_A_Register);
2592         }
2593         devpriv->stc_writew(dev, AO_BC_Load,AO_Command_1_Register);
2594         devpriv->ao_mode2&=~AO_UC_Initial_Load_Source;
2595         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2596         switch(cmd->stop_src){
2597         case TRIG_COUNT:
2598                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2599                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2600                 devpriv->stc_writel(dev, cmd->stop_arg - 1,AO_UC_Load_A_Register);
2601                 break;
2602         case TRIG_NONE:
2603                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2604                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2605                 devpriv->stc_writel(dev, 0xffffff,AO_UC_Load_A_Register);
2606                 break;
2607         default:
2608                 devpriv->stc_writel(dev, 0,AO_UC_Load_A_Register);
2609                 devpriv->stc_writew(dev, AO_UC_Load,AO_Command_1_Register);
2610                 devpriv->stc_writel(dev, cmd->stop_arg,AO_UC_Load_A_Register);
2611         }
2612
2613         devpriv->ao_cmd2&=~AO_BC_Gate_Enable;
2614         devpriv->stc_writew(dev, devpriv->ao_cmd2,AO_Command_2_Register);
2615         devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity);
2616         devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2617         devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source);
2618         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2619         devpriv->stc_writel(dev, 1,AO_UI_Load_A_Register);
2620         devpriv->stc_writew(dev, AO_UI_Load,AO_Command_1_Register);
2621         devpriv->stc_writel(dev, trigvar,AO_UI_Load_A_Register);
2622
2623         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
2624                 if(cmd->scan_end_arg>1){
2625                         devpriv->ao_mode1|=AO_Multiple_Channels;
2626                         devpriv->stc_writew(dev, AO_Number_Of_Channels(cmd->scan_end_arg-1)|
2627                                 AO_UPDATE_Output_Select(1),
2628                                 AO_Output_Control_Register);
2629                 }else{
2630                         unsigned bits;
2631                         devpriv->ao_mode1&=~AO_Multiple_Channels;
2632                         bits = AO_UPDATE_Output_Select(1);
2633                         if(boardtype.reg_type == ni_reg_m_series)
2634                                 bits |= AO_Number_Of_Channels(0);
2635                         else
2636                                 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
2637                         devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
2638                 }
2639                 devpriv->stc_writew(dev, devpriv->ao_mode1,AO_Mode_1_Register);
2640         }
2641
2642         devpriv->stc_writew(dev, AO_DAC0_Update_Mode|AO_DAC1_Update_Mode,AO_Command_1_Register);
2643
2644         devpriv->ao_mode3|=AO_Stop_On_Overrun_Error;
2645         devpriv->stc_writew(dev, devpriv->ao_mode3,AO_Mode_3_Register);
2646
2647         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
2648 #ifdef PCIDMA
2649         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
2650 #else
2651         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
2652 #endif
2653         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
2654         devpriv->stc_writew(dev, devpriv->ao_mode2,AO_Mode_2_Register);
2655
2656         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2657                 AO_TMRDACWR_Pulse_Width;
2658         if( boardtype.ao_fifo_depth )
2659                 bits |= AO_FIFO_Enable;
2660         else
2661                 bits |= AO_DMA_PIO_Control;
2662         if(boardtype.reg_type == ni_reg_m_series)
2663                 bits |= AO_Number_Of_DAC_Packages/* | AO_Multiple_DACS_Per_Package*/;
2664         devpriv->stc_writew(dev, bits, AO_Personal_Register);
2665         // enable sending of ao dma requests
2666         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
2667
2668         devpriv->stc_writew(dev, AO_Configuration_End,Joint_Reset_Register);
2669
2670         if(cmd->stop_src==TRIG_COUNT) {
2671                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,Interrupt_B_Ack_Register);
2672                 ni_set_bits(dev, Interrupt_B_Enable_Register,
2673                         AO_BC_TC_Interrupt_Enable, 1);
2674         }
2675
2676         s->async->inttrig=ni_ao_inttrig;
2677
2678         return 0;
2679 }
2680
2681 static int ni_ao_cmdtest(comedi_device *dev,comedi_subdevice *s,comedi_cmd *cmd)
2682 {
2683         int err=0;
2684         int tmp;
2685
2686         /* step 1: make sure trigger sources are trivially valid */
2687
2688         tmp=cmd->start_src;
2689         cmd->start_src &= TRIG_INT;
2690         if(!cmd->start_src || tmp!=cmd->start_src)err++;
2691
2692         tmp=cmd->scan_begin_src;
2693         cmd->scan_begin_src &= TRIG_TIMER;
2694         if(!cmd->scan_begin_src || tmp!=cmd->scan_begin_src)err++;
2695
2696         tmp=cmd->convert_src;
2697         cmd->convert_src &= TRIG_NOW;
2698         if(!cmd->convert_src || tmp!=cmd->convert_src)err++;
2699
2700         tmp=cmd->scan_end_src;
2701         cmd->scan_end_src &= TRIG_COUNT;
2702         if(!cmd->scan_end_src || tmp!=cmd->scan_end_src)err++;
2703
2704         tmp=cmd->stop_src;
2705         cmd->stop_src &= TRIG_COUNT|TRIG_NONE;
2706         if(!cmd->stop_src || tmp!=cmd->stop_src)err++;
2707
2708         if(err)return 1;
2709
2710         /* step 2: make sure trigger sources are unique and mutually compatible */
2711
2712         if(cmd->stop_src!=TRIG_COUNT &&
2713            cmd->stop_src!=TRIG_NONE)err++;
2714
2715         if(err)return 2;
2716
2717         /* step 3: make sure arguments are trivially compatible */
2718
2719         if(cmd->start_arg!=0){
2720                 cmd->start_arg=0;
2721                 err++;
2722         }
2723 #if 0
2724         /* XXX need ao_speed */
2725         if(cmd->scan_begin_arg<boardtype.ao_speed){
2726                 cmd->scan_begin_arg=boardtype.ao_speed;
2727                 err++;
2728         }
2729 #endif
2730         if(cmd->scan_begin_arg>devpriv->clock_ns*0xffffff){ /* XXX check */
2731                 cmd->scan_begin_arg=devpriv->clock_ns*0xffffff;
2732                 err++;
2733         }
2734         if(cmd->convert_arg!=0){
2735                 cmd->convert_arg=0;
2736                 err++;
2737         }
2738         if(cmd->scan_end_arg!=cmd->chanlist_len){
2739                 cmd->scan_end_arg=cmd->chanlist_len;
2740                 err++;
2741         }
2742         if(cmd->stop_src==TRIG_COUNT){ /* XXX check */
2743                 if(cmd->stop_arg>0x00ffffff){
2744                         cmd->stop_arg=0x00ffffff;
2745                         err++;
2746                 }
2747         }else{
2748                 /* TRIG_NONE */
2749                 if(cmd->stop_arg!=0){
2750                         cmd->stop_arg=0;
2751                         err++;
2752                 }
2753         }
2754
2755         if(err)return 3;
2756
2757         /* step 4: fix up any arguments */
2758
2759         tmp = cmd->scan_begin_arg;
2760         ni_ns_to_timer(dev, &cmd->scan_begin_arg, cmd->flags&TRIG_ROUND_MASK);
2761         if(tmp!=cmd->scan_begin_arg)err++;
2762
2763         if(err)return 4;
2764
2765         /* step 5: fix up chanlist */
2766
2767         if(err)return 5;
2768
2769         return 0;
2770 }
2771
2772
2773 static int ni_ao_reset(comedi_device *dev,comedi_subdevice *s)
2774 {
2775         //devpriv->ao0p=0x0000;
2776         //ni_writew(devpriv->ao0p,AO_Configuration);
2777
2778         //devpriv->ao1p=AO_Channel(1);
2779         //ni_writew(devpriv->ao1p,AO_Configuration);
2780
2781 #ifdef PCIDMA
2782         mite_dma_disarm(devpriv->mite, AO_DMA_CHAN);
2783         writel(CHOR_DMARESET | CHOR_FRESET, devpriv->mite->mite_io_addr + MITE_CHOR(AO_DMA_CHAN));
2784 #endif
2785
2786         devpriv->stc_writew(dev, AO_Configuration_Start,Joint_Reset_Register);
2787         devpriv->stc_writew(dev, AO_Disarm,AO_Command_1_Register);
2788         ni_set_bits(dev,Interrupt_B_Enable_Register,~0,0);
2789         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
2790         devpriv->stc_writew(dev, 0x3f98,Interrupt_B_Ack_Register);
2791         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
2792                 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
2793         devpriv->stc_writew(dev, 0,AO_Output_Control_Register);
2794         devpriv->stc_writew(dev, 0,AO_Start_Select_Register);
2795         devpriv->ao_cmd1=0;
2796         devpriv->stc_writew(dev, devpriv->ao_cmd1,AO_Command_1_Register);
2797         devpriv->ao_cmd2=0;
2798         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
2799         devpriv->ao_mode1=0;
2800         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
2801         devpriv->ao_mode2=0;
2802         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
2803         if(boardtype.reg_type == ni_reg_m_series)
2804                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
2805         else
2806                 devpriv->ao_mode3 = 0;
2807         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2808         devpriv->ao_trigger_select = 0;
2809         devpriv->stc_writew(dev, devpriv->ao_trigger_select,AO_Trigger_Select_Register);
2810         if(boardtype.reg_type & ni_reg_6xxx_mask){
2811                 ao_win_out(0x3, AO_Immediate_671x);
2812                 ao_win_out(CLEAR_WG, AO_Misc_611x);
2813         }
2814         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
2815
2816         return 0;
2817 }
2818
2819 static int ni_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2820         comedi_insn *insn,lsampl_t *data)
2821 {
2822 #ifdef DEBUG_DIO
2823         rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
2824                 CR_CHAN(insn->chanspec),data[0]);
2825 #endif
2826         switch(data[0]){
2827         case INSN_CONFIG_DIO_OUTPUT:
2828                 s->io_bits |= 1<<CR_CHAN(insn->chanspec);
2829                 break;
2830         case INSN_CONFIG_DIO_INPUT:
2831                 s->io_bits &= ~(1<<CR_CHAN(insn->chanspec));
2832                 break;
2833         case INSN_CONFIG_DIO_QUERY:
2834                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2835                 return insn->n;
2836                 break;
2837         default:
2838                 return -EINVAL;
2839         }
2840
2841         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
2842         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
2843         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2844
2845         return 1;
2846 }
2847
2848 static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2849         comedi_insn *insn,lsampl_t *data)
2850 {
2851 #ifdef DEBUG_DIO
2852         rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2853 #endif
2854         if(insn->n!=2)return -EINVAL;
2855         if(data[0]){
2856                 /* Perform check to make sure we're not using the
2857                    serial part of the dio */
2858                 if((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
2859                         return -EBUSY;
2860
2861                 s->state &= ~data[0];
2862                 s->state |= (data[0]&data[1]);
2863                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
2864                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
2865                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
2866         }
2867         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
2868
2869         return 2;
2870 }
2871
2872 static int ni_m_series_dio_insn_config(comedi_device *dev,comedi_subdevice *s,
2873         comedi_insn *insn, lsampl_t *data)
2874 {
2875 #ifdef DEBUG_DIO
2876         rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
2877                 CR_CHAN(insn->chanspec), data[0]);
2878 #endif
2879         switch(data[0])
2880         {
2881         case INSN_CONFIG_DIO_OUTPUT:
2882                 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2883                 break;
2884         case INSN_CONFIG_DIO_INPUT:
2885                 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2886                 break;
2887         case INSN_CONFIG_DIO_QUERY:
2888                 data[1] = (s->io_bits & (1<<CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT : COMEDI_INPUT;
2889                 return insn->n;
2890                 break;
2891         default:
2892                 return -EINVAL;
2893         }
2894
2895         ni_writel(s->io_bits, M_Offset_DIO_Direction);
2896
2897         return 1;
2898 }
2899
2900 static int ni_m_series_dio_insn_bits(comedi_device *dev,comedi_subdevice *s,
2901         comedi_insn *insn, lsampl_t *data)
2902 {
2903 #ifdef DEBUG_DIO
2904         rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n",data[0],data[1]);
2905 #endif
2906         if(insn->n!=2)return -EINVAL;
2907         if(data[0]){
2908                 s->state &= ~data[0];
2909                 s->state |= (data[0] & data[1]);
2910                 ni_writel(s->state, M_Offset_Static_Digital_Output);
2911         }
2912         data[1] = ni_readl(M_Offset_Static_Digital_Input);
2913
2914         return 2;
2915 }
2916
2917 static int ni_serial_insn_config(comedi_device *dev,comedi_subdevice *s,
2918                                  comedi_insn *insn,lsampl_t *data)
2919 {
2920         int err = insn->n;
2921         unsigned char byte_out, byte_in;
2922
2923         if(insn->n!=2)return -EINVAL;
2924
2925         switch(data[0]) {
2926         case INSN_CONFIG_SERIAL_CLOCK:
2927
2928 #ifdef DEBUG_DIO
2929                 rt_printk("SPI serial clock Config cd\n", data[1]);
2930 #endif
2931                 devpriv->serial_hw_mode = 1;
2932                 devpriv->dio_control |= DIO_HW_Serial_Enable;
2933
2934                 if(data[1] == SERIAL_DISABLED) {
2935                         devpriv->serial_hw_mode = 0;
2936                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2937                                                   DIO_Software_Serial_Control);
2938                         data[1] = SERIAL_DISABLED;
2939                         devpriv->serial_interval_ns = data[1];
2940                 }
2941                 else if(data[1] <= SERIAL_600NS) {
2942                         /* Warning: this clock speed is too fast to reliably
2943                         control SCXI. */
2944                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2945                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
2946                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
2947                         data[1] = SERIAL_600NS;
2948                         devpriv->serial_interval_ns = data[1];
2949                 }
2950                 else if(data[1] <= SERIAL_1_2US) {
2951                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
2952                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2953                                 DIO_Serial_Out_Divide_By_2;
2954                         data[1] = SERIAL_1_2US;
2955                         devpriv->serial_interval_ns = data[1];
2956                 }
2957                 else if(data[1] <= SERIAL_10US) {
2958                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
2959                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
2960                                 DIO_Serial_Out_Divide_By_2;
2961                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
2962                         600ns/1.2us. If you turn divide_by_2 off with the
2963                         slow clock, you will still get 10us, except then
2964                         all your delays are wrong. */
2965                         data[1] = SERIAL_10US;
2966                         devpriv->serial_interval_ns = data[1];
2967                 }
2968                 else {
2969                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
2970                                                   DIO_Software_Serial_Control);
2971                         devpriv->serial_hw_mode = 0;
2972                         data[1] = (data[1] / 1000) * 1000;
2973                         devpriv->serial_interval_ns = data[1];
2974                 }
2975
2976                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
2977                 devpriv->stc_writew(dev, devpriv->clock_and_fout,Clock_and_FOUT_Register);
2978                 return 1;
2979
2980         break;
2981
2982         case INSN_CONFIG_BIDIRECTIONAL_DATA:
2983
2984                 if(devpriv->serial_interval_ns == 0) {
2985                         return -EINVAL;
2986                 }
2987
2988                 byte_out = data[1] & 0xFF;
2989
2990                 if(devpriv->serial_hw_mode) {
2991                         err = ni_serial_hw_readwrite8(dev,s,byte_out,&byte_in);
2992                 } else if(devpriv->serial_interval_ns > 0) {
2993                         err = ni_serial_sw_readwrite8(dev,s,byte_out,&byte_in);
2994                 } else {
2995                         rt_printk("ni_serial_insn_config: serial disabled!\n");
2996                         return -EINVAL;
2997                 }
2998                 if(err < 0) return err;
2999                 data[1] = byte_in & 0xFF;
3000                 return insn->n;
3001
3002         break;
3003         default:
3004                 return -EINVAL;
3005         }
3006
3007 }
3008
3009 static int ni_serial_hw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3010                                    unsigned char data_out,
3011                                    unsigned char *data_in)
3012 {
3013         unsigned int status1;
3014         int err = 0, count = 20;
3015
3016 #ifdef DEBUG_DIO
3017         rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3018 #endif
3019
3020         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3021         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3022         devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3023
3024         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3025         if(status1 & DIO_Serial_IO_In_Progress_St) {
3026                 err = -EBUSY;
3027                 goto Error;
3028         }
3029
3030         devpriv->dio_control |= DIO_HW_Serial_Start;
3031         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3032         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3033
3034         /* Wait until STC says we're done, but don't loop infinitely. */
3035         while((status1 = devpriv->stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) {
3036                 /* Delay one bit per loop */
3037                 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3038                 if(--count < 0) {
3039                         rt_printk("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3040                         err = -ETIME;
3041                         goto Error;
3042                 }
3043         }
3044
3045         /* Delay for last bit. This delay is absolutely necessary, because
3046            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3047         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3048
3049         if(data_in != NULL) {
3050                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3051 #ifdef DEBUG_DIO
3052                 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3053 #endif
3054         }
3055
3056  Error:
3057         devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3058
3059         return err;
3060 }
3061
3062 static int ni_serial_sw_readwrite8(comedi_device *dev,comedi_subdevice *s,
3063                                    unsigned char data_out,
3064                                    unsigned char *data_in)
3065 {
3066         unsigned char mask, input = 0;
3067
3068 #ifdef DEBUG_DIO
3069         rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3070 #endif
3071
3072         /* Wait for one bit before transfer */
3073         comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3074
3075         for(mask = 0x80; mask; mask >>= 1) {
3076                 /* Output current bit; note that we cannot touch s->state
3077            because it is a per-subdevice field, and serial is
3078                    a separate subdevice from DIO. */
3079                 devpriv->dio_output &= ~DIO_SDOUT;
3080                 if(data_out & mask) {
3081                         devpriv->dio_output |= DIO_SDOUT;
3082                 }
3083                 devpriv->stc_writew(dev, devpriv->dio_output,DIO_Output_Register);
3084
3085                 /* Assert SDCLK (active low, inverted), wait for half of
3086                    the delay, deassert SDCLK, and wait for the other half. */
3087                 devpriv->dio_control |= DIO_Software_Serial_Control;
3088                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3089
3090                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3091
3092                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3093                 devpriv->stc_writew(dev, devpriv->dio_control,DIO_Control_Register);
3094
3095                 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3096
3097                 /* Input current bit */
3098                 if(devpriv->stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) {
3099 /*                      rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3100                         input |= mask;
3101                 }
3102         }
3103 #ifdef DEBUG_DIO
3104         rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3105 #endif
3106         if(data_in) *data_in = input;
3107
3108         return 0;
3109 }
3110
3111 static void mio_common_detach(comedi_device *dev)
3112 {
3113         if(dev->subdevices && boardtype.has_8255)
3114                 subdev_8255_cleanup(dev,dev->subdevices+3);
3115 }
3116
3117 static void init_ao_67xx(comedi_device *dev, comedi_subdevice *s)
3118 {
3119         int i;
3120
3121         for(i = 0; i < s->n_chan; i++)
3122                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx);
3123 }
3124
3125 static int ni_alloc_private(comedi_device *dev)
3126 {
3127         int ret;
3128
3129         ret = alloc_private(dev, sizeof(ni_private));
3130         if(ret < 0) return ret;
3131
3132         spin_lock_init(&devpriv->window_lock);
3133
3134         return 0;
3135 };
3136
3137 static int ni_E_init(comedi_device *dev,comedi_devconfig *it)
3138 {
3139         comedi_subdevice *s;
3140         int bits;
3141
3142         if(boardtype.n_aochan > MAX_N_AO_CHAN)
3143         {
3144                 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
3145                 return -EINVAL;
3146         }
3147
3148         if(alloc_subdevices(dev, 11) < 0)
3149                 return -ENOMEM;
3150
3151         /* analog input subdevice */
3152
3153         s=dev->subdevices+0;
3154         dev->read_subdev=s;
3155         if(boardtype.n_adchan){
3156                 s->type=COMEDI_SUBD_AI;
3157                 s->subdev_flags=SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
3158                 if(boardtype.reg_type != ni_reg_611x)
3159                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
3160                 if(boardtype.adbits > 16)
3161                         s->subdev_flags |= SDF_LSAMPL;
3162                 if(boardtype.reg_type == ni_reg_m_series)
3163                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3164                 s->n_chan=boardtype.n_adchan;
3165                 s->len_chanlist=512;
3166                 s->maxdata=(1<<boardtype.adbits)-1;
3167                 s->range_table=ni_range_lkup[boardtype.gainlkup];
3168                 s->insn_read=ni_ai_insn_read;
3169                 s->insn_config=ni_ai_insn_config;
3170                 s->do_cmdtest=ni_ai_cmdtest;
3171                 s->do_cmd=ni_ai_cmd;
3172                 s->cancel=ni_ai_reset;
3173                 s->poll=ni_ai_poll;
3174                 s->munge=ni_ai_munge;
3175         }else{
3176                 s->type=COMEDI_SUBD_UNUSED;
3177         }
3178
3179         /* analog output subdevice */
3180
3181         s=dev->subdevices+1;
3182         if(boardtype.n_aochan){
3183                 s->type=COMEDI_SUBD_AO;
3184                 s->subdev_flags=SDF_WRITABLE|SDF_DEGLITCH|SDF_GROUND;
3185                 if(boardtype.reg_type == ni_reg_m_series)
3186                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
3187                 s->n_chan=boardtype.n_aochan;
3188                 s->maxdata=(1<<boardtype.aobits)-1;
3189                 s->range_table = boardtype.ao_range_table;
3190                 s->insn_read=ni_ao_insn_read;
3191                 if(boardtype.reg_type & ni_reg_6xxx_mask){
3192                         s->insn_write=ni_ao_insn_write_671x;
3193                 }else{
3194                         s->insn_write=ni_ao_insn_write;
3195                 }
3196 #ifdef PCIDMA
3197                 if(boardtype.n_aochan){
3198 #else
3199                 if(boardtype.ao_fifo_depth){
3200 #endif
3201                         dev->write_subdev=s;
3202                         s->subdev_flags |= SDF_CMD_WRITE;
3203                         s->do_cmd=ni_ao_cmd;
3204                         s->do_cmdtest=ni_ao_cmdtest;
3205                         s->len_chanlist = boardtype.n_aochan;
3206                         if(boardtype.reg_type != ni_reg_m_series)
3207                                 s->munge=ni_ao_munge;
3208                 }
3209                 s->cancel=ni_ao_reset;
3210         }else{
3211                 s->type=COMEDI_SUBD_UNUSED;
3212         }
3213         if((boardtype.reg_type & ni_reg_67xx_mask))
3214                 init_ao_67xx(dev, s);
3215
3216         /* digital i/o subdevice */
3217
3218         s=dev->subdevices+2;
3219         s->type=COMEDI_SUBD_DIO;
3220         s->subdev_flags=SDF_WRITABLE|SDF_READABLE;
3221         s->maxdata=1;
3222         s->io_bits=0;           /* all bits input */
3223         s->range_table=&range_digital;
3224         if(boardtype.reg_type == ni_reg_m_series)
3225         {
3226                 s->n_chan = 32;
3227                 s->insn_bits = ni_m_series_dio_insn_bits;
3228                 s->insn_config=ni_m_series_dio_insn_config;
3229                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3230         }else
3231         {
3232                 s->n_chan=8;
3233                 s->insn_bits=ni_dio_insn_bits;
3234                 s->insn_config=ni_dio_insn_config;
3235                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
3236                 ni_writew(devpriv->dio_control, DIO_Control_Register);
3237         }
3238
3239         /* 8255 device */
3240         s=dev->subdevices+3;
3241         if(boardtype.has_8255){
3242                 subdev_8255_init(dev,s,ni_8255_callback,(unsigned long)dev);
3243         }else{
3244                 s->type=COMEDI_SUBD_UNUSED;
3245         }
3246
3247         /* general purpose counter/timer device */
3248         s=dev->subdevices+4;
3249         s->type = COMEDI_SUBD_COUNTER;
3250         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_CMD_READ;
3251         s->insn_read = ni_gpct_insn_read;
3252         s->insn_write = ni_gpct_insn_write;
3253         s->insn_config = ni_gpct_insn_config;
3254         s->n_chan=2;
3255         s->maxdata=1;
3256         s->do_cmdtest = ni_gpct_cmdtest;
3257         s->do_cmd = ni_gpct_cmd;
3258         s->cancel = ni_gpct_cancel;
3259 //      s->poll=ni_gpct_poll;
3260 //      s->munge=ni_gpct_munge;
3261         devpriv->an_trig_etc_reg = 0;
3262         GPCT_Reset(dev,0);
3263         GPCT_Reset(dev,1);
3264
3265         /* calibration subdevice -- ai and ao */
3266         s=dev->subdevices+5;
3267         s->type=COMEDI_SUBD_CALIB;
3268         if(boardtype.reg_type == ni_reg_m_series)
3269         {
3270                 // internal PWM analog output used for AI nonlinearity calibration
3271                 s->subdev_flags = SDF_INTERNAL;
3272                 s->insn_config = &ni_m_series_pwm_config;
3273                 s->n_chan = 1;
3274                 s->maxdata = 0;
3275                 ni_writel(0x0, M_Offset_Cal_PWM);
3276         } else if(boardtype.reg_type == ni_reg_6143)
3277         {
3278                 // internal PWM analog output used for AI nonlinearity calibration
3279                 s->subdev_flags = SDF_INTERNAL;
3280                 s->insn_config = &ni_6143_pwm_config;
3281                 s->n_chan = 1;
3282                 s->maxdata = 0;
3283         }else
3284         {
3285                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
3286                 s->insn_read = &ni_calib_insn_read;
3287                 s->insn_write = &ni_calib_insn_write;
3288                 caldac_setup(dev, s);
3289         }
3290
3291         /* EEPROM */
3292         s=dev->subdevices+6;
3293         s->type=COMEDI_SUBD_MEMORY;
3294         s->subdev_flags=SDF_READABLE|SDF_INTERNAL;
3295         s->maxdata=0xff;
3296         if(boardtype.reg_type == ni_reg_m_series)
3297         {
3298                 s->n_chan = M_SERIES_EEPROM_SIZE;
3299                 s->insn_read = &ni_m_series_eeprom_insn_read;
3300         }else
3301         {
3302                 s->n_chan = 512;
3303                 s->insn_read = &ni_eeprom_insn_read;
3304         }
3305         /* PFI */
3306         s=dev->subdevices + 7;
3307         s->type = COMEDI_SUBD_DIO;
3308         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3309         if(boardtype.reg_type == ni_reg_m_series)
3310         {
3311                 unsigned i;
3312                 s->n_chan = 16;
3313                 ni_writew(s->state, M_Offset_PFI_DO);
3314                 for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i)
3315                 {
3316                         ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1));
3317                 }
3318         }else
3319         {
3320                 s->n_chan = 10;
3321         }
3322         s->maxdata = 1;
3323         s->insn_bits = ni_pfi_insn_bits;
3324         s->insn_config = ni_pfi_insn_config;
3325         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
3326
3327         /* cs5529 calibration adc */
3328         s = dev->subdevices + 8;
3329         if(boardtype.reg_type & ni_reg_67xx_mask)
3330         {
3331                 s->type = COMEDI_SUBD_AI;
3332                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
3333                 // one channel for each analog output channel
3334                 s->n_chan = boardtype.n_aochan;
3335                 s->maxdata = (1 << 16) - 1;
3336                 s->range_table = &range_unknown; /* XXX */
3337                 s->insn_read=cs5529_ai_insn_read;
3338                 s->insn_config=NULL;
3339                 init_cs5529(dev);
3340         }else
3341         {
3342                 s->type=COMEDI_SUBD_UNUSED;
3343         }
3344
3345         /* Serial */
3346         s=dev->subdevices+9;
3347         s->type=COMEDI_SUBD_SERIAL;
3348         s->subdev_flags=SDF_READABLE|SDF_WRITABLE|SDF_INTERNAL;
3349         s->n_chan=1;
3350         s->maxdata=0xff;
3351         s->insn_config = ni_serial_insn_config;
3352         devpriv->serial_interval_ns = 0;
3353         devpriv->serial_hw_mode = 0;
3354
3355         /* RTSI */
3356         s=dev->subdevices + 10;
3357         s->type = COMEDI_SUBD_DIO;
3358         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3359         s->n_chan = 8;
3360         s->maxdata = 1;
3361         s->insn_bits = ni_rtsi_insn_bits;
3362         s->insn_config = ni_rtsi_insn_config;
3363         ni_rtsi_init(dev);
3364
3365         /* ai configuration */
3366         ni_ai_reset(dev,dev->subdevices+0);
3367         if(boardtype.reg_type == ni_reg_m_series)
3368                 ni_m_series_adc_reset(dev);
3369         if((boardtype.reg_type & ni_reg_6xxx_mask) == 0){
3370                 // BEAM is this needed for PCI-6143 ??
3371                 devpriv->clock_and_fout =
3372                         Slow_Internal_Time_Divide_By_2 |
3373                         Slow_Internal_Timebase |
3374                         Clock_To_Board_Divide_By_2 |
3375                         Clock_To_Board |
3376                         AI_Output_Divide_By_2 |
3377                         AO_Output_Divide_By_2;
3378         }else{
3379                 devpriv->clock_and_fout =
3380                         Slow_Internal_Time_Divide_By_2 |
3381                         Slow_Internal_Timebase |
3382                         Clock_To_Board_Divide_By_2 |
3383                         Clock_To_Board;
3384         }
3385         devpriv->stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register);
3386
3387         /* analog output configuration */
3388         ni_ao_reset(dev,dev->subdevices + 1);
3389
3390         if(dev->irq){
3391                 devpriv->stc_writew(dev, (IRQ_POLARITY?Interrupt_Output_Polarity:0) |
3392                         (Interrupt_Output_On_3_Pins&0) |
3393                         Interrupt_A_Enable |
3394                         Interrupt_B_Enable |
3395                         Interrupt_A_Output_Select(interrupt_pin(dev->irq)) |
3396                         Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
3397                         Interrupt_Control_Register
3398                 );
3399         }
3400
3401         /* DMA setup */
3402         /* tell the STC which dma channels to use for AI and AO */
3403         bits = 1 << ( AI_DMA_CHAN );
3404         bits |= 1 << ( AO_DMA_CHAN + 4 );
3405         ni_writeb( bits, AI_AO_Select);
3406         /* tell the STC which dma channels to use for
3407          * General purpose counters 0 and 1 */
3408         bits = 1 << ( GPC0_DMA_CHAN );
3409         bits |= 1 << ( GPC1_DMA_CHAN + 4 );
3410         ni_writeb( bits, G0_G1_Select);
3411
3412         if(boardtype.reg_type & ni_reg_6xxx_mask)
3413         {
3414                 ni_writeb( 0, Magic_611x );
3415         }else if(boardtype.reg_type == ni_reg_m_series)
3416         {
3417                 int channel;
3418                 for(channel = 0; channel < boardtype.n_aochan; ++channel)
3419                 {
3420                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
3421                         ni_writeb(0x0, M_Offset_AO_Reference_Attenuation(channel));
3422                 }
3423                 ni_writeb(0x0, M_Offset_AO_Calibration);
3424         }
3425
3426         printk("\n");
3427         return 0;
3428 }
3429
3430
3431
3432 static int ni_8255_callback(int dir,int port,int data,unsigned long arg)
3433 {
3434         comedi_device *dev=(comedi_device *)arg;
3435
3436         if(dir){
3437                 ni_writeb(data,Port_A+2*port);
3438                 return 0;
3439         }else{
3440                 return ni_readb(Port_A+2*port);
3441         }
3442 }
3443
3444 /*
3445         presents the EEPROM as a subdevice
3446 */
3447
3448 static int ni_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3449         comedi_insn *insn,lsampl_t *data)
3450 {
3451         data[0]=ni_read_eeprom(dev,CR_CHAN(insn->chanspec));
3452
3453         return 1;
3454 }
3455
3456 /*
3457         reads bytes out of eeprom
3458 */
3459
3460 static int ni_read_eeprom(comedi_device *dev,int addr)
3461 {
3462         int bit;
3463         int bitstring;
3464
3465         bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff);
3466         ni_writeb(0x04,Serial_Command);
3467         for(bit=0x8000;bit;bit>>=1){
3468                 ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command);
3469                 ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command);
3470         }
3471         bitstring=0;
3472         for(bit=0x80;bit;bit>>=1){
3473                 ni_writeb(0x04,Serial_Command);
3474                 ni_writeb(0x05,Serial_Command);
3475                 bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
3476         }
3477         ni_writeb(0x00,Serial_Command);
3478
3479         return bitstring;
3480 }
3481
3482 static int ni_m_series_eeprom_insn_read(comedi_device *dev,comedi_subdevice *s,
3483         comedi_insn *insn,lsampl_t *data)
3484 {
3485         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
3486
3487         return 1;
3488 }
3489
3490 static int ni_get_pwm_config(comedi_device *dev, lsampl_t *data)
3491 {
3492         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3493         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3494         return 3;
3495 }
3496
3497 static int ni_m_series_pwm_config(comedi_device *dev, comedi_subdevice *s,
3498         comedi_insn *insn, lsampl_t *data)
3499 {
3500         unsigned up_count, down_count;
3501         switch(data[0])
3502         {
3503         case INSN_CONFIG_PWM_OUTPUT:
3504                 switch(data[1])
3505                 {
3506                 case TRIG_ROUND_NEAREST:
3507                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3508                         break;
3509                 case TRIG_ROUND_DOWN:
3510                         up_count = data[2] / devpriv->clock_ns;
3511                         break;
3512                 case TRIG_ROUND_UP:
3513                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3514                         break;
3515                 default:
3516                         return -EINVAL;
3517                         break;
3518                 }
3519                 switch(data[3])
3520                 {
3521                 case TRIG_ROUND_NEAREST:
3522                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3523                         break;
3524                 case TRIG_ROUND_DOWN:
3525                         down_count = data[4] / devpriv->clock_ns;
3526                         break;
3527                 case TRIG_ROUND_UP:
3528                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3529                         break;
3530                 default:
3531                         return -EINVAL;
3532                         break;
3533                 }
3534                 if(up_count * devpriv->clock_ns != data[2] ||
3535                         down_count * devpriv->clock_ns != data[4])
3536                 {
3537                         data[2] = up_count * devpriv->clock_ns;
3538                         data[4] = down_count * devpriv->clock_ns;
3539                         return -EAGAIN;
3540                 }
3541                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM);
3542                 devpriv->pwm_up_count = up_count;
3543                 devpriv->pwm_down_count = down_count;
3544                 return 5;
3545                 break;
3546         case INSN_CONFIG_GET_PWM_OUTPUT:
3547                 return ni_get_pwm_config(dev, data);
3548                 break;
3549         default:
3550                 return -EINVAL;
3551                 break;
3552         }
3553         return 0;
3554 }
3555
3556 static int ni_6143_pwm_config(comedi_device *dev, comedi_subdevice *s,
3557         comedi_insn *insn, lsampl_t *data)
3558 {
3559         unsigned up_count, down_count;
3560         switch(data[0])
3561         {
3562         case INSN_CONFIG_PWM_OUTPUT:
3563                 switch(data[1])
3564                 {
3565                 case TRIG_ROUND_NEAREST:
3566                         up_count = (data[2] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3567                         break;
3568                 case TRIG_ROUND_DOWN:
3569                         up_count = data[2] / devpriv->clock_ns;
3570                         break;
3571                 case TRIG_ROUND_UP:
3572                         up_count = (data[2] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3573                         break;
3574                 default:
3575                         return -EINVAL;
3576                         break;
3577                 }
3578                 switch(data[3])
3579                 {
3580                 case TRIG_ROUND_NEAREST:
3581                         down_count = (data[4] + devpriv->clock_ns / 2) / devpriv->clock_ns;
3582                         break;
3583                 case TRIG_ROUND_DOWN:
3584                         down_count = data[4] / devpriv->clock_ns;
3585                         break;
3586                 case TRIG_ROUND_UP:
3587                         down_count = (data[4] + devpriv->clock_ns - 1) / devpriv->clock_ns;
3588                         break;
3589                 default:
3590                         return -EINVAL;
3591                         break;
3592                 }
3593                 if(up_count * devpriv->clock_ns != data[2] ||
3594                         down_count * devpriv->clock_ns != data[4])
3595                 {
3596                         data[2] = up_count * devpriv->clock_ns;
3597                         data[4] = down_count * devpriv->clock_ns;
3598                         return -EAGAIN;
3599                 }
3600                 ni_writel(up_count, Calibration_HighTime_6143);
3601                 devpriv->pwm_up_count = up_count;
3602                 ni_writel(down_count, Calibration_LowTime_6143);
3603                 devpriv->pwm_down_count = down_count;
3604                 return 5;
3605                 break;
3606         case INSN_CONFIG_GET_PWM_OUTPUT:
3607                 return ni_get_pwm_config(dev, data);
3608         default:
3609                 return -EINVAL;
3610                 break;
3611         }
3612         return 0;
3613 }
3614
3615 static void ni_write_caldac(comedi_device *dev,int addr,int val);
3616 /*
3617         calibration subdevice
3618 */
3619 static int ni_calib_insn_write(comedi_device *dev,comedi_subdevice *s,
3620         comedi_insn *insn,lsampl_t *data)
3621 {
3622         ni_write_caldac(dev,CR_CHAN(insn->chanspec),data[0]);
3623
3624         return 1;
3625 }
3626
3627 static int ni_calib_insn_read(comedi_device *dev,comedi_subdevice *s,
3628         comedi_insn *insn,lsampl_t *data)
3629 {
3630         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
3631
3632         return 1;
3633 }
3634
3635 static int pack_mb88341(int addr,int val,int *bitstring);
3636 static int pack_dac8800(int addr,int val,int *bitstring);
3637 static int pack_dac8043(int addr,int val,int *bitstring);
3638 static int pack_ad8522(int addr,int val,int *bitstring);
3639 static int pack_ad8804(int addr,int val,int *bitstring);
3640 static int pack_ad8842(int addr,int val,int *bitstring);
3641
3642 struct caldac_struct{
3643         int n_chans;
3644         int n_bits;
3645         int (*packbits)(int,int,int *);
3646 };
3647
3648 static struct caldac_struct caldacs[] = {
3649         [mb88341] = { 12, 8, pack_mb88341 },
3650         [dac8800] = { 8, 8, pack_dac8800 },
3651         [dac8043] = { 1, 12, pack_dac8043 },
3652         [ad8522]  = { 2, 12, pack_ad8522 },
3653         [ad8804] = { 12, 8, pack_ad8804 },
3654         [ad8842] = { 8, 8, pack_ad8842 },
3655         [ad8804_debug] = { 16, 8, pack_ad8804 },
3656 };
3657
3658 static void caldac_setup(comedi_device *dev,comedi_subdevice *s)
3659 {
3660         int i,j;
3661         int n_dacs;
3662         int n_chans=0;
3663         int n_bits;
3664         int diffbits=0;
3665         int type;
3666         int chan;
3667
3668         type = boardtype.caldac[0];
3669         if(type==caldac_none)return;
3670         n_bits=caldacs[type].n_bits;
3671         for(i=0;i<3;i++){
3672                 type = boardtype.caldac[i];
3673                 if(type==caldac_none)break;
3674                 if(caldacs[type].n_bits!=n_bits)diffbits=1;
3675                 n_chans+=caldacs[type].n_chans;
3676         }
3677         n_dacs=i;
3678         s->n_chan=n_chans;
3679
3680         if(diffbits){
3681
3682                 if(n_chans>MAX_N_CALDACS){
3683                         printk("BUG! MAX_N_CALDACS too small\n");
3684                 }
3685                 s->maxdata_list=devpriv->caldac_maxdata_list;
3686                 chan=0;
3687                 for(i=0;i<n_dacs;i++){
3688                         type = boardtype.caldac[i];
3689                         for(j=0;j<caldacs[type].n_chans;j++){
3690                                 s->maxdata_list[chan]=
3691                                         (1<<caldacs[type].n_bits)-1;
3692                                 chan++;
3693                         }
3694                 }
3695
3696                 for( chan = 0; chan < s->n_chan; chan++ )
3697                         ni_write_caldac( dev, i, s->maxdata_list[ i ] / 2 );
3698         }else{
3699                 type = boardtype.caldac[0];
3700                 s->maxdata=(1<<caldacs[type].n_bits)-1;
3701
3702                 for( chan = 0; chan < s->n_chan; chan++ )
3703                         ni_write_caldac( dev, i, s->maxdata / 2 );
3704         }
3705 }
3706
3707 static void ni_write_caldac(comedi_device *dev,int addr,int val)
3708 {
3709         unsigned int loadbit=0,bits=0,bit,bitstring=0;
3710         int i;
3711         int type;
3712
3713         //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
3714         if( devpriv->caldacs[ addr ] == val ) return;
3715         devpriv->caldacs[ addr ] = val;
3716
3717         for(i=0;i<3;i++){
3718                 type = boardtype.caldac[i];
3719                 if(type==caldac_none)break;
3720                 if(addr<caldacs[type].n_chans){
3721                         bits=caldacs[type].packbits(addr,val,&bitstring);
3722                         loadbit=SerDacLd(i);
3723                         //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
3724                         break;
3725                 }
3726                 addr-=caldacs[type].n_chans;
3727         }
3728
3729         for(bit=1<<(bits-1);bit;bit>>=1){
3730                 ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
3731                 comedi_udelay(1);
3732                 ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
3733                 comedi_udelay(1);
3734         }
3735         ni_writeb(loadbit,Serial_Command);
3736         comedi_udelay(1);
3737         ni_writeb(0,Serial_Command);
3738 }
3739
3740
3741
3742 static int pack_mb88341(int addr,int val,int *bitstring)
3743 {
3744         /*
3745            Fujitsu MB 88341
3746            Note that address bits are reversed.  Thanks to
3747            Ingo Keen for noticing this.
3748
3749            Note also that the 88341 expects address values from
3750            1-12, whereas we use channel numbers 0-11.  The NI
3751            docs use 1-12, also, so be careful here.
3752         */
3753         addr++;
3754         *bitstring=((addr&0x1)<<11) |
3755                   ((addr&0x2)<<9)  |
3756                   ((addr&0x4)<<7)  |
3757                   ((addr&0x8)<<5)  |
3758                   (val&0xff);
3759         return 12;
3760 }
3761
3762 static int pack_dac8800(int addr,int val,int *bitstring)
3763 {
3764         *bitstring=((addr&0x7)<<8)|(val&0xff);
3765         return 11;
3766 }
3767
3768 static int pack_dac8043(int addr,int val,int *bitstring)
3769 {
3770         *bitstring=val&0xfff;
3771         return 12;
3772 }
3773
3774 static int pack_ad8522(int addr,int val,int *bitstring)
3775 {
3776         *bitstring=(val&0xfff)|(addr ? 0xc000:0xa000);
3777         return 16;
3778 }
3779
3780 static int pack_ad8804(int addr,int val,int *bitstring)
3781 {
3782         *bitstring=((addr&0xf)<<8) | (val&0xff);
3783         return 12;
3784 }
3785
3786 static int pack_ad8842(int addr,int val,int *bitstring)
3787 {
3788         *bitstring=((addr+1)<<8) | (val&0xff);
3789         return 12;
3790 }
3791
3792
3793
3794
3795
3796 /*
3797  *
3798  *  General Purpose Counter/Timer section
3799  *
3800  */
3801
3802 /*
3803  * Low level stuff...Each STC counter has two 24 bit load registers
3804  * (A&B).  Just make it easier to access them.
3805  *
3806  * These are inlined _only_ because they are used once in subsequent
3807  * code.  Otherwise they should not be inlined.
3808  */
3809 static inline void GPCT_Load_A(comedi_device *dev, int chan, unsigned int value)
3810 {
3811         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_A_Register(chan));
3812 }
3813
3814 static inline void GPCT_Load_B(comedi_device *dev, int chan, unsigned int value)
3815 {
3816         devpriv->stc_writel(dev,  value & 0x00ffffff, G_Load_B_Register(chan));
3817 }
3818
3819 /*  Load a value into the counter, using register A as the intermediate step.
3820 *  You might use GPCT_Load_Using_A to load a 0x000000 into a counter
3821 *  reset its value.
3822 */
3823 static void GPCT_Load_Using_A(comedi_device *dev, int chan, unsigned int value)
3824 {
3825         devpriv->gpct_mode[chan] &= (~G_Load_Source_Select);
3826         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3827         GPCT_Load_A(dev,chan,value);
3828         devpriv->stc_writew(dev,  devpriv->gpct_command[chan]|G_Load,G_Command_Register(chan));
3829 }
3830
3831 /*
3832  *      Read the GPCTs current value.
3833  */
3834 static int GPCT_G_Watch(comedi_device *dev, int chan)
3835 {
3836         unsigned int hi1,hi2,lo;
3837
3838         devpriv->gpct_command[chan] &= ~G_Save_Trace;
3839         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
3840
3841         devpriv->gpct_command[chan] |= G_Save_Trace;
3842         devpriv->stc_writew(dev,  devpriv->gpct_command[chan], G_Command_Register(chan));
3843
3844         /* This procedure is used because the two registers cannot
3845          * be read atomically. */
3846         do{
3847                 hi1 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3848                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
3849                 hi2 = devpriv->stc_readw(dev,  G_Save_Register_High(chan));
3850         }while(hi1!=hi2);
3851
3852         return (hi1<<16)|lo;
3853 }
3854
3855
3856 static int GPCT_Disarm(comedi_device *dev, int chan)
3857 {
3858         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Disarm,G_Command_Register(chan));
3859         return 0;
3860 }
3861
3862
3863 static int GPCT_Arm(comedi_device *dev, int chan)
3864 {
3865         devpriv->stc_writew(dev,  devpriv->gpct_command[chan] | G_Arm,G_Command_Register(chan));
3866         /* If the counter is doing pulse width measurement, then make
3867          sure that the counter did not start counting right away.  This would
3868          indicate that we started acquiring the pulse after it had already
3869          started and our measurement would be inaccurate */
3870         if(devpriv->gpct_cur_operation[chan] == GPCT_SINGLE_PW){
3871                 int g_status;
3872
3873                 g_status=devpriv->stc_readw(dev, G_Status_Register);
3874
3875                 if(chan == 0){
3876                         //TIM 5/2/01 possible error with very short pulses
3877                         if((G0_Counting_St & g_status)|| !(G0_Armed_St&g_status)) {
3878                                 //error: we missed the beginning of the pulse
3879                                 return -EINVAL; //there is probably a more accurate error code...
3880                         }
3881                 }else{
3882                         if((G1_Counting_St & g_status)|| !(G1_Armed_St&g_status)) {
3883                                 //error: we missed the beginning of the pulse
3884                                 return -EINVAL;
3885                         }
3886                 }
3887         }
3888         return 0;
3889 }
3890
3891 static int GPCT_Set_Source(comedi_device *dev,int chan ,int source)
3892 {
3893         //printk("GPCT_Set_Source...");
3894         devpriv->gpct_input_select[chan] &= ~G_Source_Select(0x1f);//reset gate to 0
3895         switch(source) {
3896                 case GPCT_INT_CLOCK:
3897                 devpriv->gpct_input_select[chan] |= G_Source_Select(0);//INT_TIMEBASE
3898                 break;
3899         case GPCT_EXT_PIN:
3900                 if(chan==0)
3901                         devpriv->gpct_input_select[chan] |= G_Source_Select(9);//PFI8
3902                 else
3903                         devpriv->gpct_input_select[chan] |= G_Source_Select(4);//PFI3
3904                 break;
3905         default:
3906                 return -EINVAL;
3907         }
3908         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3909         //printk("exit GPCT_Set_Source\n");
3910         return 0;
3911 }
3912
3913 static int GPCT_Set_Gate(comedi_device *dev,int chan ,int gate)
3914 {
3915         //printk("GPCT_Set_Gate...");
3916         devpriv->gpct_input_select[chan] &= ~G_Gate_Select(0x1f);//reset gate to 0
3917         switch(gate) {
3918         case GPCT_NO_GATE:
3919                 devpriv->gpct_input_select[chan] |= G_Gate_Select(31);//Low
3920                 devpriv->gpct_mode[chan] |= G_Gate_Polarity;
3921                 break;
3922         case GPCT_EXT_PIN:
3923                 devpriv->gpct_mode[chan] &= ~G_Gate_Polarity;
3924                 if(chan==0){
3925                         devpriv->gpct_input_select[chan] |= G_Gate_Select(10);//PFI9
3926                 }else{
3927                         devpriv->gpct_input_select[chan] |= G_Gate_Select(5);//PFI4
3928                 }
3929                 break;
3930         default:
3931                 return -EINVAL;
3932         }
3933         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], G_Input_Select_Register(chan));
3934         devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3935         //printk("exit GPCT_Set_Gate\n");
3936         return 0;
3937 }
3938
3939 static int GPCT_Set_Direction(comedi_device *dev,int chan,int direction)
3940 {
3941         //printk("GPCT_Set_Direction...");
3942
3943         devpriv->gpct_command[chan] &= ~G_Up_Down(0x3);
3944         switch (direction) {
3945                 case GPCT_UP:
3946                         devpriv->gpct_command[chan] |= G_Up_Down(1);
3947                         break;
3948                 case GPCT_DOWN:
3949                         devpriv->gpct_command[chan] |= G_Up_Down(0);
3950                         break;
3951                 case GPCT_HWUD:
3952                         devpriv->gpct_command[chan] |= G_Up_Down(2);
3953                         break;
3954                 default:
3955                         rt_printk("Error direction=0x%08x..",direction);
3956                         return -EINVAL;
3957         }
3958         devpriv->stc_writew(dev, devpriv->gpct_command[chan], G_Command_Register(chan));
3959         //TIM 4/23/01 devpriv->stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan));
3960         //printk("exit GPCT_Set_Direction\n");
3961         return 0;
3962 }
3963
3964 static void GPCT_Event_Counting(comedi_device *dev,int chan)
3965 {
3966
3967         //NOTE: possible residual bits from multibit masks can corrupt
3968         //If you config for several measurements between Resets, watch out!
3969
3970         //printk("GPCT_Event_Counting...");
3971
3972         devpriv->gpct_cur_operation[chan] = GPCT_SIMPLE_EVENT;
3973
3974         // Gating_Mode = 1
3975         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
3976         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);
3977
3978         // Trigger_Mode_For_Edge_Gate = 1
3979         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
3980         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
3981
3982         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
3983         //printk("exit GPCT_Event_Counting\n");
3984 }
3985
3986 static void GPCT_Period_Meas(comedi_device *dev, int chan)
3987 {
3988         //printk("GPCT_Period_Meas...");
3989
3990         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PERIOD;
3991
3992
3993         //NOTE: possible residual bits from multibit masks can corrupt
3994         //If you config for several measurements between Resets, watch out!
3995         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
3996         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
3997
3998         // Output_Mode = 3
3999         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4000         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
4001
4002
4003         //Gating Mode=2
4004         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4005         devpriv->gpct_mode[chan] |= G_Gating_Mode(2);
4006
4007         // Trigger_Mode_For_Edge_Gate=0
4008         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4009         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(0);
4010
4011         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4012         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4013         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
4014         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4015
4016         // Stop_Mode = 2
4017         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4018         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
4019
4020         // Counting_Once = 2
4021         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4022         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
4023
4024         // Up_Down = 1
4025         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4026         devpriv->gpct_command[chan] |= G_Up_Down(1);
4027
4028         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4029         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4030         //printk("exit GPCT_Period_Meas\n");
4031 }
4032
4033 static void GPCT_Pulse_Width_Meas(comedi_device *dev, int chan)
4034 {
4035         //printk("GPCT_Pulse_Width_Meas...");
4036
4037         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PW;
4038
4039         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4040         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4041
4042         // Output_Mode = 3
4043         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4044         devpriv->gpct_mode[chan] |= G_Output_Mode(3);
4045
4046         //Gating Mode=1
4047         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4048         devpriv->gpct_mode[chan] |= G_Gating_Mode(1);//TIM 4/24/01 was 2
4049
4050         // Trigger_Mode_For_Edge_Gate=2
4051         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4052         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);//TIM 4/24/01 was 0
4053
4054
4055         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;//TIM 4/24/01 was 1
4056         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;//TIM 4/24/01 was 0
4057
4058         devpriv->gpct_mode[chan] &= ~G_Loading_On_TC;
4059         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4060
4061         // Stop_Mode = 0
4062         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4063         devpriv->gpct_mode[chan] |= G_Stop_Mode(0);
4064
4065         // Counting_Once = 2
4066         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4067         devpriv->gpct_mode[chan] |= G_Counting_Once(2);
4068
4069         // Up_Down = 1
4070         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4071         devpriv->gpct_command[chan] |= G_Up_Down(1);
4072
4073         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4074         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4075
4076         //printk("exit GPCT_Pulse_Width_Meas\n");
4077 }
4078
4079 /* GPCT_Gen_Single_Pulse() creates pulse of length pulsewidth which starts after the Arm
4080 signal is sent.  The pulse is delayed by the value already in the counter.  This function could
4081 be modified to send a pulse in response to a trigger event at its gate.*/
4082 static void GPCT_Gen_Single_Pulse(comedi_device *dev, int chan, unsigned int length)
4083 {
4084         //printk("GPCT_Gen_Cont...");
4085
4086         devpriv->gpct_cur_operation[chan] = GPCT_SINGLE_PULSE_OUT;
4087
4088         // Set length of the pulse
4089         GPCT_Load_B(dev,chan, length-1);
4090
4091         //Load next time using B, This is reset by GPCT_Load_Using_A()
4092         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4093
4094         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4095         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4096
4097         // Output_Mode = 3
4098         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4099         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4100
4101         //Gating Mode=0 for untriggered single pulse
4102         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4103         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/25/01 was 1
4104
4105         // Trigger_Mode_For_Edge_Gate=0
4106         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4107         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4108
4109
4110         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4111         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4112         devpriv->gpct_mode[chan] |= G_Loading_On_TC; //TIM 4/25/01
4113         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4114
4115         // Stop_Mode = 2
4116         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4117         devpriv->gpct_mode[chan] |= G_Stop_Mode(2); //TIM 4/25/01
4118
4119         // Counting_Once = 2
4120         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4121         devpriv->gpct_mode[chan] |= G_Counting_Once(1); //TIM 4/25/01
4122
4123         // Up_Down = 1
4124         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4125         devpriv->gpct_command[chan] |= G_Up_Down(0); //TIM 4/25/01 was 1
4126
4127         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4128         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4129
4130         //printk("exit GPCT_Gen_Cont\n");
4131 }
4132
4133 static void GPCT_Gen_Cont_Pulse(comedi_device *dev, int chan, unsigned int length)
4134 {
4135         //printk("GPCT_Gen_Cont...");
4136
4137         devpriv->gpct_cur_operation[chan] = GPCT_CONT_PULSE_OUT;
4138
4139         // Set length of the pulse
4140         GPCT_Load_B(dev,chan, length-1);
4141
4142         //Load next time using B, This is reset by GPCT_Load_Using_A()
4143         devpriv->gpct_mode[chan] |= G_Load_Source_Select;
4144
4145         devpriv->gpct_mode[chan] &= ~G_OR_Gate;
4146         devpriv->gpct_mode[chan] &= ~G_Gate_Select_Load_Source;
4147
4148         // Output_Mode = 3
4149         devpriv->gpct_mode[chan] &= ~(G_Output_Mode(0x3));
4150         devpriv->gpct_mode[chan] |= G_Output_Mode(2); //TIM 4/26/01 was 3
4151
4152         //Gating Mode=0 for untriggered single pulse
4153         devpriv->gpct_mode[chan] &= ~(G_Gating_Mode(0x3));
4154         devpriv->gpct_mode[chan] |= G_Gating_Mode(0); //TIM 4/26/01 was 0
4155
4156         // Trigger_Mode_For_Edge_Gate=0
4157         devpriv->gpct_mode[chan] &= ~(G_Trigger_Mode_For_Edge_Gate(0x3));
4158         devpriv->gpct_mode[chan] |= G_Trigger_Mode_For_Edge_Gate(2);
4159
4160
4161         devpriv->gpct_mode[chan] |= G_Reload_Source_Switching;
4162         devpriv->gpct_mode[chan] &= ~G_Loading_On_Gate;
4163         devpriv->gpct_mode[chan] |= G_Loading_On_TC;
4164         devpriv->gpct_mode[chan] &= ~G_Gate_On_Both_Edges;
4165
4166         // Stop_Mode = 2
4167         devpriv->gpct_mode[chan] &= ~(G_Stop_Mode(0x3));
4168         devpriv->gpct_mode[chan] |= G_Stop_Mode(0); //TIM 4/26/01
4169
4170         // Counting_Once = 2
4171         devpriv->gpct_mode[chan] &= ~(G_Counting_Once(0x3));
4172         devpriv->gpct_mode[chan] |= G_Counting_Once(0); //TIM 4/26/01
4173
4174         // Up_Down = 1
4175         devpriv->gpct_command[chan] &= ~(G_Up_Down(0x3));
4176         devpriv->gpct_command[chan] |= G_Up_Down(0);
4177
4178         //TIM 4/26/01
4179         //This seems pretty unsafe since I don't think it is cleared anywhere.
4180         //I don't think this is working
4181         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Enable;
4182         //devpriv->gpct_command[chan] &= ~G_Bank_Switch_Mode;
4183
4184
4185         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4186         devpriv->stc_writew(dev,  devpriv->gpct_command[chan],G_Command_Register(chan));
4187
4188         //printk("exit GPCT_Gen_Cont\n");
4189 }
4190
4191 static void GPCT_Reset(comedi_device *dev, int chan)
4192 {
4193         int temp_ack_reg=0;
4194
4195         //printk("GPCT_Reset...");
4196         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4197
4198         switch (chan) {
4199                 case 0:
4200                         devpriv->stc_writew(dev, G0_Reset,Joint_Reset_Register);
4201                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_TC_Interrupt_Enable,  0);
4202                         ni_set_bits(dev,Interrupt_A_Enable_Register,G0_Gate_Interrupt_Enable,0);
4203                         temp_ack_reg |= G0_Gate_Error_Confirm;
4204                         temp_ack_reg |= G0_TC_Error_Confirm;
4205                         temp_ack_reg |= G0_TC_Interrupt_Ack;
4206                         temp_ack_reg |= G0_Gate_Interrupt_Ack;
4207                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_A_Ack_Register);
4208
4209                         //problem...this interferes with the other ctr...
4210                         devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4211                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4212                         break;
4213                 case 1:
4214                         devpriv->stc_writew(dev, G1_Reset,Joint_Reset_Register);
4215                         ni_set_bits(dev,Interrupt_B_Enable_Register,G1_TC_Interrupt_Enable,  0);
4216                         ni_set_bits(dev,Interrupt_B_Enable_Register,G0_Gate_Interrupt_Enable,0);
4217                         temp_ack_reg |= G1_Gate_Error_Confirm;
4218                         temp_ack_reg |= G1_TC_Error_Confirm;
4219                         temp_ack_reg |= G1_TC_Interrupt_Ack;
4220                         temp_ack_reg |= G1_Gate_Interrupt_Ack;
4221                         devpriv->stc_writew(dev, temp_ack_reg,Interrupt_B_Ack_Register);
4222
4223                         devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4224                         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, Analog_Trigger_Etc_Register);
4225                         break;
4226         };
4227
4228         devpriv->gpct_mode[chan] = 0;
4229         devpriv->gpct_input_select[chan] = 0;
4230         devpriv->gpct_command[chan] = 0;
4231
4232         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4233
4234         devpriv->stc_writew(dev,  devpriv->gpct_mode[chan],G_Mode_Register(chan));
4235         devpriv->stc_writew(dev,  devpriv->gpct_input_select[chan],G_Input_Select_Register(chan));
4236         devpriv->stc_writew(dev,  0,G_Autoincrement_Register(chan));
4237
4238         //printk("exit GPCT_Reset\n");
4239 }
4240
4241 static int ni_gpct_insn_config(comedi_device *dev,comedi_subdevice *s,
4242         comedi_insn *insn,lsampl_t *data)
4243 {
4244         int retval=0;
4245         //printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4246         switch(data[0]){
4247         case GPCT_RESET:
4248                 if(insn->n!=1)return -EINVAL;
4249                 GPCT_Reset(dev,insn->chanspec);
4250                 break;
4251         case GPCT_SET_SOURCE:
4252                 if(insn->n!=2)return -EINVAL;
4253                 retval=GPCT_Set_Source(dev,insn->chanspec,data[1]);
4254                 break;
4255         case GPCT_SET_GATE:
4256                 if(insn->n!=2)return -EINVAL;
4257                 retval=GPCT_Set_Gate(dev,insn->chanspec,data[1]);
4258                 break;
4259         case GPCT_SET_DIRECTION:
4260                 if(insn->n!=2) return -EINVAL;
4261                 retval=GPCT_Set_Direction(dev,insn->chanspec,data[1]);
4262                 break;
4263         case GPCT_GET_INT_CLK_FRQ:
4264                 if(insn->n!=2) return -EINVAL;
4265                 //There are actually 2 internal clocks on the STC, we always
4266                 //use the fast 20MHz one at this time.  Tim  Ousley 5/1/01
4267                 //NOTE: This is not the final interface, ideally the user
4268                 //will never need to know the int. clk. freq.
4269                 data[1]=50;//50ns = 20MHz = internal timebase of STC
4270                 break;
4271         case GPCT_SET_OPERATION:
4272                 //TIM 5/1/01 if((insn->n<2)||(insn->n>3))return -EINVAL;
4273                 switch(data[1]){
4274                         case GPCT_SIMPLE_EVENT:
4275                                 GPCT_Event_Counting(dev,insn->chanspec);
4276                                 break;
4277                         case GPCT_SINGLE_PERIOD:
4278                                 GPCT_Period_Meas(dev,insn->chanspec);
4279                                 break;
4280                         case GPCT_SINGLE_PW:
4281                                 GPCT_Pulse_Width_Meas(dev,insn->chanspec);
4282                                 break;
4283                         case GPCT_SINGLE_PULSE_OUT:
4284                                 GPCT_Gen_Single_Pulse(dev,insn->chanspec,data[2]);
4285                                 break;
4286                         case GPCT_CONT_PULSE_OUT:
4287                                 GPCT_Gen_Cont_Pulse(dev,insn->chanspec,data[2]);
4288                                 break;
4289                         default:
4290                                 rt_printk("unsupported GPCT operation!\n");
4291                                 return -EINVAL;
4292                 }
4293                 break;
4294         case GPCT_ARM:
4295                 if(insn->n!=1)return -EINVAL;
4296                 retval=GPCT_Arm(dev,insn->chanspec);
4297                 break;
4298         case GPCT_DISARM:
4299                 if(insn->n!=1)return -EINVAL;
4300                 retval=GPCT_Disarm(dev,insn->chanspec);
4301                 break;
4302         default:
4303                 return -EINVAL;
4304         }
4305
4306         //catch any errors from return values
4307         if(retval==0){
4308                 return insn->n;
4309         }else{
4310                 if(data[0]!=GPCT_ARM){
4311                         rt_printk("error: retval was %d\n",retval);
4312                         rt_printk("data[0] is 0x%08x, data[1] is 0x%08x\n",data[0],data[1]);
4313                 }
4314
4315                 return retval;
4316         }
4317 }
4318
4319 static int ni_gpct_insn_read(comedi_device *dev,comedi_subdevice *s,
4320         comedi_insn *insn,lsampl_t *data) {
4321
4322         int chan=insn->chanspec;
4323         int cur_op = devpriv->gpct_cur_operation[chan];
4324
4325         //printk("in ni_gpct_insn_read, n=%d, data[0]=%d\n",insn->chanspec,data[0]);
4326         if(insn->n!=1)return -EINVAL;
4327
4328         data[0] = GPCT_G_Watch(dev,insn->chanspec);
4329
4330         /* for certain modes (period and pulse width measurment), the value
4331         in the counter is not valid until the counter stops.  If the value is
4332         invalid, return a 0 */
4333         if((cur_op == GPCT_SINGLE_PERIOD) || (cur_op == GPCT_SINGLE_PW)){
4334                 /* is the counter still running? */
4335                 if(devpriv->stc_readw(dev, G_Status_Register) & (chan?G1_Counting_St:G0_Counting_St))
4336                         data[0]=0;
4337         }
4338         return 1;
4339 }
4340
4341 static int ni_gpct_insn_write(comedi_device *dev,comedi_subdevice *s,
4342         comedi_insn *insn,lsampl_t *data) {
4343
4344         //printk("in ni_gpct_insn_write");
4345         if(insn->n!=1)return -EINVAL;
4346         GPCT_Load_Using_A(dev,insn->chanspec,data[0]);
4347         return 1;
4348 }
4349
4350 static int ni_gpct_cmd(comedi_device *dev, comedi_subdevice *s)
4351 {
4352         return 0;
4353 }
4354
4355 static int ni_gpct_cmdtest(comedi_device *dev, comedi_subdevice *s, comedi_cmd *cmd)
4356 {
4357         return 0;
4358 }
4359
4360 static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s)
4361 {
4362         return 0;
4363 }
4364
4365 /*
4366  *
4367  *  Programmable Function Inputs
4368  *
4369  */
4370
4371 static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4372 {
4373         unsigned pfi_reg_index;
4374         unsigned array_offset;
4375         if((source & 0x1f) != source) return -EINVAL;
4376         pfi_reg_index = 1 + chan / 3;
4377         array_offset = pfi_reg_index - 1;
4378         devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan);
4379         devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source);
4380         ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index));
4381         return 2;
4382 }
4383
4384 static int ni_old_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4385 {
4386         // pre-m-series boards have fixed signals on pfi pins
4387         if(source != ni_old_get_pfi_routing(dev, chan)) return -EINVAL;
4388         return 2;
4389 }
4390
4391 static int ni_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source)
4392 {
4393         if(boardtype.reg_type == ni_reg_m_series)
4394                 return ni_m_series_set_pfi_routing(dev, chan, source);
4395         else
4396                 return ni_old_set_pfi_routing(dev, chan, source);
4397 }
4398
4399 static unsigned ni_m_series_get_pfi_routing(comedi_device *dev, unsigned chan)
4400 {
4401         const unsigned array_offset = chan / 3;
4402         return MSeries_PFI_Output_Select_Source(chan, devpriv->pfi_output_select_reg[array_offset]);
4403 }
4404
4405 static unsigned ni_old_get_pfi_routing(comedi_device *dev, unsigned chan)
4406 {
4407         // pre-m-series boards have fixed signals on pfi pins
4408         switch(chan)
4409         {
4410         case 0:
4411                 return NI_PFI_OUTPUT_AI_START1;
4412                 break;
4413         case 1:
4414                 return NI_PFI_OUTPUT_AI_START2;
4415                 break;
4416         case 2:
4417                 return NI_PFI_OUTPUT_AI_CONVERT;
4418                 break;
4419         case 3:
4420                 return NI_PFI_OUTPUT_G_SRC1;
4421                 break;
4422         case 4:
4423                 return NI_PFI_OUTPUT_G_GATE1;
4424                 break;
4425         case 5:
4426                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4427                 break;
4428         case 6:
4429                 return NI_PFI_OUTPUT_AO_START1;
4430                 break;
4431         case 7:
4432                 return NI_PFI_OUTPUT_AI_START_PULSE;
4433                 break;
4434         case 8:
4435                 return NI_PFI_OUTPUT_G_SRC0;
4436                 break;
4437         case 9:
4438                 return NI_PFI_OUTPUT_G_GATE0;
4439                 break;
4440         default:
4441                 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
4442                 break;
4443         }
4444         return 0;
4445 }
4446
4447 static unsigned ni_get_pfi_routing(comedi_device *dev, unsigned chan)
4448 {
4449         if(boardtype.reg_type == ni_reg_m_series)
4450                 return ni_m_series_get_pfi_routing(dev, chan);
4451         else
4452                 return ni_old_get_pfi_routing(dev, chan);
4453 }
4454
4455 static int ni_pfi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4456         comedi_insn *insn,lsampl_t *data)
4457 {
4458         if(boardtype.reg_type != ni_reg_m_series)
4459         {
4460                 data[1] = 0;
4461                 return 2;
4462         }
4463         if(data[0])
4464         {
4465                 s->state &= ~data[0];
4466                 s->state |= (data[0] & data[1]);
4467                 ni_writew(s->state, M_Offset_PFI_DO);
4468         }
4469         data[1] = ni_readw(M_Offset_PFI_DI);
4470         return 2;
4471 }
4472
4473 static int ni_pfi_insn_config(comedi_device *dev,comedi_subdevice *s,
4474         comedi_insn *insn,lsampl_t *data)
4475 {
4476         unsigned int chan;
4477
4478         if(insn->n < 1)return -EINVAL;
4479
4480         chan = CR_CHAN(insn->chanspec);
4481
4482         switch(data[0]){
4483         case COMEDI_OUTPUT:
4484                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 1);
4485                 break;
4486         case COMEDI_INPUT:
4487                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1<<chan, 0);
4488                 break;
4489         case INSN_CONFIG_DIO_QUERY:
4490                 data[1] = (devpriv->io_bidirection_pin_reg & (1<<chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
4491                 return insn->n;
4492                 break;
4493         case INSN_CONFIG_SET_ROUTING:
4494                 return ni_set_pfi_routing(dev, chan, data[1]);
4495                 break;
4496         case INSN_CONFIG_GET_ROUTING:
4497                 data[1] = ni_get_pfi_routing(dev, chan);
4498                 return 2;
4499                 break;
4500         default:
4501                 return -EINVAL;
4502         }
4503
4504         return 1;
4505 }
4506
4507 /*
4508  *
4509  *  NI RTSI Bus Functions
4510  *
4511  */
4512 static void ni_rtsi_init(comedi_device *dev)
4513 {
4514         // Initialises the RTSI bus signal switch to a default state
4515
4516         // Set clock mode to internal
4517         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
4518         if(ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4519         {
4520                 rt_printk("ni_set_master_clock failed, bug?");
4521         }
4522         // default internal lines routing to RTSI bus lines
4523         devpriv->rtsi_trig_a_output_reg = RTSI_Trig_Output_Bits(0, NI_RTSI_OUTPUT_ADR_START1) |
4524                 RTSI_Trig_Output_Bits(1, NI_RTSI_OUTPUT_ADR_START2) |
4525                 RTSI_Trig_Output_Bits(2, NI_RTSI_OUTPUT_SCLKG) |
4526                 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
4527         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4528                 RTSI_Trig_A_Output_Register);
4529         devpriv->rtsi_trig_b_output_reg = RTSI_Trig_Output_Bits(4, NI_RTSI_OUTPUT_DA_START1) |
4530                 RTSI_Trig_Output_Bits(5, NI_RTSI_OUTPUT_G_SRC0) |
4531                 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
4532         if(boardtype.reg_type == ni_reg_m_series)
4533                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
4534         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4535                 RTSI_Trig_B_Output_Register);
4536
4537         // Sets the source and direction of the 4 on board lines
4538 //      devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
4539 }
4540
4541 static int ni_rtsi_insn_bits(comedi_device *dev,comedi_subdevice *s,
4542         comedi_insn *insn,lsampl_t *data)
4543 {
4544         if(insn->n != 2) return -EINVAL;
4545
4546         data[1] = 0;
4547
4548         return 2;
4549 }
4550
4551 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
4552  * given an arbitrary frequency input clock */
4553 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4554         unsigned *freq_divider, unsigned *freq_multiplier, unsigned *actual_period_ns)
4555 {
4556         unsigned div;
4557         unsigned best_div = 1;
4558         static const unsigned max_div = 0x10;
4559         unsigned mult;
4560         unsigned best_mult = 1;
4561         static const unsigned max_mult = 0x100;
4562         static const unsigned pico_per_nano = 1000;
4563
4564         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4565         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4566          * 20 MHz for most timing clocks */
4567         static const unsigned target_picosec = 12500;
4568         static const unsigned fudge_factor_80_to_20Mhz = 4;
4569         int best_period_picosec = 0;
4570         for(div = 1; div <= max_div; ++div)
4571         {
4572                 for(mult = 1; mult <= max_mult; ++mult)
4573                 {
4574                         unsigned new_period_ps = (reference_picosec * div) / mult;
4575                         if(abs(new_period_ps - target_picosec) < abs(best_period_picosec - target_picosec))
4576                         {
4577                                 best_period_picosec = new_period_ps;
4578                                 best_div = div;
4579                                 best_mult = mult;
4580                         }
4581                 }
4582         }
4583         if(best_period_picosec == 0)
4584         {
4585                 rt_printk("%s: bug, failed to find pll parameters\n", __FUNCTION__);
4586                 return -EIO;
4587         }
4588         *freq_divider = best_div;
4589         *freq_multiplier = best_mult;
4590         *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano;
4591         return 0;
4592 }
4593
4594 static inline unsigned num_configurable_rtsi_channels(comedi_device *dev)
4595 {
4596         if(boardtype.reg_type == ni_reg_m_series) return 8;
4597         else return 7;
4598 }
4599
4600 static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4601 {
4602         static const unsigned min_period_ns = 50;
4603         static const unsigned max_period_ns = 1000;
4604         static const unsigned timeout = 1000;
4605         unsigned pll_control_bits;
4606         unsigned freq_divider;
4607         unsigned freq_multiplier;
4608         unsigned i;
4609         int retval;
4610         if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100;
4611         // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
4612         if(period_ns < min_period_ns || period_ns > max_period_ns)
4613         {
4614                 rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec "
4615                         "for the phased-lock loop.\n", __FUNCTION__, min_period_ns, max_period_ns);
4616                 return -EINVAL;
4617         }
4618         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4619         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4620         pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
4621         devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit;
4622         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
4623         switch(source)
4624         {
4625         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4626                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
4627                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4628                         &freq_multiplier, &devpriv->clock_ns);
4629                 if(retval < 0) return retval;
4630                 break;
4631         case NI_MIO_PLL_PXI10_CLOCK:
4632                 /* pxi clock is 10MHz */
4633                 devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10;
4634                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4635                         &freq_multiplier, &devpriv->clock_ns);
4636                 if(retval < 0) return retval;
4637                 break;
4638         default:
4639                 {
4640                         unsigned rtsi_channel;
4641                         static const unsigned max_rtsi_channel = 7;
4642                         for(rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel)
4643                         {
4644                                 if(source == NI_MIO_PLL_RTSI_CLOCK(rtsi_channel))
4645                                 {
4646                                         devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_RTSI_Bits(rtsi_channel);
4647                                         break;
4648                                 }
4649                         }
4650                         if(rtsi_channel > max_rtsi_channel) return -EINVAL;
4651                         retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
4652                                 &freq_multiplier, &devpriv->clock_ns);
4653                         if(retval < 0) return retval;
4654                 }
4655                 break;
4656         }
4657         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4658         pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier);
4659 //      rt_printk("using divider=%i, multiplier=%i for PLL.  pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
4660 //      rt_printk("clock_ns=%d\n", devpriv->clock_ns);
4661         ni_writew(pll_control_bits, M_Offset_PLL_Control);
4662         devpriv->clock_source = source;
4663         /* it seems to typically take a few hundred microseconds for PLL to lock */
4664         for(i = 0; i < timeout; ++i)
4665         {
4666                 if(ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
4667                 {
4668                         break;
4669                 }
4670                 udelay(1);
4671         }
4672         if(i == timeout)
4673         {
4674                 rt_printk("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
4675                         __FUNCTION__, source, period_ns);
4676                 return -ETIMEDOUT;
4677         }
4678         return 3;
4679 }
4680
4681 static int ni_set_master_clock(comedi_device *dev, unsigned source, unsigned period_ns)
4682 {
4683         if(source == NI_MIO_INTERNAL_CLOCK)
4684         {
4685                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
4686                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4687                 devpriv->clock_ns = 50;
4688                 if(boardtype.reg_type == ni_reg_m_series)
4689                 {
4690                         devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit);
4691                         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
4692                         ni_writew(0, M_Offset_PLL_Control);
4693                 }
4694                 devpriv->clock_source = source;
4695         }else
4696         {
4697                 if(boardtype.reg_type == ni_reg_m_series)
4698                 {
4699                         return ni_mseries_set_pll_master_clock(dev, source, period_ns);
4700                 }else
4701                 {
4702                         if(source == NI_MIO_RTSI_CLOCK)
4703                         {
4704                                 devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit;
4705                                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4706                                 if(devpriv->clock_ns == 0)
4707                                 {
4708                                         rt_printk("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
4709                                                 __FUNCTION__);
4710                                         return -EINVAL;
4711                                 }else
4712                                 {
4713                                         devpriv->clock_ns = period_ns;
4714                                 }
4715                                 devpriv->clock_source = source;
4716                         }else
4717                                 return -EINVAL;
4718                 }
4719         }
4720         return 3;
4721 }
4722
4723 static int ni_valid_rtsi_output_source(comedi_device *dev, unsigned chan, unsigned source)
4724 {
4725         if(chan >= num_configurable_rtsi_channels(dev))
4726         {
4727                 if(chan == old_RTSI_clock_channel)
4728                 {
4729                         if(source == NI_RTSI_OUTPUT_RTSI_OSC) return 1;
4730                         else
4731                         {
4732                                 rt_printk("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
4733                                         __FUNCTION__, chan, old_RTSI_clock_channel);
4734                                 return 0;
4735                         }
4736                 }
4737                 return 0;
4738         }
4739         switch(source)
4740         {
4741         case NI_RTSI_OUTPUT_ADR_START1:
4742         case NI_RTSI_OUTPUT_ADR_START2:
4743         case NI_RTSI_OUTPUT_SCLKG:
4744         case NI_RTSI_OUTPUT_DACUPDN:
4745         case NI_RTSI_OUTPUT_DA_START1:
4746         case NI_RTSI_OUTPUT_G_SRC0:
4747         case NI_RTSI_OUTPUT_G_GATE0:
4748         case NI_RTSI_OUTPUT_RGOUT0:
4749         case NI_RTSI_OUTPUT_RTSI_BRD_0:
4750                 return 1;
4751                 break;
4752         case NI_RTSI_OUTPUT_RTSI_OSC:
4753                 if(boardtype.reg_type == ni_reg_m_series)
4754                         return 1;
4755                 else return 0;
4756                 break;
4757         default:
4758                 return 0;
4759                 break;
4760         }
4761 }
4762
4763 static int ni_set_rtsi_routing(comedi_device *dev, unsigned chan, unsigned source)
4764 {
4765         if(ni_valid_rtsi_output_source(dev, chan, source) == 0) return -EINVAL;
4766         if(chan < 4)
4767         {
4768                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4769                 devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4770                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4771                         RTSI_Trig_A_Output_Register);
4772         }else if(chan < 8)
4773         {
4774                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
4775                 devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source);
4776                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4777                         RTSI_Trig_B_Output_Register);
4778         }
4779         return 2;
4780 }
4781
4782 static unsigned ni_get_rtsi_routing(comedi_device *dev, unsigned chan)
4783 {
4784         if(chan < 4)
4785         {
4786                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_a_output_reg);
4787         }else if(chan < num_configurable_rtsi_channels(dev))
4788         {
4789                 return RTSI_Trig_Output_Source(chan, devpriv->rtsi_trig_b_output_reg);
4790         }else
4791         {
4792                 if(chan == old_RTSI_clock_channel)
4793                         return NI_RTSI_OUTPUT_RTSI_OSC;
4794                 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
4795                 return 0;
4796         }
4797 }
4798
4799 static int ni_rtsi_insn_config(comedi_device *dev,comedi_subdevice *s,
4800         comedi_insn *insn,lsampl_t *data)
4801 {
4802         unsigned int chan = CR_CHAN(insn->chanspec);
4803         switch(data[0]){
4804         case INSN_CONFIG_DIO_OUTPUT:
4805                 if(chan < num_configurable_rtsi_channels(dev))
4806                 {
4807                         devpriv->rtsi_trig_direction_reg |= RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4808                 }else if(chan == old_RTSI_clock_channel)
4809                 {
4810                         devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit;
4811                 }
4812                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4813                 break;
4814         case INSN_CONFIG_DIO_INPUT:
4815                 if(chan < num_configurable_rtsi_channels(dev))
4816                 {
4817                         devpriv->rtsi_trig_direction_reg &= ~RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series);
4818                 }else if(chan == old_RTSI_clock_channel)
4819                 {
4820                         devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit;
4821                 }
4822                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register);
4823                 break;
4824         case INSN_CONFIG_DIO_QUERY:
4825                 if(chan < num_configurable_rtsi_channels(dev))
4826                 {
4827                         data[1] = (devpriv->rtsi_trig_direction_reg & RTSI_Output_Bit(chan, boardtype.reg_type == ni_reg_m_series)) ?
4828                                 INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4829                 }else if(chan == old_RTSI_clock_channel)
4830                 {
4831                         data[1] = (devpriv->rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
4832                 }
4833                 return 2;
4834                 break;
4835         case INSN_CONFIG_SET_CLOCK_SRC:
4836                 return ni_set_master_clock(dev, data[1], data[2]);
4837                 break;
4838         case INSN_CONFIG_GET_CLOCK_SRC:
4839                 data[1] = devpriv->clock_source;
4840                 data[2] = devpriv->clock_ns;
4841                 return 3;
4842                 break;
4843         case INSN_CONFIG_SET_ROUTING:
4844                 return ni_set_rtsi_routing(dev, chan, data[1]);
4845                 break;
4846         case INSN_CONFIG_GET_ROUTING:
4847                 data[1] = ni_get_rtsi_routing(dev, chan);
4848                 return 2;
4849                 break;
4850         default:
4851                 return -EINVAL;
4852                 break;
4853         }
4854         return 1;
4855 }
4856
4857 static int cs5529_wait_for_idle(comedi_device *dev)
4858 {
4859         unsigned short status;
4860         const int timeout = HZ;
4861         int i;
4862
4863         for(i = 0; i < timeout; i++)
4864         {
4865                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4866                 if((status & CSS_ADC_BUSY) == 0)
4867                 {
4868                         break;
4869                 }
4870                 set_current_state(TASK_INTERRUPTIBLE);
4871                 if(schedule_timeout(1))
4872                 {
4873                         return -EIO;
4874                 }
4875         }
4876 //printk("looped %i times waiting for idle\n", i);
4877         if(i == timeout)
4878         {
4879                 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
4880                 return -ETIME;
4881         }
4882         return 0;
4883 }
4884
4885 static void cs5529_command(comedi_device *dev, unsigned short value)
4886 {
4887         static const int timeout = 100;
4888         int i;
4889
4890         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
4891         /* give time for command to start being serially clocked into cs5529.
4892          * this insures that the CSS_ADC_BUSY bit will get properly
4893          * set before we exit this function.
4894         */
4895         for(i = 0; i < timeout; i++)
4896         {
4897                 if((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
4898                         break;
4899                 comedi_udelay(1);
4900         }
4901 //printk("looped %i times writing command to cs5529\n", i);
4902         if(i == timeout)
4903         {
4904                 comedi_error(dev, "possible problem - never saw adc go busy?");
4905         }
4906 }
4907
4908 /* write to cs5529 register */
4909 static void cs5529_config_write(comedi_device *dev, unsigned int value, unsigned int reg_select_bits)
4910 {
4911         ni_ao_win_outw(dev, ((value >> 16) & 0xff), CAL_ADC_Config_Data_High_Word_67xx);
4912         ni_ao_win_outw(dev, (value & 0xffff), CAL_ADC_Config_Data_Low_Word_67xx);
4913         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4914         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
4915         if(cs5529_wait_for_idle(dev))
4916                 comedi_error(dev, "time or signal in cs5529_config_write()");
4917 }
4918
4919 /* read from cs5529 register */
4920 static unsigned int cs5529_config_read(comedi_device *dev, unsigned int reg_select_bits)
4921 {
4922         unsigned int value;
4923
4924         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
4925         cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
4926         if(cs5529_wait_for_idle(dev))
4927                 comedi_error(dev, "timeout or signal in cs5529_config_read()");
4928         value = (ni_ao_win_inw(dev, CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
4929         value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
4930         return value;
4931 }
4932
4933 static int cs5529_do_conversion(comedi_device *dev, unsigned short *data)
4934 {
4935         int retval;
4936         unsigned short status;
4937
4938         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
4939         retval = cs5529_wait_for_idle(dev);
4940         if(retval)
4941         {
4942                 comedi_error(dev, "timeout or signal in cs5529_do_conversion()");
4943                 return -ETIME;
4944         }
4945         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
4946         if(status & CSS_OSC_DETECT)
4947         {
4948                 rt_printk("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
4949                 return -EIO;
4950         }
4951         if(status & CSS_OVERRANGE)
4952         {
4953                 rt_printk("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
4954         }
4955         if(data)
4956         {
4957                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
4958                 /* cs5529 returns 16 bit signed data in bipolar mode */
4959                 *data ^= (1 << 15);
4960         }
4961         return 0;
4962 }
4963
4964 static int cs5529_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data)
4965 {
4966         int n, retval;
4967         unsigned short sample;
4968         unsigned int channel_select;
4969         const unsigned int INTERNAL_REF = 0x1000;
4970
4971         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4972          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4973          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4974         if(insn->chanspec & CR_ALT_SOURCE)
4975                 channel_select = INTERNAL_REF;
4976         else
4977                 channel_select = CR_CHAN(insn->chanspec);
4978         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
4979
4980         for(n = 0; n < insn->n; n++)
4981         {
4982                 retval = cs5529_do_conversion(dev, &sample);
4983                 if(retval < 0) return retval;
4984                 data[n] = sample;
4985         }
4986         return insn->n;
4987 }
4988
4989 static int init_cs5529(comedi_device *dev)
4990 {
4991         unsigned int config_bits = CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
4992
4993 #if 1
4994         /* do self-calibration */
4995         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, CSCMD_CONFIG_REGISTER);
4996         /* need to force a conversion for calibration to run */
4997         cs5529_do_conversion(dev, NULL);
4998 #else
4999         /* force gain calibration to 1 */
5000         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5001         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, CSCMD_CONFIG_REGISTER);
5002         if(cs5529_wait_for_idle(dev))
5003                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5004 #endif
5005         if(0)
5006         {
5007                 rt_printk("config: 0x%x\n", cs5529_config_read(dev, CSCMD_CONFIG_REGISTER));
5008                 rt_printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
5009                 rt_printk("offset: 0x%x\n", cs5529_config_read(dev, CSCMD_OFFSET_REGISTER));
5010         }
5011         return 0;
5012 }
5013
5014