From 74f8341b0214ff640ae97a059bace9c015001e9d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Micha=C5=82=20G=C3=B3rny?= Date: Tue, 15 Aug 2017 13:21:39 +0200 Subject: [PATCH] dev-ml/llvm-ocaml: Disable RISCV following upstream --- dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild | 2 +- dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild index f094afad03be..28df8234f9ed 100644 --- a/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild +++ b/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild @@ -19,7 +19,7 @@ EGIT_BRANCH="release_50" # Keep in sync with sys-devel/llvm ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC RISCV Sparc SystemZ X86 XCore ) + NVPTX PowerPC Sparc SystemZ X86 XCore ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild index d5f507e9e101..b377e8cd12a8 100644 --- a/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild +++ b/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild @@ -18,7 +18,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git # Keep in sync with sys-devel/llvm ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC RISCV Sparc SystemZ X86 XCore ) + NVPTX PowerPC Sparc SystemZ X86 XCore ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?} -- 2.26.2