From 2f25ca2030ebd53ff3e6f3d9f171a71dc22c9b5f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Micha=C5=82=20G=C3=B3rny?= Date: Mon, 12 Aug 2019 14:30:56 +0200 Subject: [PATCH] sys-devel/llvm: RISCV is no longer exp. in 9.0+ MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Closes: https://bugs.gentoo.org/691816 Signed-off-by: Michał Górny --- sys-devel/llvm/llvm-10.0.0.9999.ebuild | 4 ++-- sys-devel/llvm/llvm-9.0.0.9999.ebuild | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sys-devel/llvm/llvm-10.0.0.9999.ebuild b/sys-devel/llvm/llvm-10.0.0.9999.ebuild index 00350a42ae25..268f913570bd 100644 --- a/sys-devel/llvm/llvm-10.0.0.9999.ebuild +++ b/sys-devel/llvm/llvm-10.0.0.9999.ebuild @@ -18,10 +18,10 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git https://github.com/llvm-mirror/llvm.git" # Those are in lib/Targets, without explicit CMakeLists.txt mention -ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 RISCV ) +ALL_LLVM_EXPERIMENTAL_TARGETS=( AVR Nios2 ) # Keep in sync with CMakeLists.txt ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore + NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore "${ALL_LLVM_EXPERIMENTAL_TARGETS[@]}" ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) diff --git a/sys-devel/llvm/llvm-9.0.0.9999.ebuild b/sys-devel/llvm/llvm-9.0.0.9999.ebuild index af9151627bc9..1e231591b904 100644 --- a/sys-devel/llvm/llvm-9.0.0.9999.ebuild +++ b/sys-devel/llvm/llvm-9.0.0.9999.ebuild @@ -20,7 +20,7 @@ EGIT_BRANCH="release_90" # Keep in sync with CMakeLists.txt ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430 - NVPTX PowerPC Sparc SystemZ WebAssembly X86 XCore ) + NVPTX PowerPC RISCV Sparc SystemZ WebAssembly X86 XCore ) ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" ) # Additional licenses: -- 2.26.2