From: Mike Frysinger Date: Sun, 29 Mar 2015 19:24:29 +0000 (+0000) Subject: Drop old mips-specific patches -- they can use newer gcc-4 versions. The r10k patch... X-Git-Url: http://git.tremily.us/gitweb.cgi?a=commitdiff_plain;h=ff83c826fe86ffaa0340081b3eeae36e0bbb7d53;p=gentoo.git Drop old mips-specific patches -- they can use newer gcc-4 versions. The r10k patch has been moved to the gentoo patchset. Package-Manager: portage-2.2.18/cvs/Linux x86_64 Manifest-Sign-Key: 0xD2E96200 --- diff --git a/sys-devel/gcc/ChangeLog b/sys-devel/gcc/ChangeLog index 1d100fbb3c62..80cd0e237352 100644 --- a/sys-devel/gcc/ChangeLog +++ b/sys-devel/gcc/ChangeLog @@ -1,6 +1,15 @@ # ChangeLog for sys-devel/gcc # Copyright 1999-2015 Gentoo Foundation; Distributed under the GPL v2 -# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/ChangeLog,v 1.1053 2015/03/29 19:17:06 vapier Exp $ +# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/ChangeLog,v 1.1054 2015/03/29 19:24:26 vapier Exp $ + + 29 Mar 2015; Mike Frysinger + -files/3.4.1/gcc-3.4.1-mips-n32only.patch, + -files/3.4.1/gcc-3.4.1-mips-n64only.patch, + -files/3.4.2/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch, + -files/3.4.2/gcc-3.4.x-mips-add-march-r10k.patch, gcc-3.4.6-r2.ebuild, + metadata.xml: + Drop old mips-specific patches -- they can use newer gcc-4 versions. The r10k + patch has been moved to the gentoo patchset. 29 Mar 2015; Mike Frysinger metadata.xml: Add USE=cilk to control support for the Cilk Plus language. diff --git a/sys-devel/gcc/Manifest b/sys-devel/gcc/Manifest index 7d99aa205d14..99228d7d4d72 100644 --- a/sys-devel/gcc/Manifest +++ b/sys-devel/gcc/Manifest @@ -2,10 +2,6 @@ Hash: SHA256 AUX 3.3.4/libffi-without-libgcj.patch 890 SHA256 a422ebf05e279bdcb15627363af8101e4d6a54ca037d6da11c13b4768799d974 SHA512 6204588808a37a13dffc8c6bdf70eb453107413d0c8fffddeb360444e3e605f1ceb42c41905cfa1c4f9cbb1b22dc290e68d2728dbddb0f4d0406dd8dca6789a0 WHIRLPOOL 7260ba32fc7d60f1fa4d8667c929e16f3bdf9fe953c823c5b6876d4fea4d4fed52e67aec92cbb599d6327eac009bc4fbbc06ba85acf9848bf346384af0523363 -AUX 3.4.1/gcc-3.4.1-mips-n32only.patch 614 SHA256 f75cbf7aab59b73f23f2a6b327f9c00bfa87f38a67a054c4aa5637dcbb8dad1e SHA512 afdbf733c7325d0a7c34c6027c49a4e18af64f2e042680756ebfdd836084e050301d748a2f3ef20c73d20078082b95a6a9d9a1ed05222db4d82be213ebc0f6a2 WHIRLPOOL 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gcc/config/mips/t-linux64 -=================================================================== -RCS file: /cvsroot/gcc/gcc/gcc/config/mips/t-linux64,v -retrieving revision 1.3 -diff -u -r1.3 t-linux64 ---- gcc/config/mips/t-linux64 4 Jun 2003 05:35:15 -0000 1.3 -+++ gcc/config/mips/t-linux64 10 Aug 2004 18:26:26 -0000 -@@ -1,6 +1,6 @@ --MULTILIB_OPTIONS = mabi=32/mabi=n32/mabi=64 --MULTILIB_DIRNAMES = o32 32 64 --MULTILIB_OSDIRNAMES = ../lib ../lib32 ../lib64 -+MULTILIB_OPTIONS = mabi=n32 -+MULTILIB_DIRNAMES = -+MULTILIB_OSDIRNAMES = - - EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o - diff --git a/sys-devel/gcc/files/3.4.1/gcc-3.4.1-mips-n64only.patch b/sys-devel/gcc/files/3.4.1/gcc-3.4.1-mips-n64only.patch deleted file mode 100644 index 81baf62ec62a..000000000000 --- a/sys-devel/gcc/files/3.4.1/gcc-3.4.1-mips-n64only.patch +++ /dev/null @@ -1,17 +0,0 @@ -Index: gcc/config/mips/t-linux64 -=================================================================== -RCS file: /cvsroot/gcc/gcc/gcc/config/mips/t-linux64,v -retrieving revision 1.3 -diff -u -r1.3 t-linux64 ---- gcc/config/mips/t-linux64 4 Jun 2003 05:35:15 -0000 1.3 -+++ gcc/config/mips/t-linux64 10 Aug 2004 18:26:53 -0000 -@@ -1,6 +1,6 @@ --MULTILIB_OPTIONS = mabi=32/mabi=n32/mabi=64 --MULTILIB_DIRNAMES = o32 32 64 --MULTILIB_OSDIRNAMES = ../lib ../lib32 ../lib64 -+MULTILIB_OPTIONS = mabi=n64 -+MULTILIB_DIRNAMES = -+MULTILIB_OSDIRNAMES = - - EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o - diff --git a/sys-devel/gcc/files/3.4.2/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch b/sys-devel/gcc/files/3.4.2/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch deleted file mode 100644 index 02edc3709e2a..000000000000 --- a/sys-devel/gcc/files/3.4.2/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch +++ /dev/null @@ -1,366 +0,0 @@ -diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.c gcc-3.4.6/gcc/config/mips/mips.c ---- gcc-3.4.6.orig/gcc/config/mips/mips.c 2005-07-31 04:35:15.000000000 -0400 -+++ gcc-3.4.6/gcc/config/mips/mips.c 2006-04-08 17:41:44.000000000 -0400 -@@ -8801,6 +8801,11 @@ mips_reorg (void) - dbr_schedule (get_insns (), rtl_dump_file); - mips_avoid_hazards (); - } -+ if (mips_r10k_cache_barrier) -+ { -+ static int r10k_insert_cache_barriers (void); -+ r10k_insert_cache_barriers (); -+ } - } - - /* We need to use a special set of functions to handle hard floating -@@ -9661,5 +9666,5 @@ irix_section_type_flags (tree decl, cons - } - - #endif /* TARGET_IRIX */ -- -+#include "r10k-cacheb.c" - #include "gt-mips.h" -diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.h gcc-3.4.6/gcc/config/mips/mips.h ---- gcc-3.4.6.orig/gcc/config/mips/mips.h 2004-07-14 20:42:49.000000000 -0400 -+++ gcc-3.4.6/gcc/config/mips/mips.h 2006-04-08 17:41:01.000000000 -0400 -@@ -122,6 +122,7 @@ extern const char *mips_tune_string; - extern const char *mips_isa_string; /* for -mips{1,2,3,4} */ - extern const char *mips_abi_string; /* for -mabi={32,n32,64} */ - extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */ -+extern const char *mips_r10k_cache_barrier;/* for -mr10k-cache-barrier[={1,2}] */ - extern int mips_string_length; /* length of strings for mips16 */ - extern const struct mips_cpu_info mips_cpu_info_table[]; - extern const struct mips_cpu_info *mips_arch_info; -@@ -752,6 +753,10 @@ extern const struct mips_cpu_info *mips_ - N_("Don't call any cache flush functions"), 0}, \ - { "flush-func=", &mips_cache_flush_func, \ - N_("Specify cache flush function"), 0}, \ -+ { "r10k-cache-barrier", &mips_r10k_cache_barrier, \ -+ N_("[=1|2]\tGenerate cache barriers for SGI Indigo2/O2 R10k"), 0}, \ -+ { "ip28-cache-barrier", &mips_r10k_cache_barrier, \ -+ N_(""), 0}, \ - } - - /* This is meant to be redefined in the host dependent files. */ -diff -Naurp gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c gcc-3.4.6/gcc/config/mips/r10k-cacheb.c ---- gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-3.4.6/gcc/config/mips/r10k-cacheb.c 2006-04-08 17:41:22.000000000 -0400 -@@ -0,0 +1,318 @@ -+/* Subroutines used for MIPS code generation: generate cache-barriers -+ for SiliconGraphics IP28 and IP32/R10000 kernel-code. -+ Copyright (C) 2005,2006 peter fuerst, pf@net.alphadv.de. -+ -+This file is intended to become part of GCC. -+ -+This file is free software; you can redistribute it and/or modify it -+under the terms of the GNU General Public License as published -+by the Free Software Foundation; either version 2, or (at your -+option) any later version. -+ -+This file is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to the -+Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, -+MA 02110-1301 USA. */ -+ -+ -+#define ASM_R10K_CACHE_BARRIER "cache 0x14,0($sp)" -+ -+/* Some macros, ported back from 4.x ... */ -+ -+#define CALL_P(X) (GET_CODE (X) == CALL_INSN) -+#define MEM_P(X) (GET_CODE (X) == MEM) -+#define NONJUMP_INSN_P(X) (GET_CODE (X) == INSN) -+ -+#define SEQ_BEGIN(insn) \ -+ (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE \ -+ ? XVECEXP (PATTERN (insn), 0, 0) \ -+ : (insn)) -+ -+#define SEQ_END(insn) \ -+ (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE \ -+ ? XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1) \ -+ : (insn)) -+ -+#define FOR_EACH_SUBINSN(subinsn, insn) \ -+ for ((subinsn) = SEQ_BEGIN (insn); \ -+ (subinsn) != NEXT_INSN (SEQ_END (insn)); \ -+ (subinsn) = NEXT_INSN (subinsn)) -+ -+ -+/* Nonzero means generate special cache barriers to inhibit speculative -+ stores which might endanger cache coherency or reference invalid -+ addresses (especially on SGI's Indigo2 R10k (IP28)). */ -+const char *mips_r10k_cache_barrier; -+static int TARGET_R10K_SPECEX; -+ -+/* Check, whether an instruction is a possibly harmful store instruction, -+ i.e. a store which might cause damage, if speculatively executed. */ -+ -+/* Return truth value whether the expression `*memx' instantiates -+ (mem:M (not (stackpointer_address or constant))). */ -+ -+static int -+is_stack_pointer (rtx *x, void *data) -+{ -+ return (*x == stack_pointer_rtx); -+} -+ -+static int -+check_p_mem_expr (rtx *memx, void *data) -+{ -+ if (!MEM_P (*memx) || for_each_rtx (memx, is_stack_pointer, 0)) -+ return 0; -+ -+ /* Stores/Loads to/from constant addresses can be considered -+ harmless, since: -+ 1) the address is always valid, even when taken speculatively. -+ 2a) the location is (hopefully) never used as a dma-target, thus -+ there is no danger of cache-inconsistency. -+ 2b) uncached loads/stores are guaranteed to be non-speculative. */ -+ if ( CONSTANT_P(XEXP (*memx, 0)) ) -+ return 0; -+ -+ return 1; -+} -+ -+/* Return truth value whether we find (set (mem:M (non_stackpointer_address) -+ ...)) in instruction-pattern `body'. -+ Here we assume, that addressing with the stackpointer accesses neither -+ uncached-aliased nor invalid memory. -+ (May be, this applies to the global pointer and frame pointer also, -+ but its saver not to assume it. And probably it's not worthwile to -+ regard these registers) -+ -+ Speculative loads from invalid addresses also cause bus errors... -+ So check for (set (reg:M ...) (mem:M (non_stackpointer_address))) -+ too, unless there is an enhanced bus-error handler. */ -+ -+static int -+check_p_pattern_for_store (rtx *body, void *data) -+{ -+ if (*body && GET_CODE (*body) == SET) -+ { -+ /* Cache-barriers for SET_SRC may be requested as well. */ -+ if (!(TARGET_R10K_SPECEX & 2)) -+ body = &SET_DEST(*body); -+ -+ if (for_each_rtx (body, check_p_mem_expr, 0)) -+ return 1; -+ -+ /* Don't traverse sub-expressions again. */ -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+strmatch (const char *txt, const char *match) -+{ -+ return !strncmp(txt, match, strlen (match)); -+} -+ -+/* Check for (ins (set (mem:M (dangerous_address)) ...)) or end of the -+ current basic block in instruction `insn'. -+ `state': (internal) recursion-counter and delayslot-flag -+ Criteria to recognize end-of/next basic-block are reduplicated here -+ from final_scan_insn. -+ return >0: `insn' is critical. -+ return <0: `insn' is at end of current basic-block. -+ return 0: `insn' can be ignored. */ -+ -+static int -+check_insn_for_store (int state, rtx insn) -+{ -+ rtx body; -+ -+ if (INSN_DELETED_P (insn)) -+ return 0; -+ -+ if (LABEL_P (insn)) -+ return -1; -+ -+ if (CALL_P (insn) || JUMP_P (insn) || NONJUMP_INSN_P (insn)) -+ { -+ body = PATTERN (insn); -+ if (GET_CODE (body) == SEQUENCE) -+ { -+ /* A delayed-branch sequence. */ -+ rtx insq; -+ FOR_EACH_SUBINSN(insq, insn) -+ if (! INSN_DELETED_P (insq)) -+ { -+ /* |1: delay-slot completely contained in sequence. */ -+ if (check_insn_for_store (8+state|1, insq) > 0) -+ return 1; -+ } -+ /* Following a (conditional) branch sequence, we have a new -+ basic block. */ -+ if (JUMP_P (SEQ_BEGIN(insn))) -+ return -1; -+ /* Handle a call sequence like a conditional branch sequence. */ -+ if (CALL_P (SEQ_BEGIN(insn))) -+ return -1; -+ } -+ if (GET_CODE (body) == PARALLEL) -+ if (for_each_rtx (&body, check_p_pattern_for_store, 0)) -+ return 1; -+ -+ /* Now, only a `simple' INSN or JUMP_INSN remains to be checked. */ -+ if (NONJUMP_INSN_P (insn)) -+ { -+ /* Since we don't know what's inside, we must take inline -+ assembly to be dangerous. */ -+ if (GET_CODE (body) == ASM_INPUT) -+ { -+ const char *t = XSTR (body, 0); -+ if (t && !strmatch(t, ASM_R10K_CACHE_BARRIER)) -+ return 1; -+ } -+ -+ if (check_p_pattern_for_store (&body, 0) > 0) -+ return 1; -+ } -+ /* Handle a CALL_INSN instruction like a conditional branch. */ -+ if (JUMP_P (insn) || CALL_P (insn)) -+ { -+ /* Following a (conditional) branch, we have a new basic block. */ -+ /* But check insn(s) in delay-slot first. If we could know in -+ advance that this jump is in `.reorder' mode, where gas will -+ insert a `nop' into the delay-slot, we could skip this test. -+ Since we don't know, always assume `.noreorder', sometimes -+ emitting a cache-barrier, that isn't needed. */ -+ /* But if we are here recursively, already checking a (pseudo-) -+ delay-slot, we are done. */ -+ if ( !(state & 1) ) -+ for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn)) -+ { -+ if (LABEL_P (insn) || CALL_P (insn) || JUMP_P (insn)) -+ /* Not in delay-slot at all. */ -+ break; -+ -+ if (NONJUMP_INSN_P (insn)) -+ { -+ if (GET_CODE (PATTERN (insn)) == SEQUENCE) -+ /* Not in delay-slot at all. */ -+ break; -+ -+ if (check_insn_for_store (8+state|1, insn) > 0) -+ return 1; -+ /* We're done anyway. */ -+ break; -+ } -+ /* skip NOTE,... */; -+ } -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+ -+/* Scan a basic block, starting with `insn', for a possibly harmful store -+ instruction. If found, output a cache barrier at the start of this -+ block. */ -+ -+static int -+bb_insert_store_cache_barrier (rtx head, rtx nxtb) -+{ -+ rtx insn = head; -+ -+ if (!insn || insn == nxtb) -+ return 0; -+ -+ while ((insn = NEXT_INSN (insn)) && insn != nxtb) -+ { -+ int found; -+ -+ if (NOTE_INSN_BASIC_BLOCK_P(insn)) /* See scan_1_bb_for_store() */ -+ break; -+ -+ found = check_insn_for_store (0, insn); -+ if (found < 0) -+ break; -+ if (found > 0) -+ { -+ /* found critical store instruction */ -+ insn = gen_rtx_ASM_INPUT (VOIDmode, -+ ASM_R10K_CACHE_BARRIER "\t" -+ ASM_COMMENT_START " Cache Barrier"); -+ /* Here we rely on the assumption, that an explicit delay-slot -+ - if any - is already embedded (in a sequence) in 'head'! */ -+ insn = emit_insn_after (insn, head); -+ return 1; -+ } -+ } -+ return 0; -+} -+ -+ -+/* Scan one basic block for a possibly harmful store instruction. -+ If found, insert a cache barrier at the start of this block, -+ return number of inserted cache_barriers. */ -+ -+static int -+scan_1_bb_for_store (rtx head, rtx end) -+{ -+ rtx nxtb; -+ int count; -+ -+ /* Note: 'end' is not necessarily reached from 'head' (hidden in -+ SEQUENCE, PARALLEL), but 'nxtb' is. */ -+ nxtb = NEXT_INSN (end); -+ -+ /* Each basic block starts with zero or more CODE_LABEL(s), followed -+ by one NOTE_INSN_BASIC_BLOCK. -+ Note: bb_head may equal next_insn(bb_end) already ! */ -+ while (head && head != nxtb && LABEL_P (head)) -+ head = NEXT_INSN (head); -+ -+ if (!head || head == nxtb) -+ return 0; -+ -+ /* Handle the basic block itself, at most up to next CALL_INSN. */ -+ count = bb_insert_store_cache_barrier (head, nxtb); -+ -+ /* 1) Handle any CALL_INSN instruction like a conditional branch. -+ 2) There may be "basic blocks" in the list, which are no basic blocks -+ at all. (containing CODE_LABELs in the body or gathering several -+ other basic blocks (e.g. bb5 containing bb6,bb7,bb8)). */ -+ -+ while ((head = NEXT_INSN (head)) && head != nxtb) -+ { -+ if (INSN_DELETED_P (head)) -+ continue; -+ -+ /* Later we'll be called again for this bb on its own. */ -+ if (NOTE_INSN_BASIC_BLOCK_P(head)) -+ break; -+ -+ if (CALL_P (SEQ_BEGIN (head)) || LABEL_P (head)) -+ count += bb_insert_store_cache_barrier (head, nxtb); -+ } -+ return count; -+} -+ -+static int -+r10k_insert_cache_barriers (void) -+{ -+ if (mips_r10k_cache_barrier) -+ { -+ basic_block bb; -+ -+ const char *s = mips_r10k_cache_barrier; -+ /* Default is to protect stores (only). */ -+ TARGET_R10K_SPECEX = 1 | strtol(*s != '=' ? s:s+1, (char**)0, 0); -+ -+ FOR_EACH_BB (bb) -+ if (0 <= bb->index) -+ scan_1_bb_for_store (BB_HEAD (bb), BB_END (bb)); -+ } -+ return 0; -+} diff --git a/sys-devel/gcc/files/3.4.2/gcc-3.4.x-mips-add-march-r10k.patch b/sys-devel/gcc/files/3.4.2/gcc-3.4.x-mips-add-march-r10k.patch deleted file mode 100644 index d02a5e91f1e7..000000000000 --- a/sys-devel/gcc/files/3.4.2/gcc-3.4.x-mips-add-march-r10k.patch +++ /dev/null @@ -1,460 +0,0 @@ -diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.c gcc-3.4.1/gcc/config/mips/mips.c ---- gcc-3.4.1.orig/gcc/config/mips/mips.c 2004-06-28 09:58:42.000000000 -0400 -+++ gcc-3.4.1/gcc/config/mips/mips.c 2004-08-09 22:37:21.983939192 -0400 -@@ -707,6 +707,7 @@ const struct mips_cpu_info mips_cpu_info - - /* MIPS IV */ - { "r8000", PROCESSOR_R8000, 4 }, -+ { "r10000", PROCESSOR_R10000, 4 }, - { "vr5000", PROCESSOR_R5000, 4 }, - { "vr5400", PROCESSOR_R5400, 4 }, - { "vr5500", PROCESSOR_R5500, 4 }, -@@ -9401,6 +9402,9 @@ mips_issue_rate (void) - { - switch (mips_tune) - { -+ case PROCESSOR_R10000: -+ return 4; -+ - case PROCESSOR_R5400: - case PROCESSOR_R5500: - case PROCESSOR_R7000: -diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.h gcc-3.4.1/gcc/config/mips/mips.h ---- gcc-3.4.1.orig/gcc/config/mips/mips.h 2004-03-11 16:52:33.000000000 -0500 -+++ gcc-3.4.1/gcc/config/mips/mips.h 2004-08-09 01:02:35.042149496 -0400 -@@ -66,6 +66,7 @@ enum processor_type { - PROCESSOR_R7000, - PROCESSOR_R8000, - PROCESSOR_R9000, -+ PROCESSOR_R10000, - PROCESSOR_SB1, - PROCESSOR_SR71000 - }; -diff -Naurp gcc-3.4.1.orig/gcc/config/mips/mips.md gcc-3.4.1/gcc/config/mips/mips.md ---- gcc-3.4.1.orig/gcc/config/mips/mips.md 2004-06-25 03:35:30.000000000 -0400 -+++ gcc-3.4.1/gcc/config/mips/mips.md 2004-08-09 04:55:10.158649320 -0400 -@@ -103,6 +103,7 @@ - ;; arith integer arithmetic instruction - ;; darith double precision integer arithmetic instructions - ;; const load constant -+;; shift integer shift - ;; imul integer multiply - ;; imadd integer multiply-add - ;; idiv integer divide -@@ -120,7 +121,7 @@ - ;; multi multiword sequence (or user asm statements) - ;; nop no operation - (define_attr "type" -- "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop" -+ "unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,shift,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop" - (cond [(eq_attr "jal" "!unset") (const_string "call") - (eq_attr "got" "load") (const_string "load")] - (const_string "unknown"))) -@@ -214,7 +215,7 @@ - ;; Attribute describing the processor. This attribute must match exactly - ;; with the processor_type enumeration in mips.h. - (define_attr "cpu" -- "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000" -+ "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sr71000" - (const (symbol_ref "mips_tune"))) - - ;; The type of hardware hazard associated with this instruction. -@@ -305,12 +306,12 @@ - - (define_function_unit "memory" 1 0 - (and (eq_attr "type" "load") -- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000")) -+ (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000,r10000")) - 3 0) - - (define_function_unit "memory" 1 0 - (and (eq_attr "type" "load") -- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000")) -+ (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000,r10000")) - 2 0) - - (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0) -@@ -323,7 +324,7 @@ - - (define_function_unit "imuldiv" 1 0 - (and (eq_attr "type" "imul,imadd") -- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000")) -+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000,r10000")) - 17 17) - - ;; On them mips16, we want to stronly discourage a mult from appearing -@@ -375,7 +376,7 @@ - - (define_function_unit "imuldiv" 1 0 - (and (eq_attr "type" "idiv") -- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000")) -+ (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000,r10000")) - 38 38) - - (define_function_unit "imuldiv" 1 0 -@@ -424,6 +425,40 @@ - (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000"))) - 68 68) - -+;; R10000 has 2 integer ALUs -+(define_function_unit "alu" 2 0 -+ (and (eq_attr "type" "arith,darith,shift") -+ (eq_attr "cpu" "r10000")) -+ 1 0) -+ -+;; Only ALU1 can do shifts. We model shifts as an additional unit -+(define_function_unit "alu1" 1 0 -+ (and (eq_attr "type" "shift") -+ (eq_attr "cpu" "r10000")) -+ 1 0) -+ -+;; only ALU2 does multiplications and divisions -+(define_function_unit "alu2" 1 0 -+ (and (eq_attr "type" "imul") -+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r10000"))) -+ 6 6) -+ -+(define_function_unit "alu2" 1 0 -+ (and (eq_attr "type" "imul") -+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r10000"))) -+ 10 10) -+ -+(define_function_unit "alu2" 1 0 -+ (and (eq_attr "type" "idiv") -+ (and (eq_attr "mode" "SI") (eq_attr "cpu" "r10000"))) -+ 35 35) -+ -+(define_function_unit "alu2" 1 0 -+ (and (eq_attr "type" "idiv") -+ (and (eq_attr "mode" "DI") (eq_attr "cpu" "r10000"))) -+ 67 67) -+ -+ - ;; The R4300 does *NOT* have a separate Floating Point Unit, instead - ;; the FP hardware is part of the normal ALU circuitry. This means FP - ;; instructions affect the pipe-line, and no functional unit -@@ -432,11 +467,11 @@ - ;; instructions to be processed in the "imuldiv" unit. - - (define_function_unit "adder" 1 1 -- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")) -+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r10000")) - 3 0) - - (define_function_unit "adder" 1 1 -- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000")) -+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000,r10000")) - 2 0) - - (define_function_unit "adder" 1 1 -@@ -444,7 +479,7 @@ - 1 0) - - (define_function_unit "adder" 1 1 -- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300")) -+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r10000")) - 4 0) - - (define_function_unit "adder" 1 1 -@@ -456,6 +491,10 @@ - 3 0) - - (define_function_unit "adder" 1 1 -+ (and (eq_attr "type" "fadd,fmadd") (eq_attr "cpu" "r10000")) -+ 2 0) -+ -+(define_function_unit "adder" 1 1 - (and (eq_attr "type" "fabs,fneg") - (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000")) - 2 0) -@@ -467,7 +506,7 @@ - (define_function_unit "mult" 1 1 - (and (eq_attr "type" "fmul") - (and (eq_attr "mode" "SF") -- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000"))) -+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r10000"))) - 7 0) - - (define_function_unit "mult" 1 1 -@@ -487,7 +526,7 @@ - - (define_function_unit "mult" 1 1 - (and (eq_attr "type" "fmul") -- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))) -+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r10000"))) - 8 0) - - (define_function_unit "mult" 1 1 -@@ -500,10 +539,14 @@ - (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000"))) - 6 0) - -+(define_function_unit "mult" 1 1 -+ (and (eq_attr "type" "fmul,fmadd") (eq_attr "cpu" "r10000")) -+ 2 0) -+ - (define_function_unit "divide" 1 1 - (and (eq_attr "type" "fdiv") - (and (eq_attr "mode" "SF") -- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000"))) -+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r10000"))) - 23 0) - - (define_function_unit "divide" 1 1 -@@ -529,7 +572,7 @@ - (define_function_unit "divide" 1 1 - (and (eq_attr "type" "fdiv") - (and (eq_attr "mode" "DF") -- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300"))) -+ (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r10000"))) - 36 0) - - (define_function_unit "divide" 1 1 -@@ -547,10 +590,21 @@ - (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650"))) - 61 0) - -+;; divisions keep multiplier busy on R10000 -+(define_function_unit "mult" 1 1 -+ (and (eq_attr "type" "fdiv") -+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "r10000"))) -+ 12 14) -+ -+(define_function_unit "mult" 1 1 -+ (and (eq_attr "type" "fdiv") -+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r10000"))) -+ 19 21) -+ - ;;; ??? Is this number right? - (define_function_unit "divide" 1 1 - (and (eq_attr "type" "fsqrt,frsqrt") -- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) -+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r10000"))) - 54 0) - - (define_function_unit "divide" 1 1 -@@ -566,7 +620,7 @@ - ;;; ??? Is this number right? - (define_function_unit "divide" 1 1 - (and (eq_attr "type" "fsqrt,frsqrt") -- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000"))) -+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r10000"))) - 112 0) - - (define_function_unit "divide" 1 1 -@@ -579,6 +633,17 @@ - (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000"))) - 36 0) - -+;; sqrt is executed by multiplier on R10000 -+(define_function_unit "mult" 1 1 -+ (and (eq_attr "type" "fsqrt") -+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "r10000"))) -+ 18 20) -+ -+(define_function_unit "mult" 1 1 -+ (and (eq_attr "type" "fsqrt") -+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r10000"))) -+ 33 35) -+ - ;; R4300 FP instruction classes treated as part of the "imuldiv" - ;; functional unit: - -@@ -3157,7 +3222,7 @@ dsrl\t%3,%3,1\n\ - "@ - sll\t%0,%1,0 - sw\t%1,%0" -- [(set_attr "type" "darith,store") -+ [(set_attr "type" "shift,store") - (set_attr "mode" "SI") - (set_attr "extended_mips16" "yes,*")]) - -@@ -3191,7 +3256,7 @@ dsrl\t%3,%3,1\n\ - (match_operand:DI 2 "small_int" "I"))))] - "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32" - "dsra\t%0,%1,%2" -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI")]) - - (define_insn "" -@@ -3200,7 +3265,7 @@ dsrl\t%3,%3,1\n\ - (const_int 32))))] - "TARGET_64BIT && !TARGET_MIPS16" - "dsra\t%0,%1,32" -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI")]) - - -@@ -5241,7 +5306,7 @@ dsrl\t%3,%3,1\n\ - - return "sll\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI")]) - - (define_insn "ashlsi3_internal1_extend" -@@ -5255,7 +5320,7 @@ dsrl\t%3,%3,1\n\ - - return "sll\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI")]) - - -@@ -5273,7 +5338,7 @@ dsrl\t%3,%3,1\n\ - - return "sll\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI") - (set_attr_alternative "length" - [(const_int 4) -@@ -5374,7 +5439,7 @@ sll\t%L0,%L1,%2\n\ - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sll\t%M0,%L1,%2\;move\t%L0,%."; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "8")]) - -@@ -5429,7 +5494,7 @@ sll\t%L0,%L1,%2\n\ - - return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2"; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "16")]) - -@@ -5513,7 +5578,7 @@ sll\t%L0,%L1,%2\n\ - - return "dsll\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI")]) - - (define_insn "" -@@ -5530,7 +5595,7 @@ sll\t%L0,%L1,%2\n\ - - return "dsll\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr_alternative "length" - [(const_int 4) -@@ -5591,7 +5656,7 @@ sll\t%L0,%L1,%2\n\ - - return "sra\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI")]) - - (define_insn "ashrsi3_internal2" -@@ -5608,7 +5673,7 @@ sll\t%L0,%L1,%2\n\ - - return "sra\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI") - (set_attr_alternative "length" - [(const_int 4) -@@ -5705,7 +5770,7 @@ sra\t%M0,%M1,%2\n\ - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31"; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "8")]) - -@@ -5760,7 +5825,7 @@ sra\t%M0,%M1,%2\n\ - - return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2"; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "16")]) - -@@ -5844,7 +5909,7 @@ sra\t%M0,%M1,%2\n\ - - return "dsra\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI")]) - - (define_insn "" -@@ -5858,7 +5923,7 @@ sra\t%M0,%M1,%2\n\ - - return "dsra\t%0,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr_alternative "length" - [(const_int 4) -@@ -5918,7 +5983,7 @@ sra\t%M0,%M1,%2\n\ - - return "srl\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI")]) - - (define_insn "lshrsi3_internal2" -@@ -5935,7 +6000,7 @@ sra\t%M0,%M1,%2\n\ - - return "srl\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "SI") - (set_attr_alternative "length" - [(const_int 4) -@@ -6056,7 +6121,7 @@ srl\t%M0,%M1,%2\n\ - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "srl\t%L0,%M1,%2\;move\t%M0,%."; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "8")]) - -@@ -6111,7 +6176,7 @@ srl\t%M0,%M1,%2\n\ - - return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2"; - } -- [(set_attr "type" "darith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr "length" "16")]) - -@@ -6195,7 +6260,7 @@ srl\t%M0,%M1,%2\n\ - - return "dsrl\t%0,%1,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI")]) - - (define_insn "" -@@ -6209,7 +6274,7 @@ srl\t%M0,%M1,%2\n\ - - return "dsrl\t%0,%2"; - } -- [(set_attr "type" "arith") -+ [(set_attr "type" "shift") - (set_attr "mode" "DI") - (set_attr_alternative "length" - [(const_int 4) diff --git a/sys-devel/gcc/gcc-3.4.6-r2.ebuild b/sys-devel/gcc/gcc-3.4.6-r2.ebuild index 238d27d282fd..100cf0795e28 100644 --- a/sys-devel/gcc/gcc-3.4.6-r2.ebuild +++ b/sys-devel/gcc/gcc-3.4.6-r2.ebuild @@ -1,6 +1,6 @@ -# Copyright 1999-2014 Gentoo Foundation +# Copyright 1999-2015 Gentoo Foundation # Distributed under the terms of the GNU General Public License v2 -# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/gcc-3.4.6-r2.ebuild,v 1.38 2014/10/23 23:48:17 vapier Exp $ +# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/gcc-3.4.6-r2.ebuild,v 1.39 2015/03/29 19:24:26 vapier Exp $ EAPI="2" @@ -14,7 +14,6 @@ D_VER="0.24" inherit eutils toolchain KEYWORDS="-* alpha amd64 arm ~ia64 ~mips ppc ppc64 ~s390 ~sh sparc x86 ~x86-fbsd" -IUSE="ip28 ip32r10k n32 n64" # we need a proper glibc version for the Scrt1.o provided to the pie-ssp specs # NOTE: we SHOULD be using at least binutils 2.15.90.0.1 everywhere for proper @@ -41,34 +40,6 @@ src_prepare() { # Arch stuff case $(tc-arch) in - mips) - # If mips, and we DON'T want multilib, then rig gcc to only use n32 OR n64 - if ! is_multilib; then - use n32 && epatch "${FILESDIR}"/3.4.1/gcc-3.4.1-mips-n32only.patch - use n64 && epatch "${FILESDIR}"/3.4.1/gcc-3.4.1-mips-n64only.patch - fi - - # Patch forward-ported from a gcc-3.0.x patch that adds -march=r10000 and - # -mtune=r10000 support to gcc (Allows the compiler to generate code to - # take advantage of R10k's second ALU, perform shifts, etc.. - # - # Needs re-porting to DFA in gcc-4.0 - Any Volunteers? :) - epatch "${FILESDIR}"/3.4.2/gcc-3.4.x-mips-add-march-r10k.patch - - # This is a very special patch -- it allows us to build semi-usable kernels - # on SGI IP28 (Indigo2 Impact R10000) systems. The patch is henceforth - # regarded as a kludge by upstream, and thus, it will never get accepted upstream, - # but for our purposes of building a kernel, it works. - # Unless you're building an IP28 kernel, you really don't need care about what - # this patch does, because if you are, you are probably already aware of what - # it does. - # All that said, the abilities of this patch are disabled by default and need - # to be enabled by passing -mip28-cache-barrier. Only used to build kernels, - # There is the possibility it may be used for very specific userland apps too. - if use ip28 || use ip32r10k; then - epatch "${FILESDIR}"/3.4.2/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch - fi - ;; amd64) if is_multilib ; then sed -i -e '/GLIBCXX_IS_NATIVE=/s:false:true:' libstdc++-v3/configure || die diff --git a/sys-devel/gcc/metadata.xml b/sys-devel/gcc/metadata.xml index c5639e793ed0..a181266b55e0 100644 --- a/sys-devel/gcc/metadata.xml +++ b/sys-devel/gcc/metadata.xml @@ -12,17 +12,11 @@ Build the GCC Go language frontend. Add support for the framework for loop optimizations based on a polyhedral intermediate representation - Enable building a compiler capable of building a kernel - for SGI Indigo2 Impact R10000 (IP28) - Enable building a compiler capable of building an - experimental kernel for SGI O2 w/ R1x000 CPUs (IP32) Build SSP support into a dedicated library rather than use the code in the C library (DO NOT ENABLE THIS IF YOU DON'T KNOW WHAT IT DOES) Add support for mudflap, a pointer use checking library Allow for SLOTs to include minor version (3.3.4 instead of just 3.3) - Enable n32 ABI support on mips - Enable n64 ABI support on mips Disable PIE support (NOT FOR GENERAL USE) Disable SSP support (NOT FOR GENERAL USE) Build support for the Objective C code language