dev-ml/llvm-ocaml: Disable RISCV following upstream

diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild
index f094afad03be368e3b3f245074de9febf158f17e..28df8234f9edc27d4c6094cb68fb7cc58cd48a5f 100644 (file)
--- a/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild
+++ b/dev-ml/llvm-ocaml/llvm-ocaml-5.0.9999.ebuild
@@ -19,7 +19,7 @@ EGIT_BRANCH="release_50"
 
 # Keep in sync with sys-devel/llvm
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?}
 

diff --git a/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild b/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild
index d5f507e9e101eb04d1a8299878eb9c5da6cfc78e..b377e8cd12a8064acc37e34c5171a5d923184b35 100644 (file)
--- a/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild
+++ b/dev-ml/llvm-ocaml/llvm-ocaml-9999.ebuild
@@ -18,7 +18,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git
 
 # Keep in sync with sys-devel/llvm
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?}