INSN_CONFIG_GET_CLOCK_SRC = 2004, // Get master clock source
INSN_CONFIG_SET_OTHER_SRC = 2005, // Set other source
// INSN_CONFIG_GET_OTHER_SRC = 2006, // Get other source
+ INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE, // Get size in bytes of subdevice's on-board fifos used during streaming input/output
INSN_CONFIG_SET_COUNTER_MODE = 4097,
INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */
INSN_CONFIG_8254_READ_STATUS = 4098,
/* PWM */
INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
- INSN_GET_PWM_STATUS = 5002, /* is it running? */
+ INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay at the same time*/
INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 /* gets H bridge data: duty cycle and the sign bit */
};
AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
(for channel 0, preceding counter
- channel is channel 2 on preceding
+ channel is channel 2 on preceding
counter subdevice, for first counter
subdevice, preceding counter
subdevice is the last counter