G5 support. Note: this requires a gcc hammer branch, and is therefore still

experimental.

git-svn-id: svn+ssh://svn.gentoo.org/var/svnroot/catalyst/trunk@271 d1e1f19c-881f-0410-ab34-b69fee027534

diff --git a/arch/ppc.py b/arch/ppc.py
index d22ab739b190f1d51dddbf8cfd34cc30db79f708..46c0f154e265409d9d10d746887983341fc53638 100644 (file)
--- a/arch/ppc.py
+++ b/arch/ppc.py
@@ -35,12 +35,12 @@ class arch_g4(generic_ppc):
                self.settings["CFLAGS"]="-O2 -mcpu=7400 -maltivec -mabi=altivec"
                self.settings["HOSTUSE"]=["altivec"]
 
-#class arch_g5(generic_ppc):
-#      "builder class for ppc970 32bit mode"
-#      def __init__(self,myspec):
-#              generic_ppc.__init__(self,myspec)
-#              self.settings["CFLAGS"]="-O2 -mcpu=970 -maltivec -mabi=altivec"
-#              self.settings["HOSTUSE"]=["altivec"]
+class arch_g5(generic_ppc):
+       "builder class for ppc970 32bit mode"
+       def __init__(self,myspec):
+               generic_ppc.__init__(self,myspec)
+               self.settings["CFLAGS"]="-O2 -mcpu=970 -maltivec -mabi=altivec"
+               self.settings["HOSTUSE"]=["altivec"]
 
 
 def register(foo):