sys-devel/llvm: Disable RISCV following upstream

The RISCV target is experimental and was only accidentally added to
the main target list. Since it can no longer be enabled the usual way,
remove it from the ebuilds for now.

diff --git a/sys-devel/llvm/llvm-5.0.9999.ebuild b/sys-devel/llvm/llvm-5.0.9999.ebuild
index 66aa02b23cc37414f83a182b816ad24453b8b033..1ee42880997213f11fa8959b7c2f955ef7dc0111 100644 (file)
--- a/sys-devel/llvm/llvm-5.0.9999.ebuild
+++ b/sys-devel/llvm/llvm-5.0.9999.ebuild
@@ -20,7 +20,7 @@ EGIT_BRANCH="release_50"
 
 # Keep in sync with CMakeLists.txt
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 
 # Additional licenses:

diff --git a/sys-devel/llvm/llvm-9999.ebuild b/sys-devel/llvm/llvm-9999.ebuild
index d5e7da2b501564bf70beeaca187daf731d6ea3aa..65914f3a340be4a4800042ff7660c9107e4fe10d 100644 (file)
--- a/sys-devel/llvm/llvm-9999.ebuild
+++ b/sys-devel/llvm/llvm-9999.ebuild
@@ -19,7 +19,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git
 
 # Keep in sync with CMakeLists.txt
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 
 # Additional licenses: