From b65d7ca6c492835bf9151476978c642369a7f6b6 Mon Sep 17 00:00:00 2001 From: Tim Ousley Date: Thu, 12 Apr 2001 21:36:07 +0000 Subject: [PATCH] Tim Ousley 4/12/01: consolidated some constants in ni_stc.h and added some low level GPCTR specific writes to ni_mio_common.c --- comedi/drivers/ni_mio_common.c | 49 ++++++++++---------- comedi/drivers/ni_stc.h | 84 ++++++++++++++++++++++------------ 2 files changed, 77 insertions(+), 56 deletions(-) diff --git a/comedi/drivers/ni_mio_common.c b/comedi/drivers/ni_mio_common.c index f99ed262..f83fef02 100644 --- a/comedi/drivers/ni_mio_common.c +++ b/comedi/drivers/ni_mio_common.c @@ -2124,8 +2124,8 @@ int gpct_setup(comedi_device *dev,comedi_subdevice *s) /* win_out(0x0000,Interrupt_B_Enable_Register); */ /* G(i)_Synchronized_Gate = 1 (write) */ - devpriv->gpctr_command[0] |= G0_Synchronized_Gate; - devpriv->gpctr_command[1] |= G1_Synchronized_Gate; + devpriv->gpctr_command[0] |= G_Synchronized_Gate; + devpriv->gpctr_command[1] |= G_Synchronized_Gate; win_out(devpriv->gpctr_command[0],G_Command_Register(0)); win_out(devpriv->gpctr_command[1],G_Command_Register(1)); @@ -2146,7 +2146,7 @@ int gpct_setup(comedi_device *dev,comedi_subdevice *s) "relative position sensing" mode and then arms it */ /* G(i)_Load_Source_Select = 0 (write) */ - devpriv->gpctr_mode[0] &= ~G0_Load_Source_Select; + devpriv->gpctr_mode[0] &= ~G_Load_Source_Select; win_out(devpriv->gpctr_mode[0],G_Mode_Register(0)); /* G(i)_Load_A = initial counter value (write) */ @@ -2158,7 +2158,7 @@ int gpct_setup(comedi_device *dev,comedi_subdevice *s) /* FLUSH */ /* G(i)_Load = 1 (strobe) */ - tmpreg = devpriv->gpctr_command[0] | G0_Load; + tmpreg = devpriv->gpctr_command[0] | G_Load; win_out(tmpreg,G_Command_Register(0)); /* FLUSH */ @@ -2168,62 +2168,62 @@ int gpct_setup(comedi_device *dev,comedi_subdevice *s) devpriv->gpctr_input_select[0] |= G_Source_Select(0x01); /* G(i)_Source_Polarity = 0 (count rising edges) (write) */ - devpriv->gpctr_input_select[0] &= ~G0_Source_Polarity; + devpriv->gpctr_input_select[0] &= ~G_Source_Polarity; /* G(i)_Gate_select = 0 (write) */ devpriv->gpctr_input_select[0] &= (0xffff & G_Gate_Select(0x00)); devpriv->gpctr_input_select[0] |= G_Gate_Select(0x00); /* G(i)_OR_Gate = 0 (write) */ - devpriv->gpctr_input_select[0] &= ~G0_OR_Gate; + devpriv->gpctr_input_select[0] &= ~G_OR_Gate; /* G(i)_Output_Polarity = 0 (write) */ - devpriv->gpctr_input_select[0] &= ~G0_Output_Polarity; + devpriv->gpctr_input_select[0] &= ~G_Output_Polarity; /* G(i)_Gate_Select_Load_Source = 0 (write) */ - devpriv->gpctr_input_select[0] &= ~G0_Gate_Select_Load_Source; + devpriv->gpctr_input_select[0] &= ~G_Gate_Select_Load_Source; /* G(i)_Gate_Polarity = 0 (write) */ - devpriv->gpctr_mode[0] &= ~G0_Gate_Polarity; + devpriv->gpctr_mode[0] &= ~G_Gate_Polarity; /* G(i)_Output_Mode = 1 (one clock cycle output) (write) */ devpriv->gpctr_mode[0] &= (0xffff & G_Output_Mode(0x00)); devpriv->gpctr_mode[0] |= G_Output_Mode(0x01); /* G(i)_Reload_Source_Switching = 1 (write) */ - devpriv->gpctr_mode[0] |= G0_Reload_Source_Switching; + devpriv->gpctr_mode[0] |= G_Reload_Source_Switching; /* G(i)_Loading_On_Gate = 0 (write) */ - devpriv->gpctr_mode[0] &= ~G0_Loading_On_Gate; + devpriv->gpctr_mode[0] &= ~G_Loading_On_Gate; /* G(i)_Gating_Mode = 2 (write) */ devpriv->gpctr_mode[0] &= (0xffff & G_Gating_Mode(0x00)); devpriv->gpctr_mode[0] |= G_Gating_Mode(0x02); /* G(i)_Gate_On_Both_Edges = 0 (write) */ - devpriv->gpctr_mode[0] &= ~G0_Gate_On_Both_Edges; + devpriv->gpctr_mode[0] &= ~G_Gate_On_Both_Edges; /* G(i)_Trigger_Mode_For_Edge_Gate = 3 (write) */ devpriv->gpctr_mode[0] &= (0xffff & G_Trigger_Mode_For_Edge_Gate(0x00)); devpriv->gpctr_mode[0] |= G_Trigger_Mode_For_Edge_Gate(0x03); /* G(i)_Stop_Mode = 0 */ - devpriv->gpctr_mode[0] &= (0xffff & G0_Stop_Mode(0x00)); - devpriv->gpctr_mode[0] |= G0_Stop_Mode(0x00); + devpriv->gpctr_mode[0] &= (0xffff & G_Stop_Mode(0x00)); + devpriv->gpctr_mode[0] |= G_Stop_Mode(0x00); /* G(i)_Counting_Once = 0 (write) */ - devpriv->gpctr_mode[0] &= (0xffff & G0_Counting_Once(0x00)); - devpriv->gpctr_mode[0] |= G0_Counting_Once(0x00); + devpriv->gpctr_mode[0] &= (0xffff & G_Counting_Once(0x00)); + devpriv->gpctr_mode[0] |= G_Counting_Once(0x00); /* G(i)_Up_Down = 2 (hardware controlled) (write) */ devpriv->gpctr_command[0] &= (0xffff & G_Up_Down(0x00)); devpriv->gpctr_command[0] |= G_Up_Down(0x02); /* G(i)_Bank_Switch_Enable = 0 (write) */ - devpriv->gpctr_command[0] &= ~G0_Bank_Switch_Enable; + devpriv->gpctr_command[0] &= ~G_Bank_Switch_Enable; /* G(i)_Bank_Switch_Mode = 0 (write) */ - devpriv->gpctr_command[0] &= ~G0_Bank_Switch_Mode; + devpriv->gpctr_command[0] &= ~G_Bank_Switch_Mode; /* XXX - for now we ignore interrupts */ /* G(i)_TC_Interrupt_Enable = 0 (write) */ @@ -2327,7 +2327,8 @@ static int gpct_sp(comedi_device *dev,comedi_param *it) } #endif -#ifdef GPCTR +#define GPCTR 1 +#if GPCTR /* * Low level stuff...Each STC counter has two 24 bit load registers (A&B). Just make * it easier to access them. @@ -2346,14 +2347,10 @@ void GPCTR_Load_B(comedi_device *dev, int chan, long value){ * reset its value. */ void GPCTR_Load_Using_A(comedi_device *dev, int chan, long value){ - short int masked_mode,masked_command; - //masked win_out to set Gi_Mode_Registers load source to A - masked_mode = (chan?devpriv->gpctr_mode1:devpriv->gpctr_mode0); - masked_mode &= (~G_Mode_Load_reg_bit); - + devpriv->gpctr_mode[chan] &= (~G_Load_Source_Select); + win_out( G_Mode_Register(chan),devpriv->gpctr_mode[chan]); GPCTR_Load_A(dev,chan,value); - //masked win_out to Gi_Command_Register to tell the STC to load the value - xxx + win_out( G_Command_Register(chan), devpriv->gpctr_mode[chan]|G_Load); } #endif diff --git a/comedi/drivers/ni_stc.h b/comedi/drivers/ni_stc.h index 85a1b025..42e0f886 100644 --- a/comedi/drivers/ni_stc.h +++ b/comedi/drivers/ni_stc.h @@ -398,7 +398,7 @@ #define DIO_Parallel_Input 0x0e #define G_Autoincrement_Register(a) (68+(a)) -#define G_Command_Register(a) (6+(a)) +#define G_Command_Register(a) (6+(a)) #define G_HW_Save_Register_High(a) (8+(a)*2) #define G_HW_Save_Register_Low(a) (9+(a)*2) #define G_Input_Select_Register(a) (36+(a)) @@ -415,10 +415,10 @@ #define G_Disarm_Copy _bit15 /* strobe */ #define G_Save_Trace_Copy _bit14 #define G_Arm_Copy _bit13 /* strobe */ -#define G0_Bank_Switch_Enable _bit12 -#define G1_Bank_Switch_Enable _bit12 -#define G0_Bank_Switch_Mode _bit11 -#define G1_Bank_Switch_Mode _bit11 +//#define G0_Bank_Switch_Enable _bit12 +//#define G1_Bank_Switch_Enable _bit12 +//#define G0_Bank_Switch_Mode _bit11 +//#define G1_Bank_Switch_Mode _bit11 #define G_Bank_Switch_Start _bit10 /* strobe */ #define G_Little_Big_Endian _bit9 #define G_Synchronized_Gate _bit8 @@ -426,46 +426,70 @@ #define G_Up_Down(a) (((a)&0x03)<<5) #define G_Disarm _bit4 /* strobe */ #define G_Analog_Trigger_Reset _bit3 /* strobe */ -#define G0_Load _bit2 /* strobe */ -#define G1_Load _bit2 /* strobe */ +//#define G0_Load _bit2 /* strobe */ +//#define G1_Load _bit2 /* strobe */ #define G_Save_Trace _bit1 #define G_Arm _bit0 /* strobe */ +/*channel agnostic names for the command register #defines */ +#define G_Bank_Switch_Enable _bit12 +#define G_Bank_Switch_Mode _bit11 +#define G_Load _bit2 /* strobe */ + + /* input select register */ -#define G0_Source_Polarity _bit15 -#define G1_Source_Polarity _bit15 -#define G0_Output_Polarity _bit14 -#define G1_Output_Polarity _bit14 -#define G0_OR_Gate _bit13 -#define G1_OR_Gate _bit13 -#define G0_Gate_Select_Load_Source _bit12 -#define G1_Gate_Select_Load_Source _bit12 +//#define G0_Source_Polarity _bit15 +//#define G1_Source_Polarity _bit15 +//#define G0_Output_Polarity _bit14 +//#define G1_Output_Polarity _bit14 +//#define G0_OR_Gate _bit13 +//#define G1_OR_Gate _bit13 +//#define G0_Gate_Select_Load_Source _bit12 +//#define G1_Gate_Select_Load_Source _bit12 #define G_Gate_Select(a) (((a)&0x1f)<<7) #define G_Source_Select(a) (((a)&0x1f)<<2) #define G_Write_Acknowledges_Irq _bit1 #define G_Read_Acknowledges_Irq _bit0 +/* same input select register, but with channel agnostic names */ +#define G_Source_Polarity _bit15 +#define G_Output_Polarity _bit14 +#define G_OR_Gate _bit13 +#define G_Gate_Select_Load_Source _bit12 + + /* mode register */ -#define G0_Load_Source_Select _bit7 -#define G1_Load_Source_Select _bit7 - -#define G0_Reload_Source_Switching _bit15 -#define G1_Reload_Source_Switching _bit15 -#define G0_Loading_On_Gate _bit14 -#define G1_Loading_On_Gate _bit14 -#define G0_Gate_Polarity _bit13 -#define G1_Gate_Polarity _bit13 +//#define G0_Load_Source_Select _bit7 +//#define G1_Load_Source_Select _bit7 + +//#define G0_Reload_Source_Switching _bit15 +//#define G1_Reload_Source_Switching _bit15 +//#define G0_Loading_On_Gate _bit14 +//#define G1_Loading_On_Gate _bit14 +//#define G0_Gate_Polarity _bit13 +//#define G1_Gate_Polarity _bit13 #define G_Loading_On_TC _bit12 -#define G0_Counting_Once(a) (((a)&0x03)<<10) -#define G1_Counting_Once(a) (((a)&0x03)<<10) +//#define G0_Counting_Once(a) (((a)&0x03)<<10) +//#define G1_Counting_Once(a) (((a)&0x03)<<10) #define G_Output_Mode(a) (((a)&0x03)<<8) -#define G0_Stop_Mode(a) (((a)&0x03)<<5) -#define G1_Stop_Mode(a) (((a)&0x03)<<5) +//#define G0_Stop_Mode(a) (((a)&0x03)<<5) +//#define G1_Stop_Mode(a) (((a)&0x03)<<5) #define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3) -#define G0_Gate_On_Both_Edges _bit1 -#define G1_Gate_On_Both_Edges _bit1 +//#define G0_Gate_On_Both_Edges _bit1 +//#define G1_Gate_On_Both_Edges _bit1 #define G_Gating_Mode(a) (((a)&0x03)<<0) +/* same input mode register, but with channel agnostic names */ +#define G_Load_Source_Select _bit7 +#define G_Reload_Source_Switching _bit15 +#define G_Loading_On_Gate _bit14 +#define G_Gate_Polarity _bit13 + +#define G_Counting_Once(a) (((a)&0x03)<<10) +#define G_Stop_Mode(a) (((a)&0x03)<<5) +#define G_Gate_On_Both_Edges _bit1 + + /* CLO */ /* general purpose counter timer */ #define G0_Reset _bit2 -- 2.26.2