From 257a4045f2cc23fed45d8bda7d5d68d065d13c82 Mon Sep 17 00:00:00 2001 From: Frank Mori Hess Date: Tue, 29 Mar 2005 02:41:04 +0000 Subject: [PATCH] patch from Klaas Gadeyne which fixes problem with initialization of CounterSwap bit in the ClockConfigRegister. The patch also fixes a small bug in the configuration of the TIO to serve as an encoder: There was a copy-paste error in the code for taking into account the index pulse or not. --- comedi/drivers/mite.c | 18 ++++++++++++++++-- comedi/drivers/mite.h | 3 +++ comedi/drivers/ni_660x.c | 39 +++++++++++++++++---------------------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/comedi/drivers/mite.c b/comedi/drivers/mite.c index 554dcc34..eddd1919 100644 --- a/comedi/drivers/mite.c +++ b/comedi/drivers/mite.c @@ -59,6 +59,7 @@ #define PCI_MITE_SIZE 4096 #define PCI_DAQ_SIZE 4096 +#define PCI_DAQ_SIZE_660X 8192 MODULE_LICENSE("GPL"); @@ -120,11 +121,24 @@ int mite_setup(struct mite_struct *mite) mite->daq_phys_addr=addr; offset = mite->daq_phys_addr & ~PAGE_MASK; start = mite->daq_phys_addr & PAGE_MASK; - length = PCI_DAQ_SIZE + offset; + + // In case of a 660x board, DAQ size is 8k instead of 4k (see as shown by lspci output) + if ((mite->pcidev->device == 0x1310) || (mite->pcidev->device == 0x2c60)){ + length = PCI_DAQ_SIZE_660X + offset; + printk("mite: detected NI660X board, using PCI DAQ SIZE of 8k\n"); + } + else length = PCI_DAQ_SIZE + offset; mite->daq_io_addr = ioremap(start, length) + offset; printk("DAQ:0x%08lx mapped to %p\n",mite->daq_phys_addr,mite->daq_io_addr); - writel(mite->daq_phys_addr | WENAB , mite->mite_io_addr + MITE_IODWBSR); + // The 6602 board needs different initalisation, see the + // _updated_ (nov 2002) reg. Level Manual (filename 370505b.pdf) p. 3.55 + if (mite->pcidev->device == 0x1310 ){ + printk("mite: detected NI6602, using other I/O Window Base Size register\n"); + writel((mite->daq_phys_addr & 0xffffff00L) | WENAB_6602 , mite->mite_io_addr + MITE_IODWBSR_NI6602); + writel(0 , mite->mite_io_addr + MITE_IODWCR_NI6602); + } + else writel(mite->daq_phys_addr | WENAB , mite->mite_io_addr + MITE_IODWBSR); for( i = 0; i < NUM_MITE_DMA_CHANNELS; i++ ) { writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); diff --git a/comedi/drivers/mite.h b/comedi/drivers/mite.h index d36c2b15..ff02017d 100644 --- a/comedi/drivers/mite.h +++ b/comedi/drivers/mite.h @@ -124,6 +124,8 @@ enum mite_registers { MITE_IODWBSR = 0xc0, //IO Device Window Base Size Register MITE_CSIGR = 0x460, //chip signature + MITE_IODWBSR_NI6602 = 0xc4, // IODWBSR for 6602 boards + MITE_IODWCR_NI6602 = 0xf4 }; static inline int MITE_CHOR(int channel) // channel operation { @@ -197,6 +199,7 @@ static inline int MITE_FCR(int channel) // fifo count enum MITE_IODWBSR_bits { WENAB = 0x80, // window enable + WENAB_6602 = 0x8c // window enable for 6602 boards }; enum MITE_MCR_bits { diff --git a/comedi/drivers/ni_660x.c b/comedi/drivers/ni_660x.c index a4249b4b..9a69b001 100644 --- a/comedi/drivers/ni_660x.c +++ b/comedi/drivers/ni_660x.c @@ -777,6 +777,15 @@ static int ni_660x_attach(comedi_device *dev,comedi_devconfig *it) s->insn_config = ni_660x_dio_insn_config; s->io_bits = 0; /* all bits default to input */ + // Enabling the second chip: This "hardcodes" the counter + // outputs 5 to 8 to use the second TIO in case of a NI6602 + // board. + if (thisboard->name == "PCI-6602" ) + { + printk("NI6602: Setting Counterswap on second TIO\n"); + enable_chip(dev); + } + printk("attached\n"); /* What does this "return value" mean? Is this fixed by API?? @@ -812,7 +821,6 @@ static int GPCT_check_chipset_from_channel(comedi_device *dev, int channel) }else if ( (channel >= CTRS_PER_CHIP) && (channel < thisboard->n_ctrs) ) { chipset = 1; - // DPRINTK("NI_660x: Moving to chipset 1\n"); }else { DPRINTK("NI_660x: Channel specification not between limits\n"); @@ -844,8 +852,6 @@ ni_660x_GPCT_rinsn(comedi_device *dev, comedi_subdevice *s, /* ============================================================ */ /* 1 subdevice with 8 channels, differentation based on channel */ - DPRINTK("NI_660x: INSN_READ on channel %d\n", subdev_channel); - // Check what Application of Counter this channel is configured for switch(ni_660x_gpct_config[subdev_channel].App) { @@ -888,24 +894,16 @@ ni_660x_GPCT_rinsn(comedi_device *dev, comedi_subdevice *s, } static void -enable_chip(comedi_device *dev, int chipset) +enable_chip(comedi_device *dev) { /* See P. 3.5 of the Register-Level Programming manual. This bit has to be set, otherwise, you can't use the second chip. */ - if ( chipset == 1) - { - writel(CounterSwap,dev->iobase + GPCT_OFFSET[chipset] - + registerData[ClockConfigRegister].offset); - }else - { - writel(0x0,dev->iobase + GPCT_OFFSET[chipset] - + registerData[ClockConfigRegister].offset); - } + writel(CounterSwap,dev->iobase + GPCT_OFFSET[1] + + registerData[ClockConfigRegister].offset); + return 0; } - - static int ni_660x_GPCT_insn_config(comedi_device *dev, comedi_subdevice *s, comedi_insn *insn, lsampl_t *data) @@ -915,7 +913,6 @@ ni_660x_GPCT_insn_config(comedi_device *dev, comedi_subdevice *s, int counter_channel = GPCT_check_counter_channel_from_subdev_channel(subdev_channel); DPRINTK("NI_660x: INSN_CONFIG: Configuring Channel %d\n", subdev_channel); - enable_chip(dev, chipset); // Check what type of Counter the user requested, data[0] contains // the Application type @@ -979,13 +976,13 @@ ni_660x_GPCT_insn_config(comedi_device *dev, comedi_subdevice *s, // Load (latch) this value into the counter writew(Load,dev->iobase + GPCT_OFFSET[chipset] + registerData[GxCommandRegister(counter_channel)].offset); - /* - Set Counting Mode into GPCT_X1 / 2 / 4 (as set by user - - Take into account Z pulse (index pulse) only when both - channel A and B are high (arbitrary choice) + /* - Set Counting Mode into GPCT_X1 / 2 / 4 (as set by user) + - When to take into account index pulse (as set by user) + - Take into account index pulse (as set by user) */ writew(((ni_660x_gpct_config[subdev_channel]).data[0] | (ni_660x_gpct_config[subdev_channel]).data[1] | - (ni_660x_gpct_config[subdev_channel]).data[1] ), + (ni_660x_gpct_config[subdev_channel]).data[2] ), dev->iobase + GPCT_OFFSET[chipset] + registerData[GxCountingModeRegister(counter_channel)].offset); // Put counter in input mode @@ -1122,7 +1119,6 @@ ni_660x_GPCT_insn_config(comedi_device *dev, comedi_subdevice *s, break; case GPCT_SIMPLE_EVENT: DPRINTK("NI_660x: INSN_CONFIG: Config Simple Event Counter\n"); - //printk("NI_660x: INSN_CONFIG: Config Simple Event Counter\n"); ni_660x_gpct_config[subdev_channel].App = CountingAndTimeMeasurement; // Reset the counter @@ -1257,7 +1253,6 @@ static int ni_660x_GPCT_inttrig(comedi_device *dev, int counter_channel = GPCT_check_counter_channel_from_subdev_channel(subdev_channel); DPRINTK("Triggering channel %d\n", subdev_channel); - enable_chip(dev, chipset); // Reset the counter writew(GxReset(counter_channel),dev->iobase + GPCT_OFFSET[chipset] -- 2.26.2