From: Andrew Gaffney Date: Sat, 17 Nov 2007 02:29:51 +0000 (+0000) Subject: apply patch for mips n32 support from Stuart Longland in bug... X-Git-Tag: CATALYST_2_0_6_916~235 X-Git-Url: http://git.tremily.us/?a=commitdiff_plain;h=ddb192a134a5e59f19be2ed3fdc6578a9cb25b04;p=catalyst.git apply patch for mips n32 support from Stuart Longland in bug #197917 git-svn-id: svn+ssh://svn.gentoo.org/var/svnroot/catalyst/trunk@1259 d1e1f19c-881f-0410-ab34-b69fee027534 --- diff --git a/ChangeLog b/ChangeLog index 829e0bc7..f6813658 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,6 +1,10 @@ # Copyright 2002-2007 Gentoo Foundation; Distributed under the GPL v2 # $Id: $ + 17 Nov 2007; Andrew Gaffney arch/mips.py: + apply patch for mips n32 support from Stuart Longland + in bug #197917 + 17 Nov 2007; Andrew Gaffney targets/livecd-stage2/livecd-stage2-controller.sh, targets/support/livecdfs-update.sh: diff --git a/arch/mips.py b/arch/mips.py index ba48a9f4..d2bb80bf 100644 --- a/arch/mips.py +++ b/arch/mips.py @@ -65,12 +65,26 @@ class arch_mipsel3(generic_mipsel): generic_mipsel.__init__(self,myspec) self.settings["CFLAGS"]="-O2 -mips3 -mabi=32 -pipe" +class arch_mipsel3n32(generic_mipsel): + "Builder class for all MIPS III [Little-endian N32]" + def __init__(self,myspec): + generic_mipsel.__init__(self,myspec) + self.settings["CFLAGS"]="-O2 -mips3 -mabi=n32 -pipe" + self.settings["CHOST"]="mips64el-unknown-linux-gnu" + class arch_mipsel4(generic_mipsel): "Builder class for all MIPS IV [Little-endian]" def __init__(self,myspec): generic_mipsel.__init__(self,myspec) self.settings["CFLAGS"]="-O2 -mips4 -mabi=32 -pipe" +class arch_mipsel4n32(generic_mipsel): + "Builder class for all MIPS IV [Little-endian N32]" + def __init__(self,myspec): + generic_mipsel.__init__(self,myspec) + self.settings["CFLAGS"]="-O2 -mips4 -mabi=n32 -pipe" + self.settings["CHOST"]="mips64el-unknown-linux-gnu" + def register(): @@ -86,9 +100,12 @@ def register(): "mipsel1" :arch_mipsel1, "mipsel2" :arch_mipsel2, "mipsel3" :arch_mipsel3, + "mipsel3n32" :arch_mipsel3n32, "mipsel4" :arch_mipsel4, + "mipsel4n32" :arch_mipsel4n32, "sgir4k" :arch_mips3, "sgir5k" :arch_mips4, "sgir10kplus" :arch_mips4, + "loongson" :arch_mipsel3, "cobalt" :arch_mipsel4 }, ("mips","mips64"))