From: Ian Abbott <abbotti@mev.co.uk>
Date: Mon, 28 May 2012 09:40:42 +0000 (+0100)
Subject: amplc_dio200: Enable enhanced features of PCIe boards.
X-Git-Url: http://git.tremily.us/?a=commitdiff_plain;h=9d8df7bc69a653f9baff2c04ef2aa4e5db7d0b3d;p=comedi.git

amplc_dio200: Enable enhanced features of PCIe boards.

The new PCIe boards have some enhanced features compared to the old PCI
boards, although none of these features are supported by amplc_dio200
yet.

Enable the enhanced features in hardware, and use dio200_layouts[] to
indicate which boards support the enhanced features.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---

diff --git a/comedi/drivers/amplc_dio200.c b/comedi/drivers/amplc_dio200.c
index ae06b6ff..5e8a394f 100644
--- a/comedi/drivers/amplc_dio200.c
+++ b/comedi/drivers/amplc_dio200.c
@@ -270,6 +270,9 @@ order they appear in the channel list.
 #define DIO200_YGAT_SCE		0x1c	/* Group Y gate selection register */
 #define DIO200_ZGAT_SCE		0x1d	/* Group Z gate selection register */
 #define DIO200_INT_SCE		0x1e	/* Interrupt enable/status register */
+/* Extra registers for new PCIe boards */
+#define DIO200_ENHANCE		0x20	/* 1 to enable enhanced features */
+#define DIO200_VERSION		0x24	/* Hardware version */
 
 /*
  * Macros for constructing value for DIO_200_?CLK_SCE and
@@ -471,6 +474,7 @@ typedef struct dio200_layout_struct {
 	unsigned char sdinfo[DIO200_MAX_SUBDEVS];	/* depends on sdtype */
 	char has_int_sce;	/* has interrupt enable/status register */
 	char has_clk_gat_sce;	/* has clock/gate selection registers */
+	char has_enhancements;	/* has enhanced features */
 } dio200_layout;
 
 static const dio200_layout dio200_layouts[] = {
@@ -483,6 +487,7 @@ static const dio200_layout dio200_layouts[] = {
 				0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:0,
 		},
 	[pc214_layout] = {
 	      n_subdevs:4,
@@ -491,6 +496,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x08, 0x10, 0x01},
 	      has_int_sce:0,
 	      has_clk_gat_sce:0,
+	      has_enhancements:0,
 		},
 	[pc215_layout] = {
 	      n_subdevs:5,
@@ -500,6 +506,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x08, 0x10, 0x14, 0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:0,
 		},
 	[pc218_layout] = {
 	      n_subdevs:7,
@@ -511,6 +518,7 @@ static const dio200_layout dio200_layouts[] = {
 				0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:0,
 		},
 	[pc272_layout] = {
 	      n_subdevs:4,
@@ -519,6 +527,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x08, 0x10, 0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:0,
+	      has_enhancements:0,
 		},
 #ifdef CONFIG_COMEDI_PCI
 	[pcie215_layout] = {
@@ -528,6 +537,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x00, 0x08, 0x00, 0x10, 0x14, 0x00, 0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:1,
 		},
 	[pcie236_layout] = {
 	      n_subdevs:8,
@@ -536,6 +546,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x00, 0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:1,
 		},
 	[pcie296_layout] = {
 	      n_subdevs:8,
@@ -544,6 +555,7 @@ static const dio200_layout dio200_layouts[] = {
 	      sdinfo:	{0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x00, 0x3F},
 	      has_int_sce:1,
 	      has_clk_gat_sce:1,
+	      has_enhancements:1,
 		},
 #endif
 };
@@ -1704,6 +1716,10 @@ dio200_pcie_board_setup(comedi_device * dev)
 	}
 	writel(0x80, brbase + 0x50);
 	iounmap(brbase);
+	/*
+	 * Enable "enhanced" features of board.
+	 */
+	dio200_write8(dev, DIO200_ENHANCE, 1);
 	return 0;
 }
 #endif