From: Ian Abbott Date: Mon, 13 Nov 2006 14:06:57 +0000 (+0000) Subject: Fixed some C++-isms: mixed declarations and code. X-Git-Tag: r0_7_74~157 X-Git-Url: http://git.tremily.us/?a=commitdiff_plain;h=38457118a8dbd13f02140ab21074519766535399;p=comedi.git Fixed some C++-isms: mixed declarations and code. --- diff --git a/comedi/comedi_fops.c b/comedi/comedi_fops.c index c99b204e..0bc54ee1 100644 --- a/comedi/comedi_fops.c +++ b/comedi/comedi_fops.c @@ -1758,10 +1758,11 @@ static int __init comedi_init(void) for(i=0;idevt; comedi_devices[i].minor = MINOR(class_dev->devt); diff --git a/comedi/drivers.c b/comedi/drivers.c index 05a286a8..7ebc8196 100644 --- a/comedi/drivers.c +++ b/comedi/drivers.c @@ -316,9 +316,7 @@ void *comedi_recognize(comedi_driver *driv, const char *name) { if(strcmp(*name_ptr, name) == 0) return name_ptr; - unsigned long address = (unsigned long)name_ptr; - address += driv->offset; - name_ptr = (const char**)address; + name_ptr = (const char **)((char *)name_ptr + driv->offset); } return NULL; @@ -335,9 +333,7 @@ void comedi_report_boards(comedi_driver *driv) for(i = 0; i < driv->num_names; i++) { printk(" %s\n", *name_ptr); - unsigned long address = (unsigned long)name_ptr; - address += driv->offset; - name_ptr = (const char**)address; + name_ptr = (const char **)((char *)name_ptr + driv->offset); } if(driv->num_names == 0) diff --git a/comedi/drivers/ni_65xx.c b/comedi/drivers/ni_65xx.c index a551a6df..e45c40c9 100644 --- a/comedi/drivers/ni_65xx.c +++ b/comedi/drivers/ni_65xx.c @@ -395,19 +395,23 @@ static int ni_65xx_dio_insn_config(comedi_device *dev,comedi_subdevice *s, static int ni_65xx_dio_insn_bits(comedi_device *dev,comedi_subdevice *s, comedi_insn *insn,lsampl_t *data) { - if(insn->n != 2) return -EINVAL; - const unsigned base_bitfield_channel = CR_CHAN(insn->chanspec); + unsigned base_bitfield_channel; const unsigned max_ports_per_bitfield = 5; unsigned read_bits = 0; unsigned j; + if(insn->n != 2) return -EINVAL; + base_bitfield_channel = CR_CHAN(insn->chanspec); for(j = 0; j < max_ports_per_bitfield; ++j) { const unsigned port = sprivate(s)->base_port + ni_65xx_port_by_channel(base_bitfield_channel) + j; + unsigned base_port_channel; + unsigned port_mask, port_data, port_read_bits; + int bitshift; if(port >= ni_65xx_total_num_ports(board(dev))) break; - const unsigned base_port_channel = port * ni_65xx_channels_per_port; - unsigned port_mask = data[0]; - unsigned port_data = data[1]; - int bitshift = base_port_channel - base_bitfield_channel; + base_port_channel = port * ni_65xx_channels_per_port; + port_mask = data[0]; + port_data = data[1]; + bitshift = base_port_channel - base_bitfield_channel; if(bitshift >= 32 || bitshift <= -32) break; if(bitshift > 0) { @@ -422,14 +426,15 @@ static int ni_65xx_dio_insn_bits(comedi_device *dev,comedi_subdevice *s, port_data &= 0xff; if(port_mask) { + unsigned bits; private(dev)->output_bits[port] &= ~port_mask; private(dev)->output_bits[port] |= port_data & port_mask; - unsigned bits = private(dev)->output_bits[port]; + bits = private(dev)->output_bits[port]; if(board(dev)->invert_outputs) bits = ~bits; writeb(bits, private(dev)->mite->daq_io_addr + Port_Data(port)); // rt_printk("wrote 0x%x to port %i\n", bits, port); } - unsigned port_read_bits = readb(private(dev)->mite->daq_io_addr + Port_Data(port)); + port_read_bits = readb(private(dev)->mite->daq_io_addr + Port_Data(port)); // rt_printk("read 0x%x from port %i\n", port_read_bits, port); if(bitshift > 0) { @@ -580,6 +585,7 @@ static int ni_65xx_intr_insn_config(comedi_device *dev, comedi_subdevice *s, static int ni_65xx_attach(comedi_device *dev,comedi_devconfig *it) { comedi_subdevice *s; + unsigned i; int ret; printk("comedi%d: ni_65xx:",dev->minor); @@ -654,7 +660,6 @@ static int ni_65xx_attach(comedi_device *dev,comedi_devconfig *it) s->private = ni_65xx_alloc_subdevice_private(); if(s->private == NULL) return -ENOMEM; sprivate(s)->base_port = 0; - unsigned i; for(i = 0; i < board(dev)->num_dio_ports; ++i) { // configure all ports for input @@ -678,7 +683,6 @@ static int ni_65xx_attach(comedi_device *dev,comedi_devconfig *it) s->insn_bits = ni_65xx_intr_insn_bits; s->insn_config = ni_65xx_intr_insn_config; - unsigned i; for(i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) { writeb(0x00, private(dev)->mite->daq_io_addr + Filter_Enable(i)); diff --git a/comedi/drivers/ni_mio_common.c b/comedi/drivers/ni_mio_common.c index a426e9e2..2ad7abbe 100644 --- a/comedi/drivers/ni_mio_common.c +++ b/comedi/drivers/ni_mio_common.c @@ -1458,11 +1458,12 @@ static void ni_m_series_load_channelgain_list(comedi_device *dev,unsigned int n_ // offset = 1 << (boardtype.adbits - 1); if((list[0] & CR_ALT_SOURCE)) { + unsigned bypass_bits; chan = CR_CHAN(list[0]); range = CR_RANGE(list[0]); range_code = ni_gainlkup[boardtype.gainlkup][range]; dither = ((list[0] & CR_ALT_FILTER) != 0); - unsigned bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; + bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit; bypass_bits |= chan; bypass_bits |= (devpriv->ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask | MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask | @@ -2331,9 +2332,10 @@ static int ni_m_series_ao_config_chanlist(comedi_device *dev, comedi_subdevice * } for(i=0;irange_table->range + range; + krange = s->range_table->range + range; invert = 0; conf = 0; switch(krange->max - krange->min) @@ -2625,8 +2627,9 @@ static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s) AO_UPDATE_Output_Select(1), AO_Output_Control_Register); }else{ + unsigned bits; devpriv->ao_mode1&=~AO_Multiple_Channels; - unsigned bits = AO_UPDATE_Output_Select(1); + bits = AO_UPDATE_Output_Select(1); if(boardtype.reg_type == ni_reg_m_series) bits |= AO_Number_Of_Channels(0); else @@ -3300,9 +3303,9 @@ static int ni_E_init(comedi_device *dev,comedi_devconfig *it) s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; if(boardtype.reg_type == ni_reg_m_series) { + unsigned i; s->n_chan = 16; ni_writew(s->state, M_Offset_PFI_DO); - unsigned i; for(i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { ni_writew(devpriv->pfi_output_select_reg[i], M_Offset_PFI_Output_Select(i + 1)); @@ -4362,9 +4365,11 @@ static int ni_gpct_cancel(comedi_device *dev, comedi_subdevice *s) static int ni_m_series_set_pfi_routing(comedi_device *dev, unsigned chan, unsigned source) { + unsigned pfi_reg_index; + unsigned array_offset; if((source & 0x1f) != source) return -EINVAL; - const unsigned pfi_reg_index = 1 + chan / 3; - const unsigned array_offset = pfi_reg_index - 1; + pfi_reg_index = 1 + chan / 3; + array_offset = pfi_reg_index - 1; devpriv->pfi_output_select_reg[array_offset] &= ~MSeries_PFI_Output_Select_Mask(chan); devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source); ni_writew(devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index)); @@ -4555,6 +4560,7 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to * 20 MHz for most timing clocks */ static const unsigned target_picosec = 12500; + static const unsigned fudge_factor_80_to_20Mhz = 4; int best_period_picosec = 0; for(div = 1; div <= max_div; ++div) { @@ -4576,7 +4582,6 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, } *freq_divider = best_div; *freq_multiplier = best_mult; - static const unsigned fudge_factor_80_to_20Mhz = 4; *actual_period_ns = (best_period_picosec * fudge_factor_80_to_20Mhz + (pico_per_nano / 2)) / pico_per_nano; return 0; } @@ -4589,10 +4594,16 @@ static inline unsigned num_configurable_rtsi_channels(comedi_device *dev) static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, unsigned period_ns) { - if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100; - // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that static const unsigned min_period_ns = 50; static const unsigned max_period_ns = 1000; + static const unsigned timeout = 1000; + unsigned pll_control_bits; + unsigned freq_divider; + unsigned freq_multiplier; + unsigned i; + int retval; + if(source == NI_MIO_PLL_PXI10_CLOCK) period_ns = 100; + // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that if(period_ns < min_period_ns || period_ns > max_period_ns) { rt_printk("%s: you must specify an input clock frequency between %i and %i nanosec " @@ -4601,12 +4612,9 @@ static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, } devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, RTSI_Trig_Direction_Register); - unsigned pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; + pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; devpriv->clock_and_fout2 |= MSeries_Timebase1_Select_Bit; devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask; - int retval; - unsigned freq_divider; - unsigned freq_multiplier; switch(source) { case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: @@ -4647,8 +4655,6 @@ static int ni_mseries_set_pll_master_clock(comedi_device *dev, unsigned source, // rt_printk("clock_ns=%d\n", devpriv->clock_ns); ni_writew(pll_control_bits, M_Offset_PLL_Control); devpriv->clock_source = source; - unsigned i; - static const unsigned timeout = 1000; /* it seems to typically take a few hundred microseconds for PLL to lock */ for(i = 0; i < timeout; ++i) {