From: David Schleef Date: Fri, 8 Mar 2002 22:06:38 +0000 (+0000) Subject: Change direct writing of shadow registers to win_in() and win_out(), X-Git-Tag: r0_7_64~76 X-Git-Url: http://git.tremily.us/?a=commitdiff_plain;h=3320e918bb8d2cb582f9f767d1ec44532620b640;p=comedi.git Change direct writing of shadow registers to win_in() and win_out(), and fix win_in() and win_out() to write directly to shadow registers if possible. Added 611x register definitions to ni_stc.h. Change caldacs on 611x boards to ad8804_debug. --- diff --git a/comedi/drivers/ni_atmio.c b/comedi/drivers/ni_atmio.c index 2b256a39..0da2920e 100644 --- a/comedi/drivers/ni_atmio.c +++ b/comedi/drivers/ni_atmio.c @@ -250,8 +250,40 @@ static int ni_irqpin[]={-1,-1,-1,0,1,2,-1,3,-1,-1,4,5,6,-1,-1,7}; #define ni_readw(a) (inw((a)+dev->iobase)) #define ni_writeb(a,b) (outb((a),(b)+dev->iobase)) #define ni_readb(a) (inb((a)+dev->iobase)) -#define ni_writeb_p(a,b) (outb_p((a),(b)+dev->iobase)) -#define ni_readb_p(a) (inb_p((a)+dev->iobase)) + +/* How we access windowed registers */ + +/* We automatically take advantage of STC registers that can be + * read/written directly in the I/O space of the board. The + * AT-MIO devices map the low 8 STC registers to iobase+addr*2. */ + +#define win_out(data,addr) do{ \ + if((addr)<8){ \ + ni_writew((data),(addr)*2); \ + }else{ \ + ni_writew((addr),Window_Address); \ + ni_writew((data),Window_Data); \ + } \ +}while(0) + +#define win_out2(data,addr) do{ \ + win_out((data)>>16, (addr)); \ + win_out((data)&0xffff, (addr)+1); \ +}while(0) + +#define win_in(addr) ( \ + ((addr)<8) \ + ? (ni_readw(((addr))*2)) \ + : (ni_writew((addr),Window_Address),ni_readw(Window_Data))) + +#define win_save() (ni_readw(Window_Address)) +#define win_restore(a) (ni_writew((a),Window_Address)) + +#define ao_win_out(a,b) do{ \ + ni_writew((b),AO_Window_Address_671x); \ + ni_writew((a),AO_Window_Data_671x); \ +}while(0) + #ifdef HAVE_ISAPNP diff --git a/comedi/drivers/ni_mio_common.c b/comedi/drivers/ni_mio_common.c index 9409cd2f..d18d2b62 100644 --- a/comedi/drivers/ni_mio_common.c +++ b/comedi/drivers/ni_mio_common.c @@ -62,26 +62,6 @@ #define MDPRINTK(format,args...) #endif -/* How we access windowed registers */ - -#define win_out(a,b) do{ \ - ni_writew((b),Window_Address); \ - ni_writew((a),Window_Data); \ - }while(0) -#define win_out2(a,b) do{ \ - ni_writew((b),Window_Address); \ - ni_writew(((a)>>16)&0xffff,Window_Data); \ - ni_writew((b)+1,Window_Address); \ - ni_writew((a)&0xffff,Window_Data); \ - }while(0) -#define win_in(b) (ni_writew((b),Window_Address),ni_readw(Window_Data)) -#define win_save() (ni_readw(Window_Address)) -#define win_restore(a) (ni_writew((a),Window_Address)) -#define ao_win_out(a,b) do{ \ - ni_writew((b),AO_Window_Address_671x); \ - ni_writew((a),AO_Window_Data_671x); \ - }while(0) - /* A timeout count */ #define NI_TIMEOUT 1000 @@ -331,8 +311,8 @@ static void ni_E_interrupt(int irq,void *d,struct pt_regs * regs) */ wsave=win_save(); - a_status=ni_readw(AI_Status_1); - b_status=ni_readw(AO_Status_1); + a_status=win_in(AI_Status_1_Register); + b_status=win_in(AO_Status_1_Register); #ifdef PCIDMA m_status=readl(mite->mite_io_addr+MITE_CHSR+CHAN_OFFSET(mite->chan)); #endif @@ -511,7 +491,7 @@ static void handle_a_interrupt(comedi_device *dev,unsigned short status) } #endif // !PCIDMA - if(ack) ni_writew(ack,Interrupt_A_Ack); + if(ack) win_out(ack,Interrupt_A_Ack_Register); comedi_event(dev,s,s->async->events); } @@ -523,17 +503,17 @@ static void handle_b_interrupt(comedi_device *dev,unsigned short b_status) if(b_status==0xffff)return; if(b_status&AO_Overrun_St){ - rt_printk("ni-E: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,ni_readw(AO_Status_2)); + rt_printk("ni-E: AO FIFO underrun status=0x%04x status2=0x%04x\n",b_status,win_in(AO_Status_2_Register)); } if(b_status&AO_BC_TC_St){ - rt_printk("ni-E: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,ni_readw(AO_Status_2)); + rt_printk("ni-E: AO BC_TC status=0x%04x status2=0x%04x\n",b_status,win_in(AO_Status_2_Register)); } if(b_status&AO_FIFO_Request_St) ni_ao_fifo_half_empty(dev,s); - b_status=ni_readw(AO_Status_1); + b_status=win_in(AO_Status_1_Register); if(b_status&Interrupt_B_St){ if(b_status&AO_FIFO_Request_St){ rt_printk("ni_mio_common: AO buffer underrun\n"); @@ -667,7 +647,7 @@ static void ni_handle_fifo_dregs(comedi_device *dev) while(1){ n=(s->async->data_len-s->async->buf_int_ptr)/sizeof(sampl_t); for(i=0;iasync->cur_chan=j; return; } @@ -854,7 +834,7 @@ static int ni_ai_insn_read(comedi_device *dev,comedi_subdevice *s,comedi_insn *i for(n=0;nn;n++){ win_out(1,AI_Command_1_Register); for(i=0;iao_cmd2|AO_START1_Pulse,AO_Command_2); + win_out(devpriv->ao_cmd2|AO_START1_Pulse,AO_Command_2_Register); s->async->inttrig=NULL; @@ -1766,7 +1746,7 @@ static int ni_ao_cmd(comedi_device *dev,comedi_subdevice *s) } devpriv->ao_cmd2&=~AO_BC_Gate_Enable; - ni_writew(devpriv->ao_cmd2,AO_Command_2); + win_out(devpriv->ao_cmd2,AO_Command_2_Register); devpriv->ao_mode1&=~(AO_UI_Source_Select(0x1f)|AO_UI_Source_Polarity); win_out(devpriv->ao_mode1,AO_Mode_1_Register); devpriv->ao_mode2&=~(AO_UI_Reload_Mode(3)|AO_UI_Initial_Load_Source); @@ -1932,7 +1912,7 @@ static int ni_dio_insn_bits(comedi_device *dev,comedi_subdevice *s, devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); win_out(devpriv->dio_output,DIO_Output_Register); } - data[1] = ni_readw(DIO_Parallel_Input); + data[1] = win_in(DIO_Parallel_Input_Register); return 2; } @@ -2071,7 +2051,7 @@ static int ni_E_init(comedi_device *dev,comedi_devconfig *it) win_out(AO_Disarm,AO_Command_1_Register); win_out(0,Interrupt_B_Enable_Register); win_out(0x0010,AO_Personal_Register); - ni_writew(0x3f98,Interrupt_B_Ack); + win_out(0x3f98,Interrupt_B_Ack_Register); win_out(0x1430,AO_Personal_Register); win_out(0,AO_Output_Control_Register); win_out(0,AO_Start_Select_Register); @@ -2140,18 +2120,18 @@ static int ni_read_eeprom(comedi_device *dev,int addr) int bitstring; bitstring=0x0300|((addr&0x100)<<3)|(addr&0xff); - ni_writeb_p(0x04,Serial_Command); + ni_writeb(0x04,Serial_Command); for(bit=0x8000;bit;bit>>=1){ - ni_writeb_p(0x04|((bit&bitstring)?0x02:0),Serial_Command); - ni_writeb_p(0x05|((bit&bitstring)?0x02:0),Serial_Command); + ni_writeb(0x04|((bit&bitstring)?0x02:0),Serial_Command); + ni_writeb(0x05|((bit&bitstring)?0x02:0),Serial_Command); } bitstring=0; for(bit=0x80;bit;bit>>=1){ - ni_writeb_p(0x04,Serial_Command); - ni_writeb_p(0x05,Serial_Command); - bitstring|=((ni_readb_p(XXX_Status)&0x01)?bit:0); + ni_writeb(0x04,Serial_Command); + ni_writeb(0x05,Serial_Command); + bitstring|=((ni_readb(XXX_Status)&0x01)?bit:0); } - ni_writeb_p(0x00,Serial_Command); + ni_writeb(0x00,Serial_Command); return bitstring; } diff --git a/comedi/drivers/ni_mio_cs.c b/comedi/drivers/ni_mio_cs.c index 865f1f77..7ebd2fd9 100644 --- a/comedi/drivers/ni_mio_cs.c +++ b/comedi/drivers/ni_mio_cs.c @@ -162,8 +162,39 @@ static ni_board ni_boards[]={ #define ni_readw(a) (inw((a)+dev->iobase)) #define ni_writeb(a,b) (outb((a),(b)+dev->iobase)) #define ni_readb(a) (inb((a)+dev->iobase)) -#define ni_writeb_p(a,b) (outb_p((a),(b)+dev->iobase)) -#define ni_readb_p(a) (inb_p((a)+dev->iobase)) + +/* How we access windowed registers */ + +/* We automatically take advantage of STC registers that can be + * read/written directly in the I/O space of the board. The + * DAQCard devices map the low 8 STC registers to iobase+addr*2. */ + +#define win_out(data,addr) do{ \ + if((addr)<8){ \ + ni_writew((data),(addr)*2); \ + }else{ \ + ni_writew((addr),Window_Address); \ + ni_writew((data),Window_Data); \ + } \ +}while(0) + +#define win_out2(data,addr) do{ \ + win_out((data)>>16, (addr)); \ + win_out((data)&0xffff, (addr)+1); \ +}while(0) + +#define win_in(addr) ( \ + ((addr)<8) \ + ? (ni_readw(((addr))*2)) \ + : (ni_writew((addr),Window_Address),ni_readw(Window_Data))) + +#define win_save() (ni_readw(Window_Address)) +#define win_restore(a) (ni_writew((a),Window_Address)) + +#define ao_win_out(a,b) do{ \ + ni_writew((b),AO_Window_Address_671x); \ + ni_writew((a),AO_Window_Data_671x); \ +}while(0) typedef struct{ diff --git a/comedi/drivers/ni_pcimio.c b/comedi/drivers/ni_pcimio.c index d4f98196..da74d8a0 100644 --- a/comedi/drivers/ni_pcimio.c +++ b/comedi/drivers/ni_pcimio.c @@ -429,7 +429,8 @@ static ni_board ni_boards[]={ ao_671x: 1, ao_unipolar: 0, ao_fifo_depth: 2048, - caldac: {mb88341,mb88341,ad8522},/* XXX */ + reg_611x: 1, + caldac: {ad8804_debug,ad8804_debug,ad8804_debug},/* XXX */ }, { device_id: 0x14f0, name: "pci-6111e", @@ -444,7 +445,8 @@ static ni_board ni_boards[]={ ao_671x: 1, ao_unipolar: 0, ao_fifo_depth: 2048, - caldac: {mb88341,mb88341,ad8522},/* XXX */ + reg_611x: 1, + caldac: {ad8804_debug,ad8804_debug,ad8804_debug},/* XXX */ }, { device_id: 0x1880, name: "pci-6711", @@ -582,8 +584,42 @@ COMEDI_INITCLEANUP(driver_pcimio); #define ni_readw(a) (readw(dev->iobase+(a))) #define ni_writeb(a,b) (writeb((a),dev->iobase+(b))) #define ni_readb(a) (readb(dev->iobase+(a))) -#define ni_writeb_p(a,b) (ni_writeb(a,b),ni_writeb(a,b)) -#define ni_readb_p(a) (ni_readb(a),ni_readb(a)) + +/* How we access STC registers */ + +/* We automatically take advantage of STC registers that can be + * read/written directly in the I/O space of the board. Most + * PCIMIO devices map the low 8 STC registers to iobase+addr*2. + * The 611x devices map the write registers to iobase+addr*2, and + * the read registers to iobase+(addr-1)*2. */ + +#define win_out(data,addr) do{ \ + if((addr)<8){ \ + ni_writew((data),(addr)*2); \ + }else{ \ + ni_writew((addr),Window_Address); \ + ni_writew((data),Window_Data); \ + } \ +}while(0) + +#define win_out2(data,addr) do{ \ + win_out((data)>>16, (addr)); \ + win_out((data)&0xffff, (addr)+1); \ +}while(0) + +#define win_in(addr) ( \ + ((addr)<7) \ + ? (ni_readw(((addr) - boardtype.reg_611x)*2)) \ + : (ni_writew((addr),Window_Address),ni_readw(Window_Data))) + +#define win_save() (ni_readw(Window_Address)) +#define win_restore(a) (ni_writew((a),Window_Address)) + +#define ao_win_out(a,b) do{ \ + ni_writew((b),AO_Window_Address_671x); \ + ni_writew((a),AO_Window_Data_671x); \ +}while(0) + #define interrupt_pin(a) 0 diff --git a/comedi/drivers/ni_stc.h b/comedi/drivers/ni_stc.h index 347b06d6..de4d41c0 100644 --- a/comedi/drivers/ni_stc.h +++ b/comedi/drivers/ni_stc.h @@ -132,7 +132,9 @@ #define AO_UPDATE2_Pulse _bit1 #define AO_START1_Pulse _bit0 -#define DIO_Input_Register 7 +#define AO_Status_2_Register 6 + +#define DIO_Parallel_Input_Register 7 #define DIO_SDIN _bit4 #define AI_Command_1_Register 8 @@ -386,23 +388,6 @@ #define AI_External_Gate_Polarity _bit5 #define AI_External_Gate_Select(a) (a) - -/* 16 bit registers shadowed from DAQ-STC */ -#define Window_Address 0x00 -#define Window_Data 0x02 -#define Interrupt_A_Ack 0x04 -#define AI_Status_1 0x04 -#define Interrupt_B_Ack 0x06 -#define AO_Status_1 0x06 -#define AI_Command_2 0x08 -#define G_Status 0x08 -#define AO_Command_2 0x0a -#define AI_Status_2 0x0a -#define G0_Command 0x0c -#define AO_Status_2 0x0c -#define G1_Command 0x0e -#define DIO_Parallel_Input 0x0e - #define G_Autoincrement_Register(a) (68+(a)) #define G_Command_Register(a) (6+(a)) #define G_HW_Save_Register(a) (8+(a)*2) @@ -520,6 +505,24 @@ /* Additional windowed registers unique to E series */ +/* 16 bit registers shadowed from DAQ-STC */ +#define Window_Address 0x00 +#define Window_Data 0x02 +#if 0 +#define Interrupt_A_Ack 0x04 +#define AI_Status_1 0x04 +#define Interrupt_B_Ack 0x06 +#define AO_Status_1 0x06 +#define AI_Command_2 0x08 +#define G_Status 0x08 +#define AO_Command_2 0x0a +#define AI_Status_2 0x0a +#define G0_Command 0x0c +#define AO_Status_2 0x0c +#define G1_Command 0x0e +#define DIO_Parallel_Input 0x0e +#endif + #define Configuration_Memory_Clear 82 #define ADC_FIFO_Clear 83 #define DAC_FIFO_Clear 84 @@ -559,6 +562,22 @@ #define DAC0_Direct_Data 0x18 #define DAC1_Direct_Data 0x1a + +/* 611x registers (these boards differ from the e-series) */ + +#define AI_Command_2_Register_611x 8 +//#define AO_Status_1_Register_611x 4 +#define DAC_FIFO_Data_611x 0x14 + +#if 0 +#define AI_Status_1_611x 0x02 +#define AO_Status_1_611x 0x04 +#define G_Status_611x 0x06 +#define AI_Status_2_611x 0x08 +#define AO_Status_2_611x 0x0a +#define DIO_Parallel_Input_611x 0x0c +#endif + /* 671x registers */ #define AO_Window_Address_671x 0x18 /* W 16 */ @@ -570,6 +589,7 @@ #define AO_Immediate_671x 0x11 /* W 16 */ + #define SerDacLd(x) (0x08<<(x)) /* @@ -606,6 +626,8 @@ typedef struct ni_board_struct{ int ao_671x : 1; + int reg_611x : 1; + enum caldac_enum caldac[3]; }ni_board;