Devices: [National Instruments] AT-MIO-16E-1 (ni_atmio),
AT-MIO-16E-2, AT-MIO-16E-10, AT-MIO-16DE-10, AT-MIO-64E-3,
AT-MIO-16XE-50, AT-MIO-16XE-10, AT-AI-16XE-10
+Status: works
+Updated: Sat, 16 Mar 2002 17:34:48 -0800
The isapnptools package is required to use this board. Use isapnp to
configure the I/O base for the board, and then pass the same value as
a parameter in comedi_config. A sample isapnp.conf file is included
-in the etc/ directory.
-
-Assuming that the NI spec is correct, the driver should correctly
-identify every board in the series. Each channel should have the
-appropriate parameters, i.e., input/output ranges, number of bits,
-etc. If the driver fails to recognize your card or does not have
-the correct parameters, please contact me.
+in the etc/ directory of Comedilib.
Comedilib includes a utility to autocalibrate these boards. The
boards seem to boot into a state where the all calibration DACs
External triggering is supported for some events. The channel index
(scan_begin_arg, etc.) maps to PFI0 - PFI9.
+
+Some of the more esoteric triggering possibilities of these boards
+are not supported.
*/
/*
The real guts of the driver is in ni_mio_common.c, which is included
/* How we access registers */
+#define ni_writel(a,b) (outl((a),(b)+dev->iobase))
+#define ni_readl(a) (inl((a)+dev->iobase))
#define ni_writew(a,b) (outw((a),(b)+dev->iobase))
#define ni_readw(a) (inw((a)+dev->iobase))
#define ni_writeb(a,b) (outb((a),(b)+dev->iobase))
int i,n;
int j;
unsigned int mask;
+ unsigned int dl;
mask=(1<<boardtype.adbits)-1;
j=s->async->cur_chan;
data=s->async->data+s->async->buf_int_ptr;
+ if(boardtype.reg_611x){
+ while(1){
+ n=(s->async->data_len-s->async->buf_int_ptr)/sizeof(sampl_t);
+ for(i=0;i<n;i++){
+ if(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St){
+ /* Check if there's a single sample stuck in the FIFO */
+ if(ni_readb(Status_611x)&0x80){
+ dl=ni_readl(ADC_FIFO_Data_611x);
+ *data = (dl&0xffff) + devpriv->ai_xorlist[j];
+ j++;
+ if(j>=s->async->cmd.chanlist_len){
+ j=0;
+ }
+ data++;
+ s->async->buf_int_ptr+=sizeof(sampl_t);
+ s->async->buf_int_count+=sizeof(sampl_t);
+ }
+ s->async->cur_chan=j;
+ return;
+ }
+ dl=ni_readl(ADC_FIFO_Data_611x);
+
+ /* This may get the hi/lo data in the wrong order */
+ *data = (dl>>16) + devpriv->ai_xorlist[j];
+ j++;
+ if(j>=s->async->cmd.chanlist_len){
+ j=0;
+ //s->events |= COMEDI_CB_EOS;
+ }
+ data++;
+ s->async->buf_int_ptr+=sizeof(sampl_t);
+ s->async->buf_int_count+=sizeof(sampl_t);
+
+ *data = (dl&0xffff) + devpriv->ai_xorlist[j];
+ j++;
+ if(j>=s->async->cmd.chanlist_len){
+ j=0;
+ //s->events |= COMEDI_CB_EOS;
+ }
+ data++;
+ s->async->buf_int_ptr+=sizeof(sampl_t);
+ s->async->buf_int_count+=sizeof(sampl_t);
+ }
+ s->async->buf_int_ptr=0;
+ data=s->async->data;
+ s->async->events |= COMEDI_CB_EOBUF;
+ }
+ }else{
while(1){
n=(s->async->data_len-s->async->buf_int_ptr)/sizeof(sampl_t);
for(i=0;i<n;i++){
data=s->async->data;
s->async->events |= COMEDI_CB_EOBUF;
}
+ }
}
#ifdef PCIDMA
mite->dir = COMEDI_INPUT;
mite_prep_dma(mite);
- /*tell the STC to use DMA0 for AI.
- Select the MITE DMA channel to use, 0x01=A*/
- ni_writeb(0x01,AI_AO_Select);
-
/*start the MITE*/
mite_dma_arm(mite);
}
signbits=devpriv->ai_xorlist[0];
for(n=0;n<insn->n;n++){
win_out(1,AI_Command_1_Register);
- for(i=0;i<NI_TIMEOUT;i++){
- if(!(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St))
- break;
+ if(boardtype.reg_611x){
+ /* The 611x has screwy 32-bit FIFOs. */
+ for(i=0;i<NI_TIMEOUT;i++){
+ if(ni_readb(Status_611x)&0x80)
+ break;
+ }
+ }else{
+ for(i=0;i<NI_TIMEOUT;i++){
+ if(!(win_in(AI_Status_1_Register)&AI_FIFO_Empty_St))
+ break;
+ }
}
if(i==NI_TIMEOUT){
rt_printk("ni_E: timeout 2\n");
win_restore(wsave);
return -ETIME;
}
- d = ni_readw(ADC_FIFO_Data_Register)+signbits;
- data[n] = d;
+ if(boardtype.reg_611x){
+ d = ni_readl(ADC_FIFO_Data_611x)&0xffff;
+ }else{
+ d = ni_readw(ADC_FIFO_Data_Register);
+ }
+ data[n] = d + signbits;
}
win_restore(wsave);
return insn->n;
);
}
+ /* DMA setup */
+ /* tell the STC to use DMA0 for AI, DMA1 for AO */
+ ni_writeb(0x21,AI_AO_Select);
+
+ /* PFI setup */
pfi_setup(dev);
printk("\n");
/* How we access registers */
+#define ni_writel(a,b) (outl((a),(b)+dev->iobase))
+#define ni_readl(a) (inl((a)+dev->iobase))
#define ni_writew(a,b) (outw((a),(b)+dev->iobase))
#define ni_readw(a) (inw((a)+dev->iobase))
#define ni_writeb(a,b) (outb((a),(b)+dev->iobase))
Driver: ni_pcimio.o
Description: National Instruments PCI-MIO-E series (all boards)
Author: ds
-Status: mainly limited by Comedi infrastructure
+Status: works
Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6040E,
PXI-6040E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
PCI-6110E, PCI-6111E, PCI-6711, PCI-6713, PXI-6071E, PXI-6070E,
PXI-6052E, PCI-6036E, PCI-6731, PCI-6733
+Updated: Sat, 16 Mar 2002 17:34:48 -0800
These boards are almost identical to the AT-MIO E series, except that
-they use the PCI bus instead of ISA (i.e., AT). See the notes above for
-ni_atmio.o for additional information about these boards.
+they use the PCI bus instead of ISA (i.e., AT). See the notes for
+the ni_atmio.o driver for additional information about these boards.
Autocalibration is supported on many of the devices, using the
calibration utility in Comedilib.
work on 673x.
Information (number of channels, bits, etc.) for some devices may be
-incorrect.
+incorrect. Please check this and submit a bug if there are problems
+for your device.
Bugs:
- - Driver doesn't stop correctly when DMA is enabled.
+ - When DMA is enabled, COMEDI_EV_SCAN_END and COMEDI_EV_CONVERT do
+ not work correctly.
+ - There are reported problems with the 61xx and 67xx boards.
*/
/*
/* How we access registers */
+#define ni_writel(a,b) (writel((a),dev->iobase+(b)))
+#define ni_readl(a) (readl(dev->iobase+(a)))
#define ni_writew(a,b) (writew((a),dev->iobase+(b)))
#define ni_readw(a) (readw(dev->iobase+(a)))
#define ni_writeb(a,b) (writeb((a),dev->iobase+(b)))
projects / comedi.git / commitdiff