PCI9111_8254_MODE_2|
PCI9111_8254_BINARY_COUNTER);
- udelay(1);
+ comedi_udelay(1);
pci9111_8254_counter_2_set (dev_private->timer_divisor_2);
pci9111_8254_counter_1_set (dev_private->timer_divisor_1);
for (n=0; n<insn->n; n++) {
outw(0, dev->iobase+PCI9118_SOFTTRG); /* start conversion */
- udelay(2);
+ comedi_udelay(2);
timeout=100;
while (timeout--) {
if (inl(dev->iobase+PCI9118_ADSTAT) & AdStatus_ADrdy) goto conv_finish;
- udelay(1);
+ comedi_udelay(1);
}
comedi_error(dev,"A/D insn timeout");
outl(devpriv->AdControlReg,dev->iobase+PCI9118_ADCNTRL);
devpriv->AdFunctionReg=AdFunction_PDTrg|AdFunction_PETrg; // positive triggers, no S&H, no burst, burst stop, no post trigger, no about trigger, trigger stop
outl(devpriv->AdFunctionReg,dev->iobase+PCI9118_ADFUNC);
- udelay(1);
+ comedi_udelay(1);
outl(0,dev->iobase+PCI9118_DELFIFO); // flush FIFO
inl(dev->iobase+PCI9118_ADSTAT); // flush A/D and INT status register
inl(dev->iobase+PCI9118_INTSRC);
#endif
#endif
outl(0,dev->iobase+PCI9118_SCANMOD); // close scan queue
-// udelay(100); // important delay, or first sample will be cripled
+// comedi_udelay(100); // important delay, or first sample will be cripled
DPRINTK("adl_pci9118 EDBG: END: setup_channel_list()\n");
return 1; // we can serve this with scan logic
outl(0x74, dev->iobase + PCI9118_CNTCTRL);
outl(0xb4, dev->iobase + PCI9118_CNTCTRL);
// outl(0x30, dev->iobase + PCI9118_CNTCTRL);
- udelay(1);
+ comedi_udelay(1);
if ((mode==1)||(mode==2)||(mode==4)) {
outl(divisor2 & 0xff, dev->iobase + PCI9118_CNT2);
outl(devpriv->ao_data[0],dev->iobase+PCI9118_DA1);// reset A/D outs to 0V
outl(devpriv->ao_data[1],dev->iobase+PCI9118_DA2);
outl(0,dev->iobase+PCI9118_DO); // reset digi outs to L
- udelay(10);
+ comedi_udelay(10);
inl(dev->iobase+PCI9118_AD_DATA);
outl(0,dev->iobase+PCI9118_DELFIFO); // flush FIFO
outl(0,dev->iobase+PCI9118_INTSRC); // remove INT requests
for (n=0; n<insn->n; n++) {
outw(0, dev->iobase+PCI171x_SOFTTRG); /* start conversion */
DPRINTK("adv_pci1710 B n=%d ST=%4x\n",n,inw(dev->iobase+PCI171x_STATUS));
- //udelay(1);
+ //comedi_udelay(1);
DPRINTK("adv_pci1710 C n=%d ST=%4x\n",n,inw(dev->iobase+PCI171x_STATUS));
timeout=100;
while (timeout--) {
//devpriv->status1 |= 0x0009;
outw(devpriv->status1, dev->iobase + 4);
- udelay(1);
+ comedi_udelay(1);
status1 = devpriv->status1;
//if(chan)status1 &= ~0x0008;
printk("0x%04x\n",status1);
outw(status1, dev->iobase + 4);
- udelay(1);
+ comedi_udelay(1);
for(bit=15;bit>=0;bit--){
int b = (d>>bit)&1;
printk("0x%04x\n",status1 | b | 0x0000);
outw(status1 | b | 0x0000, dev->iobase + 4);
- udelay(1);
+ comedi_udelay(1);
printk("0x%04x\n",status1 | b | 0x0004);
outw(status1 | b | 0x0004, dev->iobase + 4);
- udelay(1);
+ comedi_udelay(1);
}
outw(devpriv->status1, dev->iobase + 4);
register_bits |= SERIAL_DATA_IN_BIT;
else
register_bits &= ~SERIAL_DATA_IN_BIT;
- udelay( write_delay );
+ comedi_udelay( write_delay );
outw( register_bits, devpriv->control_status + CALIBRATION_REG);
}
}
static const int num_caldac_channels = 8;
static const int bitstream_length = 11;
unsigned int bitstream = ((address & 0x7) << 8) | value;
- static const int caldac_8800_udelay = 1;
+ static const int caldac_8800_comedi_udelay = 1;
if(address >= num_caldac_channels)
{
write_calibration_bitstream( dev, 0, bitstream, bitstream_length );
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
outw(SELECT_8800_BIT, devpriv->control_status + CALIBRATION_REG);
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
outw(0, devpriv->control_status + CALIBRATION_REG);
return 0;
static const int bitstream_length = 7;
unsigned int bitstream = value & 0x7f;
unsigned int register_bits;
- static const int ad7376_udelay = 1;
+ static const int ad7376_comedi_udelay = 1;
register_bits = SELECT_TRIMPOT_BIT;
- udelay( ad7376_udelay );
+ comedi_udelay( ad7376_comedi_udelay );
outw( register_bits, devpriv->control_status + CALIBRATION_REG);
write_calibration_bitstream( dev, register_bits, bitstream, bitstream_length );
- udelay(ad7376_udelay);
+ comedi_udelay(ad7376_comedi_udelay);
outw(0, devpriv->control_status + CALIBRATION_REG);
return 0;
static const int bitstream_length = 10;
unsigned int bitstream = ( ( channel & 0x1 ) << 8 ) | ( value & 0xff );
unsigned int register_bits;
- static const int ad8402_udelay = 1;
+ static const int ad8402_comedi_udelay = 1;
register_bits = SELECT_TRIMPOT_BIT;
- udelay( ad8402_udelay );
+ comedi_udelay( ad8402_comedi_udelay );
outw( register_bits, devpriv->control_status + CALIBRATION_REG);
write_calibration_bitstream( dev, register_bits, bitstream, bitstream_length );
- udelay(ad8402_udelay);
+ comedi_udelay(ad8402_comedi_udelay);
outw(0, devpriv->control_status + CALIBRATION_REG);
return 0;
{
if( ( inb( s5933_base_addr + AMCC_OP_REG_MCSR_NVCMD ) & MCSR_NV_BUSY ) == 0 )
return 0;
- udelay( 1 );
+ comedi_udelay( 1 );
}
return -1;
}
if( pipe_full_bits( bits ) )
break;
}
- udelay(1);
+ comedi_udelay(1);
}
DEBUG_PRINT(" looped %i times waiting for data\n", i);
if(i == timeout)
static const int bitstream_length = 10;
unsigned int bit, register_bits;
unsigned int bitstream = ( ( channel & 0x3 ) << 8 ) | ( value & 0xff );
- static const int ad8402_udelay = 1;
+ static const int ad8402_comedi_udelay = 1;
priv(dev)->ad8402_state[ channel ] = value;
register_bits = SELECT_8402_64XX_BIT;
- udelay( ad8402_udelay );
+ comedi_udelay( ad8402_comedi_udelay );
writew( register_bits, priv(dev)->main_iobase + CALIBRATION_REG );
for( bit = 1 << ( bitstream_length - 1 ); bit; bit >>= 1 )
register_bits |= SERIAL_DATA_IN_BIT;
else
register_bits &= ~SERIAL_DATA_IN_BIT;
- udelay( ad8402_udelay );
+ comedi_udelay( ad8402_comedi_udelay );
writew( register_bits, priv(dev)->main_iobase + CALIBRATION_REG );
- udelay( ad8402_udelay );
+ comedi_udelay( ad8402_comedi_udelay );
writew( register_bits | SERIAL_CLOCK_BIT, priv(dev)->main_iobase + CALIBRATION_REG );
}
- udelay( ad8402_udelay );
+ comedi_udelay( ad8402_comedi_udelay );
writew( 0, priv(dev)->main_iobase + CALIBRATION_REG );
}
const int plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
uint16_t value;
static const int value_length = 16;
- static const int eeprom_udelay = 1;
+ static const int eeprom_comedi_udelay = 1;
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
// make sure we don't send anything to the i2c bus on 4020
priv(dev)->plx_control_bits |= CTL_USERO;
writel(priv(dev)->plx_control_bits, plx_control_addr);
// activate serial eeprom
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits |= CTL_EE_CS;
writel(priv(dev)->plx_control_bits, plx_control_addr);
for(bit = 1 << (bitstream_length - 1); bit; bit >>= 1)
{
// set bit to be written
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
if(bitstream & bit)
priv(dev)->plx_control_bits |= CTL_EE_W;
else
priv(dev)->plx_control_bits &= ~CTL_EE_W;
writel(priv(dev)->plx_control_bits, plx_control_addr);
// clock in bit
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits |= CTL_EE_CLK;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
writel(priv(dev)->plx_control_bits, plx_control_addr);
}
for(bit = 1 << (value_length - 1); bit; bit >>= 1)
{
// clock out bit
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits |= CTL_EE_CLK;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
if(readl(plx_control_addr) & CTL_EE_R)
value |= bit;
}
// deactivate eeprom serial input
- udelay(eeprom_udelay);
+ comedi_udelay(eeprom_comedi_udelay);
priv(dev)->plx_control_bits &= ~CTL_EE_CS;
writel(priv(dev)->plx_control_bits, plx_control_addr);
static const int bitstream_length = 11;
unsigned int bitstream = ((address & 0x7) << 8) | value;
unsigned int bit, register_bits;
- static const int caldac_8800_udelay = 1;
+ static const int caldac_8800_comedi_udelay = 1;
if(address >= num_caldac_channels)
{
register_bits = 0;
if(bitstream & bit)
register_bits |= SERIAL_DATA_IN_BIT;
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
register_bits |= SERIAL_CLOCK_BIT;
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
}
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
- udelay(caldac_8800_udelay);
+ comedi_udelay(caldac_8800_comedi_udelay);
writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
return 0;
}
// Their i2c requires a huge delay on setting clock or data high for some reason
-static const int i2c_high_udelay = 1000;
-static const int i2c_low_udelay = 10;
+static const int i2c_high_comedi_udelay = 1000;
+static const int i2c_low_comedi_udelay = 10;
// set i2c data line high or low
static void i2c_set_sda(comedi_device *dev, int state)
// set data line high
priv(dev)->plx_control_bits &= ~data_bit;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(i2c_high_udelay);
+ comedi_udelay(i2c_high_comedi_udelay);
}else // set data line low
{
priv(dev)->plx_control_bits |= data_bit;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(i2c_low_udelay);
+ comedi_udelay(i2c_low_comedi_udelay);
}
}
// set clock line high
priv(dev)->plx_control_bits &= ~clock_bit;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(i2c_high_udelay);
+ comedi_udelay(i2c_high_comedi_udelay);
}else // set clock line low
{
priv(dev)->plx_control_bits |= clock_bit;
writel(priv(dev)->plx_control_bits, plx_control_addr);
- udelay(i2c_low_udelay);
+ comedi_udelay(i2c_low_comedi_udelay);
}
}
{
daqboard2000_hw *fpga = devpriv->daq;
- udelay(4);
+ comedi_udelay(4);
fpga->acqScanListFIFO = entry & 0x00ff;
- udelay(4);
+ comedi_udelay(4);
fpga->acqScanListFIFO = (entry >> 8) & 0x00ff;
}
fpga->acqControl = DAQBOARD2000_SeqStartScanList;
for (timeout = 0 ; timeout < 20 ; timeout++) {
if (fpga->acqControl & DAQBOARD2000_AcqConfigPipeFull) { break; }
- //udelay(2);
+ //comedi_udelay(2);
}
fpga->acqControl = DAQBOARD2000_AdcPacerEnable;
for (timeout = 0 ; timeout < 20 ; timeout++) {
if (fpga->acqControl & DAQBOARD2000_AcqLogicScanning) { break; }
- //udelay(2);
+ //comedi_udelay(2);
}
for (timeout = 0 ; timeout < 20 ; timeout++) {
if (fpga->acqControl & DAQBOARD2000_AcqResultsFIFOHasValidData) { break;}
- //udelay(2);
+ //comedi_udelay(2);
}
data[i] = fpga->acqResultsFIFO;
fpga->acqControl = DAQBOARD2000_AdcPacerDisable;
* OK, since it works OK without enabling the DAC's, let's keep
* it as simple as possible...
*/
- //fpga->dacControl = (chan + 2) * 0x0010 | 0x0001; udelay(1000);
+ //fpga->dacControl = (chan + 2) * 0x0010 | 0x0001; comedi_udelay(1000);
fpga->dacSetting[chan] = data[i];
for (timeout = 0 ; timeout < 20 ; timeout++) {
if ((fpga->dacControl & ((chan + 1) * 0x0010)) == 0) { break; }
- //udelay(2);
+ //comedi_udelay(2);
}
devpriv->ao_readback[chan] = data[i];
/*
* Since we never enabled the DAC's, we don't need to disable it...
- * fpga->dacControl = (chan + 2) * 0x0010 | 0x0000; udelay(1000);
+ * fpga->dacControl = (chan + 2) * 0x0010 | 0x0000; comedi_udelay(1000);
*/
}
{
printk("daqboard2000_resetLocalBus\n");
writel(DAQBOARD2000_SECRLocalBusHi, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
writel(DAQBOARD2000_SECRLocalBusLo, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
}
static void daqboard2000_reloadPLX(comedi_device *dev)
{
printk("daqboard2000_reloadPLX\n");
writel(DAQBOARD2000_SECRReloadLo, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
writel(DAQBOARD2000_SECRReloadHi, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
writel(DAQBOARD2000_SECRReloadLo, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
}
static void daqboard2000_pulseProgPin(comedi_device *dev)
{
printk("daqboard2000_pulseProgPin 1\n");
writel(DAQBOARD2000_SECRProgPinHi, devpriv->plx + 0x6c);
- udelay(10000);
+ comedi_udelay(10000);
writel(DAQBOARD2000_SECRProgPinLo, devpriv->plx + 0x6c);
- udelay(10000); /* Not in the original code, but I like symmetry... */
+ comedi_udelay(10000); /* Not in the original code, but I like symmetry... */
}
static int daqboard2000_pollCPLD(comedi_device *dev, int mask) {
result=1;
break;
}
- udelay(100);
+ comedi_udelay(100);
}
- udelay(5);
+ comedi_udelay(5);
return result;
}
{
int result = 0;
- udelay(10);
+ comedi_udelay(10);
writew(data, devpriv->daq + 0x1000);
if ((readw(devpriv->daq + 0x1000) & DAQBOARD2000_CPLD_INIT) ==
DAQBOARD2000_CPLD_INIT) {
daqboard2000_hw *fpga = devpriv->daq;
/* Disable hardware triggers */
- udelay(2);
+ comedi_udelay(2);
fpga->trigControl = DAQBOARD2000_TrigAnalog | DAQBOARD2000_TrigDisable;
- udelay(2);
+ comedi_udelay(2);
fpga->trigControl = DAQBOARD2000_TrigTTL | DAQBOARD2000_TrigDisable;
/* Stop the scan list FIFO from loading the configuration pipe */
- udelay(2);
+ comedi_udelay(2);
fpga->acqControl = DAQBOARD2000_SeqStopScanList;
/* Stop the pacer clock */
- udelay(2);
+ comedi_udelay(2);
fpga->acqControl = DAQBOARD2000_AdcPacerDisable;
/* Stop the input dma (abort channel 1) */
fpga->refDacs = 0x80 | DAQBOARD2000_PosRefDacSelect;
for (timeout = 0 ; timeout < 20 ; timeout++) {
if ((fpga->dacControl & DAQBOARD2000_RefBusy) == 0) { break; }
- udelay(2);
+ comedi_udelay(2);
}
/* printk("DAQBOARD2000_PosRefDacSelect %d\n", timeout);*/
fpga->refDacs = 0x80 | DAQBOARD2000_NegRefDacSelect;
for (timeout = 0 ; timeout < 20 ; timeout++) {
if ((fpga->dacControl & DAQBOARD2000_RefBusy) == 0) { break; }
- udelay(2);
+ comedi_udelay(2);
}
/* printk("DAQBOARD2000_NegRefDacSelect %d\n", timeout);*/
}
range &= 0xf;
outb(range, dev->iobase + DAS800_GAIN);
- udelay(5);
+ comedi_udelay(5);
for(n = 0; n < insn->n; n++)
{
outb_p(DT_C_STOP, dev->iobase+DT2801_CMD);
//dt2801_wait_for_ready(dev);
- udelay(100);
+ comedi_udelay(100);
timeout=10000;
do{
stat = inb_p(dev->iobase+DT2801_STATUS);
outb_p(DT_C_RESET, dev->iobase+DT2801_CMD);
//dt2801_writecmd(dev,DT_C_RESET);
- udelay(100);
+ comedi_udelay(100);
timeout=10000;
do{
stat = inb_p(dev->iobase+DT2801_STATUS);
#if 0
outb(0, dev->iobase + DT2811_ADCSR);
- udelay(100);
+ comedi_udelay(100);
i = inb(dev->iobase + DT2811_ADDATLO);
i = inb(dev->iobase + DT2811_ADDATHI);
#endif
outb(DT2811_CLRERROR | DT2811_INTENB, dev->iobase + DT2811_ADCSR);
outb(0, dev->iobase + DT2811_ADGCR);
- udelay(100);
+ comedi_udelay(100);
irq = probe_irq_off(irqs);
restore_flags(flags);
for(i=0;i<DT2814_TIMEOUT;i++){
status = inb(dev->iobase+DT2814_CSR);
printk("dt2814: status: %02x\n",status);
-udelay(10);
+comedi_udelay(10);
if(status&DT2814_FINISH)
break;
}
dev->board_name = "dt2814";
outb(0,dev->iobase+DT2814_CSR);
- udelay(100);
+ comedi_udelay(100);
if(inb(dev->iobase+DT2814_CSR)&DT2814_ERR){
printk("reset error (fatal)\n");
return -EIO;
outb(0,dev->iobase+DT2814_CSR);
- udelay(100);
+ comedi_udelay(100);
irq=probe_irq_off(irqs);
restore_flags(flags);
/* This is incredibly slow (approx 20 ms) */
unsigned int status;
- udelay(1000);
+ comedi_udelay(1000);
status = inb(dev->iobase + DT2815_STATUS);
if (status == 4) {
unsigned int program;
int _i; \
for(_i=0;_i<DT2821_TIMEOUT;_i++){ \
if(a){_i=0;break;} \
- udelay(5); \
+ comedi_udelay(5); \
} \
if(_i){b} \
}while(0)
/* trigger interrupt */
- udelay(100);
+ comedi_udelay(100);
irq = probe_irq_off(irqs);
restore_flags(flags);
status=readw(dev->iobase+DPR_Command_Mbx);
if((status&DT3000_COMPLETION_MASK)!=DT3000_NOTPROCESSED)
break;
- udelay(1);
+ comedi_udelay(1);
}
if((status&DT3000_COMPLETION_MASK)==DT3000_NOERROR){
return 0;
outb(chan,iobase+2); /* select chan */
outb(0,iobase+3); /* start conversion */
/* XXX should test "done" flag instead of delay */
- udelay(30); /* sleep 30 usec */
+ comedi_udelay(30); /* sleep 30 usec */
lo_byte = inb(iobase+2); /* low 8 byte */
hi_byte = inb(iobase+3) & 0xf; /* high 4 bit and mask */
data[n] = lo_byte + (hi_byte << 8);
uint32_t plx_intcsr_bits;
writel( BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG );
- udelay( 10 );
+ comedi_udelay( 10 );
writel( almost_empty_bits( 32 ) | almost_full_bits( 32 ),
priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG );
printk("icp multi B n=%d ST=%4x\n",n,readw(dev->iobase+ICP_MULTI_ADC_CSR));
#endif
- udelay(1);
+ comedi_udelay(1);
#ifdef ICP_MULTI_EXTDEBUG
printk("icp multi C n=%d ST=%4x\n",n,readw(dev->iobase+ICP_MULTI_ADC_CSR));
printk("icp multi D n=%d tm=%d ST=%4x\n",n,timeout,readw(dev->iobase+ICP_MULTI_ADC_CSR));
#endif
- udelay(1);
+ comedi_udelay(1);
}
// If we reach here, a timeout has occurred
printk("icp multi A n=%d tm=%d ST=%4x\n",n,timeout,readw(dev->iobase+ICP_MULTI_DAC_CSR));
#endif
- udelay(1);
+ comedi_udelay(1);
}
// If we reach here, a timeout has occurred
writew(devpriv->DacCmdStatus, dev->iobase+ICP_MULTI_DAC_CSR);
// Delay to allow DAC time to recover
- udelay(1);
+ comedi_udelay(1);
}
// Digital outputs to 0
{
if((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
break;
- udelay(1000);
+ comedi_udelay(1000);
}
if(i == timeout)
{
{
if(inw(dev->iobase + STATUS_REG) & FNE_BIT)
break;
- udelay(1);
+ comedi_udelay(1);
}
if(i == timeout)
{
{
if(inw(dev->iobase + STATUS_REG) & FNE_BIT)
break;
- udelay(1);
+ comedi_udelay(1);
}
if(i == timeout)
{
devpriv->command1_bits |= ADC_SCAN_EN_BIT;
/* need a brief delay before enabling scan, or scan list will get screwed when you switch
* between scan up to scan down mode - dunno why */
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
}
{
if(thisboard->read_byte(dev->iobase + STATUS1_REG) & DATA_AVAIL_BIT)
break;
- udelay( 1 );
+ comedi_udelay( 1 );
}
if(i == timeout)
{
devpriv->command5_bits |= SDATA_BIT;
else
devpriv->command5_bits &= ~SDATA_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// set clock to load bit
devpriv->command5_bits |= SCLOCK_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
}
}
{
// set serial clock
devpriv->command5_bits |= SCLOCK_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// clear clock bit
devpriv->command5_bits &= ~SCLOCK_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// read bits most significant bit first
- udelay(1);
+ comedi_udelay(1);
devpriv->status2_bits = thisboard->read_byte(dev->iobase + STATUS2_REG);
if(devpriv->status2_bits & EEPROM_OUT_BIT)
{
// enable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// send read instruction
// disable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
return value;
// enable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// send write_enable instruction
labpc_serial_out(dev, write_enable_instruction, write_length);
devpriv->command5_bits &= ~EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// send write instruction
devpriv->command5_bits |= EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
labpc_serial_out(dev, write_instruction, write_length);
// send 8 bit address to write to
// write value
labpc_serial_out(dev, value, write_length);
devpriv->command5_bits &= ~EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// disable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
return 0;
// enable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
// send read status instruction
// disable read/write to eeprom
devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
return value;
// clear caldac load bit and make sure we don't write to eeprom
devpriv->command5_bits &= ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
/* write 4 bit channel, LSB first (NI appears to have gotten confused here
// set and clear caldac bit to load caldac value
devpriv->command5_bits |= CALDAC_LOAD_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
- udelay(1);
+ comedi_udelay(1);
thisboard->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
}
if( win_in( AI_Status_1_Register ) & AI_FIFO_Empty_St &&
mite_bytes_in_transit( mite, AI_DMA_CHAN ) == 0 )
break;
- udelay( 1 );
+ comedi_udelay( 1 );
}
if( i == timeout )
{
if(boardtype.reg_611x){
for(n=0; n < num_adc_stages_611x; n++){
win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
- udelay(1);
+ comedi_udelay(1);
}
for(n=0; n<insn->n; n++){
win_out(AI_CONVERT_Pulse, AI_Command_1_Register);
win_out(1,ADC_FIFO_Clear);
return;
}
- udelay(1);
+ comedi_udelay(1);
}
rt_printk("ni_mio_common: timeout loading channel/gain list\n");
}
win_out(devpriv->ao_mode3,AO_Mode_3_Register);
/* wait for DACs to be loaded */
- udelay(100);
+ comedi_udelay(100);
win_out(devpriv->ao_cmd1|AO_UI_Arm|AO_UC_Arm|AO_BC_Arm|AO_DAC1_Update_Mode|AO_DAC0_Update_Mode,
AO_Command_1_Register);
for(bit=1<<(bits-1);bit;bit>>=1){
ni_writeb(((bit&bitstring)?0x02:0),Serial_Command);
- udelay(1);
+ comedi_udelay(1);
ni_writeb(1|((bit&bitstring)?0x02:0),Serial_Command);
- udelay(1);
+ comedi_udelay(1);
}
ni_writeb(loadbit,Serial_Command);
- udelay(1);
+ comedi_udelay(1);
ni_writeb(0,Serial_Command);
}
need to slow down DAC loading. I don't trust NI's claim that
two writes to the PCI bus slows IO enough. I would prefer to
- use udelay(). Timing specs: (clock)
+ use comedi_udelay(). Timing specs: (clock)
AD8522 30ns
DAC8043 120ns
DAC8800 60ns
hi = inb(dev->iobase + PCL711_AD_HI);
if (!(hi & PCL711_DRDY))
goto ok;
- udelay(1);
+ comedi_udelay(1);
}
rt_printk("comedi%d: pcl711: A/D timeout\n", dev->minor);
return -ETIME;
setup_range_channel(dev, s, insn->chanspec, 1); // select channel and renge
for(n=0;n<insn->n;n++){
outb(255, dev->iobase + PCL812_SOFTTRIG); /* start conversion */
- udelay(5);
+ comedi_udelay(5);
timeout = 50; /* wait max 50us, it must finish under 33us */
while (timeout--) {
hi = inb(dev->iobase + PCL812_AD_HI);
if (!(hi & PCL812_DRDY))
goto conv_finish;
- udelay(1);
+ comedi_udelay(1);
}
rt_printk("comedi%d: pcl812: (%s at 0x%x) A/D insn read timeout\n", dev->minor, dev->board_name, dev->iobase);
outb(devpriv->mode_reg_int|0, dev->iobase + PCL812_MODE);
setup_range_channel(dev, s, insn->chanspec, 1); // select channel and renge
for(n=0;n<insn->n;n++){
outb(255, dev->iobase + PCL812_SOFTTRIG); /* start conversion */
- udelay(5);
+ comedi_udelay(5);
timeout = 50; /* wait max 50us, it must finish under 33us */
while (timeout--) {
if (!(inb(dev->iobase + ACL8216_STATUS) & ACL8216_DRDY))
goto conv_finish;
- udelay(1);
+ comedi_udelay(1);
}
rt_printk("comedi%d: pcl812: (%s at 0x%x) A/D insn read timeout\n", dev->minor, dev->board_name, dev->iobase);
outb(0, dev->iobase + PCL812_MODE);
if (!(inb(dev->iobase + ACL8216_STATUS) & ACL8216_DRDY)) {
err=0; break;
}
- udelay(1);
+ comedi_udelay(1);
}
} else {
mask=0x0fff;
if (!(inb(dev->iobase + PCL812_AD_HI) & PCL812_DRDY)) {
err=0; break;
}
- udelay(1);
+ comedi_udelay(1);
}
}
outb(gain_reg, dev->iobase + PCL812_GAIN); /* select gain */
if (wait) {
- udelay(devpriv->max_812_ai_mode0_rangewait); // XXX this depends on selected range and can be very long for some high gain ranges!
+ comedi_udelay(devpriv->max_812_ai_mode0_rangewait); // XXX this depends on selected range and can be very long for some high gain ranges!
}
}
#endif
outb(0xb4, dev->iobase + PCL812_CTRCTL);
outb(0x74, dev->iobase + PCL812_CTRCTL);
- udelay(1);
+ comedi_udelay(1);
if (mode==1) {
outb(divisor2 & 0xff, dev->iobase + PCL812_CTR2);
case boardPCL813:
case boardISO813:
case boardACL8113:
- udelay(5);
+ comedi_udelay(5);
break;
}
- udelay(5);
+ comedi_udelay(5);
#ifdef PCL812_EXTDEBUG
rt_printk("pcl812 EDBG: END: pcl812_reset(...)\n");
#endif
outb (0, dev->iobase + PCL816_CLRINT); /* clear INT (conversion end) flag */
break;
}
- udelay (1);
+ comedi_udelay (1);
}
// Return timeout error
if(!timeout) {
while (timeout--) {
if (!(inb (dev->iobase + PCL816_STATUS) & PCL816_STATUS_DRDY_MASK))
break;
- udelay (1);
+ comedi_udelay (1);
}
if(!timeout) { // timeout, bail error
outb (0, dev->iobase + PCL816_CLRINT); /* clear INT request */
if (!check_and_setup_channel_list (dev, s, cmd->chanlist, cmd->chanlist_len))
return -EINVAL;
- udelay (1);
+ comedi_udelay (1);
devpriv->ai_act_scan=0;
case INT_TYPE_AI1_INT:
case INT_TYPE_AI3_INT:
outb (inb (dev->iobase + PCL816_CONTROL) & 0x73, dev->iobase + PCL816_CONTROL); /* Stop A/D */
- udelay (1);
+ comedi_udelay (1);
outb (0, dev->iobase + PCL816_CONTROL); /* Stop A/D */
outb (0xb0, dev->iobase + PCL816_CTRCTL); /* Stop pacer */
outb (0x70, dev->iobase + PCL816_CTRCTL);
static int pcl816_check (int iobase)
{
outb (0x00, iobase + PCL816_MUX);
- udelay (1);
+ comedi_udelay (1);
if (inb (iobase + PCL816_MUX) != 0x00)
return 1; //there isn't card
outb (0x55, iobase + PCL816_MUX);
- udelay (1);
+ comedi_udelay (1);
if (inb (iobase + PCL816_MUX) != 0x55)
return 1; //there isn't card
outb (0x00, iobase + PCL816_MUX);
- udelay (1);
+ comedi_udelay (1);
outb (0x18, iobase + PCL816_CONTROL);
- udelay (1);
+ comedi_udelay (1);
if (inb (iobase + PCL816_CONTROL) != 0x18)
return 1; //there isn't card
return 0; // ok, card exist
{
// outb (0, dev->iobase + PCL818_DA_LO); // DAC=0V
// outb (0, dev->iobase + PCL818_DA_HI);
-// udelay (1);
+// comedi_udelay (1);
// outb (0, dev->iobase + PCL818_DO_HI); // DO=$0000
// outb (0, dev->iobase + PCL818_DO_LO);
-// udelay (1);
+// comedi_udelay (1);
outb (0, dev->iobase + PCL816_CONTROL);
outb (0, dev->iobase + PCL816_MUX);
outb (0, dev->iobase + PCL816_CLRINT);
outb (0x32, dev->iobase + PCL816_CTRCTL);
outb (0xff, dev->iobase + PCL816_CTR0);
outb (0x00, dev->iobase + PCL816_CTR0);
- udelay (1);
+ comedi_udelay (1);
outb(0xb4, dev->iobase + PCL816_CTRCTL); // set counter 2 as mode 3
outb(0x74, dev->iobase + PCL816_CTRCTL); // set counter 1 as mode 3
- udelay(1);
+ comedi_udelay(1);
if (mode == 1) {
DPRINTK("mode %d, divisor1 %d, divisor2 %d\n", mode, divisor1, divisor2);
outb (CR_RANGE(chanlist[0]), dev->iobase + PCL816_RANGE); /* select gain */
}
- udelay (1);
+ comedi_udelay (1);
outb (devpriv->ai_act_chanlist[0] | (devpriv->ai_act_chanlist[seglen - 1] << 4),
dev->iobase + PCL816_MUX); /* select channel interval to scan */
while (timeout--) {
if (inb(dev->iobase + PCL818_STATUS) & 0x10)
goto conv_finish;
- udelay(1);
+ comedi_udelay(1);
}
comedi_error(dev,"A/D insn timeout");
/* clear INT (conversion end) flag */
while (timeout--) {
if (inb(dev->iobase + PCL818_STATUS) & 0x10) goto conv_finish;
- udelay(1);
+ comedi_udelay(1);
}
outb(0,dev->iobase+PCL818_STATUS); /* clear INT request */
comedi_error(dev,"A/D mode1/3 IRQ without DRDY!");
start_pacer(dev, -1, 0, 0); // stop pacer
if (!check_and_setup_channel_list(dev, s, it)) return -EINVAL;
- udelay(1);
+ comedi_udelay(1);
devpriv->int13_act_scan=it->n;
devpriv->int13_act_chan=0;
outb(0xb4, dev->iobase + PCL818_CTRCTL);
outb(0x74, dev->iobase + PCL818_CTRCTL);
outb(0x30, dev->iobase + PCL818_CTRCTL);
- udelay(1);
+ comedi_udelay(1);
if (mode==1) {
outb(divisor2 & 0xff, dev->iobase + PCL818_CTR2);
outb(CR_RANGE(it->chanlist[i]), dev->iobase+PCL818_RANGE); /* select gain */
}
- udelay(1);
+ comedi_udelay(1);
/* select channel interval to sca n*/
outb(devpriv->act_chanlist[0] | (devpriv->act_chanlist[seglen-1] << 4),
case INT_TYPE_AO3_INT:
#endif
outb(inb(dev->iobase+PCL818_CONTROL)& 0x73, dev->iobase+PCL818_CONTROL); /* Stop A/D */
- udelay(1);
+ comedi_udelay(1);
outb(0, dev->iobase+PCL818_CONTROL); /* Stop A/D */
outb(0xb4, dev->iobase + PCL818_CTRCTL);/* Stop pacer */
outb(0x74, dev->iobase + PCL818_CTRCTL);
static int pcl818_check(int iobase)
{
outb(0x00, iobase + PCL818_MUX);
- udelay(1);
+ comedi_udelay(1);
if (inb(iobase + PCL818_MUX)!=0x00) return 1; //there isn't card
outb(0x55, iobase + PCL818_MUX);
- udelay(1);
+ comedi_udelay(1);
if (inb(iobase + PCL818_MUX)!=0x55) return 1; //there isn't card
outb(0x00, iobase + PCL818_MUX);
- udelay(1);
+ comedi_udelay(1);
outb(0x18, iobase + PCL818_CONTROL);
- udelay(1);
+ comedi_udelay(1);
if (inb(iobase + PCL818_CONTROL)!=0x18) return 1; //there isn't card
return 0; // ok, card exist
}
}
outb(0, dev->iobase + PCL818_DA_LO); // DAC=0V
outb(0, dev->iobase + PCL818_DA_HI);
- udelay(1);
+ comedi_udelay(1);
outb(0, dev->iobase + PCL818_DO_HI); // DO=$0000
outb(0, dev->iobase + PCL818_DO_LO);
- udelay(1);
+ comedi_udelay(1);
outb(0, dev->iobase + PCL818_CONTROL);
outb(0, dev->iobase + PCL818_CNTENABLE);
outb(0, dev->iobase + PCL818_MUX);
for( i = 0; ( dma_status & PLX_DMA_DONE_BIT ) && i < timeout; i++ )
{
dma_status = readb( dma_cs_addr );
- udelay( 1 );
+ comedi_udelay( 1 );
}
if( i == timeout )
{
}
// disable channel
writeb( 0, dma_cs_addr );
- udelay( 1 );
+ comedi_udelay( 1 );
// abort channel
writeb( PLX_DMA_ABORT_BIT, dma_cs_addr );
// wait for dma done bit
dma_status = readb( dma_cs_addr );
for( i = 0; ( dma_status & PLX_DMA_DONE_BIT ) == 0 && i < timeout; i++ )
{
- udelay( 1 );
+ comedi_udelay( 1 );
dma_status = readb( dma_cs_addr );
}
if( i == timeout )
#define RTD_DMA_TIMEOUT 33000 /* 1 msec */
#else
/* by delaying, power and electrical noise are reduced somewhat */
-#define WAIT_QUIETLY udelay (1)
+#define WAIT_QUIETLY comedi_udelay (1)
#define RTD_ADC_TIMEOUT 2000 /* in usec */
#define RTD_DAC_TIMEOUT 2000 /* in usec */
#define RTD_DMA_TIMEOUT 1000 /* in usec */
/* initialize board, per RTD spec */
/* also, initialize shadow registers */
RtdResetBoard (dev);
- udelay (100); /* needed? */
+ comedi_udelay (100); /* needed? */
RtdInterruptMask (dev,0); /* and sets shadow */
RtdInterruptClearMask (dev,~0); /* and sets shadow */
RtdInterruptClear(dev); /* clears bits set by mask */
/* disable channel (required) */
writeb(0, dma_cs_addr);
- udelay(1); /* needed?? */
+ comedi_udelay(1); /* needed?? */
/* set abort bit for channel */
writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
return -EIO;
}
if (status & RTI800_DONE)break;
- //udelay(8);
+ //comedi_udelay(8);
}
if(t == 0){
rt_printk("rti800: timeout\n");
if (count == 1) { result = ch; }
break;
}
- udelay(100);
+ comedi_udelay(100);
}
set_fs(oldfs);
}
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
+#include <linux/delay.h>
#ifdef CONFIG_COMEDI_RT
#ifdef CONFIG_COMEDI_RTAI
#include <rtai.h>
+#include <rtai_sched.h>
#endif
#ifdef CONFIG_COMEDI_RTL
#include <rtl_core.h>
+#include <time.h>
//#ifdef RTLINUX_VERSION_CODE
#include <rtl_sync.h>
//#endif
}
+/* define a RT safe udelay */
+static inline void comedi_udelay( unsigned int usec )
+{
+#if defined(CONFIG_COMEDI_RTAI)
+ static const int nanosec_per_usec = 1000;
+ rt_busy_sleep( usec * nanosec_per_usec );
+#elif defined(CONFIG_COMEDI_RTL)
+ usleep( usec );
+#else
+ udelay( usec );
+#endif
+}
+
#endif