apply patch for mips n32 support from Stuart Longland <redhatter@gentoo.org> in bug...

git-svn-id: svn+ssh://svn.gentoo.org/var/svnroot/catalyst/trunk@1259 d1e1f19c-881f-0410-ab34-b69fee027534

diff --git a/ChangeLog b/ChangeLog
index 829e0bc7e490177534cb12355a3067a3d0654d25..f681365848ac5b6b9b32e66c5f7d87295ec3eb52 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,6 +1,10 @@
 # Copyright 2002-2007 Gentoo Foundation; Distributed under the GPL v2
 # $Id: $
 
+  17 Nov 2007; Andrew Gaffney <agaffney@gentoo.org> arch/mips.py:
+  apply patch for mips n32 support from Stuart Longland <redhatter@gentoo.org>
+  in bug #197917
+
   17 Nov 2007; Andrew Gaffney <agaffney@gentoo.org>
   targets/livecd-stage2/livecd-stage2-controller.sh,
   targets/support/livecdfs-update.sh:

diff --git a/arch/mips.py b/arch/mips.py
index ba48a9f4e35641187b631028d1bfeb4a7b010650..d2bb80bf23485a5be46fee97c61ec94216c3e3f4 100644 (file)
--- a/arch/mips.py
+++ b/arch/mips.py
@@ -65,12 +65,26 @@ class arch_mipsel3(generic_mipsel):
                generic_mipsel.__init__(self,myspec)
                self.settings["CFLAGS"]="-O2 -mips3 -mabi=32 -pipe"
 
+class arch_mipsel3n32(generic_mipsel):
+       "Builder class for all MIPS III [Little-endian N32]"
+       def __init__(self,myspec):
+               generic_mipsel.__init__(self,myspec)
+               self.settings["CFLAGS"]="-O2 -mips3 -mabi=n32 -pipe"
+               self.settings["CHOST"]="mips64el-unknown-linux-gnu"
+
 class arch_mipsel4(generic_mipsel):
        "Builder class for all MIPS IV [Little-endian]"
        def __init__(self,myspec):
                generic_mipsel.__init__(self,myspec)
                self.settings["CFLAGS"]="-O2 -mips4 -mabi=32 -pipe"
 
+class arch_mipsel4n32(generic_mipsel):
+       "Builder class for all MIPS IV [Little-endian N32]"
+       def __init__(self,myspec):
+               generic_mipsel.__init__(self,myspec)
+               self.settings["CFLAGS"]="-O2 -mips4 -mabi=n32 -pipe"
+               self.settings["CHOST"]="mips64el-unknown-linux-gnu"
+
 
 
 def register():
@@ -86,9 +100,12 @@ def register():
                        "mipsel1"       :arch_mipsel1,
                        "mipsel2"       :arch_mipsel2,
                        "mipsel3"       :arch_mipsel3,
+                       "mipsel3n32"    :arch_mipsel3n32,
                        "mipsel4"       :arch_mipsel4,
+                       "mipsel4n32"    :arch_mipsel4n32,
                        "sgir4k"        :arch_mips3, 
                        "sgir5k"        :arch_mips4,
                        "sgir10kplus"   :arch_mips4,
+                       "loongson"      :arch_mipsel3,
                        "cobalt"        :arch_mipsel4
        }, ("mips","mips64"))