ni_writew(lo,Configuration_Memory_Low);
}
- prime the channel/gain list */
+ /* prime the channel/gain list */
win_out(1,AI_Command_1_Register);
for(i=0;i<40;i++){
int bits;
/* interrupt on FIFO, errors, SC_TC */
- bits=0x00a1;
+ bits=AI_FIFO_Interrupt_Enable|AI_Error_Interrupt_Enable|
+ AI_SC_TC_Interrupt_Enable;
+ //bits|=Pass_Thru_0_Interrupt_Enable;
if(it->flags&TRIG_WAKE_EOS){
/* wake on end-of-scan */
break;
}
-bits=AI_SC_TC_Interrupt_Enable;
-bits|=AI_Error_Interrupt_Enable;
-//bits|=Pass_Thru_0_Interrupt_Enable;
win_out(0x3f80,Interrupt_A_Ack_Register); /* clear interrupts */
win_out(bits,Interrupt_A_Enable_Register) ;
dev->irq=mite_irq(devpriv->mite);
+{
+ int i;
+ printk("\n");
+ for(i=2048;i<4096;i+=2){
+ printk("%04x ",readw(dev->iobase+i));
+ if((i%64)==62)printk("\n");
+ }
+}
if(dev->irq==0){
printk(" unknown irq (bad)\n");
}else{