sys-devel/clang: Disable RISCV following upstream
authorMichał Górny <mgorny@gentoo.org>
Tue, 15 Aug 2017 11:19:07 +0000 (13:19 +0200)
committerMichał Górny <mgorny@gentoo.org>
Tue, 15 Aug 2017 12:35:27 +0000 (14:35 +0200)
sys-devel/clang/clang-5.0.9999.ebuild
sys-devel/clang/clang-9999.ebuild

index df33aa3a8b7ae5e49a953946f94f7b69d8c6df94..268b06fbc7ba0e546825079d3ff6a7babc51ad7b 100644 (file)
@@ -20,7 +20,7 @@ EGIT_BRANCH="release_50"
 
 # Keep in sync with sys-devel/llvm
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?}
 
index 57378c25ed3fa9d2f82f1c317ead5380c4c2e760..73335e4fa4f4f2eb20a73e67bd384b4ef49f9eb4 100644 (file)
@@ -19,7 +19,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/clang.git
 
 # Keep in sync with sys-devel/llvm
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
-       NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+       NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 LLVM_TARGET_USEDEPS=${ALL_LLVM_TARGETS[@]/%/?}