if((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
break;
udelay(1000);
- // probably should sleep instead of using udelay since wait is so long
}
if(i == timeout)
{
return 0;
}
-// XXX doesn't seem to work
static int a2150_ai_rinsn(comedi_device *dev, comedi_subdevice *s, comedi_insn *insn, lsampl_t *data)
{
unsigned int i, n;
- static const int timeout = 10000;
+ static const int timeout = 100000;
+ static const int filter_delay = 36;
// clear fifo and reset triggering circuitry
outw(0, dev->iobase + FIFO_RESET_REG);
// start aquisition for soft trigger
outw(0, dev->iobase + FIFO_START_REG);
- /* there is a 35.6 sample delay for data to get through the antialias filter
- * so we might as well wait a while */
- udelay(500);
+ /* there is a 35.6 sample delay for data to get through the antialias filter */
+ for(n = 0; n < filter_delay; n++)
+ {
+ for(i = 0; i < timeout; i++)
+ {
+ if(inw(dev->iobase + STATUS_REG) & FNE_BIT)
+ break;
+ udelay(1);
+ }
+ if(i == timeout)
+ {
+ comedi_error(dev, "timeout");
+ return -ETIME;
+ }
+ inw(dev->iobase + FIFO_DATA_REG);
+ }
// read data
for(n = 0; n < insn->n; n++)
{
if(inw(dev->iobase + STATUS_REG) & FNE_BIT)
break;
+ udelay(1);
}
if(i == timeout)
{
thisboard->read_byte(dev->iobase + ADC_FIFO_REG);
thisboard->read_byte(dev->iobase + ADC_FIFO_REG);
- // give it a little settling time
- udelay(5);
-
for(n = 0; n < insn->n; n++)
{
/* trigger conversion */
pcl711_set_changain(dev,insn->chanspec);
- /*
- a sensible precaution to wait for the mux to
- settle here. is 10us enough?
- */
- udelay(10);
-
for(n=0;n<insn->n;n++){
/*
* Write the correct mode (software polling) and start polling by writing
hi = inb(dev->iobase + PCL711_AD_HI);
if (!(hi & PCL711_DRDY))
goto ok;
+ udelay(1);
}
rt_printk("comedi%d: pcl711: A/D timeout\n", dev->minor);
return -ETIME;
int timeout;
DPRINTK("mode 0 analog input\n");
+ // software trigger, DMA and INT off
+ outb (0, dev->iobase + PCL816_CONTROL);
+ // clear INT (conversion end) flag
+ outb (0, dev->iobase + PCL816_CLRINT);
+
+ // Set the input channel
+ outb (CR_CHAN(insn->chanspec) & 0xf, dev->iobase + PCL816_MUX);
+ outb (CR_RANGE(insn->chanspec), dev->iobase + PCL816_RANGE); /* select gain */
for(n=0;n<insn->n;n++){
- // software trigger, DMA and INT off
- outb (0, dev->iobase + PCL816_CONTROL);
- // clear INT (conversion end) flag
- outb (0, dev->iobase + PCL816_CLRINT);
-
- // Set the input channel
- outb (CR_CHAN(insn->chanspec) & 0xf, dev->iobase + PCL816_MUX);
- outb (CR_RANGE(insn->chanspec), dev->iobase + PCL816_RANGE); /* select gain */
- udelay (5);
outb (0, dev->iobase + PCL816_AD_LO); /* start conversion */
- timeout=100;
+ timeout=100;
while (timeout--) {
if (!(inb (dev->iobase + PCL816_STATUS) & PCL816_STATUS_DRDY_MASK)) {
// return read value
int n;
int timeout;
+ /* software trigger, DMA and INT off */
+ outb(0, dev->iobase+PCL818_CONTROL);
+
+ /* select channel */
+ outb(muxonechan[CR_CHAN(insn->chanspec)],
+ dev->iobase+PCL818_MUX);
+
+ /* select gain */
+ outb(CR_RANGE(insn->chanspec),
+ dev->iobase+PCL818_RANGE);
+
for(n=0;n<insn->n;n++){
- /* software trigger, DMA and INT off */
- outb(0, dev->iobase+PCL818_CONTROL);
/* clear INT (conversion end) flag */
outb(0, dev->iobase+PCL818_CLRINT);
- /* select channel */
- outb(muxonechan[CR_CHAN(insn->chanspec)],
- dev->iobase+PCL818_MUX);
-
- /* select gain */
- outb(CR_RANGE(insn->chanspec),
- dev->iobase+PCL818_RANGE);
-
- udelay(5);
/* start conversion */
outb(0, dev->iobase+PCL818_AD_LO);
while (timeout--) {
if (inb(dev->iobase + PCL818_STATUS) & 0x10)
goto conv_finish;
+ udelay(1);
}
comedi_error(dev,"A/D insn timeout");
/* clear INT (conversion end) flag */