unsigned long clk_sce_iobase; /* CLK_SCE base address */
unsigned long gat_sce_iobase; /* GAT_SCE base address */
int which; /* Bit 5 of CLK_SCE or GAT_SCE */
- int has_clk_gat_sce;
unsigned clock_src[3]; /* Current clock sources */
unsigned gate_src[3]; /* Current gate sources */
spinlock_t spinlock;
dio200_subdev_8254 *subpriv = s->private;
unsigned char byte;
- if (!subpriv->has_clk_gat_sce)
+ if (!thislayout->has_clk_gat_sce)
return -1;
if (counter_number > 2)
return -1;
{
dio200_subdev_8254 *subpriv = s->private;
- if (!subpriv->has_clk_gat_sce)
+ if (!thislayout->has_clk_gat_sce)
return -1;
if (counter_number > 2)
return -1;
dio200_subdev_8254 *subpriv = s->private;
unsigned char byte;
- if (!subpriv->has_clk_gat_sce)
+ if (!thislayout->has_clk_gat_sce)
return -1;
if (counter_number > 2)
return -1;
dio200_subdev_8254 *subpriv = s->private;
unsigned clock_src;
- if (!subpriv->has_clk_gat_sce)
+ if (!thislayout->has_clk_gat_sce)
return -1;
if (counter_number > 2)
return -1;
*/
static int
dio200_subdev_8254_init(comedi_device * dev, comedi_subdevice * s,
- unsigned long iobase, unsigned offset, int has_clk_gat_sce)
+ unsigned long iobase, unsigned offset)
{
dio200_subdev_8254 *subpriv;
unsigned int chan;
spin_lock_init(&subpriv->spinlock);
subpriv->iobase = offset + iobase;
- subpriv->has_clk_gat_sce = has_clk_gat_sce;
- if (has_clk_gat_sce) {
+ if (thislayout->has_clk_gat_sce) {
/* Derive CLK_SCE and GAT_SCE register offsets from
* 8254 offset. */
subpriv->clk_sce_iobase =
for (chan = 0; chan < 3; chan++) {
i8254_set_mode(subpriv->iobase, 0, chan,
I8254_MODE0 | I8254_BINARY);
- if (subpriv->has_clk_gat_sce) {
+ if (thislayout->has_clk_gat_sce) {
/* Gate source 0 is VCC (logic 1). */
dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
/* Clock source 0 is the dedicated clock input. */
case sd_8254:
/* counter subdevice (8254) */
ret = dio200_subdev_8254_init(dev, s, iobase,
- layout->sdinfo[n], layout->has_clk_gat_sce);
+ layout->sdinfo[n]);
if (ret < 0) {
return ret;
}