if( boardtype.reg_611x == 0 ) return;
/* Check if there's a single sample stuck in the FIFO */
- if(ni_readb(Status_611x)&0x80){
+ if(ni_readb(XXX_Status)&0x80){
dl=ni_readl(ADC_FIFO_Data_611x);
data = (dl&0xffff) + devpriv->ai_offset[async->cur_chan++];
async->cur_chan %= async->cmd.chanlist_len;
#ifdef PCIDMA
mite_dma_disarm(devpriv->mite, AI_DMA_CHAN);
#endif
- win_out(AI_Reset,Joint_Reset_Register);
/* ai configuration */
- win_out(AI_Configuration_Start,Joint_Reset_Register);
+ win_out( AI_Configuration_Start | AI_Reset, Joint_Reset_Register );
ni_set_bits(dev, Interrupt_A_Enable_Register,
AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable|
AI_STOP_Interrupt_Enable| AI_Error_Interrupt_Enable|
AI_FIFO_Interrupt_Enable,0);
- // XXX do interrupt ack
-
win_out(1,ADC_FIFO_Clear);
ni_writeb(0, Misc_Command);
/* The 611x has screwy 32-bit FIFOs. */
d = 0;
for(i=0; i<NI_TIMEOUT; i++){
- if(ni_readb(Status_611x)&0x80)
+ if(ni_readb(XXX_Status)&0x80)
{
d = ( ni_readl(ADC_FIFO_Data_611x) >> 16 ) & 0xffff;
break;
bits |= 1 << ( GPC1_DMA_CHAN + 4 );
ni_writeb( bits, G0_G1_Select);
+ /* 611x init */
+ if( boardtype.reg_611x )
+ {
+ ni_writeb( 0, Magic_611x );
+ }
+
printk("\n");
return 0;
for(bit=0x80;bit;bit>>=1){
ni_writeb(0x04,Serial_Command);
ni_writeb(0x05,Serial_Command);
- bitstring|=((ni_readb(XXX_Status)&0x01)?bit:0);
+ bitstring|=((ni_readb(XXX_Status)&PROMOUT)?bit:0);
}
ni_writeb(0x00,Serial_Command);
static int pcimio_attach(comedi_device *dev,comedi_devconfig *it)
{
int ret;
-
+
printk("comedi%d: ni_pcimio:",dev->minor);
-
+
ret=alloc_private(dev,sizeof(ni_private));
if(ret<0)return ret;
printk(" %s",boardtype.name);
dev->board_name=boardtype.name;
-
+
ret = mite_setup(devpriv->mite);
if(ret < 0)
{
dev->irq=mite_irq(devpriv->mite);
- if(dev->irq==0){
+ if(dev->irq==0){
printk(" unknown irq (bad)\n");
}else{
- printk(" ( irq = %d )",dev->irq);
- if( (ret=comedi_request_irq(dev->irq,ni_E_interrupt,NI_E_IRQ_FLAGS,"ni_pcimio",dev))<0 ){
- printk(" irq not available\n");
+ printk(" ( irq = %d )",dev->irq);
+ if( (ret=comedi_request_irq(dev->irq,ni_E_interrupt,NI_E_IRQ_FLAGS,"ni_pcimio",dev))<0 ){
+ printk(" irq not available\n");
dev->irq=0;
- }
+ }
}
ret = ni_E_init(dev,it);
#define AI_Configuration_End _bit8
#define AO_Configuration_Start _bit5
#define AI_Configuration_Start _bit4
+#define G1_Reset _bit3
+#define G0_Reset _bit2
#define AO_Reset _bit1
#define AI_Reset _bit0
#define G0_Save_St _bit0
/* general purpose counter timer */
-#define G0_Reset _bit2
-#define G1_Reset _bit3
#define G0_TC_Interrupt_Enable _bit6
#define G1_TC_Interrupt_Enable _bit9
#define G0_Gate_Interrupt_Enable _bit8
/* 8 bit registers */
#define XXX_Status 0x01
+enum XXX_Status_Bits
+{
+ PROMOUT = 0x1,
+ AI_FIFO_LOWER_NOT_EMPTY = 0x8,
+};
#define Serial_Command 0x0d
#define Misc_Command 0x0f
#define Port_A 0x19
/* 611x registers (these boards differ from the e-series) */
#define Magic_611x 0x19 /* w8 (new) */
-#define Status_611x 0x01 /* r8 (additional bits) */
-enum Status_611x_Bits
-{
- AI_FIFO_LOWER_NOT_EMPTY = 0x8,
-};
#define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
#define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */
#define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */
#define AO_FIFO_Offset_Load_611x 0x13 /* W32? */
-#define AO_Configuration_611x 0x16 /* w16 */
#define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */
#define AO_Window_Addr_611x 0x18 /* w16 */
#define AO_Window_Data_611x 0x1e /* w16 */