fixes for big endian machines

diff --git a/comedi/drivers/cb_pcidas64.c b/comedi/drivers/cb_pcidas64.c
index 802752e5fa8da5ef567f2c0e74281018df6c6fca..7719fa850e73de092f7ab948b19f80c931f65571 100644 (file)
--- a/comedi/drivers/cb_pcidas64.c
+++ b/comedi/drivers/cb_pcidas64.c
@@ -1183,6 +1183,14 @@ static void init_plx9080(comedi_device *dev)
        DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n", readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
        DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n", readb(plx_iobase + PLX_DMA0_CS_REG));
        DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n", readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
+       DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
+
+#ifdef __BIG_ENDIAN
+       bits = BIGEND_DMA0 | BIGEND_DMA1;
+#else
+       bits = 0;
+#endif
+       writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
 
        disable_plx_interrupts( dev );
 
@@ -1549,14 +1557,14 @@ static int attach(comedi_device *dev, comedi_devconfig *it)
        // initialize dma descriptors
        for(index = 0; index < DMA_RING_COUNT; index++)
        {
-               priv(dev)->dma_desc[index].pci_start_addr = priv(dev)->ai_buffer_phys_addr[index];
+               priv(dev)->dma_desc[index].pci_start_addr = __cpu_to_le32(priv(dev)->ai_buffer_phys_addr[index]);
                if(board(dev)->layout == LAYOUT_4020)
-                       priv(dev)->dma_desc[index].local_start_addr = priv(dev)->local1_iobase + ADC_FIFO_REG;
+                       priv(dev)->dma_desc[index].local_start_addr = __cpu_to_le32(priv(dev)->local1_iobase + ADC_FIFO_REG);
                else
-                       priv(dev)->dma_desc[index].local_start_addr = priv(dev)->local0_iobase + ADC_FIFO_REG;
-               priv(dev)->dma_desc[index].transfer_size = 0;
-               priv(dev)->dma_desc[index].next = (priv(dev)->dma_desc_phys_addr + ((index + 1) % (DMA_RING_COUNT)) * sizeof(priv(dev)->dma_desc[0])) |
-                       PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
+                       priv(dev)->dma_desc[index].local_start_addr = __cpu_to_le32(priv(dev)->local0_iobase + ADC_FIFO_REG);
+               priv(dev)->dma_desc[index].transfer_size = __cpu_to_le32(0);
+               priv(dev)->dma_desc[index].next = __cpu_to_le32((priv(dev)->dma_desc_phys_addr + ((index + 1) % (DMA_RING_COUNT)) * sizeof(priv(dev)->dma_desc[0])) |
+                       PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI);
        }
 
        priv(dev)->hw_revision = hw_revision( dev, readw(priv(dev)->main_iobase + HW_STATUS_REG ) );
@@ -2428,8 +2436,8 @@ static int ai_cmd(comedi_device *dev,comedi_subdevice *s)
                priv(dev)->dma_index = 0;
 
                // set dma transfer size
-               for( i = 0; i < DMA_RING_COUNT; i++)
-                       priv(dev)->dma_desc[ i ].transfer_size = dma_transfer_size( dev ) * sizeof( uint16_t );
+               for(i = 0; i < DMA_RING_COUNT; i++)
+                       priv(dev)->dma_desc[i].transfer_size = __cpu_to_le32(dma_transfer_size(dev) * sizeof(uint16_t));
 
                /* These register are supposedly unused during chained dma,
                 * but I have found that left over values from last operation

diff --git a/comedi/drivers/plx9080.h b/comedi/drivers/plx9080.h
index 5fc7c4bb91aea53bc186d7caefd7a6238fce0bb6..c837f8a78b6ddb6d8b2578a6e5e45e3726f2c0b4 100644 (file)
--- a/comedi/drivers/plx9080.h
+++ b/comedi/drivers/plx9080.h
@@ -85,6 +85,20 @@ enum marb_bits
        MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
        MARB_USE_SUBSYSTEM_IDS = 0x20000000,
 };
+
+#define PLX_BIGEND_REG 0xc
+enum bigend_bits
+{
+       BIGEND_CONFIG = 0x1,    /* use big endian ordering for configuration register accesses*/
+       BIGEND_DIRECT_MASTER = 0x2,
+       BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
+       BIGEND_ROM = 0x8,
+       BIGEND_BYTE_LANE = 0x10, /* use byte lane consisting of most significant bits instead of least significant */
+       BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
+       BIGEND_DMA1 = 0x40,
+       BIGEND_DMA0 = 0x80,
+};
+
 /* Note: The Expansion ROM  stuff is only relevant to the PC environment.
 **       This expansion ROM code is executed by the host CPU at boot time.
 **       For this reason no bit definitions are provided here.