bugfix for #59882
authorJohn P. Davis <zhen@gentoo.org>
Tue, 10 Aug 2004 04:25:08 +0000 (04:25 +0000)
committerJohn P. Davis <zhen@gentoo.org>
Tue, 10 Aug 2004 04:25:08 +0000 (04:25 +0000)
git-svn-id: svn+ssh://svn.gentoo.org/var/svnroot/catalyst/trunk@427 d1e1f19c-881f-0410-ab34-b69fee027534

ChangeLog
arch/mips.py

index 402cf6fa249dec7230fc39a91050fc2573cbcb56..a9816d96f3e29cdc2bbc6d44962f05e8eb28a916 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,6 +1,10 @@
 # ChangeLog for gentoo/src/catalyst 
 # Copyright 2002-2004 Gentoo Technologies, Inc.; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo/src/catalyst/ChangeLog,v 1.76 2004/08/03 00:09:24 zhen Exp $
+# $Header: /var/cvsroot/gentoo/src/catalyst/ChangeLog,v 1.77 2004/08/10 04:25:08 zhen Exp $
+
+  10 Aug 2004; John Davis <zhen@gentoo.org> arch/mips.py:
+  add support for mips4n32 subarch. thanks to iluxa@gentoo.org. closes bug
+  #59882.
 
   02 Aug 2004; John Davis <zhen@gentoo.org> modules/generic_stage_target.py:
   fix for bug #58208
index c08d977d69a80710e4f5acb51aeb96e27993ac0f..94a6a75e9d9388882debc1e205c03f093b21fce3 100644 (file)
@@ -44,6 +44,13 @@ class arch_mips4(generic_mips):
                generic_mips.__init__(self,myspec)
                self.settings["CFLAGS"]="-O2 -mips4 -mabi=32 -fomit-frame-pointer"
 
+class arch_mips4n32(generic_mips):
+       "Builder class for MIPS IV [Big-endian N32]"
+       def __init__(self,myspec):
+               generic_mips.__init__(self,myspec)
+               self.settings["CFLAGS"]="-O2 -mips4 -mabi=n32 -fomit-frame-pointer"
+               self.settings["CHOST"]="mips64-unknown-linux-gnu"
+
 class arch_mipsel1(generic_mipsel):
        "Builder class for all MIPS I [Little-endian]"
        def __init__(self,myspec):
@@ -78,6 +85,7 @@ def register(foo):
                        "mips2"         :arch_mips2,
                        "mips3"         :arch_mips3,
                        "mips4"         :arch_mips4,
+                       "mips4n32"      :arch_mips4n32,
                        "mipsel"        :arch_mipsel1,
                        "mipsel1"       :arch_mipsel1,
                        "mipsel2"       :arch_mipsel2,