int n;
/* reset fifo */
- devpriv->stc_writew(dev, 0,DAC_FIFO_Clear);
+ devpriv->stc_writew(dev, 1,DAC_FIFO_Clear);
if(boardtype.reg_type & ni_reg_6xxx_mask)
ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
ni_set_bits(dev, Interrupt_B_Enable_Register, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
interrupt_b_bits = AO_Error_Interrupt_Enable;
#ifdef PCIDMA
- devpriv->stc_writew(dev, 0, DAC_FIFO_Clear);
+ devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
if(boardtype.reg_type & ni_reg_6xxx_mask)
ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
ni_ao_setup_MITE_dma(dev, &s->async->cmd);
case AO_Command_1_Register:
offset = M_Offset_AO_Command_1;
break;
+ case AO_Command_2_Register:
+ offset = M_Offset_AO_Command_2;
+ break;
case AO_Mode_1_Register:
offset = M_Offset_AO_Mode_1;
break;
case AO_Start_Select_Register:
offset = M_Offset_AO_Start_Select;
break;
+ case AO_Trigger_Select_Register:
+ offset = M_Offset_AO_Trigger_Select;
+ break;
case Clock_and_FOUT_Register:
offset = M_Offset_Clock_and_FOUT;
break;