return 0;
}
-static inline int i8254_mm_load(unsigned long base_address,
+static inline int i8254_mm_load(void *base_address,
unsigned int counter_number, unsigned int count, unsigned int mode)
{
unsigned int byte;
unsigned long main_phys_iobase;
unsigned long dio_counter_phys_iobase;
// base addresses (ioremapped)
- unsigned long plx9080_iobase;
- unsigned long main_iobase;
- unsigned long dio_counter_iobase;
+ void *plx9080_iobase;
+ void *main_iobase;
+ void *dio_counter_iobase;
// local address (used by dma controller)
uint32_t local0_iobase;
uint32_t local1_iobase;
static void init_plx9080(comedi_device *dev)
{
uint32_t bits;
- unsigned long plx_iobase = priv(dev)->plx9080_iobase;
+ void *plx_iobase = priv(dev)->plx9080_iobase;
priv(dev)->plx_control_bits = readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
static int setup_subdevices(comedi_device *dev)
{
comedi_subdevice *s;
- unsigned long dio_8255_iobase;
+ void *dio_8255_iobase;
int i;
if( alloc_subdevices( dev, 10 ) < 0 )
if(board(dev)->layout == LAYOUT_4020)
{
dio_8255_iobase = priv(dev)->main_iobase + I8255_4020_REG;
- subdev_8255_init(dev, s, dio_callback_4020, dio_8255_iobase);
+ subdev_8255_init(dev, s, dio_callback_4020, (unsigned long) dio_8255_iobase);
} else
{
dio_8255_iobase = priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
- subdev_8255_init(dev, s, dio_callback, dio_8255_iobase);
+ subdev_8255_init(dev, s, dio_callback, (unsigned long) dio_8255_iobase);
}
}else
s->type = COMEDI_SUBD_UNUSED;
priv(dev)->dio_counter_phys_iobase = pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
// remap, won't work with 2.0 kernels but who cares
- priv(dev)->plx9080_iobase = (unsigned long)ioremap(priv(dev)->plx9080_phys_iobase,
+ priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
pci_resource_len(pcidev, PLX9080_BADDRINDEX));
- priv(dev)->main_iobase = (unsigned long)ioremap(priv(dev)->main_phys_iobase,
+ priv(dev)->main_iobase = ioremap(priv(dev)->main_phys_iobase,
pci_resource_len(pcidev, MAIN_BADDRINDEX));
- priv(dev)->dio_counter_iobase = (unsigned long)ioremap(priv(dev)->dio_counter_phys_iobase,
+ priv(dev)->dio_counter_iobase = ioremap(priv(dev)->dio_counter_phys_iobase,
pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
DEBUG_PRINT(" plx9080 remapped to 0x%lx\n", priv(dev)->plx9080_iobase);
uint32_t next_transfer_addr;
int j;
int num_samples = 0;
- unsigned long pci_addr_reg;
+ void *pci_addr_reg;
if(channel)
pci_addr_reg = priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
{
unsigned int num_bytes;
unsigned int next_transfer_addr;
- unsigned long pci_addr_reg = priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
+ void *pci_addr_reg = priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
unsigned int buffer_index;
do
{
if(dir)
{
- writeb(data, iobase + port);
+ writeb(data, (void*) (iobase + port));
DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
return 0;
}else
{
- return readb(iobase + port);
+ return readb((void*)(iobase + port));
}
}
{
if(dir)
{
- writew(data, iobase + 2 * port);
+ writew(data, (void*)(iobase + 2 * port));
return 0;
}else
{
- return readw(iobase + 2 * port);
+ return readw((void*)(iobase + 2 * port));
}
}
static const int read_command = 0x6;
unsigned int bitstream = (read_command << 8) | address;
unsigned int bit;
- const unsigned long plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
+ void * const plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
uint16_t value;
static const int value_length = 16;
static const int eeprom_comedi_udelay = 1;
static void i2c_set_sda(comedi_device *dev, int state)
{
static const int data_bit = CTL_EE_W;
- unsigned long plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
+ void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
if(state)
{
static void i2c_set_scl(comedi_device *dev, int state)
{
static const int clock_bit = CTL_USERO;
- unsigned long plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
+ void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
if(state)
{
{
int result = 0;
if(dir){
- writew(data,ioaddr+port*2);
+ writew(data, (void*)(ioaddr+port*2));
result = 0;
}else{
- result = readw(ioaddr+port*2);
+ result = readw((void*)(ioaddr+port*2));
}
/*
printk("daqboard2000_8255_cb %x %d %d %2.2x -> %2.2x\n",
int i;
unsigned int status = 0;
- writew(cmd,dev->iobase+DPR_Command_Mbx);
+ writew(cmd,devpriv->io_addr+DPR_Command_Mbx);
for(i=0;i<TIMEOUT;i++){
- status=readw(dev->iobase+DPR_Command_Mbx);
+ status=readw(devpriv->io_addr+DPR_Command_Mbx);
if((status&DT3000_COMPLETION_MASK)!=DT3000_NOTPROCESSED)
break;
comedi_udelay(1);
static unsigned int dt3k_readsingle(comedi_device *dev,unsigned int subsys,
unsigned int chan,unsigned int gain)
{
- writew(subsys,dev->iobase+DPR_SubSys);
+ writew(subsys,devpriv->io_addr+DPR_SubSys);
- writew(chan,dev->iobase+DPR_Params(0));
- writew(gain,dev->iobase+DPR_Params(1));
+ writew(chan,devpriv->io_addr+DPR_Params(0));
+ writew(gain,devpriv->io_addr+DPR_Params(1));
dt3k_send_cmd(dev,CMD_READSINGLE);
- return readw(dev->iobase+DPR_Params(2));
+ return readw(devpriv->io_addr+DPR_Params(2));
}
static void dt3k_writesingle(comedi_device *dev,unsigned int subsys,
unsigned int chan,unsigned int data)
{
- writew(subsys,dev->iobase+DPR_SubSys);
+ writew(subsys,devpriv->io_addr+DPR_SubSys);
- writew(chan,dev->iobase+DPR_Params(0));
- writew(0,dev->iobase+DPR_Params(1));
- writew(data,dev->iobase+DPR_Params(2));
+ writew(chan,devpriv->io_addr+DPR_Params(0));
+ writew(0,devpriv->io_addr+DPR_Params(1));
+ writew(data,devpriv->io_addr+DPR_Params(2));
dt3k_send_cmd(dev,CMD_WRITESINGLE);
}
comedi_subdevice *s = dev->subdevices + 0;
unsigned int status;
- status = readw(dev->iobase+DPR_Intr_Flag);
+ status = readw(devpriv->io_addr+DPR_Intr_Flag);
debug_intr_flags(status);
if(status & DT3000_ADFULL){
int i;
sampl_t data;
- front = readw(dev->iobase + DPR_AD_Buf_Front);
+ front = readw(devpriv->io_addr + DPR_AD_Buf_Front);
count = front - devpriv->ai_front;
if(count<0)count += AI_FIFO_DEPTH;
rear = devpriv->ai_rear;
for(i=0;i<count;i++){
- data = readw(dev->iobase + DPR_ADC_buffer + rear);
+ data = readw(devpriv->io_addr + DPR_ADC_buffer + rear);
comedi_buf_put(s->async, data);
rear++;
if(rear>=AI_FIFO_DEPTH)rear = 0;
}
devpriv->ai_rear = rear;
- writew(rear,dev->iobase + DPR_AD_Buf_Rear);
+ writew(rear,devpriv->io_addr + DPR_AD_Buf_Rear);
}
chan=CR_CHAN(cmd->chanlist[i]);
range=CR_RANGE(cmd->chanlist[i]);
- writew((range<<6)|chan,dev->iobase+DPR_ADC_buffer+i);
+ writew((range<<6)|chan,devpriv->io_addr+DPR_ADC_buffer+i);
}
aref=CR_AREF(cmd->chanlist[0]);
- writew(cmd->scan_end_arg,dev->iobase+DPR_Params(0));
+ writew(cmd->scan_end_arg,devpriv->io_addr+DPR_Params(0));
printk("param[0]=0x%04x\n",cmd->scan_end_arg);
if(cmd->convert_src==TRIG_TIMER){
divider = dt3k_ns_to_timer(50,&cmd->convert_arg,
cmd->flags&TRIG_ROUND_MASK);
- writew((divider>>16),dev->iobase+DPR_Params(1));
+ writew((divider>>16),devpriv->io_addr+DPR_Params(1));
printk("param[1]=0x%04x\n",divider>>16);
- writew((divider&0xffff),dev->iobase+DPR_Params(2));
+ writew((divider&0xffff),devpriv->io_addr+DPR_Params(2));
printk("param[2]=0x%04x\n",divider&0xffff);
}else{
/* not supported */
if(cmd->scan_begin_src==TRIG_TIMER){
tscandiv = dt3k_ns_to_timer(100,&cmd->scan_begin_arg,
cmd->flags&TRIG_ROUND_MASK);
- writew((tscandiv>>16),dev->iobase+DPR_Params(3));
+ writew((tscandiv>>16),devpriv->io_addr+DPR_Params(3));
printk("param[3]=0x%04x\n",tscandiv>>16);
- writew((tscandiv&0xffff),dev->iobase+DPR_Params(4));
+ writew((tscandiv&0xffff),devpriv->io_addr+DPR_Params(4));
printk("param[4]=0x%04x\n",tscandiv&0xffff);
}else{
/* not supported */
}
mode = DT3000_AD_RETRIG_INTERNAL | 0 | 0;
- writew(mode,dev->iobase+DPR_Params(5));
+ writew(mode,devpriv->io_addr+DPR_Params(5));
printk("param[5]=0x%04x\n",mode);
- writew(aref==AREF_DIFF,dev->iobase+DPR_Params(6));
+ writew(aref==AREF_DIFF,devpriv->io_addr+DPR_Params(6));
printk("param[6]=0x%04x\n",aref==AREF_DIFF);
- writew(AI_FIFO_DEPTH/2,dev->iobase+DPR_Params(7));
+ writew(AI_FIFO_DEPTH/2,devpriv->io_addr+DPR_Params(7));
printk("param[7]=0x%04x\n",AI_FIFO_DEPTH/2);
- writew(SUBS_AI,dev->iobase+DPR_SubSys);
+ writew(SUBS_AI,devpriv->io_addr+DPR_SubSys);
ret = dt3k_send_cmd(dev,CMD_CONFIG);
writew(DT3000_ADFULL | DT3000_ADSWERR | DT3000_ADHWERR,
- dev->iobase + DPR_Int_Mask);
+ devpriv->io_addr + DPR_Int_Mask);
debug_n_ints = 0;
- writew(SUBS_AI,dev->iobase+DPR_SubSys);
+ writew(SUBS_AI,devpriv->io_addr+DPR_SubSys);
ret = dt3k_send_cmd(dev,CMD_START);
return 0;
{
int ret;
- writew(SUBS_AI,dev->iobase+DPR_SubSys);
+ writew(SUBS_AI,devpriv->io_addr+DPR_SubSys);
ret = dt3k_send_cmd(dev,CMD_STOP);
- writew(0, dev->iobase + DPR_Int_Mask);
+ writew(0, devpriv->io_addr + DPR_Int_Mask);
return 0;
}
static void dt3k_dio_config(comedi_device *dev,int bits)
{
/* XXX */
- writew(SUBS_DOUT,dev->iobase+DPR_SubSys);
+ writew(SUBS_DOUT,devpriv->io_addr+DPR_SubSys);
- writew(bits,dev->iobase+DPR_Params(0));
+ writew(bits,devpriv->io_addr+DPR_Params(0));
#if 0
/* don't know */
- writew(0,dev->iobase+DPR_Params(1));
- writew(0,dev->iobase+DPR_Params(2));
+ writew(0,devpriv->io_addr+DPR_Params(1));
+ writew(0,devpriv->io_addr+DPR_Params(2));
#endif
dt3k_send_cmd(dev,CMD_CONFIG);
int i;
for(i=0;i<insn->n;i++){
- writew(SUBS_MEM,dev->iobase+DPR_SubSys);
- writew(addr,dev->iobase+DPR_Params(0));
- writew(1,dev->iobase+DPR_Params(1));
+ writew(SUBS_MEM,devpriv->io_addr+DPR_SubSys);
+ writew(addr,devpriv->io_addr+DPR_Params(0));
+ writew(1,devpriv->io_addr+DPR_Params(1));
dt3k_send_cmd(dev,CMD_READCODE);
- data[i]=readw(dev->iobase+DPR_Params(2));
+ data[i]=readw(devpriv->io_addr+DPR_Params(2));
}
return i;
printk("0x%08lx mapped to %p, ",devpriv->phys_addr,devpriv->io_addr);
#endif
- dev->iobase = (unsigned long)devpriv->io_addr;
-
return 0;
}
unsigned long plx9080_phys_iobase;
unsigned long hpdi_phys_iobase;
// base addresses (ioremapped)
- unsigned long plx9080_iobase;
- unsigned long hpdi_iobase;
+ void *plx9080_iobase;
+ void *hpdi_iobase;
uint32_t *dio_buffer[ NUM_DMA_BUFFERS ]; // dma buffers
dma_addr_t dio_buffer_phys_addr[ NUM_DMA_BUFFERS ]; // physical addresses of dma buffers
struct plx_dma_desc *dma_desc; // array of dma descriptors read by plx9080, allocated to get proper alignment
static void init_plx9080(comedi_device *dev)
{
uint32_t bits;
- unsigned long plx_iobase = priv(dev)->plx9080_iobase;
+ void *plx_iobase = priv(dev)->plx9080_iobase;
// plx9080 dump
DEBUG_PRINT(" plx interrupt status 0x%x\n", readl(plx_iobase + PLX_INTRCS_REG));
priv(dev)->hpdi_phys_iobase = pci_resource_start(pcidev, HPDI_BADDRINDEX);
// remap, won't work with 2.0 kernels but who cares
- priv(dev)->plx9080_iobase = (unsigned long) ioremap( priv(dev)->plx9080_phys_iobase,
+ priv(dev)->plx9080_iobase = ioremap( priv(dev)->plx9080_phys_iobase,
pci_resource_len( pcidev, PLX9080_BADDRINDEX ) );
- priv(dev)->hpdi_iobase = (unsigned long) ioremap( priv(dev)->hpdi_phys_iobase,
+ priv(dev)->hpdi_iobase = ioremap( priv(dev)->hpdi_phys_iobase,
pci_resource_len( pcidev, HPDI_BADDRINDEX ) );
DEBUG_PRINT(" plx9080 remapped to 0x%lx\n", priv(dev)->plx9080_iobase);
uint32_t next_transfer_addr;
int j;
int num_samples = 0;
- unsigned long pci_addr_reg;
+ void *pci_addr_reg;
if(channel)
pci_addr_reg = priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
#endif
// Disable A/D conversion ready interrupt
devpriv->IntEnable &= ~ADC_READY;
- writew(devpriv->IntEnable,dev->iobase + ICP_MULTI_INT_EN);
+ writew(devpriv->IntEnable,devpriv->io_addr + ICP_MULTI_INT_EN);
// Clear interrupt status
devpriv->IntStatus |= ADC_READY;
- writew(devpriv->IntStatus,dev->iobase + ICP_MULTI_INT_STAT);
+ writew(devpriv->IntStatus,devpriv->io_addr + ICP_MULTI_INT_STAT);
// Set up appropriate channel, mode and range data, for specified channel
setup_channel_list(dev, s, &insn->chanspec, 1);
#ifdef ICP_MULTI_EXTDEBUG
- printk("icp_multi A ST=%4x IO=%lx\n",readw(dev->iobase+ICP_MULTI_ADC_CSR), dev->iobase+ICP_MULTI_ADC_CSR);
+ printk("icp_multi A ST=%4x IO=%p\n",readw(devpriv->io_addr+ICP_MULTI_ADC_CSR), devpriv->io_addr+ICP_MULTI_ADC_CSR);
#endif
for (n=0; n<insn->n; n++) {
// Set start ADC bit
devpriv->AdcCmdStatus |= ADC_ST;
- writew(devpriv->AdcCmdStatus, dev->iobase+ICP_MULTI_ADC_CSR);
+ writew(devpriv->AdcCmdStatus, devpriv->io_addr+ICP_MULTI_ADC_CSR);
devpriv->AdcCmdStatus &= ~ADC_ST;
#ifdef ICP_MULTI_EXTDEBUG
- printk("icp multi B n=%d ST=%4x\n",n,readw(dev->iobase+ICP_MULTI_ADC_CSR));
+ printk("icp multi B n=%d ST=%4x\n",n,readw(devpriv->io_addr+ICP_MULTI_ADC_CSR));
#endif
comedi_udelay(1);
#ifdef ICP_MULTI_EXTDEBUG
- printk("icp multi C n=%d ST=%4x\n",n,readw(dev->iobase+ICP_MULTI_ADC_CSR));
+ printk("icp multi C n=%d ST=%4x\n",n,readw(devpriv->io_addr+ICP_MULTI_ADC_CSR));
#endif
// Wait for conversion to complete, or get fed up waiting
timeout=100;
while (timeout--) {
- if (!(readw(dev->iobase+ICP_MULTI_ADC_CSR) & ADC_BSY))
+ if (!(readw(devpriv->io_addr+ICP_MULTI_ADC_CSR) & ADC_BSY))
goto conv_finish;
#ifdef ICP_MULTI_EXTDEBUG
if (!(timeout%10))
- printk("icp multi D n=%d tm=%d ST=%4x\n",n,timeout,readw(dev->iobase+ICP_MULTI_ADC_CSR));
+ printk("icp multi D n=%d tm=%d ST=%4x\n",n,timeout,readw(devpriv->io_addr+ICP_MULTI_ADC_CSR));
#endif
comedi_udelay(1);
// Disable interrupt
devpriv->IntEnable &= ~ADC_READY;
- writew(devpriv->IntEnable,dev->iobase + ICP_MULTI_INT_EN);
+ writew(devpriv->IntEnable,devpriv->io_addr + ICP_MULTI_INT_EN);
// Clear interrupt status
devpriv->IntStatus |= ADC_READY;
- writew(devpriv->IntStatus,dev->iobase + ICP_MULTI_INT_STAT);
+ writew(devpriv->IntStatus,devpriv->io_addr + ICP_MULTI_INT_STAT);
// Clear data received
data[n]=0;
return -ETIME;
conv_finish:
- data[n] = (readw(dev->iobase+ICP_MULTI_AI) >> 4 ) & 0x0fff;
+ data[n] = (readw(devpriv->io_addr+ICP_MULTI_AI) >> 4 ) & 0x0fff;
}
// Disable interrupt
devpriv->IntEnable &= ~ADC_READY;
- writew(devpriv->IntEnable,dev->iobase + ICP_MULTI_INT_EN);
+ writew(devpriv->IntEnable,devpriv->io_addr + ICP_MULTI_INT_EN);
// Clear interrupt status
devpriv->IntStatus |= ADC_READY;
- writew(devpriv->IntStatus,dev->iobase + ICP_MULTI_INT_STAT);
+ writew(devpriv->IntStatus,devpriv->io_addr + ICP_MULTI_INT_STAT);
#ifdef ICP_MULTI_EXTDEBUG
printk("icp multi EDBG: END: icp_multi_insn_read_ai(...) n=%d\n",n);
#endif
// Disable D/A conversion ready interrupt
devpriv->IntEnable &= ~DAC_READY;
- writew(devpriv->IntEnable,dev->iobase + ICP_MULTI_INT_EN);
+ writew(devpriv->IntEnable,devpriv->io_addr + ICP_MULTI_INT_EN);
// Clear interrupt status
devpriv->IntStatus |= DAC_READY;
- writew(devpriv->IntStatus,dev->iobase + ICP_MULTI_INT_STAT);
+ writew(devpriv->IntStatus,devpriv->io_addr + ICP_MULTI_INT_STAT);
// Get channel number and range
chan = CR_CHAN(insn->chanspec);
devpriv->DacCmdStatus |= this_board->rangecode[range];
devpriv->DacCmdStatus |= (chan << 8);
- writew(devpriv->DacCmdStatus, dev->iobase+ICP_MULTI_DAC_CSR);
+ writew(devpriv->DacCmdStatus, devpriv->io_addr+ICP_MULTI_DAC_CSR);
for (n=0; n<insn->n; n++) {
// Wait for analogue output data register to be ready for new data, or get fed up waiting
timeout=100;
while (timeout--) {
- if (!(readw(dev->iobase+ICP_MULTI_DAC_CSR) & DAC_BSY))
+ if (!(readw(devpriv->io_addr+ICP_MULTI_DAC_CSR) & DAC_BSY))
goto dac_ready;
#ifdef ICP_MULTI_EXTDEBUG
if (!(timeout%10))
- printk("icp multi A n=%d tm=%d ST=%4x\n",n,timeout,readw(dev->iobase+ICP_MULTI_DAC_CSR));
+ printk("icp multi A n=%d tm=%d ST=%4x\n",n,timeout,readw(devpriv->io_addr+ICP_MULTI_DAC_CSR));
#endif
comedi_udelay(1);
// Disable interrupt
devpriv->IntEnable &= ~DAC_READY;
- writew(devpriv->IntEnable,dev->iobase + ICP_MULTI_INT_EN);
+ writew(devpriv->IntEnable,devpriv->io_addr + ICP_MULTI_INT_EN);
// Clear interrupt status
devpriv->IntStatus |= DAC_READY;
- writew(devpriv->IntStatus,dev->iobase + ICP_MULTI_INT_STAT);
+ writew(devpriv->IntStatus,devpriv->io_addr + ICP_MULTI_INT_STAT);
// Clear data received
devpriv->ao_data[chan]=0;
dac_ready:
// Write data to analogue output data register
- writew(data[n], dev->iobase + ICP_MULTI_AO);
+ writew(data[n], devpriv->io_addr + ICP_MULTI_AO);
// Set DAC_ST bit to write the data to selected channel
devpriv->DacCmdStatus |= DAC_ST;
- writew(devpriv->DacCmdStatus, dev->iobase+ICP_MULTI_DAC_CSR);
+ writew(devpriv->DacCmdStatus, devpriv->io_addr+ICP_MULTI_DAC_CSR);
devpriv->DacCmdStatus &= ~DAC_ST;
// Save analogue output data
*/
static int icp_multi_insn_bits_di(comedi_device *dev,comedi_subdevice *s, comedi_insn *insn, lsampl_t *data)
{
- data[1] = readw(dev->iobase + ICP_MULTI_DI);
+ data[1] = readw(devpriv->io_addr + ICP_MULTI_DI);
return 2;
}
printk("Digital outputs = %4x \n", s->state);
- writew(s->state, dev->iobase + ICP_MULTI_DO);
+ writew(s->state, devpriv->io_addr + ICP_MULTI_DO);
}
- data[1] = readw(dev->iobase + ICP_MULTI_DI);
+ data[1] = readw(devpriv->io_addr + ICP_MULTI_DI);
#ifdef ICP_MULTI_EXTDEBUG
printk("icp multi EDBG: END: icp_multi_insn_bits_do(...)\n");
#endif
// Is this interrupt from our board?
- int_no = readw(dev->iobase + ICP_MULTI_INT_STAT) & Status_IRQ;
+ int_no = readw(devpriv->io_addr + ICP_MULTI_INT_STAT) & Status_IRQ;
if (!int_no)
// No, exit
return IRQ_NONE;
#ifdef ICP_MULTI_EXTDEBUG
- printk("icp multi EDBG: interrupt_service_icp_multi() ST: %4x\n",readw(dev->iobase + ICP_MULTI_INT_STAT));
+ printk("icp multi EDBG: interrupt_service_icp_multi() ST: %4x\n",readw(devpriv->io_addr + ICP_MULTI_INT_STAT));
#endif
// Determine which interrupt is active & handle it
devpriv->AdcCmdStatus |= range;
/* Output channel, range, mode to ICP Multi*/
- writew(devpriv->AdcCmdStatus, dev->iobase+ICP_MULTI_ADC_CSR);
+ writew(devpriv->AdcCmdStatus, devpriv->io_addr+ICP_MULTI_ADC_CSR);
#ifdef ICP_MULTI_EXTDEBUG
printk("GS: %2d. [%4x]=%4x %4x\n", i, chanprog, range, devpriv->act_chanlist[i]);
printk("icp_multi EDBG: BGN: icp_multi_reset(...)\n");
#endif
// Clear INT enables and requests
- writew(0, dev->iobase + ICP_MULTI_INT_EN);
- writew(0x00ff, dev->iobase + ICP_MULTI_INT_STAT);
+ writew(0, devpriv->io_addr + ICP_MULTI_INT_EN);
+ writew(0x00ff, devpriv->io_addr + ICP_MULTI_INT_STAT);
if (this_board->n_aochan)
// Set DACs to 0..5V range and 0V output
devpriv->DacCmdStatus |= (i << 8);
// Output 0V
- writew(0, dev->iobase+ICP_MULTI_AO);
+ writew(0, devpriv->io_addr+ICP_MULTI_AO);
// Set start conversion bit
devpriv->DacCmdStatus |= DAC_ST;
// Output to command / status register
- writew(devpriv->DacCmdStatus, dev->iobase+ICP_MULTI_DAC_CSR);
+ writew(devpriv->DacCmdStatus, devpriv->io_addr+ICP_MULTI_DAC_CSR);
// Delay to allow DAC time to recover
comedi_udelay(1);
}
// Digital outputs to 0
- writew(0, dev->iobase + ICP_MULTI_DO);
+ writew(0, devpriv->io_addr + ICP_MULTI_DO);
#ifdef ICP_MULTI_EXTDEBUG
printk("icp multi EDBG: END: icp_multi_reset(...)\n");
iobase=io_addr[2];
-// if(check_mem_region(iobase, ICP_MULTI_SIZE))
-// {
+ if(!request_mem_region(iobase, ICP_MULTI_SIZE, "icp_multi"))
+ {
/* Couldn't allocate io space */
-// printk(KERN_WARNING "couldn't allocate IO space\n");
-// return -EIO;
-// }
-// request_mem_region(iobase, ICP_MULTI_SIZE, "icp_multi");
+ printk(KERN_WARNING "couldn't allocate IO space\n");
+ return -EIO;
+ }
devpriv->phys_iobase = iobase;
printk(", b:s:f=%d:%d:%d, io=0x%8lx \n", pci_bus, pci_slot, pci_func, iobase);
printk("0x%08lx mapped to %p, ", iobase, devpriv->io_addr);
#endif
- dev->iobase = (unsigned long)devpriv->io_addr;
-
dev->board_name = this_board->name;
n_subdevices = 0;
if (dev->irq)
comedi_free_irq(dev->irq,dev);
- if (dev->iobase) {
+ if (dev->private && devpriv->io_addr) {
iounmap(devpriv->io_addr);
-// release_mem_region(iobase, ICP_MULTI_SIZE);
+ release_mem_region(devpriv->phys_iobase, ICP_MULTI_SIZE);
}
if (pci_list_builded) {
typedef union {
- unsigned long iobase;
+ void *iobase;
struct {
- unsigned long iobase;
+ void *iobase;
comedi_lrange *ao_range_list[2]; /* range of channels of ao module */
lsampl_t last_data[2];
}pci20006;
struct {
- unsigned long iobase;
+ void *iobase;
int timebase;
int settling_time;
int ai_gain;
} pci20xxx_subdev_private;
typedef struct {
+ void *ioaddr;
pci20xxx_subdev_private subdev_private[PCI20000_MODULES];
} pci20xxx_private;
if ((ret = alloc_private(dev, sizeof(pci20xxx_private))) < 0)
return ret;
- dev->iobase = it->options[0];
+ devpriv->ioaddr = (void*) it->options[0];
dev->board_name = "pci20kc";
/* Check PCI-20001 C-2A Carrier Board ID */
- if ((readb(dev->iobase) & PCI20000_ID) != PCI20000_ID) {
+ if ((readb(devpriv->ioaddr) & PCI20000_ID) != PCI20000_ID) {
printk("comedi%d: ii_pci20kc", dev->minor);
- printk(" PCI-20001 C-2A Carrier Board at base=0x%05lx not found !\n", dev->iobase);
+ printk(" PCI-20001 C-2A Carrier Board at base=0x%p not found !\n", devpriv->ioaddr);
return -EINVAL;
}
printk("comedi%d:\n", dev->minor);
- printk("ii_pci20kc: PCI-20001 C-2A at base=0x%05lx\n", dev->iobase);
+ printk("ii_pci20kc: PCI-20001 C-2A at base=0x%p\n", devpriv->ioaddr);
for (i = 0; i < PCI20000_MODULES; i++) {
s = dev->subdevices + i;
- id = readb(dev->iobase + (i+1) * PCI20000_OFFSET);
+ id = readb(devpriv->ioaddr + (i+1) * PCI20000_OFFSET);
s->private = devpriv->subdev_private +i;
sdp = s->private;
switch(id){
case PCI20006_ID:
- sdp->pci20006.iobase = dev->iobase + (i+1) * PCI20000_OFFSET;
+ sdp->pci20006.iobase = devpriv->ioaddr + (i+1) * PCI20000_OFFSET;
pci20006_init(dev,s,it->options[2*i+2],it->options[2*i+3]);
printk("comedi%d: ii_pci20kc", dev->minor);
printk(" PCI-20006 module in slot %d \n", i+1);
break;
case PCI20341_ID:
- sdp->pci20341.iobase = dev->iobase + (i+1) * PCI20000_OFFSET;
+ sdp->pci20341.iobase = devpriv->ioaddr + (i+1) * PCI20000_OFFSET;
pci20341_init(dev,s,it->options[2*i+2],it->options[2*i+3]);
printk("comedi%d: ii_pci20kc", dev->minor);
printk(" PCI-20341 module in slot %d \n", i+1);
mask &= s->io_bits;
if(mask&0x000000ff)
- writeb((s->state>>0)&0xff, dev->iobase + PCI20000_DIO_0 );
+ writeb((s->state>>0)&0xff, devpriv->ioaddr + PCI20000_DIO_0 );
if(mask&0x0000ff00)
- writeb((s->state>>8)&0xff, dev->iobase + PCI20000_DIO_1 );
+ writeb((s->state>>8)&0xff, devpriv->ioaddr + PCI20000_DIO_1 );
if(mask&0x00ff0000)
- writeb((s->state>>16)&0xff, dev->iobase + PCI20000_DIO_2 );
+ writeb((s->state>>16)&0xff, devpriv->ioaddr + PCI20000_DIO_2 );
if(mask&0xff000000)
- writeb((s->state>>24)&0xff, dev->iobase + PCI20000_DIO_3 );
+ writeb((s->state>>24)&0xff, devpriv->ioaddr + PCI20000_DIO_3 );
- data[1] = readb(dev->iobase + PCI20000_DIO_0 );
- data[1] |= readb(dev->iobase + PCI20000_DIO_1 )<<8;
- data[1] |= readb(dev->iobase + PCI20000_DIO_2 )<<16;
- data[1] |= readb(dev->iobase + PCI20000_DIO_3 )<<24;
+ data[1] = readb(devpriv->ioaddr + PCI20000_DIO_0 );
+ data[1] |= readb(devpriv->ioaddr + PCI20000_DIO_1 )<<8;
+ data[1] |= readb(devpriv->ioaddr + PCI20000_DIO_2 )<<16;
+ data[1] |= readb(devpriv->ioaddr + PCI20000_DIO_3 )<<24;
return 2;
}
unsigned char control_23;
unsigned char buffer;
- control_01 = readb(dev->iobase + PCI20000_DIO_CONTROL_01);
- control_23 = readb(dev->iobase + PCI20000_DIO_CONTROL_23);
- buffer = readb(dev->iobase + PCI20000_DIO_BUFFER);
+ control_01 = readb(devpriv->ioaddr + PCI20000_DIO_CONTROL_01);
+ control_23 = readb(devpriv->ioaddr + PCI20000_DIO_CONTROL_23);
+ buffer = readb(devpriv->ioaddr + PCI20000_DIO_BUFFER);
if(s->io_bits & 0x000000ff ){
/* output port 0 */
control_23 = (control_23 & DIO_CAND) | PCI20000_DIO_OIC;
buffer = (buffer &(~(DIO_BI<<DIO_PS_3)));
}
- writeb(control_01, dev->iobase + PCI20000_DIO_CONTROL_01);
- writeb(control_23, dev->iobase + PCI20000_DIO_CONTROL_23);
- writeb(buffer, dev->iobase + PCI20000_DIO_BUFFER);
+ writeb(control_01, devpriv->ioaddr + PCI20000_DIO_CONTROL_01);
+ writeb(control_23, devpriv->ioaddr + PCI20000_DIO_CONTROL_23);
+ writeb(buffer, devpriv->ioaddr + PCI20000_DIO_BUFFER);
}
#if 0
/* XXX it would be a good idea to only update the registers
that _need_ to be updated. This requires changes to
comedi, however. */
- writeb((s->state>>0)&0xff, dev->iobase + PCI20000_DIO_0 );
- writeb((s->state>>8)&0xff, dev->iobase + PCI20000_DIO_1 );
- writeb((s->state>>16)&0xff, dev->iobase + PCI20000_DIO_2 );
- writeb((s->state>>24)&0xff, dev->iobase + PCI20000_DIO_3 );
+ writeb((s->state>>0)&0xff, devpriv->ioaddr + PCI20000_DIO_0 );
+ writeb((s->state>>8)&0xff, devpriv->ioaddr + PCI20000_DIO_1 );
+ writeb((s->state>>16)&0xff, devpriv->ioaddr + PCI20000_DIO_2 );
+ writeb((s->state>>24)&0xff, devpriv->ioaddr + PCI20000_DIO_3 );
}
static unsigned int pci20xxx_di(comedi_device * dev, comedi_subdevice * s)
/* XXX same note as above */
unsigned int bits;
- bits = readb(dev->iobase + PCI20000_DIO_0 );
- bits |= readb(dev->iobase + PCI20000_DIO_1 )<<8;
- bits |= readb(dev->iobase + PCI20000_DIO_2 )<<16;
- bits |= readb(dev->iobase + PCI20000_DIO_3 )<<24;
+ bits = readb(devpriv->ioaddr + PCI20000_DIO_0 );
+ bits |= readb(devpriv->ioaddr + PCI20000_DIO_1 )<<8;
+ bits |= readb(devpriv->ioaddr + PCI20000_DIO_2 )<<16;
+ bits |= readb(devpriv->ioaddr + PCI20000_DIO_3 )<<24;
return bits;
}
typedef struct
{
struct pci_dev* pci_device;
- unsigned long plx_regbase; // PLX configuration base address
- unsigned long me_regbase; // Base address of the Meilhaus card
+ void *plx_regbase; // PLX configuration base address
+ void *me_regbase; // Base address of the Meilhaus card
unsigned int plx_regbase_size; // Size of PLX configuration space
unsigned int me_regbase_size; // Size of Meilhaus space
plx_regbase_tmp &= PCI_BASE_ADDRESS_MEM_MASK;
dev_private->plx_regbase_size = plx_regbase_size_tmp;
- dev_private->plx_regbase = (unsigned int) ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
+ dev_private->plx_regbase = ioremap(plx_regbase_tmp, plx_regbase_size_tmp);
// Read Meilhaus register base address [PCI_BASE_ADDRESS #2].
me_regbase_tmp &= PCI_BASE_ADDRESS_MEM_MASK;
dev_private->me_regbase_size = me_regbase_size_tmp;
- dev_private->me_regbase = (unsigned int) ioremap(me_regbase_tmp, me_regbase_size_tmp);
+ dev_private->me_regbase = ioremap(me_regbase_tmp, me_regbase_size_tmp);
// Download firmware and reset card
if(board->device_id == ME2600_DEVICE_ID)
{
return mite->pcidev->device;
};
-static inline unsigned long mite_iobase(struct mite_struct *mite)
-{
- return (unsigned long) mite->daq_io_addr;
-};
-
void mite_init(void);
void mite_cleanup(void);
data[1] = interval*200;
if(interval!=devpriv->filter_interval){
- writeb(interval&0xff, dev->iobase + Filter_Interval(0));
- writeb((interval>>8)&0xff, dev->iobase + Filter_Interval(1));
- writeb((interval>>16)&0x0f, dev->iobase + Filter_Interval(2));
+ writeb(interval&0xff, devpriv->mite->daq_io_addr + Filter_Interval(0));
+ writeb((interval>>8)&0xff, devpriv->mite->daq_io_addr + Filter_Interval(1));
+ writeb((interval>>16)&0x0f, devpriv->mite->daq_io_addr + Filter_Interval(2));
- writeb(ClrInterval, dev->iobase + Clear_Register);
+ writeb(ClrInterval, devpriv->mite->daq_io_addr + Clear_Register);
devpriv->filter_interval = interval;
}
devpriv->filter_enable &= ~(1<<chan);
}
- writeb(devpriv->filter_enable, dev->iobase + Filter_Enable(0));
- writeb(devpriv->filter_enable>>8, dev->iobase + Filter_Enable(1));
- writeb(devpriv->filter_enable>>16, dev->iobase + Filter_Enable(2));
+ writeb(devpriv->filter_enable, devpriv->mite->daq_io_addr + Filter_Enable(0));
+ writeb(devpriv->filter_enable>>8, devpriv->mite->daq_io_addr + Filter_Enable(1));
+ writeb(devpriv->filter_enable>>16, devpriv->mite->daq_io_addr + Filter_Enable(2));
return 2;
}
{
if(insn->n!=2)return -EINVAL;
- data[1] = readb(dev->iobase+Port_Register(0));
- data[1] |= readb(dev->iobase+Port_Register(1))<<8;
- data[1] |= readb(dev->iobase+Port_Register(2))<<16;
+ data[1] = readb(devpriv->mite->daq_io_addr+Port_Register(0));
+ data[1] |= readb(devpriv->mite->daq_io_addr+Port_Register(1))<<8;
+ data[1] |= readb(devpriv->mite->daq_io_addr+Port_Register(2))<<16;
return 2;
}
/* The open relay state on the board cooresponds to 1,
* but in Comedi, it is represented by 0. */
if(data[0]&0x0000ff){
- writeb((s->state^0xff),dev->iobase+Port_Register(3));
+ writeb((s->state^0xff),devpriv->mite->daq_io_addr+Port_Register(3));
}
if(data[0]&0x00ff00){
- writeb((s->state>>8)^0xff,dev->iobase+Port_Register(4));
+ writeb((s->state>>8)^0xff,devpriv->mite->daq_io_addr+Port_Register(4));
}
if(data[0]&0xff0000){
- writeb((s->state>>16)^0xff,dev->iobase+Port_Register(5));
+ writeb((s->state>>16)^0xff,devpriv->mite->daq_io_addr+Port_Register(5));
}
}
data[1] = s->state;
comedi_subdevice *s = dev->subdevices + 2;
unsigned int status;
- status = readb(dev->iobase + Change_Status);
+ status = readb(devpriv->mite->daq_io_addr + Change_Status);
if((status & MasterInterruptStatus) == 0) return IRQ_NONE;
if((status & EdgeStatus) == 0) return IRQ_NONE;
- writeb(ClrEdge | ClrOverflow, dev->iobase + Clear_Register);
+ writeb(ClrEdge | ClrOverflow, devpriv->mite->daq_io_addr + Clear_Register);
comedi_buf_put(s->async, 0);
s->async->events |= COMEDI_CB_EOS;
{
//comedi_cmd *cmd = &s->async->cmd;
- writeb(ClrEdge|ClrOverflow, dev->iobase + Clear_Register);
+ writeb(ClrEdge|ClrOverflow, devpriv->mite->daq_io_addr + Clear_Register);
writeb(FallingEdgeIntEnable|RisingEdgeIntEnable|
MasterInterruptEnable|EdgeIntEnable,
- dev->iobase + Master_Interrupt_Control);
+ devpriv->mite->daq_io_addr + Master_Interrupt_Control);
return 0;
}
static int ni6527_intr_cancel(comedi_device *dev,comedi_subdevice *s)
{
- writeb(0x00, dev->iobase + Master_Interrupt_Control);
+ writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
return 0;
}
if(insn->n < 1)return -EINVAL;
if(data[0] != INSN_CONFIG_CHANGE_NOTIFY)return -EINVAL;
- writeb(data[1], dev->iobase + Rising_Edge_Detection_Enable(0));
- writeb(data[1]>>8, dev->iobase + Rising_Edge_Detection_Enable(1));
- writeb(data[1]>>16, dev->iobase + Rising_Edge_Detection_Enable(2));
+ writeb(data[1], devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(0));
+ writeb(data[1]>>8, devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(1));
+ writeb(data[1]>>16, devpriv->mite->daq_io_addr + Rising_Edge_Detection_Enable(2));
- writeb(data[2], dev->iobase + Falling_Edge_Detection_Enable(0));
- writeb(data[2]>>8, dev->iobase + Falling_Edge_Detection_Enable(1));
- writeb(data[2]>>16, dev->iobase + Falling_Edge_Detection_Enable(2));
+ writeb(data[2], devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(0));
+ writeb(data[2]>>8, devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(1));
+ writeb(data[2]>>16, devpriv->mite->daq_io_addr + Falling_Edge_Detection_Enable(2));
return 2;
}
printk("error setting up mite\n");
return ret;
}
- dev->iobase = mite_iobase(devpriv->mite);
dev->board_name=this_board->name;
dev->irq=mite_irq(devpriv->mite);
printk(" %s",dev->board_name);
- printk(" ID=0x%02x", readb(dev->iobase + ID_Register));
+ printk(" ID=0x%02x", readb(devpriv->mite->daq_io_addr + ID_Register));
if((ret=alloc_subdevices(dev,3))<0)
return ret;
s->insn_bits = ni6527_intr_insn_bits;
s->insn_config = ni6527_intr_insn_config;
- writeb(0x00, dev->iobase + Filter_Enable(0));
- writeb(0x00, dev->iobase + Filter_Enable(1));
- writeb(0x00, dev->iobase + Filter_Enable(2));
+ writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(0));
+ writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(1));
+ writeb(0x00, devpriv->mite->daq_io_addr + Filter_Enable(2));
writeb(ClrEdge|ClrOverflow|ClrFilter|ClrInterval,
- dev->iobase + Clear_Register);
- writeb(0x00, dev->iobase + Master_Interrupt_Control);
+ devpriv->mite->daq_io_addr + Clear_Register);
+ writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
ret=comedi_request_irq(dev->irq,ni6527_interrupt,SA_SHIRQ,"ni6527",dev);
if(ret<0){
static int ni6527_detach(comedi_device *dev)
{
- if(dev->iobase){
- writeb(0x00, dev->iobase + Master_Interrupt_Control);
+ if(devpriv && devpriv->mite && devpriv->mite->daq_io_addr){
+ writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
}
if(dev->irq){
printk("error setting up mite\n");
return ret;
}
- dev->iobase = mite_iobase(devpriv->mite);
dev->board_name = thisboard->name;
/* we don't support the interrupt yet */
//dev->irq = mite_irq(devpriv->mite);
value is
*/
int tmpdata[2];
- unsigned long address;
+ void *address;
/* ============================================================ */
/* 1 subdevice with 8 channels, differentation based on channel */
return -EINVAL;
}
// Now proceed with reading data
- address = dev->iobase
- + GPCT_OFFSET[chipset] +
- registerData[GxSWSaveRegister(counter_channel)].offset;
+ address = devpriv->mite->daq_io_addr
+ + GPCT_OFFSET[chipset] +
+ registerData[GxSWSaveRegister(counter_channel)].offset;
for ( i=0 ; i < insn->n ; i++ )
{
tmpdata[0] = readl(address);
it will try to use the same pins as the first chip.
*/
if(chipset)
- writel(CounterSwap,dev->iobase + GPCT_OFFSET[1]
+ writel(CounterSwap,devpriv->mite->daq_io_addr + GPCT_OFFSET[1]
+ registerData[ClockConfigRegister].offset);
else
- writel(0,dev->iobase + GPCT_OFFSET[0]
+ writel(0,devpriv->mite->daq_io_addr + GPCT_OFFSET[0]
+ registerData[ClockConfigRegister].offset);
}
(ni_660x_gpct_config[subdev_channel]).data[2] = 0;
// Reset the counter
- writew(GxReset(counter_channel),dev->iobase + GPCT_OFFSET[chipset]
+ writew(GxReset(counter_channel),devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxxJointResetRegister(counter_channel)].offset);
// Disarm
- writew(Disarm,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Disarm,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Put 0 as initial counter value in the load register
- writel(0x0,dev->iobase + GPCT_OFFSET[chipset]
+ writel(0x0,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Load (latch) this value into the counter
- writew(Load,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Load,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
/* - Set Counting Mode into GPCT_X1 / 2 / 4 (as set by user)
- When to take into account index pulse (as set by user)
writew(((ni_660x_gpct_config[subdev_channel]).data[0] |
(ni_660x_gpct_config[subdev_channel]).data[1] |
(ni_660x_gpct_config[subdev_channel]).data[2] ),
- dev->iobase + GPCT_OFFSET[chipset]
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCountingModeRegister(counter_channel)].offset);
// Put counter in input mode
// Not necessary since this is the default ...
- /* writel(Counter_A_Is_Input, dev->iobase
+ /* writel(Counter_A_Is_Input, devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[IOConfigReg36_39].offset);
*/
// Arm the counter and put it into Hardware UpDown mode (depending
// on the UP/DOWN IO pin: 0 = down
- writew(UpDownHardware|Arm,dev->iobase + GPCT_OFFSET[chipset]
+ writew(UpDownHardware|Arm,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
break;
case INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR:
return -EINVAL;
}
// Reset the counter
- writew(GxReset(counter_channel), dev->iobase + GPCT_OFFSET[chipset]
+ writew(GxReset(counter_channel), devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxxJointResetRegister(counter_channel)].offset);
// Disarm
- writew(Disarm, dev->iobase + GPCT_OFFSET[chipset]
+ writew(Disarm, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
/* Put PULSE_DELAY as initial counter value into load
register A */
- writel((ni_660x_gpct_config[subdev_channel]).data[1], dev->iobase
+ writel((ni_660x_gpct_config[subdev_channel]).data[1], devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Load (latch) this value into the counter
- writew(Load,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Load,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Now Put PULSE_WIDTH in the LOAD register A
- writel((ni_660x_gpct_config[subdev_channel]).data[0],dev->iobase
+ writel((ni_660x_gpct_config[subdev_channel]).data[0],devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Put Source input to internal 20 MHz clock
TODO: MAKE THIS A DATA FIELD!! to allow different clocks
(See TODO)
================================================== */
- writew(SourceSelectTimebase1, dev->iobase
+ writew(SourceSelectTimebase1, devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxInputSelectRegister(counter_channel)].offset);
/* Choose to Load on reaching TC and
Stop counting after second TC
Choose Load register A to load from */
writew(LoadOnTC | OutputTogglesOnTC | StopOn2ndTC | LoadSourceSelectA,
- dev->iobase + GPCT_OFFSET[chipset]
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxModeRegister(counter_channel)].offset);
// Configure Counter for output
- writel(pin_is_output(0), dev->iobase
+ writel(pin_is_output(0), devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[IOConfigReg(chipset, counter_channel)].offset);
case INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR:
return -EINVAL;
}
// Reset the counter
- writew(GxReset(counter_channel),dev->iobase + GPCT_OFFSET[chipset]
+ writew(GxReset(counter_channel),devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxxJointResetRegister(counter_channel)].offset);
// Disarm counter
- writew(Disarm,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Disarm,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Put PULSE_WIDTH as initial counter value into load register A
- writel((ni_660x_gpct_config[subdev_channel]).data[0],dev->iobase
+ writel((ni_660x_gpct_config[subdev_channel]).data[0],devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Load (latch) this value into the counter
- writew(Load,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Load,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Now Put (PULSE_PERIOD - PULSE_WIDTH) in the load register B
writel((ni_660x_gpct_config[subdev_channel]).data[1]
- (ni_660x_gpct_config[subdev_channel]).data[0],
- dev->iobase + GPCT_OFFSET[chipset]
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxLoadBRegister(counter_channel)].offset);
// Put Source input to internal 20 MHz clock
/* ==================================================
TODO: MAKE THIS A DATA FIELD!! to allow different clocks
(See TODO)
================================================== */
- writew(SourceSelectTimebase1,dev->iobase
+ writew(SourceSelectTimebase1,devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxInputSelectRegister(counter_channel)].offset);
/* Switch between Load registers everytime
Change State of G_OUT on TC (Terminal Count)
Choose Load register A to load from */
writew(ReloadSourceSwitching|LoadOnTC|OutputTogglesOnTC,
- dev->iobase + GPCT_OFFSET[chipset]
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxModeRegister(counter_channel)].offset);
// Configure Counter for output
- writel(pin_is_output(0), dev->iobase
+ writel(pin_is_output(0), devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[IOConfigReg(chipset, counter_channel)].offset);
// Arm the counter and tell it to count down
- writew(Arm|UpDownDown,dev->iobase + GPCT_OFFSET[chipset]
+ writew(Arm|UpDownDown,devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
break;
case GPCT_SIMPLE_EVENT:
CountingAndTimeMeasurement;
// Reset the counter
writew(GxReset(counter_channel),
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxxJointResetRegister(counter_channel)].offset);
// Disarm
writew(Disarm,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxCommandRegister(counter_channel)].offset);
// Put 0 as initial counter value in the load register
writel(0x0,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxLoadARegister(counter_channel)].offset);
// Load (latch) this value into the counter
writew(Load,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxCommandRegister(counter_channel)].offset);
// Set gate logic low, & select source pin dedicated to channel
writew(GateSelectLogicLow|SourceSelectSourcePinI,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxInputSelectRegister(counter_channel)].offset);
// Disable gate for simple event counting
writew(GatingModeDisabled,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxModeRegister(counter_channel)].offset);
// Use normal counting mode (instead of synchronous)
writew(CountingModeNormal,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxCountingModeRegister(counter_channel)].offset
);
// Put counter in input mode
// Not necessary since this is the default ...
/* writel(Counter_A_Is_Input, //NOT WORKING -- REFER KG's file.
- * dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ * devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
* IOConfigReg36_39].offset); */
// Arm the counter and put it into always counting up mode
writew(UpDownUp|Arm,
- dev->iobase + GPCT_OFFSET[chipset] + registerData[
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset] + registerData[
GxCommandRegister(counter_channel)].offset);
break;
default:
{
case PositionMeasurement:
// Disarm the counter
- writew(Disarm, dev->iobase + GPCT_OFFSET[chipset]
+ writew(Disarm, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Write the value into the load register
- writel(*data, dev->iobase + GPCT_OFFSET[chipset]
+ writel(*data, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Latch the value into the counter
- writew(Load, dev->iobase + GPCT_OFFSET[chipset]
+ writew(Load, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
// Arm the counter again and put UpDownHardware in!
- writew(UpDownHardware|Arm, dev->iobase + GPCT_OFFSET[chipset]
+ writew(UpDownHardware|Arm, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
break;
case SinglePulseGeneration:
DPRINTK("NI_660X: INSN_WRITE: SPG: Arming the counter\n");
// Tell the counter to count down and arm
- writew(Arm|UpDownDown, dev->iobase + GPCT_OFFSET[chipset]
+ writew(Arm|UpDownDown, devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxCommandRegister(counter_channel)].offset);
break;
case PulseTrainGeneration:
return -EINVAL;
}
// Put PULSE_WIDTH as initial counter value into load register A
- writel((ni_660x_gpct_config[subdev_channel]).data[0],dev->iobase
+ writel((ni_660x_gpct_config[subdev_channel]).data[0],devpriv->mite->daq_io_addr
+ GPCT_OFFSET[chipset]
+ registerData[GxLoadARegister(counter_channel)].offset);
// Put (PULSE_PERIOD - PULSE_WIDTH) in the load register B
writel( (ni_660x_gpct_config[subdev_channel]).data[1]
- (ni_660x_gpct_config[subdev_channel]).data[0],
- dev->iobase + GPCT_OFFSET[chipset]
+ devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxLoadBRegister(counter_channel)].offset);
break;
default: // Impossible
DPRINTK("Triggering channel %d\n", subdev_channel);
// Reset the counter
- writew(GxReset(counter_channel),dev->iobase + GPCT_OFFSET[chipset]
+ writew(GxReset(counter_channel),devpriv->mite->daq_io_addr + GPCT_OFFSET[chipset]
+ registerData[GxxJointResetRegister(counter_channel)].offset);
return 0;
}
s->state |= data[0]&data[1];
/* Write out the new digital output lines */
/* Check if data < n_chan ?? */
- writew(s->state,dev->iobase + registerData[STCDIOOutput].offset);
+ writew(s->state,devpriv->mite->daq_io_addr + registerData[STCDIOOutput].offset);
}
/* on return, data[1] contains the value of the digital
* input and output lines. */
- data[1]=readw(dev->iobase + registerData[STCDIOParallelInput].offset);
+ data[1]=readw(devpriv->mite->daq_io_addr + registerData[STCDIOParallelInput].offset);
return 2;
}
break;
};
// No GPCT_OFFSET[chipset] offset here??
- writew(s->io_bits,dev->iobase + registerData[STCDIOControl].offset);
+ writew(s->io_bits,devpriv->mite->daq_io_addr + registerData[STCDIOControl].offset);
/* Should we do also something with the IO configuration registers,
see p 3-38 of register level prog. manual
*/
printk("error setting up mite\n");
return ret;
}
- dev->iobase=mite_iobase(devpriv->mite);
dev->board_name=thisboard->name;
dev->irq=mite_irq(devpriv->mite);
printk(" %s",dev->board_name);
s->insn_bits = ni_670x_dio_insn_bits;
s->insn_config = ni_670x_dio_insn_config;
- writel(0x10 ,dev->iobase + MISC_CONTROL_OFFSET); /* Config of misc registers */
- writel(0x00 ,dev->iobase + AO_CONTROL_OFFSET); /* Config of ao registers */
+ writel(0x10 ,devpriv->mite->daq_io_addr + MISC_CONTROL_OFFSET); /* Config of misc registers */
+ writel(0x00 ,devpriv->mite->daq_io_addr + AO_CONTROL_OFFSET); /* Config of ao registers */
printk("attached\n");
for(i=0;i<insn->n;i++){
writel(((chan&15)<<1) | ((chan&16)>>4),
- dev->iobase + AO_CHAN_OFFSET); /* First write in channel register which channel to use */
- writel(data[i],dev->iobase + AO_VALUE_OFFSET); /* write channel value */
+ devpriv->mite->daq_io_addr + AO_CHAN_OFFSET); /* First write in channel register which channel to use */
+ writel(data[i],devpriv->mite->daq_io_addr + AO_VALUE_OFFSET); /* write channel value */
devpriv->ao_readback[chan] = data[i];
}
{
s->state &= ~data[0];
s->state |= data[0]&data[1];
- writel(s->state,dev->iobase + DIO_PORT0_DATA_OFFSET);
+ writel(s->state,devpriv->mite->daq_io_addr + DIO_PORT0_DATA_OFFSET);
}
/* on return, data[1] contains the value of the digital
* input lines. */
- data[1]=readl(dev->iobase + DIO_PORT0_DATA_OFFSET);
+ data[1]=readl(devpriv->mite->daq_io_addr + DIO_PORT0_DATA_OFFSET);
return 2;
}
return -EINVAL;
break;
}
- writel(s->io_bits,dev->iobase + DIO_PORT0_DIR_OFFSET);
+ writel(s->io_bits,devpriv->mite->daq_io_addr + DIO_PORT0_DIR_OFFSET);
return insn->n;
}
}
static inline unsigned int labpc_readb(unsigned long address)
{
- return readb(address);
+ return readb((void*) address);
}
static inline void labpc_writeb(unsigned int byte, unsigned long address)
{
- writeb(byte, address);
+ writeb(byte, (void*) address);
}
static labpc_board labpc_boards[] =
unsigned int counter_number, unsigned int count, unsigned int mode)
{
if(thisboard->memory_mapped_io)
- return i8254_mm_load(base_address, counter_number, count, mode);
+ return i8254_mm_load((void*)base_address, counter_number, count, mode);
else
return i8254_load(base_address, counter_number, count, mode);
}
{
if(dir)
{
- writeb(data, iobase + port);
+ writeb(data, (void*) (iobase + port));
return 0;
}else
{
- return readb(iobase + port);
+ return readb((void*)(iobase + port));
}
}
static int nidio96_8255_cb(int dir,int port,int data,unsigned long iobase)
{
if(dir){
- writeb(data,iobase+port);
+ writeb(data,(void*)(iobase + port));
return 0;
}else{
- return readb(iobase+port);
+ return readb((void*)(iobase + port));
}
}
unsigned int m_status;
int retval = 1;
- status = readb(dev->iobase+Interrupt_And_Window_Status);
- flags = readb(dev->iobase+Group_1_Flags);
+ status = readb(devpriv->mite->daq_io_addr+Interrupt_And_Window_Status);
+ flags = readb(devpriv->mite->daq_io_addr+Group_1_Flags);
m_status = readl(mite->mite_io_addr + MITE_CHSR(DI_DMA_CHAN));
//interrupcions parasites
work++;
if(work>20){
DPRINTK("too much work in interrupt\n");
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
break;
}
work++;
if(work>100){
DPRINTK("too much work in interrupt\n");
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
goto out;
}
- AuxData = readl(dev->iobase+Group_1_FIFO);
+ AuxData = readl(devpriv->mite->daq_io_addr+Group_1_FIFO);
data1 = AuxData & 0xffff;
data2 = (AuxData & 0xffff0000) >> 16;
comedi_buf_put(async,data1);
comedi_buf_put(async,data2);
//DPRINTK("read:%d, %d\n",data1,data2);
- flags = readb(dev->iobase+Group_1_Flags);
+ flags = readb(devpriv->mite->daq_io_addr+Group_1_Flags);
}
//DPRINTK("buf_int_count: %d\n",async->buf_int_count);
//DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",IntEn,flags,status);
if(flags & CountExpired){
DPRINTK("CountExpired\n");
- writeb(ClearExpired,dev->iobase+Group_1_Second_Clear);
+ writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear);
async->events |= COMEDI_CB_EOA;
- writeb(0x00,dev->iobase+OpMode);
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+OpMode);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
#ifdef USE_DMA
mite_dma_disarm(mite, DI_DMA_CHAN);
writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(DI_DMA_CHAN));
break;
}else if(flags & Waited){
DPRINTK("Waited\n");
- writeb(ClearWaited,dev->iobase+Group_1_First_Clear);
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(ClearWaited,devpriv->mite->daq_io_addr+Group_1_First_Clear);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
#ifdef USE_DMA
mite_dma_disarm(mite, DI_DMA_CHAN);
break;
}else if(flags & PrimaryTC){
DPRINTK("PrimaryTC\n");
- writeb(ClearPrimaryTC,dev->iobase+Group_1_First_Clear);
+ writeb(ClearPrimaryTC,devpriv->mite->daq_io_addr+Group_1_First_Clear);
async->events |= COMEDI_CB_EOA;
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
}else if(flags & SecondaryTC){
DPRINTK("SecondaryTC\n");
- writeb(ClearSecondaryTC,dev->iobase+Group_1_First_Clear);
+ writeb(ClearSecondaryTC,devpriv->mite->daq_io_addr+Group_1_First_Clear);
async->events |= COMEDI_CB_EOA;
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
}
#if 0
else{
printk("ni_pcidio: unknown interrupt\n");
async->events |= COMEDI_CB_ERROR|COMEDI_CB_EOA;
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
}
#endif
- flags = readb(dev->iobase+Group_1_Flags);
- status = readb(dev->iobase+Interrupt_And_Window_Status);
+ flags = readb(devpriv->mite->daq_io_addr+Group_1_Flags);
+ status = readb(devpriv->mite->daq_io_addr+Interrupt_And_Window_Status);
//DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,status=0x%02x\n",
// IntEn,flags,status);
//ni_pcidio_print_flags(flags);
#if unused
if(!tag){
- writeb(0x03,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x03,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
}
#endif
return IRQ_RETVAL(retval);
struct timeval tv;
do_gettimeofday(&tv);
- a=readb(dev->iobase+Group_Status);
- b=readb(dev->iobase+Group_1_Flags);
+ a=readb(devpriv->mite->daq_io_addr+Group_Status);
+ b=readb(devpriv->mite->daq_io_addr+Group_1_Flags);
if(n_int < 10){
DPRINTK("status 0x%02x flags 0x%02x time %06d\n",a,b,(int)tv.tv_usec);
}
while(b&1){
- writew(0xff,dev->iobase+Group_1_FIFO);
- b=readb(dev->iobase+Group_1_Flags);
+ writew(0xff,devpriv->mite->daq_io_addr+Group_1_FIFO);
+ b=readb(devpriv->mite->daq_io_addr+Group_1_Flags);
}
- b=readb(dev->iobase+Group_1_Flags);
+ b=readb(devpriv->mite->daq_io_addr+Group_1_Flags);
if(n_int < 10){
DPRINTK("new status 0x%02x\n",b);
default:
return -EINVAL;
}
- writel(s->io_bits,dev->iobase+Port_Pin_Directions(0));
+ writel(s->io_bits,devpriv->mite->daq_io_addr+Port_Pin_Directions(0));
return 1;
}
if(data[0]){
s->state &= ~data[0];
s->state |= (data[0]&data[1]);
- writel(s->state,dev->iobase+Port_IO(0));
+ writel(s->state,devpriv->mite->daq_io_addr+Port_IO(0));
}
- data[1] = readl(dev->iobase+Port_IO(0));
+ data[1] = readl(devpriv->mite->daq_io_addr+Port_IO(0));
return 2;
}
comedi_cmd *cmd = &s->async->cmd;
/* XXX configure ports for input*/
- writel(0x0000,dev->iobase+Port_Pin_Directions(0));
+ writel(0x0000,devpriv->mite->daq_io_addr+Port_Pin_Directions(0));
if(1){
/* enable fifos A B C D */
- writeb(0x0f,dev->iobase+Data_Path);
+ writeb(0x0f,devpriv->mite->daq_io_addr+Data_Path);
/* set transfer width a 32 bits*/
writeb(TransferWidth(0) | TransferLength(0),
- dev->iobase+Transfer_Size_Control);
+ devpriv->mite->daq_io_addr+Transfer_Size_Control);
}else{
- writeb(0x03,dev->iobase+Data_Path);
+ writeb(0x03,devpriv->mite->daq_io_addr+Data_Path);
writeb(TransferWidth(3) | TransferLength(0),
- dev->iobase+Transfer_Size_Control);
+ devpriv->mite->daq_io_addr+Transfer_Size_Control);
}
/* protocol configuration */
if(cmd->scan_begin_src == TRIG_TIMER){
/* page 4-5, "input with internal REQs" */
- writeb( 0 ,dev->iobase+OpMode);
- writeb(0x00,dev->iobase+ClockReg);
- writeb( 1 ,dev->iobase+Sequence);
- writeb(0x04,dev->iobase+ReqReg);
- writeb( 4 ,dev->iobase+BlockMode);
- writeb( 3 ,dev->iobase+LinePolarities);
- writeb(0xc0,dev->iobase+AckSer);
+ writeb( 0 ,devpriv->mite->daq_io_addr+OpMode);
+ writeb(0x00,devpriv->mite->daq_io_addr+ClockReg);
+ writeb( 1 ,devpriv->mite->daq_io_addr+Sequence);
+ writeb(0x04,devpriv->mite->daq_io_addr+ReqReg);
+ writeb( 4 ,devpriv->mite->daq_io_addr+BlockMode);
+ writeb( 3 ,devpriv->mite->daq_io_addr+LinePolarities);
+ writeb(0xc0,devpriv->mite->daq_io_addr+AckSer);
writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
- TRIG_ROUND_NEAREST),dev->iobase+StartDelay);
- writeb( 1 ,dev->iobase+ReqDelay);
- writeb( 1 ,dev->iobase+ReqNotDelay);
- writeb( 1 ,dev->iobase+AckDelay);
- writeb(0x0b,dev->iobase+AckNotDelay);
- writeb(0x01,dev->iobase+Data1Delay);
+ TRIG_ROUND_NEAREST),devpriv->mite->daq_io_addr+StartDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+ReqDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+ReqNotDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+AckDelay);
+ writeb(0x0b,devpriv->mite->daq_io_addr+AckNotDelay);
+ writeb(0x01,devpriv->mite->daq_io_addr+Data1Delay);
/* manual, page 4-5: ClockSpeed comment is incorrectly listed
* on DAQOptions */
- writew(0 ,dev->iobase+ClockSpeed);
- writeb(0 ,dev->iobase+DAQOptions);
+ writew(0 ,devpriv->mite->daq_io_addr+ClockSpeed);
+ writeb(0 ,devpriv->mite->daq_io_addr+DAQOptions);
}else{
/* TRIG_EXT */
/* page 4-5, "input with external REQs" */
- writeb( 0 ,dev->iobase+OpMode);
- writeb(0x00,dev->iobase+ClockReg);
- writeb( 0 ,dev->iobase+Sequence);
- writeb(0x00,dev->iobase+ReqReg);
- writeb( 4 ,dev->iobase+BlockMode);
- writeb( 0 ,dev->iobase+LinePolarities);
- writeb(0x00,dev->iobase+AckSer);
- writel( 1 ,dev->iobase+StartDelay);
- writeb( 1 ,dev->iobase+ReqDelay);
- writeb( 1 ,dev->iobase+ReqNotDelay);
- writeb( 1 ,dev->iobase+AckDelay);
- writeb(0x0C,dev->iobase+AckNotDelay);
- writeb(0x10,dev->iobase+Data1Delay);
- writew( 0 ,dev->iobase+ClockSpeed);
- writeb(0x60,dev->iobase+DAQOptions);
+ writeb( 0 ,devpriv->mite->daq_io_addr+OpMode);
+ writeb(0x00,devpriv->mite->daq_io_addr+ClockReg);
+ writeb( 0 ,devpriv->mite->daq_io_addr+Sequence);
+ writeb(0x00,devpriv->mite->daq_io_addr+ReqReg);
+ writeb( 4 ,devpriv->mite->daq_io_addr+BlockMode);
+ writeb( 0 ,devpriv->mite->daq_io_addr+LinePolarities);
+ writeb(0x00,devpriv->mite->daq_io_addr+AckSer);
+ writel( 1 ,devpriv->mite->daq_io_addr+StartDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+ReqDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+ReqNotDelay);
+ writeb( 1 ,devpriv->mite->daq_io_addr+AckDelay);
+ writeb(0x0C,devpriv->mite->daq_io_addr+AckNotDelay);
+ writeb(0x10,devpriv->mite->daq_io_addr+Data1Delay);
+ writew( 0 ,devpriv->mite->daq_io_addr+ClockSpeed);
+ writeb(0x60,devpriv->mite->daq_io_addr+DAQOptions);
}
if(cmd->stop_src == TRIG_COUNT){
- writel(cmd->stop_arg,dev->iobase+Transfer_Count);
+ writel(cmd->stop_arg,devpriv->mite->daq_io_addr+Transfer_Count);
}else{
/* XXX */
}
#ifdef USE_DMA
- writeb(0x05,dev->iobase+DMA_Line_Control);
- writeb(0x30,dev->iobase+Group_1_First_Clear);
+ writeb(0x05,devpriv->mite->daq_io_addr+DMA_Line_Control);
+ writeb(0x30,devpriv->mite->daq_io_addr+Group_1_First_Clear);
setup_mite_dma(dev,s);
#else
- writeb(0x00,dev->iobase+DMA_Line_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+DMA_Line_Control);
#endif
/* clear and enable interrupts */
- writeb(0xff,dev->iobase+Group_1_First_Clear);
- //writeb(ClearExpired,dev->iobase+Group_1_Second_Clear);
+ writeb(0xff,devpriv->mite->daq_io_addr+Group_1_First_Clear);
+ //writeb(ClearExpired,devpriv->mite->daq_io_addr+Group_1_Second_Clear);
- writeb(IntEn,dev->iobase+Interrupt_Control);
- writeb(0x03,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(IntEn,devpriv->mite->daq_io_addr+Interrupt_Control);
+ writeb(0x03,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
if(cmd->stop_src == TRIG_NONE) {
devpriv->OpModeBits = DataLatching(0) | RunMode(7);
}
if(cmd->start_src == TRIG_NOW){
/* start */
- writeb(devpriv->OpModeBits, dev->iobase+OpMode);
+ writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr+OpMode);
s->async->inttrig = NULL;
}else{
/* TRIG_INT */
{
if(trignum!=0)return -EINVAL;
- writeb(devpriv->OpModeBits, dev->iobase+OpMode);
+ writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr+OpMode);
s->async->inttrig = NULL;
return 1;
static int ni_pcidio_cancel(comedi_device *dev, comedi_subdevice *s)
{
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
return 0;
}
{
static const int timeout = 1000;
int i, j;
- writew(0x80 | fpga_index, dev->iobase + Firmware_Control_Register);
- writew(0xc0 | fpga_index, dev->iobase + Firmware_Control_Register);
- for(i = 0; (readw(dev->iobase + Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i)
+ writew(0x80 | fpga_index, devpriv->mite->daq_io_addr + Firmware_Control_Register);
+ writew(0xc0 | fpga_index, devpriv->mite->daq_io_addr + Firmware_Control_Register);
+ for(i = 0; (readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i)
{
udelay(1);
}
printk("ni_pcidio: failed to load fpga %i, waiting for status 0x2\n", fpga_index);
return -EIO;
}
- writew(0x80 | fpga_index, dev->iobase + Firmware_Control_Register);
- for(i = 0; readw(dev->iobase + Firmware_Status_Register) != 0x3 && i < timeout; ++i)
+ writew(0x80 | fpga_index, devpriv->mite->daq_io_addr + Firmware_Control_Register);
+ for(i = 0; readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) != 0x3 && i < timeout; ++i)
{
udelay(1);
}
{
unsigned int value = data[j++];
value |= data[j++] << 8;
- writew(value, dev->iobase + Firmware_Data_Register);
- for(i = 0; (readw(dev->iobase + Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i)
+ writew(value, devpriv->mite->daq_io_addr + Firmware_Data_Register);
+ for(i = 0; (readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i)
{
udelay(1);
}
if(need_resched())
schedule();
}
- writew(0x0, dev->iobase + Firmware_Control_Register);
+ writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
return 0;
}
{
int ret;
int i;
- writew(0x0, dev->iobase + Firmware_Control_Register);
+ writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
for(i = 0; i < 3; ++i)
{
ret = pci_6534_reset_fpga(dev, i);
if(ret < 0) break;
}
- writew(0x0, dev->iobase + Firmware_Mask_Register);
+ writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
return ret;
}
static void pci_6534_init_main_fpga(comedi_device *dev)
{
- writel(0, dev->iobase + FPGA_Control1_Register);
- writel(0, dev->iobase + FPGA_Control2_Register);
- writel(0, dev->iobase + FPGA_SCALS_Counter_Register);
- writel(0, dev->iobase + FPGA_SCAMS_Counter_Register);
- writel(0, dev->iobase + FPGA_SCBLS_Counter_Register);
- writel(0, dev->iobase + FPGA_SCBMS_Counter_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
+ writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
}
static int pci_6534_upload_firmware(comedi_device *dev, int options[])
printk("error setting up mite\n");
return ret;
}
- dev->iobase = mite_iobase(devpriv->mite);
dev->board_name=this_board->name;
dev->irq=mite_irq(devpriv->mite);
if(!this_board->is_diodaq){
for(i=0;i<this_board->n_8255;i++){
subdev_8255_init(dev,dev->subdevices+i,
- nidio96_8255_cb,(unsigned long)(dev->iobase+NIDIO_8255_BASE(i)));
+ nidio96_8255_cb,(unsigned long)(devpriv->mite->daq_io_addr+NIDIO_8255_BASE(i)));
}
}else{
- printk(" rev=%d",readb(dev->iobase+Chip_Version));
+ printk(" rev=%d",readb(devpriv->mite->daq_io_addr+Chip_Version));
s=dev->subdevices+0;
s->len_chanlist=32; /* XXX */
s->buf_change = ni_pcidio_change;
- writel(0,dev->iobase+Port_IO(0));
- writel(0,dev->iobase+Port_Pin_Directions(0));
- writel(0,dev->iobase+Port_Pin_Mask(0));
+ writel(0,devpriv->mite->daq_io_addr+Port_IO(0));
+ writel(0,devpriv->mite->daq_io_addr+Port_Pin_Directions(0));
+ writel(0,devpriv->mite->daq_io_addr+Port_Pin_Mask(0));
/* disable interrupts on board */
- writeb(0x00,dev->iobase+Master_DMA_And_Interrupt_Control);
+ writeb(0x00,devpriv->mite->daq_io_addr+Master_DMA_And_Interrupt_Control);
ret=comedi_request_irq(dev->irq,nidio_interrupt,SA_SHIRQ,"ni_pcidio",dev);
if(ret<0){
/* How we access registers */
-#define ni_writel(a,b) (writel((a),dev->iobase+(b)))
-#define ni_readl(a) (readl(dev->iobase+(a)))
-#define ni_writew(a,b) (writew((a),dev->iobase+(b)))
-#define ni_readw(a) (readw(dev->iobase+(a)))
-#define ni_writeb(a,b) (writeb((a),dev->iobase+(b)))
-#define ni_readb(a) (readb(dev->iobase+(a)))
+#define ni_writel(a,b) (writel((a), (void*)(dev->iobase + (b))))
+#define ni_readl(a) (readl((void*)(dev->iobase + (a))))
+#define ni_writew(a,b) (writew((a), (void*)(dev->iobase + (b))))
+#define ni_readw(a) (readw((void*)(dev->iobase + (a))))
+#define ni_writeb(a,b) (writeb((a), (void*)(dev->iobase + (b))))
+#define ni_readb(a) (readb((void*)(dev->iobase + (a))))
/* How we access STC registers */
#define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */
#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1)
-static inline int plx9080_abort_dma( unsigned long iobase, unsigned int channel )
+static inline int plx9080_abort_dma(void *iobase, unsigned int channel )
{
- unsigned long dma_cs_addr;
+ void *dma_cs_addr;
uint8_t dma_status;
const int timeout = 10000;
unsigned int i;
projects / comedi.git / commitdiff